Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device.The display panel comprises a plurality of first pixel circuits and a plurality of second pixel circuits, the first pixel circuits are located in a display area and arranged in an array mode, each first pixel circuit is connected with a light-emitting element, and the first pixel circuits are used for driving the light-emitting elements to emit light; wherein at least n rows of first pixel circuits perform threshold voltage compensation at the same time; the second pixel circuits are located in the non-display area and arranged in an array mode, and the second pixel circuits are used for supplementing the number of rows of pixel circuits which conduct threshold voltage compensation at the same time to n rows when threshold voltage compensation is conducted on the first row of first pixel circuits and / or the last row of first pixel circuits, the compensation current of the first row of first pixel circuits and / or the last row of first pixel circuits is compensated; wherein the number of the transistors in the second pixel circuit is smaller than that of the transistors in the first pixel circuit. According to the scheme, the problem of abnormal display of the first and last rows of pixels can be solved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, display panels are moving towards high refresh rates.

[0003] At high refresh rates, there is a problem of abnormal display of pixels in the first and last rows. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device to solve the problem of abnormal display of pixels in the first and last rows.

[0005] According to one aspect of the present invention, there is provided a display panel, the display panel having a display area and a non-display area arranged around the display area, the display panel comprising:

[0006] A plurality of first pixel circuits, the plurality of first pixel circuits are located in the display area and arranged in an array of m rows, each of the first pixel circuits is connected to a light-emitting element, and the first pixel circuit is used to drive the light-emitting element to emit light; wherein at least n rows of the first pixel circuits simultaneously perform threshold voltage compensation, m and n are both positive integers greater than 1, and m is greater than n;

[0007] a plurality of second pixel circuits, the plurality of second pixel circuits being located in the non-display area and arranged in an array of t rows, the second pixel circuits being used to configure the second pixel circuits in row x to perform the threshold voltage compensation when the first pixel circuits in row a perform the threshold voltage compensation, and / or being used to configure the second pixel circuits in row y to perform the threshold voltage compensation when the first pixel circuits in row b perform the threshold voltage compensation, t, a, x, b and y are all positive integers greater than 1, x and y are both not greater than t, and a+x and b+y are both not greater than n;

[0008] The number of transistors in the second pixel circuit is less than the number of transistors in the first pixel circuit.

[0009] Optionally, x is equal to na, and / or, y is equal to nb;

[0010] Preferably, t is equal to 2n-2, wherein n-1 rows of the second pixel circuits are arranged in the non-display area close to the first row of the first pixel circuits, and n-1 rows of the second pixel circuits are arranged in the non-display area close to the last row of the first pixel circuits;

[0011] Optionally, the number of the second pixel circuits in a row is less than or equal to the number of the first pixel circuits in a row.

[0012] Optionally, the second pixel circuit includes a first driving module, a first initialization module, a first compensation module and a first storage module;

[0013] A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is used to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the first end of the first driving module;

[0014] A first end of the first driving module is connected to a first power line, a second end of the first driving module is connected to a first end of the first compensation module, a second end of the first compensation module is connected to a control end of the first driving module, the control end of the first compensation module is connected to a second scan line, and the first compensation module is used to compensate for a threshold voltage of the first driving module in a threshold voltage compensation stage;

[0015] Optionally, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, and the first storage module includes a first storage capacitor; a first electrode of the first transistor is connected to the first power line, a second electrode of the first transistor is connected to the first electrode of the second transistor, a second electrode of the second transistor is connected to the gate of the first transistor, and the gate of the second transistor is connected to the second scan line, a first electrode of the third transistor is connected to the first initialization signal line, a second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; a first electrode of the first storage capacitor is connected to the gate of the first transistor, and a second electrode of the first storage capacitor is connected to the first electrode of the first transistor;

[0016] Optionally, the first transistor, the second transistor and the third transistor are all P-type transistors.

[0017] Optionally, the second pixel circuit includes a first driving module, a first initialization module, a first compensation module and a first storage module;

[0018] A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, and the first initialization module is used to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase; the first storage module is connected between the control end and the second end of the first driving module;

[0019] The first end of the first driving module is connected to the first end of the first compensation module, the second end of the first driving module is connected to the second power line, the second end of the first compensation module is connected to the control end of the first driving module, the control end of the first compensation module is connected to the second scan line, and the first compensation module is used to compensate for the threshold voltage of the first driving module in the threshold voltage compensation stage;

[0020] Optionally, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, and the first storage module includes a first storage capacitor; a first electrode of the first transistor is connected to a first electrode of the second transistor, a second electrode of the first transistor is connected to the second power line, a second electrode of the second transistor is connected to a gate of the first transistor, and a gate of the second transistor is connected to the second scan line, a first electrode of the third transistor is connected to the first initialization signal line, a second electrode of the third transistor is connected to the gate of the first transistor, and a gate of the third transistor is connected to the first scan line, a first electrode of the first storage capacitor is connected to the gate of the first transistor, and a second electrode of the first storage capacitor is connected to the second electrode of the first transistor;

[0021] Optionally, the first transistor, the second transistor and the third transistor are all N-type transistors.

[0022] Optionally, the second pixel circuit includes a first driving module, a first initialization module, a first compensation module, an auxiliary module and a first storage module;

[0023] A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is used to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the first end of the first driving module;

[0024] The first end of the first driving module is connected to the first power line via the auxiliary module, the second end of the first driving module is connected to the first end of the first compensation module, the second end of the first compensation module is connected to the second power line, the control end of the first compensation module is connected to the second scan line, the first compensation module is used to compensate the threshold voltage of the first driving module in the threshold voltage compensation stage, and the control end of the auxiliary module is connected to the third scan line;

[0025] Optionally, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, the auxiliary module includes a fourth transistor, and the first storage module includes a first storage capacitor; the first electrode of the first transistor is connected to the second electrode of the fourth transistor, the first electrode of the fourth transistor is connected to the first power line, the gate of the fourth transistor is connected to the third scan line, the second electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to the second power line, the gate of the second transistor is connected to the second scan line, the first electrode of the third transistor is connected to the first initialization signal line, the second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; the first electrode of the first storage capacitor is connected to the gate of the first transistor, and the second electrode of the first storage capacitor is connected to the first electrode of the first transistor;

[0026] Optionally, the first transistor, the second transistor, the third transistor and the fourth transistor are all P-type transistors.

[0027] Optionally, the second pixel circuit includes a first driving module, a first initialization module, a first compensation module, an auxiliary module and a first storage module;

[0028] A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is used to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the second end of the first driving module;

[0029] The first end of the first driving module is connected to the first power line via the first compensation module, the second end of the first driving module is connected to the first end of the auxiliary module, the second end of the auxiliary module is connected to the second power line, the control end of the first compensation module is connected to the third scan line, the first compensation module is used to compensate the threshold voltage of the first driving module in the threshold voltage compensation stage, and the control end of the auxiliary module is connected to the second scan line;

[0030] Optionally, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, the auxiliary module includes a fourth transistor, and the first storage module includes a first storage capacitor; the first electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the second transistor is connected to the first power line, the gate of the second transistor is connected to the third scan line, the second electrode of the first transistor is connected to the first electrode of the fourth transistor, the second electrode of the fourth transistor is connected to the second power line, the gate of the fourth transistor is connected to the second scan line, the first electrode of the third transistor is connected to the first initialization signal line, the second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; the first electrode of the first storage capacitor is connected to the gate of the first transistor, and the second electrode of the first storage capacitor is connected to the second electrode of the first transistor;

[0031] Optionally, the first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors.

[0032] Optionally, a turn-on time of the first compensation module is equal to a row time of n rows of the first pixel circuits.

[0033] Optionally, in the same row of the second pixel circuits, the second pixel circuits share the same first initialization module and the first storage module;

[0034] Optionally, the first initialization module and the first storage module in the second pixel circuit of each row are arranged at the position of the second pixel circuit in the first column or the last column;

[0035] Optionally, in the same row of the second pixel circuits, the second pixel circuits share the same first compensation module.

[0036] Optionally, the first pixel circuit includes a second driving module, a data writing module, a second compensation module, a second storage module, a third storage module, a second initialization module, a third initialization module and a light emitting module;

[0037] Optionally, the second driving module and the light emitting module are connected between a third power line and a fourth power line, the data writing module is connected between the data line and the first end of the second storage module, the control end of the data writing module is connected to a fourth scan line, the second end of the second storage module is connected to the control end of the second driving module, and the third storage module is connected between the first end of the second driving module and the first end of the second storage module;

[0038] The second compensation module is connected between the second end and the control end of the second driving module, the control end of the second compensation module is connected to the fifth scan line, and the second compensation module is used to compensate the threshold voltage of the second driving module in the threshold voltage compensation stage;

[0039] The second initialization module is connected between the second initialization signal line and the first end of the second storage module, and the control end of the second initialization module is connected to the fifth scan line;

[0040] The third initialization module is connected between the third initialization signal line and the first end of the second driving module, and the control end of the third initialization module is connected to the sixth scan line;

[0041] Optionally, the on-time of the second compensation module is equal to the row time of n rows of the first pixel circuits;

[0042] Optionally, the first pixel circuit further includes a first light-emitting control module and a second light-emitting control module, wherein a first end of the first light-emitting control module is connected to the third power line, a second end of the first light-emitting control module is connected to a second end of the second driving module, a first end of the second light-emitting control module is connected to a first end of the second driving module, a second end of the second light-emitting control module is connected to a first end of the light-emitting module, and a second end of the light-emitting module is connected to the fourth power line; a control end of the first light-emitting control module is connected to a first light-emitting control signal line, and a control end of the second light-emitting control module is connected to a second light-emitting control signal line;

[0043] Optionally, the first pixel circuit further includes a fourth initialization module, the fourth initialization module is connected between a fourth initialization signal line and the first end of the light emitting module, and a control end of the fourth initialization module is connected to the sixth scan line.

[0044] According to another aspect of the present invention, a display device is provided. The display device includes the display panel provided by any embodiment of the present invention.

[0045] The technical solution provided by the embodiment of the present invention is that the first pixel circuit arranged in the display area is used to drive the light-emitting element to emit light, and at least n rows of first pixel circuits perform threshold voltage compensation at the same time; by arranging multiple rows of second pixel circuits in the non-display area, a corresponding pixel circuit row is provided in front of the first row of first pixel circuits and / or behind the last row of first pixel circuits, so that when the first row of first pixel circuits and / or the last row of first pixel circuits perform threshold voltage compensation, the pixel circuit row that is compensated simultaneously with the first row of first pixel circuits and / or the last row of first pixel circuits is padded to n rows or close to n rows, thereby compensating the compensation current of the first row of first pixel circuits and / or the last row of first pixel circuits, thereby making the compensation current corresponding to the first row of first pixel circuits and / or the last row of first pixel circuits consistent with the compensation current corresponding to the first pixel circuits in other intermediate rows, so that the compensation effect of the threshold voltage of each row of first pixel circuits in the display area is consistent, avoiding the problem of abnormal display of the first row of pixels in the display area. In addition, since the number of transistors in the second pixel circuit is less than the number of transistors in the first pixel circuit, it is beneficial to reduce the occupied space of the second pixel circuit, thereby reducing the width of the non-display area and reducing the impact on the frame of the display panel.

[0046] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 A schematic diagram of a compensation process of pixel circuits in each row in a display panel in the related art;

[0049] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of a compensation process of pixel circuits in each row of a display panel provided by an embodiment of the present invention;

[0051] Figure 4 A schematic structural diagram of a second pixel circuit provided by an embodiment of the present invention;

[0052] Figure 5A schematic diagram of another structure of a second pixel circuit provided by an embodiment of the present invention

[0053] Figure 6 A driving timing diagram of a second pixel circuit provided by an embodiment of the present invention;

[0054] Figure 7 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention;

[0055] Figure 8 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention;

[0056] Fig. 9 A driving timing diagram of another second pixel circuit provided by an embodiment of the present invention;

[0057] Fig.10 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention;

[0058] Fig.11 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention;

[0059] Fig.12 A driving timing diagram of another second pixel circuit provided by an embodiment of the present invention;

[0060] Fig.13 A schematic structural diagram of another second pixel circuit provided in an embodiment of the present invention;

[0061] Fig.14 A schematic structural diagram of another second pixel circuit provided by an embodiment of the present invention;

[0062] Fig.15 A driving timing diagram of another second pixel circuit provided by an embodiment of the present invention;

[0063] Fig.16 A structural schematic diagram of an arrangement of a second pixel circuit provided by an embodiment of the present invention;

[0064] Fig.17 A structural schematic diagram of another arrangement of a second pixel circuit provided by an embodiment of the present invention;

[0065] Fig.18 A schematic structural diagram of a first pixel circuit provided by an embodiment of the present invention;

[0066] Fig.19 A schematic structural diagram of another first pixel circuit provided by an embodiment of the present invention;

[0067] Fig. 20A driving timing diagram of a first pixel circuit provided by an embodiment of the present invention;

[0068] Fig.21 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0069] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0070] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0071] As described in the background technology, the existing display panel has the problem of abnormal display of the first and last rows of pixels under high refresh frequency. The inventor has found that the reason for the above problem is that under high refresh frequency, the row time of the pixel circuit is greatly compressed, resulting in the inability of the compensation process of the internal compensation circuit to be completed within the row time. In order to solve the above problem, the related technology adopts the method of cross-row compensation to compensate the threshold voltage. The so-called cross-row compensation refers to the threshold voltage compensation time of the pixel circuit exceeding the row time, so that the compensation time spans multiple rows of row time, that is, there is a phenomenon of simultaneous compensation of multiple rows of pixel circuits to improve the compensation effect. However, in the current display panel, the compensation method of the pixel circuit is a charge-discharge structure, and the multiple rows of pixel circuits charge and discharge the first storage capacitor at the same time, and there is a phenomenon that the DC voltage participating in the compensation has an instantaneous voltage drop, and because the number of rows compensated by the first and last row pixel circuits at the same time is insufficient, the DC voltage participating in the compensation of the first and last row pixel circuits will be different from the DC voltage at other positions, which will cause the problem of abnormal display of the first and last row pixels.

[0072] For example, Figure 1A schematic diagram of a compensation process of pixel circuits in each row of a display panel in the related art, referring to Figure 1 , the X direction represents time, and the Y direction represents pixel rows. Taking the compensation of 5 rows of pixel circuits at the same time as an example, during the compensation process, the pixel circuits in the middle row overlap the compensation time of 2 rows of pixel circuits at the same time. For example, during the threshold voltage compensation process of the 8th row of pixel circuits Row8, the two rows above (the 6th row of pixel circuits Row6 and the 7th row of pixel circuits Row7) and the two rows below (the 9th row of pixel circuits Row9 and the 10th row of pixel circuits Row10) simultaneously perform threshold voltage compensation, and the voltage drop of the DC voltage used for compensation of each row of pixel circuits is 1V. However, there is no pixel circuit row overlapping with the pixel circuit of the 1st row Row1 above it, so the voltage drop of the DC voltage used for compensation of the pixel circuit of the 1st row Row1 is less than 1V, resulting in different compensation currents of the pixel circuit of the 1st row Row1 and the pixel circuit of the middle row, which in turn causes the compensation effect of the threshold voltage of the pixel circuit of the 1st row Row1 to be inconsistent with the compensation effect of the middle row, resulting in abnormal driving of the pixel circuit of the 1st row Row1 and abnormal display of the pixel of the 1st row Row1. The compensation effect of the pixel circuit in the last row (taking Row15 as an example) is the same as the compensation effect of the pixel circuit in Row1.

[0073] like Figure 1 At the middle dotted line, during the simultaneous compensation process, the first 5 rows and the last 5 rows of pixel circuits will lack corresponding pixel circuit rows.

[0074] In view of the above problems, an embodiment of the present invention provides a display panel, which adds redundant pixel circuits to make up for the missing pixel circuit rows of the first and last rows of pixel circuits during the compensation process. Figure 2 A schematic diagram of a display panel according to an embodiment of the present invention is provided. Figure 2 The display panel provided in this embodiment has a display area AA and a non-display area NA arranged around the display area, and the display panel includes:

[0075] A plurality of first pixel circuits 11, the plurality of first pixel circuits 11 are located in the display area AA and are arranged in an array of m rows, each first pixel circuit AA is connected to a light-emitting element, and the first pixel circuit 11 is used to drive the light-emitting element to emit light; wherein at least n rows of first pixel circuits 11 perform threshold voltage compensation simultaneously, m and n are both positive integers greater than 1, and m is greater than n;

[0076] A plurality of second pixel circuits 21, the plurality of second pixel circuits 21 are located in the non-display area NA and are arranged in an array of t rows, the second pixel circuits 21 are used to configure the second pixel circuits in the x row to perform threshold voltage compensation when the first pixel circuits 11 in the previous a row perform threshold voltage compensation, and / or, when the first pixel circuits 11 in the next b row perform threshold voltage compensation, configure the second pixel circuits 21 in the y row to perform threshold voltage compensation, t, a, x, b and y are all positive integers greater than 1, x and y are not greater than t, and a+x and b+y are not greater than n;

[0077] The number of transistors in the second pixel circuit 21 is smaller than the number of transistors in the first pixel circuit 11 .

[0078] Specifically, the first pixel circuit 11 is arranged in the display area AA, with a total of m rows, and is connected to the light-emitting element (not shown in the figure), and can be used to drive the light-emitting element to emit light, thereby realizing screen display. The second pixel circuit 21 is arranged in the non-display area NA, with a total of t rows, and is not connected to the light-emitting element, that is, the second pixel circuit 21 is a redundant pixel circuit, which can be used to make up the number of rows missing from the first pixel circuit 11 in the first and last rows. For example, there are a total of n rows of first pixel circuits 11 that perform threshold voltage compensation at the same time, but for the first pixel circuits 11 in the first a rows, since the number of rows of the first pixel circuits 11 in front of each row in the first a rows is less than n-1 rows, wherein the number of rows of the difference between the first pixel circuit 11 in the first row and the first pixel circuit 11 in the ath row decreases successively. At this time, the threshold voltage compensation can be performed by controlling the second pixel circuit 21 in the x rows, so that when the first pixel circuit 11 in the first a rows performs threshold voltage compensation, the number of rows of the pixel circuits that perform threshold voltage compensation at the same time is close to n rows, or equal to n rows, so as to reduce the compensation difference when the first pixel circuit 11 in the first a rows in the display area AA performs threshold voltage. Similarly, for the first pixel circuits 11 in the last b rows, since the number of rows of the first pixel circuits 11 behind the last b rows is less than n-1 rows, the number of rows of the first pixel circuits 11 behind the nb-th row to the first pixel circuits 11 in the last row increases successively. At this time, by controlling the second pixel circuits 21 in the y row to perform threshold voltage compensation, when the first pixel circuits 11 in the last b rows perform threshold voltage compensation, the number of rows of the pixel circuits that perform threshold voltage compensation at the same time is close to n rows, or equal to n rows, so as to reduce the compensation difference of the first pixel circuits 11 in the last b rows in the display area AA when performing threshold voltage compensation.

[0079] Figure 3 A schematic diagram of a compensation process of pixel circuits in each row of a display panel provided by an embodiment of the present invention, with reference to Figure 3, taking the case where 5 rows of first pixel circuits 11 perform threshold voltage compensation at the same time as an example (i.e., n=5), the corresponding rows of second pixel circuits 21 are added in front of the first pixel circuit 11 in the first row Row1 and behind the first pixel circuit 11 in the last row (in the figure, only Row15 is used as the last row in the display area AA for illustration, i.e., m=15), so that when the first pixel circuits 11 in the first / last row perform threshold voltage compensation for multiple rows at the same time, the first pixel circuits 11 in the first / last row can be supplemented. For example, in this embodiment, 4 rows of second pixel circuits 21 are added to the first and last row first pixel circuits 11, respectively, Du1, Du2...Du8, i.e., t=8. In this way, at the start time of the threshold voltage compensation of the first pixel circuit 11 near the first row Row1 (the position of the first dotted line), the second pixel circuit Du1 in the first row, the second pixel circuit Du2 in the second row, the second pixel circuit Du3 in the third row, the second pixel circuit Du4 in the fourth row and the first pixel circuit Row1 in the first row perform compensation at the same time. As time goes by, at the end time of the threshold voltage compensation of the first pixel circuit Row1 in the first row (the position of the second dotted line), the first pixel circuit Row1 in the first row, the first pixel circuit Row2 in the second row, the first pixel circuit Row3 in the third row, the first pixel circuit Row4 in the fourth row and the first pixel circuit Row5 in the fifth row perform compensation at the same time. Compensation is performed simultaneously. Therefore, during the compensation process of the first pixel circuit Row1 in the first row, there are always 4 rows of pixel circuits that perform compensation together with it, so that the compensation current corresponding to the first pixel circuit Row1 in the first row is consistent with the compensation currents corresponding to the first pixel circuits in other rows; similarly, during the compensation process of the first pixel circuit 11 in the last row, there are always 4 rows of pixel circuits that perform compensation together with it, so that the compensation current corresponding to the first pixel circuit 11 in the last row is consistent with the compensation currents corresponding to the first pixel circuits 11 in other middle rows, so that the compensation effect of the threshold voltage of the first pixel circuits 11 in each row in the display area AA is consistent, avoiding the problem of display abnormality of the first and last rows of pixels in the display area AA.

[0080] In actual operation, two rows of pixel circuits before and after the current row participate in compensation simultaneously.

[0081] It should be noted that if there is a process of simultaneously performing threshold voltage compensation for the first pixel circuits 11 in n rows, the number of rows compensated by the first pixel circuits 11 in the first 4 rows and the first pixel circuits 11 in the last 4 rows is insufficient, and the number of missing rows decreases or increases successively (the number of missing rows of the first pixel circuits 11 in the first 4 rows decreases successively, and the number of missing rows of the first pixel circuits 11 in the last 4 rows increases successively, that is, the number of missing rows of the first pixel circuits 11 in the first row Row1 and the first pixel circuits 11 in the last row is the largest). In the present embodiment, since the first pixel circuits 11 in the first and last rows in the display area AA both have n-1 rows of pixel circuits (including the first pixel circuits 11 in row a and the second pixel circuits 21 in row x, or including the first pixel circuits 11 in row b and the second pixel circuits 21 in row y) to perform compensation simultaneously with them, the first pixel circuits 11 in the second row and the second to last row in the display area AA also have n-1 rows of pixel circuits to perform compensation simultaneously with them. That is to say, while ensuring that the first pixel circuits 11 in the first and last rows in the display area AA have n-1 rows of pixel circuits to compensate simultaneously with them, each row of first pixel circuits 11 in the display area AA has other n-1 rows of pixel circuits to compensate simultaneously with the pixel circuit in that row.

[0082] In this embodiment, since the second pixel circuit 21 is not connected to the light-emitting element and the second pixel circuit 21 has a compensation function, the second pixel circuit 21 only needs to have a compensation circuit, so that the number of transistors in the second pixel circuit 21 is smaller than the number of transistors in the first pixel circuit 11, thereby reducing the occupied area of ​​the second pixel circuit 21, which is beneficial to reducing the border width.

[0083] According to the technical solution provided by the embodiment of the present invention, the first pixel circuit 11 arranged in the display area is used to drive the light-emitting element to emit light, and at least n rows of first pixel circuits 11 perform threshold voltage compensation simultaneously; by arranging multiple rows of second pixel circuits 21 in the non-display area, there are corresponding pixel circuit rows in front of the first row Row1 first pixel circuit 11 and / or behind the last row of first pixel circuits 11, so that when the threshold voltage compensation is performed on the first row Row1 first pixel circuit 11 and / or the last row of first pixel circuits 11, the pixel circuit rows that are compensated simultaneously with the first row Row1 first pixel circuit 11 and / or the last row of first pixel circuits 11 are padded to n rows or close to n rows, thereby compensating the compensation current of the first row Row1 first pixel circuit 11 and / or the last row of first pixel circuits 11, and further making the compensation current corresponding to the first row Row1 first pixel circuit 11 and / or the last row of first pixel circuits 11 consistent with the compensation current corresponding to the first pixel circuits 11 in other intermediate rows, so that the compensation effect of the threshold voltage of the first pixel circuits 11 in each row in the display area AA is consistent, thereby avoiding the problem of display abnormality of the first row of pixels in the display area AA. In addition, since the number of transistors in the second pixel circuit 21 is smaller than the number of transistors in the first pixel circuit 11, it is beneficial to reduce the space occupied by the second pixel circuit 21, thereby helping to reduce the width of the non-display area and reduce the impact on the frame of the display panel.

[0084] Optionally, x is equal to na, and / or y is equal to nb, so that the pixel circuit rows that are compensated simultaneously in the first row Row1 first pixel circuit 11 and / or the last row first pixel circuit 11 are filled to n rows to eliminate the differences in compensation currents corresponding to the first pixel circuits 11 in each row.

[0085] Continue to refer Figure 2 and Figure 3 Optionally, in this embodiment, at least n-1 rows of second pixel circuits 21 are arranged in the non-display area NA close to the first row Row1 first pixel circuit 11, and at least n-1 rows of second pixel circuits 21 are arranged in the non-display area NA close to the last row of first pixel circuits 11.

[0086] Optionally, t is equal to 2n-2. An n-1 row of second pixel circuits 21 is arranged in the non-display area NA near the first row Row1 first pixel circuit 11, and an n-1 row of second pixel circuits 21 is arranged in the non-display area NA near the last row of first pixel circuits 11, so as to ensure that the first and last rows of first pixel circuits 11 have n-1 rows of pixel circuits to perform threshold voltage compensation simultaneously therewith.

[0087] Among them, each row of second pixel circuits 21 is arranged in the non-display area NA. In order to meet the compensation requirements of the first and last rows of first pixel circuits 11, the minimum number of rows of second pixel circuits 21 that need to be arranged can be flexibly set according to the number of rows of first pixel circuits 11 in the display area AA that simultaneously perform threshold voltage compensation. For example, if there are 5 rows of first pixel circuits 11 that simultaneously perform threshold voltage compensation, at least 4 rows of second pixel circuits 21 need to be added to the first and last rows of first pixel circuits 11 to meet the requirement that there are 5 rows of pixel circuits that simultaneously perform threshold voltage compensation during the compensation process of the first pixel circuits 11 in the first row Row1 and the first pixel circuits 11 in the last row.

[0088] Of course, in other embodiments, according to the requirements of image processing quality, stability, reliability, etc., more than 4 rows of second pixel circuits 21 can be added to realize redundant pixels, and the timing can be controlled so that only 5 rows of pixel circuits perform the threshold voltage compensation process at the same time.

[0089] The structure of the second pixel circuit 21 in FIG. 4 is introduced below. The purpose of increasing the non-display area NA space to a smaller extent is achieved by optimizing the structure of the second pixel circuit 21, so as to reduce the impact of adding the second pixel circuit 21 on the frame of the display panel.

[0090] In an optional implementation manner provided in this embodiment, Figure 4 A schematic diagram of a second pixel circuit according to an embodiment of the present invention is provided. Figure 4 On the basis of the above embodiments, optionally, the second pixel circuit 21 includes a first driving module 101, a first initialization module 102, a first compensation module 103 and a first storage module 104; a first end of the first initialization module 104 is connected to a first initialization signal line RE1, a second end of the first initialization module 102 is connected to a control end of the first driving module 101, a control end of the first initialization module 102 is connected to a first scanning line, the first scanning line is used to transmit a first scanning signal S1, and the first initialization module 102 is used to increase the first initialization voltage vref on the first initialization signal line RE1 during the initialization stage. 1 is transmitted to the control end of the first driving module 101, the first storage module 104 is connected between the control end and the first end of the first driving module 101; the first end of the first driving module 101 is connected to the first power line L1, the second end of the first driving module 101 is connected to the first end of the first compensation module 103, the second end of the first compensation module 103 is connected to the control end of the first driving module 101, the control end of the first compensation module 103 is connected to the second scan line, the second scan line is used to transmit the second scan signal S2, and the first compensation module 103 is used to compensate the threshold voltage of the first driving module 101 in the threshold voltage compensation stage.

[0091] The first driving module 101 is not connected to the light emitting element, so the second pixel circuit 21 does not need to write data and is only used to achieve threshold voltage compensation, thereby reducing the number of modules in the second pixel circuit 21.

[0092] Figure 5 A schematic diagram of the structure of another second pixel circuit provided by an embodiment of the present invention, specifically: Figure 4 The second pixel circuit shown is refined into a device structure, referring to Figure 4 and Figure 5 The first driving module 101 includes a first transistor M1, the first compensation module 103 includes a second transistor M2, the first initialization module 102 includes a third transistor M3, and the first storage module 104 includes a first storage capacitor C1; a first electrode of the first transistor M1 is connected to the first power line L1, a second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, a second electrode of the second transistor M2 is connected to the gate of the first transistor M1, and the gate of the second transistor M2 is connected to the second scan line, a first electrode of the third transistor M3 is connected to the first initialization signal line RE1, a second electrode of the third transistor M3 is connected to the gate of the first transistor M1, and the gate of the third transistor M3 is connected to the first scan line; a first electrode of the first storage capacitor C1 is connected to the gate of the first transistor M1, and a second electrode of the first storage capacitor C1 is connected to the first electrode of the first transistor M1.

[0093] Figure 6 A driving timing diagram of a second pixel circuit provided in an embodiment of the present invention can be applied to Figure 5 The second pixel circuit 21 shown, wherein Figure 5 The first transistor M1, the second transistor M2 and the third transistor M3 in the second pixel circuit 21 are all P-type transistors. The first electrode of the first transistor M1 is the source electrode, and the second electrode is the drain electrode. The first transistor (driving transistor) M1 is a diode connection mode. Based on the above embodiments, combined with Figure 5 and Figure 6 Taking a row of second pixel circuits 21 arranged close to the last row of first pixel circuits 11 as an example, the working process of the second pixel circuits 21 includes an initialization phase T1 and a threshold voltage compensation phase T2.

[0094] In the initialization stage T1, the first scanning signal S1 is at a low level, the second scanning signal S2 is at a high level, the third transistor M3 is turned on, and the second transistor M2 is turned off. The first initialization voltage Vref1 is transmitted to the gate of the first transistor M1 through the third transistor M3, initializes the gate of the first transistor M1, and turns on the first transistor M1.

[0095] In the threshold voltage compensation stage T2, the first scanning signal S1 is at a high level, the second scanning signal S2 is at a low level, the third transistor M3 is turned off, and the second transistor M2 is turned on. The first power supply voltage VDD transmitted on the first power line L1 charges the gate of the first transistor M1 through the first transistor M1 and the second transistor M2. When the gate voltage of the first transistor M1 reaches VDD+Vth1, the first transistor M1 is turned off, and the first storage capacitor C1 stores the gate voltage of the first transistor M1. Wherein, Vth1 is the threshold voltage of the first transistor M1.

[0096] The conduction time of the first compensation module 103 is equal to the row time of the n-row first pixel circuits 11. That is, the duration of the threshold voltage compensation phase T2 is equal to the row time of the n-row first pixel circuits 11 to improve the compensation rate of the threshold voltage.

[0097] In another optional implementation provided in this embodiment, Figure 7 A schematic diagram of another second pixel circuit provided by an embodiment of the present invention, referring to Figure 7 On the basis of the above embodiments, optionally, the second pixel circuit 21 includes a first driving module 101, a first initialization module 102, a first compensation module 103 and a first storage module 104; a first end of the first initialization module 102 is connected to the first initialization signal line RE1, a second end of the first initialization module 102 is connected to the control end of the first driving module 101, the control end of the first initialization module 102 is connected to the first scan line, and the first initialization module 102 is used to transmit the first initialization voltage Vref1 on the first initialization signal line RE1 to the control end of the first driving module 101 in the initialization stage; the first storage module 104 is connected between the control end and the second end of the first driving module 101; a first end of the first driving module 101 is connected to the first end of the first compensation module 101, a second end of the first driving module 101 is connected to the second power line L2, a second end of the first compensation module 103 is connected to the control end of the first driving module 101, the control end of the first compensation module 103 is connected to the second scan line, and the first compensation module 103 is used to compensate for the threshold voltage of the first driving module 101 in the threshold voltage compensation stage.

[0098] Figure 8 A schematic diagram of the structure of another second pixel circuit provided by an embodiment of the present invention, specifically: Figure 7 The second pixel circuit 21 is shown in detail as a device structure, referring to Figure 7 and Figure 8, the first driving module 101 includes a first transistor M1, the first compensation module 103 includes a second transistor M2, the first initialization module 102 includes a third transistor M3, and the first storage module 104 includes a first storage capacitor C1; the first electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, the second electrode of the first transistor M1 is connected to the second power line L2, the second electrode of the second transistor M2 is connected to the gate of the first transistor M1, the gate of the second transistor M3 is connected to the second scan line, the first electrode of the third transistor M3 is connected to the first initialization signal line RE1, the second electrode of the third transistor M3 is connected to the gate of the first transistor M1, the gate of the third transistor M3 is connected to the first scan line, the first electrode of the first storage capacitor C1 is connected to the gate of the first transistor M1, and the second electrode of the first storage capacitor C1 is connected to the second electrode of the first transistor M1. Wherein, Figure 8 The first transistor M1 of the second pixel circuit 21 is also connected in a diode manner. Figure 6 The structure shown is different in that the first transistor M1 , the second transistor M2 and the third transistor M3 are all N-type transistors, the first electrode of the first transistor M1 is a drain, and the second electrode is a source.

[0099] Fig. 9 Another driving timing diagram of the second pixel circuit provided in the embodiment of the present invention can be applied to Figure 8 The second pixel circuit 21 shown in FIG. Figure 8 and Fig. 9 The working process of the second pixel circuit 21 provided in this embodiment includes: an initialization stage T1 and a threshold voltage compensation stage T2.

[0100] In the initialization stage T1, the first scanning signal S1 is at a high level, the second scanning signal S2 is at a low level, the third transistor M3 is turned on, and the second transistor M2 is turned off. The first initialization voltage Vref1 is transmitted to the gate of the first transistor M1 through the third transistor M3, initializes the gate of the first transistor M1, and turns on the first transistor M1.

[0101] In the threshold voltage compensation stage T2, the first scanning signal S1 is at a low level, the second scanning signal S2 is at a high level, the third transistor M3 is turned off, and the second transistor M2 is turned on. The gate voltage of the first transistor M1 is discharged through the second transistor M2, the first transistor M1, and the second power line L2. When the gate voltage of the first transistor M1 reaches V2+Vth1, the first transistor M1 is turned off, and the first storage capacitor C1 stores the gate voltage of the first transistor M1. Among them, Vth1 is the threshold voltage of the first transistor M1, V2 is the second power supply voltage transmitted on the second power line, and V2 can be less than the first initialization voltage Vref1.

[0102] The conduction time of the first compensation module 103 is equal to the row time of the n-row first pixel circuits 11. That is, the duration of the threshold voltage compensation phase T2 is equal to the row time of the n-row first pixel circuits 11 to improve the compensation rate of the threshold voltage.

[0103] In another optional implementation provided in this embodiment, Fig.10 A schematic diagram of another second pixel circuit provided by an embodiment of the present invention, referring to Fig.10 Optionally, the second pixel circuit 21 includes a first driving module 101, a first initialization module 102, a first compensation module 103, an auxiliary module 105 and a first storage module 104; a first end of the first initialization module 102 is connected to a first initialization signal line RE1, a second end of the first initialization module 102 is connected to a control end of the first driving module 101, and the control end of the first initialization module 102 is connected to a first scanning line. The first initialization module 102 is used to respond to a first scanning signal S1 on the first scanning line during the initialization stage, and transmit a first initialization voltage Vref1 on the first initialization signal line RE1 to the control end of the first driving module 101. The first storage The module 104 is connected between the control end and the first end of the first driving module 101; the first end of the first driving module 101 is connected to the first power line L1 via the auxiliary module 105, the second end of the first driving module 101 is connected to the first end of the first compensation module 103, the second end of the first compensation module 103 is connected to the second power line L2, the control end of the first compensation module 103 is connected to the second scan line, the first compensation module 103 is used to respond to the second scan signal S2 on the second scan line during the threshold voltage compensation stage, and compensate for the threshold voltage of the first driving module 101, and the control end of the auxiliary module 105 is connected to the third scan line, and is used to respond to the third scan signal on the second scan line.

[0104] Fig.11 A schematic diagram of the structure of another second pixel circuit provided by an embodiment of the present invention, specifically: Fig.10 The second pixel circuit shown is a schematic diagram of a specific device structure, referring to Fig.11, the first driving module 101 includes a first transistor M1, the first compensation module 103 includes a second transistor M2, the first initialization module 102 includes a third transistor M3, the auxiliary module 105 includes a fourth transistor M4, and the first storage module 104 includes a first storage capacitor C1; the first electrode of the first transistor M1 is connected to the second electrode of the fourth transistor M4, the first electrode of the fourth transistor M4 is connected to the first power line L1, the gate of the fourth transistor M4 is connected to the third scan line, the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, the second electrode of the second transistor M2 is connected to the second power line L2, the gate of the second transistor M2 is connected to the second scan line, the first electrode of the third transistor M3 is connected to the first initialization signal line RE1, the second electrode of the third transistor M3 is connected to the gate of the first transistor M1, and the gate of the third transistor M3 is connected to the first scan line; the first electrode of the first storage capacitor C1 is connected to the gate of the first transistor M1, and the second electrode of the first storage capacitor C1 is connected to the first electrode of the first transistor M1. Here, the first transistor M1, the second transistor M2 and the third transistor M3 are all P-type transistors, the first electrode of the first transistor M1 is the source, and the second electrode is the drain.

[0105] Fig.12 Another driving timing diagram of the second pixel circuit provided in the embodiment of the present invention can be applied to Fig.11 The second pixel circuit 21 shown in FIG. Fig.11 and Fig.12 The working process of the second pixel circuit 21 includes an initialization phase T1 and a threshold voltage compensation phase T2.

[0106] In the initialization stage T1, the first scanning signal S1 is at a low level, the second scanning signal S2 is at a high level, the third scanning signal S3 is at a low level, the fourth transistor M4 and the third transistor M3 are turned on, and the second transistor M2 is turned off. The first initialization voltage Vref1 is transmitted to the gate of the first transistor M1 through the third transistor M3, the gate of the first transistor M1 is initialized, and the first transistor M1 is turned on. At the same time, the first power supply voltage VDD on the first power line L1 is transmitted to the first electrode of the first transistor M1 through the fourth transistor M4, and the first electrode of the first transistor M1 is initialized.

[0107] In the threshold voltage compensation stage T2, the first scanning signal S1 is at a low level, the second scanning signal S2 is at a low level, the third scanning signal S3 is at a high level, the second transistor M2 and the third transistor M3 are turned on, and the fourth transistor M4 is turned off. The first initialization voltage Vref1 continuously supplies power to the gate of the first transistor M1, and the voltage of the first electrode of the first transistor M1 is discharged through the first transistor M1 and the second transistor M2. When the voltage of the first electrode of the first transistor M1 reaches Vref1+Vth1, the first transistor M1 is turned off, and the threshold voltage compensation is achieved. The first storage capacitor C1 stores the gate voltage of the first transistor M1. Among them, Vth1 is the threshold voltage of the first transistor M1.

[0108] The conduction time of the first compensation module 103 is equal to the row time of the n-row first pixel circuits 11. That is, the duration of the threshold voltage compensation phase T2 is equal to the row time of the n-row first pixel circuits 11 to improve the compensation rate of the threshold voltage.

[0109] In another optional implementation provided in this embodiment, Fig.13 A schematic diagram of the structure of another second pixel circuit provided in an embodiment of the present invention, referring to Fig.13 Optionally, the second pixel circuit 21 includes a first driving module 101, a first initialization module 102, a first compensation module 103, an auxiliary module 105 and a first storage module 104; a first end of the first initialization module 102 is connected to a first initialization signal line RE1, a second end of the first initialization module 102 is connected to a control end of the first driving module 101, and a control end of the first initialization module 102 is connected to a first scanning line. The first initialization module 101 is used to respond to a first scanning signal S1 on the first scanning line during an initialization phase, and transmit a first initialization voltage Vref1 on the first initialization signal line RE1 to the first driving module The first storage module 104 is connected between the control end and the second end of the first driving module 101; the first end of the first driving module 101 is connected to the first power line L1 via the first compensation module 103, the second end of the first driving module 101 is connected to the first end of the auxiliary module 105, the second end of the auxiliary module 105 is connected to the second power line L2, the control end of the first compensation module 103 is connected to the third scan line, the first compensation module 103 is used to compensate the threshold voltage of the first driving module 101 in response to the third scan signal S3 on the third scan line in the threshold voltage compensation stage, and the control end of the auxiliary module 105 is connected to the second scan line.

[0110] Fig.14 A schematic diagram of the structure of another second pixel circuit provided by an embodiment of the present invention, specifically: Fig.13 The second pixel circuit shown is a schematic diagram of a device structure, referring to Fig.14The first driving module 101 includes a first transistor M1, the first compensation module 103 includes a second transistor M2, the first initialization module 102 includes a third transistor M3, the auxiliary module 105 includes a fourth transistor M4, and the first storage module 104 includes a first storage capacitor C1; a first electrode of the first transistor M1 is connected to a second electrode of the second transistor M2, a first electrode of the second transistor M2 is connected to a first power line L1, a gate of the second transistor M2 is connected to a third scan line, a second electrode of the first transistor M1 is connected to a first electrode of a fourth transistor M4, a second electrode of the fourth transistor M4 is connected to a second power line L2, a gate of the fourth transistor M4 is connected to the second scan line, a first electrode of the third transistor M3 is connected to a first initialization signal line RE1, a second electrode of the third transistor M3 is connected to a gate of the first transistor M1, and a gate of the third transistor M3 is connected to the first scan line; a first electrode of the first storage capacitor C1 is connected to a gate of the first transistor M1, and a second electrode of the first storage capacitor C1 is connected to a second electrode of the first transistor M1.

[0111] in, Fig.14 The second pixel circuit 21 and Fig.11 The first transistors M1 in the second pixel circuit 21 are all source follower connected, only the channel type and connection relationship of the transistors are different, and the number of transistors included in the two is the same. In this embodiment, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all N-type transistors.

[0112] Fig.15 Another driving timing diagram of the second pixel circuit provided in the embodiment of the present invention can be applied to Fig.14 The second pixel circuit 21 shown in FIG. Fig.14 and Fig.15 The working process of the second pixel circuit 21 provided in this embodiment includes: an initialization stage T1 and a threshold voltage compensation stage T2.

[0113] In the initialization stage T1, the first scanning signal S1 is at a high level, the second scanning signal S2 is at a high level, the third scanning signal S3 is at a low level, the third transistor M3 and the fourth transistor M4 are turned on, and the second transistor M2 is turned off. The first initialization voltage Vref1 is transmitted to the gate of the first transistor M1 through the third transistor M3, the gate of the first transistor M1 is initialized, and the first transistor M1 is turned on. At the same time, the second power supply voltage V2 is transmitted to the second electrode of the first transistor M1 through the fourth transistor M4, and the second electrode of the first transistor M1 is initialized.

[0114] In the threshold voltage compensation stage T2, the first scanning signal S1 is at a high level, the second scanning signal S2 is at a low level, the third scanning signal S3 is at a high level, the second transistor M2 and the third transistor M3 are turned on, and the fourth transistor M4 is turned off. The first initialization voltage Vref1 continuously supplies power to the gate of the first transistor M1, and the voltage of the second electrode of the first transistor M1 leaks through the fourth transistor M4. When the voltage of the second electrode of the first transistor M1 reaches Vref1+Vth1, the first transistor M1 is turned off, and the threshold voltage compensation is achieved. The first storage capacitor C1 stores the gate voltage of the first transistor M1. Among them, Vth1 is the threshold voltage of the first transistor M1.

[0115] The conduction time of the first compensation module 103 is equal to the row time of the n-row first pixel circuits 11. That is, the duration of the threshold voltage compensation phase T2 is equal to the row time of the n-row first pixel circuits 11 to improve the compensation rate of the threshold voltage.

[0116] In the above-mentioned four structures and driving timings of the second pixel circuit 21, Sn-last Row is a control signal for controlling the compensation transistor in the last row of the first pixel circuit 11, and the second scanning signal S2 or the third scanning signal S3 (the scanning signal connected to the second transistor M2) corresponding to the row can be obtained by shifting Sn-last Row.

[0117] In this embodiment, the second pixel circuit 21 includes at most four transistors and one first storage capacitor, which can greatly reduce the space added by the non-display area NA and help reduce the impact on the frame.

[0118] In the actual design process, any one of the above four structures of the second pixel circuit 21 can be selected according to specific needs. The following is an example of a connection structure of an N-type transistor source follower. Fig.16 A schematic diagram of a second pixel circuit arrangement method provided by an embodiment of the present invention, referring to Fig.16 The display area AA includes a plurality of pixel units arranged in an array, each pixel unit includes a plurality of sub-pixels, for example, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, each sub-pixel corresponds to a first pixel circuit 11, that is, three first pixel circuits 11 are arranged under each pixel unit. In the non-display area, only one second pixel circuit 21, three second pixel circuits 21, or two second pixel circuits 21 may be arranged under each pixel unit.

[0119] Specifically, since the second pixel circuits 21 are used to compensate for the compensation current of the first and last rows of the first pixel circuits 11, as long as the second pixel circuits 21 in each row can generate the required compensation current value, the uniformity of the compensation current of each row of pixel circuits (including the first pixel circuits 11 and the second pixel circuits 21) can be ensured. Therefore, the number of second pixel circuits 21 in a row can be less than the number of first pixel circuits 11 in a row (e.g. Fig.16 As shown), the space occupied by the second pixel circuit 21 can be reduced. Even if the threshold voltage compensation time is too long, the width of the non-display area NA can be effectively reduced by reducing the number of second pixel circuits 21 and the number of transistors inside the second pixel circuit 21, so as to reduce the impact on the border of the display panel.

[0120] Of course, in other embodiments, the number of the second pixel circuits 21 in a row may also be equal to the number of the first pixel circuits 11 in a row.

[0121] Optionally, in this embodiment, in the same row of second pixel circuits 21 , each second pixel circuit 21 shares the same first initialization module 102 and first storage module 104 . Fig.17 A structural diagram of another arrangement of the second pixel circuit provided by an embodiment of the present invention, referring to Fig.14 and Fig.17 , taking the second pixel circuit 21 as the fourth structure as an example, the third transistor M3 included in the first initialization module 102 and the first storage capacitor C1 included in the first storage module 104 are pulled out and set at the location of the first or last column of the second pixel circuit 21, while the second pixel circuits 21 in other columns share the same third transistor M3 and first storage capacitor C1 with the first or last column of the second pixel circuit 21. In this way, the number of transistors and the number of storage capacitors in part of the second pixel circuit 21 can be further reduced, thereby further reducing the occupied space of the second pixel circuit 21, so as to further reduce the increase in the frame size caused by the addition of the second pixel circuit 21.

[0122] In extreme cases, the first initialization module 102, the first compensation module 103, the auxiliary module 105 and the first storage module 104 in the second pixel circuit 21 can all be pulled out, so that except for the first or last column of second pixel circuits 21, the second pixel circuits 21 in other columns only include the first driving module 101, and the other modules are shared with the first or last column of second pixel circuits 21, so as to minimize the increase in space around the display area AA, that is, to minimize the increase in the border size.

[0123] Optionally, in Fig.17In the structure shown, since multiple second pixel circuits 21 in the same row share the same third transistor M3 (first initialization module 102), in order to ensure that the first transistors M1 of the entire row are smoothly turned on, the third transistor M3 and / or the first storage capacitor C1 can be optimized to increase the driving capability of the third transistor M3 and the storage capacity of the first storage capacitor C1, thereby meeting the timing matching requirements.

[0124] Optionally, this embodiment further provides a structure of a first pixel circuit 11, Fig.18 A schematic diagram of the structure of a first pixel circuit provided by an embodiment of the present invention, referring to Fig.18 On the basis of the above embodiments, optionally, the first pixel circuit 11 includes a second driving module 111, a data writing module 112, a second compensation module 113, a second storage module 115, a third storage module 116, a second initialization module 114, a third initialization module 117 and a light-emitting module 121, the second driving module 11 and the light-emitting module 121 are connected between the third power line L3 and the fourth power line L4, the data writing module 112 is connected between the data line and the first end of the second storage module 115, the control end of the data writing module 112 is connected to the fourth scan line, the second end of the second storage module 115 is connected to the control end of the second driving module 111, and the third storage module 116 is connected between the first end of the second driving module 11 and the first end of the second storage module 115;

[0125] The second compensation module 113 is connected between the second end and the control end of the second driving module 111, the control end of the second compensation module 113 is connected to the fifth scan line, and the second compensation module 113 is used to compensate for the threshold voltage of the second driving module 111 in the threshold voltage compensation stage; wherein the conduction time of the second compensation module 113 is equal to the row time of the n-row first pixel circuit 11.

[0126] The second initialization module 114 is connected between the second initialization signal line and the first end of the second storage module 115, and the control end of the second initialization module 114 is connected to the fifth scan line; the third initialization module 117 is connected between the third initialization signal line and the first end of the second driving module 111, and the control end of the third initialization module 117 is connected to the sixth scan line.

[0127] Optionally, the first pixel circuit 11 also includes a first light-emitting control module 118 and a second light-emitting control module 119, the first end of the first light-emitting control module 118 is connected to the third power line L3, the second end of the first light-emitting control module 118 is connected to the second end of the second driving module 111, the first end of the second light-emitting control module 119 is connected to the first end of the second driving module 111, the second end of the second light-emitting control module 119 is connected to the first end of the light-emitting module 121, and the second end of the light-emitting module 121 is connected to the fourth power line L4; the control end of the first light-emitting control module 118 is connected to the first light-emitting control signal line, and the control end of the second light-emitting control module 119 is connected to the second light-emitting control signal line.

[0128] The first pixel circuit 11 further includes a fourth initialization module 120 , which is connected between the fourth initialization signal line and the first end of the light emitting module 120 , and a control end of the fourth initialization module 120 is connected to the sixth scan line.

[0129] Fig.19 A schematic structural diagram of another first pixel circuit provided by an embodiment of the present invention, specifically: Fig.18 The first pixel circuit shown is a schematic diagram of a specific device structure, referring to Fig.18 and Fig.19 The first driving module 111 includes a driving transistor Q1, the second compensation module 113 includes a compensation transistor Q2, the data writing module 112 includes a data writing transistor Q3, the second initialization module 114 includes a second initialization transistor Q4, the first light-emitting control module 118 includes a first light-emitting control transistor Q5, the second light-emitting control module 119 includes a second light-emitting control transistor Q6, the third initialization module 117 includes a third initialization transistor Q7, the fourth initialization module 120 includes a fourth initialization transistor Q8, the light-emitting module 121 includes a light-emitting diode D1, the second storage module 115 includes a second storage capacitor C2, and the third storage module 116 includes a third storage capacitor C3.

[0130] The first light-emitting control transistor Q5, the driving transistor Q1, the second light-emitting control transistor Q6 and the light-emitting diode D1 are connected in series between the third power line L3 and the fourth power line L4 in sequence, the gate of the first light-emitting control transistor Q5 is connected to the first light-emitting control signal line, and the gate of the second light-emitting control transistor Q6 is connected to the second light-emitting control signal line.

[0131] The compensation transistor Q2 is connected between the first electrode and the gate of the driving transistor Q1, and the gate of the compensation transistor Q2 is connected to the fifth scanning line; the data writing transistor Q3 is connected between the data line and the first electrode of the second storage capacitor C2, and the gate of the data writing transistor Q3 is connected to the fourth scanning line; the second electrode of the second storage capacitor C2 is connected to the gate of the driving transistor Q1; the third storage capacitor C3 is connected between the second electrode of the driving transistor Q1 and the first electrode of the second storage capacitor C2.

[0132] The second initialization transistor Q4 is connected between the second initialization signal line and the first electrode of the second storage capacitor C2, and the gate of the second initialization transistor Q4 is connected to the fifth scan line; the third initialization transistor Q7 is connected between the third initialization signal line and the second electrode of the driving transistor Q1, the fourth initialization transistor Q8 is connected between the fourth initialization signal line and the first electrode of the light-emitting diode D1, and the gate of the third initialization transistor Q7 and the gate of the fourth initialization transistor Q8 are both connected to the sixth scan line.

[0133] Fig. 20 A driving timing diagram of a first pixel circuit provided by an embodiment of the present invention, referring to Fig.19 and Fig. 20 The working process of the first pixel circuit 11 includes: an initialization phase t1, a threshold voltage compensation phase t2, a data writing phase t3 and a light emitting phase t4. Among them, at least the threshold voltage compensation phase t2 of the first pixel circuit 11 of the first and last rows overlaps with the threshold voltage compensation phase T2 of the second pixel circuit 21 in time, and the threshold voltage compensation phase t2 of each row of the first pixel circuit 11 is greater than a row time, for example, the sum of n row times, where n is an integer greater than 1.

[0134] Taking the case where all transistors are N-type transistors as an example, the specific working process of the first pixel circuit 11 is as follows:

[0135] In the initialization stage t1, the fourth scanning signal on the fourth scanning line is at a low level, the fifth scanning signal on the fifth scanning line is at a high level, the sixth scanning signal on the sixth scanning line is at a low level, the first light-emitting control signal EM1 on the first light-emitting control signal line is at a high level, and the second light-emitting control signal EM2 on the second light-emitting control signal line is at a low level. Therefore, the compensation transistor Q2, the second initialization transistor Q4 and the first light-emitting control transistor Q5 are turned on, the second initialization voltage Vini1 on the second initialization signal line is transmitted to the first electrode of the second storage capacitor C2 via the second initialization transistor Q4, and the third power supply voltage ELVDD on the third power supply line L3 is transmitted to the second electrode of the second storage capacitor C2 (i.e., the gate of the driving transistor Q1) via the first light-emitting control transistor Q5 and the compensation transistor Q2, so as to realize the initialization of the second storage capacitor C2. At this time, the potential of the second electrode of the driving transistor Q1 changes with the display grayscale of the previous frame. Since the gate of the driving transistor Q1 is reset to the third power supply voltage ELVDD of the high potential, the driving transistor Q1 is turned on.

[0136] In the threshold voltage compensation stage t2, the fourth scanning signal on the fourth scanning line is at a low level, the fifth scanning signal on the fifth scanning line is at a high level, the sixth scanning signal on the sixth scanning line is at a high level, the first light-emitting control signal EM1 on the first light-emitting control signal line is at a low level, and the second light-emitting control signal EM2 on the second light-emitting control signal line is at a low level. Therefore, the compensation transistor Q2, the second initialization transistor Q4, the third initialization transistor Q7 and the fourth initialization transistor Q8 are turned on, the second electrode of the driving transistor Q1 is reset to the third initialization voltage VEH on the third initialization signal line, and the first electrode of the light-emitting diode D1 is reset to the fourth initialization voltage Vini2 on the fourth initialization signal line. The compensation transistor Q2 is continuously turned on, the driving transistor Q1 maintains a diode connection mode, and the gate of the driving transistor Q1 is discharged through the compensation transistor Q2 and the third initialization transistor Q7 until the gate of the driving transistor Q1 is VEH+VTH1, the driving transistor Q1 is turned off, and the compensation ends, wherein VTH1 is the threshold voltage of the driving transistor Q1.

[0137] Among them, the time of the threshold voltage compensation stage t2 is greater than the row time, and there is a situation where multiple rows of first pixel circuits 11 are compensated at the same time. In this embodiment, multiple rows of second pixel circuits 21 are arranged in the non-display area, so that there are corresponding pixel circuit rows in front of the first row Row1 first pixel circuit 11 and / or behind the last row first pixel circuit 11, so that when the threshold voltage compensation is performed on the first row Row1 first pixel circuit 11 and / or the last row first pixel circuit 11, the pixel circuit rows that are compensated at the same time as the first row Row1 first pixel circuit 11 and / or the last row first pixel circuit 11 are padded to n rows, thereby compensating the compensation current of the first row Row1 first pixel circuit 11 and / or the last row first pixel circuit 11, and then making the compensation current corresponding to the first row Row1 first pixel circuit 11 and / or the last row first pixel circuit 11 consistent with the compensation current corresponding to the first pixel circuit 11 in other middle rows, so that the compensation effect of the threshold voltage of each row of the first pixel circuit 11 in the display area AA is consistent, avoiding the problem of abnormal display of the first row of pixels in the display area AA.

[0138] Optionally, the fourth initialization signal line may be multiplexed as the third initialization signal line to reduce the number of signal lines.

[0139] In the data writing stage t3, the fourth scanning signal on the fourth scanning line is at a high level, the fifth scanning signal on the fifth scanning line is at a low level, the sixth scanning signal on the sixth scanning line is at a high level, the first light-emitting control signal EM1 on the first light-emitting control signal line is at a low level, and the second light-emitting control signal EM2 on the second light-emitting control signal line is at a low level. Therefore, the data writing transistor Q3, the third initialization transistor Q7 and the fourth initialization transistor Q8 are turned on, the first electrode of the second storage capacitor C2 jumps from the second initialization voltage Vini1 to the data voltage Vdata, and under the coupling effect of the second storage capacitor C2, the gate voltage change of the driving transistor Q1 is k*(Vdata-Vini1), where k=c2 / (c2+c0), c2 is the capacitance of the second storage capacitor C2, and C0 is other capacitance (such as coupling capacitance) of the gate of the driving transistor Q1. At this time, the gate voltage of the driving transistor Q1 becomes VEH+VTH1+k*(Vdata-Vini1), and the voltage of the second electrode of the driving transistor Q1 maintains the third initialization voltage VEH.

[0140] In the light-emitting stage t4, the fourth scanning signal on the fourth scanning line is at a low level, the fifth scanning signal on the fifth scanning line is at a low level, the sixth scanning signal on the sixth scanning line is at a low level, the first light-emitting control signal EM1 on the first light-emitting control signal line is at a high level, and the second light-emitting control signal EM2 on the second light-emitting control signal line is at a high level. Therefore, the first light-emitting control transistor Q5 and the second light-emitting control transistor Q6 are turned on, a current loop is formed between the third power line L3 and the fourth power line L4, and the driving transistor Q1 generates a driving current I to drive the light-emitting diode D1 to emit light. At this time, the voltage of the first electrode of the light-emitting diode D1 changes from Vini2 to ELVSS+VD1. When the fourth initialization voltage Vini2 is reused as the third initialization voltage VEH, that is, VEH=Vini2, the voltage of the second electrode of the driving transistor Q1 also changes from Vini2 to ELVSS+VD1. According to the principle that the voltage difference across the capacitor remains unchanged, the gate voltage of the driving transistor Q1 becomes VEH+VTH1+k*(Vdata-Vini1)+k*(ELVSS+VD1-Vini2)=Vini2+VTH1+k*(Vdata-Vini1)+k*(ELVSS+VD1-Vini2). Ignoring other capacitances at the gate of the driving transistor Q1, when k is equal to 1 or approximately equal to 1, the above formula becomes VTH1+Vdata-Vini1+ELVSS+VD1, that is, the gate voltage of the driving transistor Q1 is VTH1+Vdata-Vini1+ELVSS+VD1.

[0141] Among them, the driving current I can be expressed as:

[0142]

[0143] Wherein, μ is the electron mobility of the driving transistor Q1, Cox is the channel capacitance per unit area of ​​the driving transistor Q1, W / L is the width-to-length ratio of the driving transistor Q1, VTH1 is the threshold voltage of the driving transistor Q1, and VD1 is the voltage drop of the light emitting diode D1.

[0144] The third power line L3 connected to the first pixel circuit 11 provided in this embodiment can be reused as the first power line L1 connected to the second pixel circuit 21, and the fourth power line L4 can also be reused as the second power line L2. Of course, there can also be four independent power lines.

[0145] Optionally, an embodiment of the present invention further provides a display device, which includes the display panel provided by any embodiment of the present invention. Therefore, the display device also has the beneficial effects described in any of the above embodiments. Fig.21A structural schematic diagram of a display device provided in an embodiment of the present invention. In this embodiment, the display device 200 can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals and other products. The embodiment of the present invention does not make any special limitation on this.

[0146] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0147] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: The display panel has a display area and a non-display area arranged around the display area, and the display panel includes: A plurality of first pixel circuits, the plurality of first pixel circuits are located in the display area and arranged in an array of m rows, each of the first pixel circuits is connected to a light-emitting element, and the first pixel circuit is used to drive the light-emitting element to emit light; wherein at least n rows of the first pixel circuits simultaneously perform threshold voltage compensation, m and n are both positive integers greater than 1, and m is greater than n; a plurality of second pixel circuits, the plurality of second pixel circuits being located in the non-display area and arranged in an array of t rows, the second pixel circuits being used to configure the second pixel circuits in row x to perform the threshold voltage compensation when the first pixel circuits in row a perform the threshold voltage compensation, and / or being used to configure the second pixel circuits in row y to perform the threshold voltage compensation when the first pixel circuits in row b perform the threshold voltage compensation, t, a, x, b and y are all positive integers greater than 1, x and y are both not greater than t, and a+x and b+y are both not greater than n; The number of transistors in the second pixel circuit is less than the number of transistors in the first pixel circuit.

2. The display panel according to claim 1, characterized in that: x is equal to na, and / or, y is equal to nb; Preferably, t is equal to 2n-2, wherein n-1 rows of the second pixel circuits are arranged in the non-display area close to the first row of the first pixel circuits, and n-1 rows of the second pixel circuits are arranged in the non-display area close to the last row of the first pixel circuits; Preferably, the number of the second pixel circuits in a row is less than or equal to the number of the first pixel circuits in a row.

3. The display panel according to claim 1, characterized in that: The second pixel circuit includes a first driving module, a first initialization module, a first compensation module and a first storage module; A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is used to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the first end of the first driving module; A first end of the first driving module is connected to a first power line, a second end of the first driving module is connected to a first end of the first compensation module, a second end of the first compensation module is connected to a control end of the first driving module, the control end of the first compensation module is connected to a second scan line, and the first compensation module is used to compensate for a threshold voltage of the first driving module in a threshold voltage compensation stage; Preferably, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, and the first storage module includes a first storage capacitor; a first electrode of the first transistor is connected to the first power line, a second electrode of the first transistor is connected to the first electrode of the second transistor, a second electrode of the second transistor is connected to the gate of the first transistor, the gate of the second transistor is connected to the second scan line, a first electrode of the third transistor is connected to the first initialization signal line, a second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; a first electrode of the first storage capacitor is connected to the gate of the first transistor, and a second electrode of the first storage capacitor is connected to the first electrode of the first transistor; Preferably, the first transistor, the second transistor and the third transistor are all P-type transistors.

4. The display panel according to claim 1, characterized in that: The second pixel circuit includes a first driving module, a first initialization module, a first compensation module and a first storage module; A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, and the first initialization module is used to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase; the first storage module is connected between the control end and the second end of the first driving module; The first end of the first driving module is connected to the first end of the first compensation module, the second end of the first driving module is connected to the second power line, the second end of the first compensation module is connected to the control end of the first driving module, the control end of the first compensation module is connected to the second scan line, and the first compensation module is used to compensate for the threshold voltage of the first driving module in the threshold voltage compensation stage; Preferably, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, and the first storage module includes a first storage capacitor; a first electrode of the first transistor is connected to a first electrode of the second transistor, a second electrode of the first transistor is connected to the second power line, a second electrode of the second transistor is connected to a gate of the first transistor, a gate of the second transistor is connected to the second scan line, a first electrode of the third transistor is connected to the first initialization signal line, a second electrode of the third transistor is connected to the gate of the first transistor, a gate of the third transistor is connected to the first scan line, a first electrode of the first storage capacitor is connected to the gate of the first transistor, and a second electrode of the first storage capacitor is connected to the second electrode of the first transistor; Preferably, the first transistor, the second transistor and the third transistor are all N-type transistors.

5. The display panel according to claim 1, characterized in that: The second pixel circuit includes a first driving module, a first initialization module, a first compensation module, an auxiliary module and a first storage module; A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is used to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the first end of the first driving module; The first end of the first driving module is connected to the first power line via the auxiliary module, the second end of the first driving module is connected to the first end of the first compensation module, the second end of the first compensation module is connected to the second power line, the control end of the first compensation module is connected to the second scan line, the first compensation module is used to compensate the threshold voltage of the first driving module in the threshold voltage compensation stage, and the control end of the auxiliary module is connected to the third scan line; Preferably, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, the auxiliary module includes a fourth transistor, and the first storage module includes a first storage capacitor; the first electrode of the first transistor is connected to the second electrode of the fourth transistor, the first electrode of the fourth transistor is connected to the first power line, the gate of the fourth transistor is connected to the third scan line, the second electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to the second power line, the gate of the second transistor is connected to the second scan line, the first electrode of the third transistor is connected to the first initialization signal line, the second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; the first electrode of the first storage capacitor is connected to the gate of the first transistor, and the second electrode of the first storage capacitor is connected to the first electrode of the first transistor; Preferably, the first transistor, the second transistor, the third transistor and the fourth transistor are all P-type transistors.

6. The display panel according to claim 1, characterized in that: The second pixel circuit includes a first driving module, a first initialization module, a first compensation module, an auxiliary module and a first storage module; A first end of the first initialization module is connected to a first initialization signal line, a second end of the first initialization module is connected to a control end of the first driving module, the control end of the first initialization module is connected to a first scan line, the first initialization module is used to transmit a first initialization voltage on the first initialization signal line to the control end of the first driving module during an initialization phase, and the first storage module is connected between the control end and the second end of the first driving module; The first end of the first driving module is connected to the first power line via the first compensation module, the second end of the first driving module is connected to the first end of the auxiliary module, the second end of the auxiliary module is connected to the second power line, the control end of the first compensation module is connected to the third scan line, the first compensation module is used to compensate the threshold voltage of the first driving module in the threshold voltage compensation stage, and the control end of the auxiliary module is connected to the second scan line; Preferably, the first driving module includes a first transistor, the first compensation module includes a second transistor, the first initialization module includes a third transistor, the auxiliary module includes a fourth transistor, and the first storage module includes a first storage capacitor; the first electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the second transistor is connected to the first power line, the gate of the second transistor is connected to the third scan line, the second electrode of the first transistor is connected to the first electrode of the fourth transistor, the second electrode of the fourth transistor is connected to the second power line, the gate of the fourth transistor is connected to the second scan line, the first electrode of the third transistor is connected to the first initialization signal line, the second electrode of the third transistor is connected to the gate of the first transistor, and the gate of the third transistor is connected to the first scan line; the first electrode of the first storage capacitor is connected to the gate of the first transistor, and the second electrode of the first storage capacitor is connected to the second electrode of the first transistor; Preferably, the first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors.

7. The display panel according to any one of claims 3 to 6, characterized in that: The conduction time of the first compensation module is equal to the row time of n rows of the first pixel circuits.

8. The display panel according to any one of claims 3 to 6, characterized in that: In the second pixel circuits of the same row, the second pixel circuits share the same first initialization module and the first storage module; Preferably, the first initialization module and the first storage module in the second pixel circuit of each row are arranged at the position of the second pixel circuit in the first column or the last column; Preferably, in the same row of the second pixel circuits, the second pixel circuits share the same first compensation module.

9. The display panel according to claim 1, characterized in that: The first pixel circuit includes a second driving module, a data writing module, a second compensation module, a second storage module, a third storage module, a second initialization module, a third initialization module and a light emitting module; The second driving module and the light emitting module are connected between the third power line and the fourth power line, the data writing module is connected between the data line and the first end of the second storage module, the control end of the data writing module is connected to the fourth scanning line, the second end of the second storage module is connected to the control end of the second driving module, and the third storage module is connected between the first end of the second driving module and the first end of the second storage module; The second compensation module is connected between the second end and the control end of the second driving module, the control end of the second compensation module is connected to the fifth scan line, and the second compensation module is used to compensate the threshold voltage of the second driving module in the threshold voltage compensation stage; The second initialization module is connected between the second initialization signal line and the first end of the second storage module, and the control end of the second initialization module is connected to the fifth scan line; The third initialization module is connected between the third initialization signal line and the first end of the second driving module, and the control end of the third initialization module is connected to the sixth scan line; Preferably, the conduction time of the second compensation module is equal to the row time of n rows of the first pixel circuits; Preferably, the first pixel circuit further comprises a first light-emitting control module and a second light-emitting control module, wherein a first end of the first light-emitting control module is connected to the third power line, a second end of the first light-emitting control module is connected to a second end of the second driving module, a first end of the second light-emitting control module is connected to a first end of the second driving module, a second end of the second light-emitting control module is connected to a first end of the light-emitting module, and a second end of the light-emitting module is connected to the fourth power line; a control end of the first light-emitting control module is connected to a first light-emitting control signal line, and a control end of the second light-emitting control module is connected to a second light-emitting control signal line; Preferably, the first pixel circuit further includes a fourth initialization module, the fourth initialization module is connected between a fourth initialization signal line and the first end of the light emitting module, and a control end of the fourth initialization module is connected to the sixth scan line.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

Images