Display panel, driving method thereof and display device

Abstract

The embodiment of the invention provides a display panel, a driving method thereof and a display device, relates to the technical field of display, and optimizes a pixel circuit driving mode. The display panel comprises a pixel circuit, and the pixel circuit comprises a driving module; the control end of the first reset module is connected with the first scanning line, the first end is connected with the first reset line, and the second end is connected with the control end of the driving module; the control end of the data writing module is connected with the second scanning line, the first end is connected with the data line, and the second end is connected with the first end of the driving module; the control end of the first light-emitting control module is connected with a light-emitting control line, the first end is connected with the second end of the driving module, and the second end is connected with a light-emitting element; the enabling levels of the first scanning signal and the second scanning signal are low levels, the second scanning signal has an enabling level within the time covered by a non-enabling level of the light emitting control signal, and the total duration of the enabling level in the first scanning signal is larger than the duration of the enabling level in the second scanning signal.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] The display panel includes a pixel circuit, which is used to output a driving current to the light-emitting element to drive the light-emitting element to emit light. However, in the related art, the driving method of the pixel circuit is not good, which easily causes some poor display problems and thus affects the display performance. Summary of the invention

[0003] Embodiments of the present invention provide a display panel and a driving method thereof, and a display device, which are used to optimize the driving mode of a pixel circuit and improve display performance.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including a pixel circuit, wherein the pixel circuit includes: Driver module; a first reset module, wherein a control end of the first reset module is electrically connected to a first scan line for providing a first scan signal, a first end of the first reset module is electrically connected to a first reset line, and a second end of the first reset module is electrically connected to a control end of the driving module; a data writing module, wherein a control end of the data writing module is electrically connected to a second scanning line for providing a second scanning signal, a first end of the data writing module is electrically connected to a data line, and a second end of the data writing module is electrically connected to a first end of the driving module; a first light-emitting control module, wherein a control end of the first light-emitting control module is electrically connected to a light-emitting control line for providing a light-emitting control signal, a first end of the first light-emitting control module is electrically connected to a second end of the driving module, and a second end of the first light-emitting control module is electrically connected to a light-emitting element; Among them, the enable levels of the first scanning signal and the second scanning signal are both low levels, the second scanning signal has an enable level within the time covered by a non-enable level in the light-emitting control signal, and the total duration of the enable level in the first scanning signal is greater than the duration of the enable level in the second scanning signal.

[0005] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a method for driving a display panel, wherein the display panel includes a pixel circuit, and the pixel circuit includes: Driver module; a first reset module, wherein a control end of the first reset module is electrically connected to a first scan line for providing a first scan signal, a first end of the first reset module is electrically connected to a first reset line, and a second end of the first reset module is electrically connected to a control end of the driving module; a data writing module, wherein a control end of the data writing module is electrically connected to a second scanning line for providing a second scanning signal, a first end of the data writing module is electrically connected to a data line, and a second end of the data writing module is electrically connected to a first end of the driving module; a first light-emitting control module, wherein a control end of the first light-emitting control module is electrically connected to a light-emitting control line for providing a light-emitting control signal, a first end of the first light-emitting control module is electrically connected to a second end of the driving module, and a second end of the first light-emitting control module is electrically connected to a light-emitting element; Wherein, the enable levels of the first scanning signal and the second scanning signal are both low levels; The driving method includes: controlling the second scanning signal to output an enable level within the time covered by a non-enable level in the light-emitting control signal, and controlling the total duration of the enable level in the first scanning signal to be greater than the duration of the enable level in the second scanning signal.

[0006] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0007] The technical solution provided by the embodiment of the present invention has the following beneficial effects: In an embodiment of the present invention, during the time covered by a single high level of the light-emitting control signal, the total duration of the low level in the first scanning signal is relatively large, and the first reset transistor resets the gate of the driving transistor for a longer time, so that the driving transistor is restored to its initial working state to a greater extent, and its threshold voltage returns to a normal level. Then, when grayscale switching is performed, the driving transistor can quickly be in a normal state to effectively improve the problems of short-term image retention and brightness difference in the first frame. At the same time, during the time covered by a single high level of the light-emitting control signal, the second scanning signal has only one low level, so the driving transistor will only write a voltage once, and the voltage written is the data voltage required by itself. In this way, the node potential of the driving transistor will not be affected by the display signal in the previous circuit row, and the problem of black text bright bars can be avoided.

[0008] In addition, in the embodiment of the present invention, the second scanning signal has a relatively small number of pulses output, and thus the power consumption of the panel can be reduced to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0010] Figure 1 A schematic diagram of a structure of a display panel in the related art; Figure 2 A schematic diagram of a structure of a pixel circuit in the related art; Figure 3 It is a timing diagram in the related art; Figure 4 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention; Figure 5 A schematic diagram of a structure of a pixel circuit provided by an embodiment of the present invention; Figure 6 A timing diagram provided by an embodiment of the present invention; Figure 7 A box plot provided by an embodiment of the present invention; Figure 8 Another box plot provided by an embodiment of the present invention; Fig. 9 Another timing diagram provided by an embodiment of the present invention; Fig.10 A schematic diagram of the structure of a first shift unit provided in an embodiment of the present invention; Fig.11 for Fig.10 A corresponding timing diagram; Fig.12 A schematic diagram of the structure of a second shift unit provided in an embodiment of the present invention; Fig.13 for Fig.12 A corresponding timing diagram; Fig.14 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention; Fig.15 Another timing diagram provided by an embodiment of the present invention; Fig.16 Another timing diagram provided by an embodiment of the present invention; Fig.17 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention; Fig.18 Another timing diagram provided by an embodiment of the present invention; Fig.19 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention; Fig. 20 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention; Fig.21 Another timing diagram provided by an embodiment of the present invention; Fig. 22 Another timing diagram provided by an embodiment of the present invention; Fig.23 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.24 Another timing diagram provided by an embodiment of the present invention; Fig.25 A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention; Fig.26 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0011] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0012] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0014] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0015] Before describing the technical solutions provided by the embodiments of the present invention, the present invention first describes the problems existing in the related art.

[0016] like Figure 1 and Figure 2 As shown, Figure 1 is a structural schematic diagram of a display panel in the related art, Figure 2 It is a structural diagram of a pixel circuit in the related art. The display panel includes a plurality of circuit rows 1' arranged along a first direction x. The circuit row 1' includes a plurality of pixel circuits 2' arranged along a second direction y. The first direction x intersects the second direction y.

[0017] The pixel circuit 2 ′ includes a driving transistor M1 ′, a first reset transistor M2 ′, a data writing transistor M3 ′, a threshold compensation transistor M4 ′ and a first light emission control transistor M5 ′.

[0018] Among them, the gate of the first reset transistor M2' is electrically connected to the first scan line Scan1', the first electrode is electrically connected to the reset line Ref', and the second electrode is electrically connected to the gate of the driving transistor M1'. The gate of the data writing transistor M3' is electrically connected to the second scan line Scan2', the first electrode is electrically connected to the data line Data', and the second electrode is electrically connected to the first electrode of the driving transistor M1'. The gate of the threshold compensation transistor M4' is electrically connected to the second scan line Scan2', the first electrode is electrically connected to the second electrode of the driving transistor M1', and the second electrode is electrically connected to the gate of the driving transistor M1'. The gate of the first light-emitting control transistor M5' is electrically connected to the light-emitting control line Emit', the first electrode is electrically connected to the second electrode of the driving transistor M1', and the second electrode is electrically connected to the light-emitting element D'.

[0019] When the display panel switches grayscale, due to the hysteresis effect of the driving transistor M1', short-term image sticking and the difference between the brightness of the first frame after switching and the brightness of other frames will occur. Figure 3 As shown, Figure 3 This is a timing diagram in the related technology. The related technology proposes that within the time covered by a high level in the light-emitting control signal, both the first scanning signal and the second scanning signal are driven by multiple pulses, for example, the first scanning signal and the second scanning signal are driven by three pulses, so that the driving transistor M1' is reset multiple times and the voltage is written multiple times, so as to achieve the purpose of repeatedly refreshing the node potential of the driving transistor M1'.

[0020] For example, in one configuration, see Figure 1 The display panel further includes a shift register 3', which includes a plurality of shift units 4' arranged in cascade. One shift unit 4' is electrically connected to the second scan line Scan2' corresponding to the previous circuit row 1' and the first scan line Scan1' corresponding to the next circuit row 1'. The shift unit 3' is controlled to output multiple pulses, so as to achieve multi-pulse driving of the first scan signal and the second scan signal.

[0021] Alternatively, in other structures, the display panel may also include at least two groups of shift registers, one group of shift registers is electrically connected to the first scan line Scan1', used to control the first scan line Scan1' to perform multi-pulse driving, and the other group of shift registers is electrically connected to the second scan line Scan2', used to control the second scan line Scan2' to perform multi-pulse driving.

[0022] However, the inventors discovered during the research that, in the process of driving the transistor M1' for multiple voltage writes, during the first few writes, because the data line Data' transmits the data voltage required by the pixel circuit 2' in the previous circuit row 1', the voltages written in the first few times are the data voltages corresponding to the pixel circuit 2' in the previous circuit row 1', and only the last write will write the data voltage that should correspond to the pixel circuit row 1' to which it is located. In this way, the voltage write of this circuit row 1' will be affected by the display signals of other circuit rows 1'.

[0023] For example, when the previous circuit row 1' needs to display a black pattern, and the current circuit row 1' needs to display a white pattern, the data voltage required by the pixel circuit 2' in the previous circuit row 1' will be relatively large, and the data voltage required by the pixel circuit 2' in the current circuit row 1' will be relatively small. For example, the data voltage corresponding to the pixel circuit 2' in the previous circuit row 1' is 7V, and the data voltage corresponding to the pixel circuit 2' in the current circuit row 1' is 3V. Then, when the driving transistor M1' of the pixel circuit 2' in the current circuit row 1' is reset and voltage written for the first few times, the gate-source voltage of the driving transistor M1' will be very large, causing the negative bias of the driving transistor M1' to be more serious, and then when the data voltage required by the current circuit row 1' is written for the last time, the brightness will be too bright due to insufficient voltage writing, causing the display panel to have a poor display problem of black text and bright bars.

[0024] In this regard, an embodiment of the present invention proposes a technical solution. By adopting this technical solution, the problem of short-term afterimage and brightness difference in the first frame can be effectively improved, while the phenomenon of black text bright bars can be avoided.

[0025] An embodiment of the present invention provides a display panel, which may be a display panel of various types such as an organic light emitting diode (OLED), an active matrix organic light emitting diode (AMOLED), or a light emitting diode (LED).

[0026] like Figure 4 and Figure 5 As shown, Figure 4 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 5 This is a structural schematic diagram of a pixel circuit provided in an embodiment of the present invention. The display panel includes a pixel circuit 01 and a light-emitting element 02.

[0027] The pixel circuit 01 includes a driving module 1 , a first resetting module 2 , a data writing module 3 and a first light emitting control module 4 .

[0028] The control end of the first reset module 2 is electrically connected to the first scan line Scan1 for providing the first scan signal, the first end of the first reset module 2 is electrically connected to the first reset line Ref1 , and the second end of the first reset module 2 is electrically connected to the control end of the driving module 1 .

[0029] The control end of the data writing module 3 is electrically connected to the second scanning line Scan2 for providing a second scanning signal, the first end of the data writing module 3 is electrically connected to the data line Data, and the second end of the data writing module 3 is electrically connected to the first end of the driving module 1 .

[0030] The control end of the first light-emitting control module 4 is electrically connected to the light-emitting control line Emit for providing a light-emitting control signal, the first end of the first light-emitting control module 4 is electrically connected to the second end of the driving module 1 , and the second end of the first light-emitting control module 4 is electrically connected to the light-emitting element 02 .

[0031] like Figure 6 As shown, Figure 6 A timing diagram provided by an embodiment of the present invention, wherein the enable levels of the first scanning signal and the second scanning signal are both low level. During the time covered by a non-enable level in the light-emitting control signal, the second scanning signal has an enable level, and the total duration of the enable level in the first scanning signal is greater than the duration of the enable level in the second scanning signal.

[0032] In a more specific structure, the driving module 1 includes a driving transistor M1. The first reset module 2 includes a first reset transistor M2, the gate of the first reset transistor M2 is electrically connected to the first scan line Scan1, the first electrode is electrically connected to the first reset line Ref1, and the second electrode is electrically connected to the gate of the driving transistor M1. The data writing module 3 includes a data writing transistor M3, the first electrode of the data writing transistor M3 is electrically connected to the second scan line Scan2, the first electrode is electrically connected to the data line Data, and the second electrode is electrically connected to the first electrode of the driving transistor M1. The first light emitting control module 4 includes a first light emitting control transistor M4, the gate of the first light emitting control transistor M4 is electrically connected to the light emitting control line Emit, the first electrode is electrically connected to the second electrode of the driving transistor M1, and the second electrode is electrically connected to the light emitting element 02.

[0033] In the embodiment of the present invention, the enable level of the first scanning signal is low level and the disable level is high level, and the enable level of the second scanning signal is low level and the disable level is high level. This means that the first reset transistor M2 and the data write transistor M3 are both P-type transistors, for example, both are low temperature polysilicon (LTPS) transistors with better device stability. The first reset transistor M2 is turned on in response to the low level of the first scanning signal, and the reset voltage is written into the gate of the driving module 1. The data write transistor M3 is turned on in response to the low level of the second scanning signal, and the data voltage is written into the first electrode of the driving module 1.

[0034] In addition, the light emitting control signal may also be a low level for the enable level and a high level for the disable level. At this time, the first light emitting control transistor M4 may also be a LTPS transistor. The first light emitting control transistor M4 is turned on in response to the low level of the light emitting control signal, and transmits the driving current converted by the driving transistor M1 to the light emitting element O2.

[0035] In an embodiment of the present invention, during the time covered by a single high level of the light-emitting control signal, the total duration of the low level in the first scanning signal is greater than the duration of the low level in the second scanning signal, and the first reset transistor M2 can reset the driving transistor M1 for a longer time, thereby improving the reset capability of the driving transistor M1, so that it is restored to its initial working state to a greater extent, and its threshold voltage returns to a normal level. Therefore, when grayscale switching is performed, the driving transistor M1 can quickly be in a normal state, effectively improving the problems of short-term image retention and brightness difference in the first frame. At the same time, during the time covered by a single high level of the light-emitting control signal, the second scanning signal has only a low level, that is, the driving transistor M1 will only write a voltage once, and the data voltage written is the data voltage required by itself. In this way, the node potential of the driving transistor M1 will not be affected by the display signal in the previous circuit row, thereby avoiding the problem of black text bright bars.

[0036] In addition, compared with the related art, the second scanning signal in the embodiment of the present invention has a smaller number of pulses output, and thus can reduce the power consumption of the panel to a certain extent.

[0037] It should be noted that the embodiment of the present invention utilizes two groups of different shift registers to separately drive the first scan line Scan1 and the second scan line Scan2, so as to perform the above-mentioned different designs for the timing of the first scan signal and the second scan signal, thereby achieving the purpose of improving the afterimage, improving the brightness difference of the first frame and preventing the appearance of black text bright bars.

[0038] In a possible implementation, combining Figure 5 and Figure 6, within the time covered by a non-enable level in the light emitting control signal, the first scanning signal has an enable level, and the enable level in the first scanning signal is located before the enable level in the second scanning signal.

[0039] The duration of the enable level in the first scanning signal is t1, the duration of the enable level in the second scanning signal is t2, and t1>t2.

[0040] Based on this driving method, during the time covered by a non-enable level in the light-emitting control signal, both the first scanning signal and the second scanning signal are driven by a single pulse. Among them, the single low level in the first scanning signal has a long duration, and the first scanning signal drives the first reset transistor M2 to be turned on for a long time, and the driving transistor M1 is reset for a long time, so that the driving transistor M1 is restored to the initial working state to a greater extent, and the problem of afterimage and brightness difference in the first frame is effectively improved when grayscale is switched. Moreover, compared with the related art, the number of pulses output by the first scanning signal is also small, which can further reduce the power consumption of the panel, for example, it can be optimized by about 10mW.

[0041] In one possible implementation, t1≥2 t2, thereby significantly extending the duration of the low level in the first scanning signal, ensuring that the driving transistor M1 has sufficient reset time.

[0042] During display, the circuit row 5 is scanned line by line. The scanning time of a single circuit row 5 can be defined as the line time H, .

[0043] Wherein, n is the number of rows of pixel circuits 01 in the display panel. In other words, combined with Figure 4 The display panel includes a plurality of circuit rows 5 arranged along a first direction x, the circuit rows 5 include a plurality of pixel circuits 01 arranged along a second direction y, the first direction x intersects the second direction y, and n is the number of the circuit rows 5.

[0044] f is the basic frequency or the current driving frequency of the display panel.

[0045] Regarding the value of f, in one case, the display panel has a base frequency, and other lower frequency drives are all achieved by downconverting the base frequency. For example, the base frequency is 120Hz, and one frame is 8.33ms. When the display panel needs to be driven at 60Hz, a data refresh cycle at 60Hz includes two frames, one of which is a write frame and the other is a hold frame. When the display panel needs to be driven at 30Hz, a data refresh cycle at 30Hz includes four frames, one of which is a write frame and the other three are hold frames. In this case, the scanning time of circuit row 5 is one frame corresponding to the base frequency divided by the number of circuit rows 5. Therefore, the value of f in the formula is the base frequency.

[0046] In another case, the lower frequency drive is not achieved by frequency reduction, but only by increasing the scanning time of circuit row 5 to lengthen the duration of the data refresh cycle corresponding to the lower frequency. For example, when the display panel needs to be driven at 60Hz, a data refresh cycle at 60Hz is a frame, and a frame is 16.67ms. When the display panel needs to be driven at 30Hz, a data refresh cycle at 30Hz is a frame, and a frame is 33.33ms. In this case, the scanning time of circuit row 5 is a frame corresponding to the current driving frequency divided by the number of circuit rows 5. Therefore, the value of f in the formula is the current driving frequency of the display panel.

[0047] In the embodiment of the present invention, t2 may be equal to 1H, and accordingly, t1≥2H.

[0048] Furthermore, t1≤20 As mentioned above, when t2=1H, t1 satisfies: 2H≤t1≤20H. For example, t1 can be equal to 2H, 4H, 8H or 12H, etc.

[0049] Under the premise that the short-term afterimage and the brightness difference of the first frame can be improved, t1 should not be designed to be too large. If t1 is too large, the light-emitting control signal needs to further increase its high-level duration to ensure that it can completely cover the low level of the first scanning signal and the low level of the second scanning signal, but this will reduce the light-emitting time. The length of the light-emitting time will affect the human eye's perception of brightness changes. If the light-emitting time is too short and the brightness changes rapidly, the human eye may be more likely to notice flicker. For this reason, in order to ensure a better stroboscopic effect visibility measure (SVM), t1 can be designed to be less than or equal to 20 t2.

[0050] In this regard, the embodiment of the present invention also conducted tests: like Figure 7 As shown, Figure 7A box plot is provided by an embodiment of the present invention, wherein: Figure 7 The vertical axis "JNCD" in the figure represents the minimum noticeable color difference, which can be used to reflect the short-term afterimage ability. The larger the value, the more obvious the short-term afterimage. Figure 7 [T0] in the horizontal axis refers to the instantaneous afterimage capability of black-to-white switching, [T10] refers to the afterimage capability after 10s of black-to-white switching, "3pulse-POR" means that in the related technology, within the time covered by a high level in the light-emitting control signal, the first scanning signal outputs three low levels, and the duration of a single low level is 1H, and "1 pulse-4H" means that in an embodiment of the present invention, within the time covered by a high level in the light-emitting control signal, the first scanning signal outputs a low level, and the duration of the low level is 4H.

[0051] according to Figure 7 It can be seen that compared with the related art, based on the design of the first scanning signal in the embodiment of the present invention, the JNCD value is significantly reduced, and the short-term image sticking is significantly improved. For example, compared with "3 pulse-POR [T0]", the JNCD corresponding to "1 pulse-4H [T0]" is reduced from 5.19 to 4.09. like Figure 8 As shown, Figure 8 Another box plot provided by an embodiment of the present invention, wherein: Figure 8 The percentage indicated by the vertical axis is the percentage of the actual brightness of the first frame to the target brightness. The larger the value, the closer the actual brightness of the first frame is to the target brightness, and the smaller the brightness difference between the first frame and other frames is. The horizontal axis is t1, that is, in the embodiment of the present invention, the first scanning signal outputs a low level during the time covered by a high level in the light control signal, and the horizontal axis is the duration of the low level in the first scanning signal.

[0052] according to Figure 8 It can be seen that when t1 increases to more than 2H, the actual brightness of the first frame is significantly improved, and it is closer to the target brightness.

[0053] In one possible implementation, see Figure 6 The moment when the light-emitting control signal jumps from the enable level to the non-enable level is the first moment p1, the moment when the first scanning signal jumps from the non-enable level to the enable level is the second moment p2, and the interval between the first moment p1 and the second moment p2 is ΔT1, 0<ΔT1≤1H.

[0054] The moment when the first scanning signal jumps from the enable level to the disable level is the third moment p3, the moment when the second scanning signal jumps from the disable level to the enable level is the fourth moment p4, and the interval between the third moment p3 and the fourth moment p4 is ΔT2, 0<ΔT2≤1H.

[0055] , n is the number of rows of pixel circuits 01 in the display panel, and f is the basic frequency or the current driving frequency of the display panel. The definition of the row time H has been described in detail in the above embodiments and will not be repeated here.

[0056] When ΔT1 and ΔT2 meet the above definition, the interval between the low edge of the first scanning signal and the high edge of the light-emitting control signal is at most 1H, and the interval between the two is relatively short. At the same time, the interval between the high edge of the first scanning signal and the low edge of the second scanning signal is also at most 1H, and the interval between the two is also relatively short. Then, under the condition that the high level duration of the light-emitting control signal is certain, the duration of the low level in the first scanning signal can be further extended to increase the reset time.

[0057] In a possible implementation, Fig. 9 As shown, Fig. 9 Another timing diagram provided by an embodiment of the present invention, within the time covered by a non-enable level in the light-emitting control signal, the first scanning signal has at least two enable levels, and the enable level in the first scanning signal is located before the enable level in the second scanning signal.

[0058] In this driving mode, the first scanning signal performs multi-pulse driving, and the driving transistor M1 is reset multiple times before writing data, which can also increase the total reset time of the driving transistor M1, effectively improving the problem of residual image and brightness difference in the first frame. Moreover, this first scanning signal can still be driven by the shift register corresponding to the first scanning signal in the related art, without matching an additional shift register for the first scanning signal, and the panel design adjustment is relatively small.

[0059] In one possible implementation, see Figure 4 The display panel further includes a first shift register 6, which includes a plurality of first shift units 7 arranged in cascade, and the first shift unit 7 is electrically connected to the first scan line Scan1 for outputting a first scan signal to the first scan line Scan1 connected thereto.

[0060] The display panel further includes a second shift register 8, which includes a plurality of second shift units 9 arranged in cascade. The second shift unit 9 is electrically connected to the second scan line Scan2 and is used to output a second scan signal to the second scan line Scan2 connected thereto.

[0061] The display panel further includes a third shift register 10. The third shift register 10 includes a plurality of third shift units 11 arranged in cascade. The third shift unit 11 is electrically connected to the light emitting control line Emit and is used to output a light emitting control signal to the light emitting control line Emit connected thereto.

[0062] The embodiment of the present invention configures a separate shift register for driving the first scan line Scan1 and the second scan line Scan2, and can design the timing of the first scan signal and the second scan signal differently. For example, the number of pulses of the first scan signal or the low-level duration of a single pulse can be adjusted more flexibly and separately, so as to better balance the improvement of afterimage, the improvement of the brightness difference of the first frame and the prevention of the appearance of black text bright bars.

[0063] The first shift unit 7 , the second shift unit 9 and the third shift unit 11 may adopt different circuit structures, so as to output signals with different waveforms as the first scanning signal, the second scanning signal and the light emitting control signal respectively.

[0064] The following is a circuit structure of the first shift unit 7 and the second shift unit 9 respectively illustrated in the embodiments of the present invention.

[0065] In a circuit structure that the first shift unit 7 can adopt, as Fig.10 and Fig.11 As shown, Fig.10 A schematic diagram of the structure of the first shift unit 7 provided in an embodiment of the present invention, Fig.11 for Fig.10 Corresponding to a timing diagram, the first shift unit 7 includes: The first transistor T1 has a gate electrically connected to the first clock line CK1, a first electrode electrically connected to the output terminal Out1_i-1 of the previous-stage first shift unit 7, and a second electrode electrically connected to the first node N1.

[0066] The second transistor T2 has a gate electrically connected to the first clock line CK1 , a first electrode electrically connected to the low potential signal line VGL, and a second electrode electrically connected to the second node N2 .

[0067] The third transistor T3 has a gate electrically connected to the first node N1, a first electrode electrically connected to the first clock line CK1, and a second electrode electrically connected to the second node N2.

[0068] The fourth transistor T4 has a gate electrically connected to the low potential signal line VGL, and a first electrode electrically connected to the second node N2.

[0069] The fifth transistor T5 has a gate electrically connected to the second electrode of the fourth transistor T4 and a first electrode electrically connected to the second clock line CK2.

[0070] The sixth transistor T6 has a gate electrically connected to the second clock line CK2 , a first electrode electrically connected to the second electrode of the fifth transistor T5 , and a second electrode electrically connected to the third node N3 .

[0071] The seventh transistor T7 has a gate electrically connected to the first node N1 , a first electrode electrically connected to the high potential signal line VGH, and a second electrode electrically connected to the third node N3 .

[0072] The eighth transistor T8 has a gate electrically connected to the second node N2 and a first electrode electrically connected to the high potential signal line VGH.

[0073] The ninth transistor T9 has a gate electrically connected to the low potential signal line VGL, a first electrode electrically connected to the first node N1, and a second electrode electrically connected to the fourth node N4.

[0074] The tenth transistor T10 has a gate electrically connected to the fourth node N4, a first electrode electrically connected to the second clock line CK2, and a second electrode electrically connected to the second electrode of the eighth transistor T8.

[0075] The eleventh transistor T11 has a gate electrically connected to the control line Reset, a first electrode electrically connected to the high potential signal line VGH, and a second electrode electrically connected to the first node N1.

[0076] The twelfth transistor T12 has a gate electrically connected to the third node N3 , a first electrode electrically connected to the high potential signal line VGH, and a second electrode electrically connected to the output terminal Out1_i.

[0077] The thirteenth transistor T13 has a gate electrically connected to the fourth node N4, a first electrode electrically connected to the low potential signal line VGL, and a second electrode electrically connected to the output terminal Out1_i.

[0078] The first capacitor C1 has a first electrode plate electrically connected to the gate of the fifth transistor T5 and a second electrode plate electrically connected to the second electrode of the fifth transistor T5.

[0079] The second capacitor C2 has a first electrode plate electrically connected to the second electrode of the tenth transistor T10 and a second electrode plate electrically connected to the fourth node N4.

[0080] The third capacitor C3 has a first plate electrically connected to the third node N3 and a second plate electrically connected to the high potential signal line VGH.

[0081] It should be noted that Fig.10 This is only an example of a structure of the first shift unit 7. In other optional implementations of the present invention, first shift units 7 with other structures may also be used to output the signal waveform required by the first scan line Scan1.

[0082] In a circuit structure that the second shift unit 9 can adopt, Fig.12 and Fig.13 As shown, Fig.12 A schematic diagram of the structure of the second shift unit 9 provided in an embodiment of the present invention, Fig.13 for Fig.12 Corresponding to a timing diagram, the second shift unit 9 includes: The fourteenth transistor T14 has a gate electrically connected to the third clock line CK3 and a first electrode electrically connected to the output terminal Out2_i-1 of the second shift unit 9 of the previous stage.

[0083] The fifteenth transistor T15 has a gate electrically connected to the third clock line CK3 , a first electrode electrically connected to the second electrode of the fourteenth transistor T14 , and a second electrode electrically connected to the fifth node N5 .

[0084] The sixteenth transistor T16 has a gate electrically connected to the fifth node N5, a first electrode electrically connected to the third clock line CK3, and a second electrode electrically connected to the sixth node N6.

[0085] The seventeenth transistor T17 has a gate electrically connected to the third clock line CK3 , a first electrode electrically connected to the low potential signal line VGL, and a second electrode electrically connected to the sixth node N6 .

[0086] The eighteenth transistor T18 has a gate electrically connected to the sixth node N6 and a first electrode electrically connected to the high potential signal line VGH.

[0087] The nineteenth transistor T19 has a gate electrically connected to the fourth clock line CK4, a first electrode electrically connected to the second electrode of the eighteenth transistor T18, and a second electrode electrically connected to the fifth node N5.

[0088] The twentieth transistor T20 has a gate electrically connected to the low potential signal line VGL, a first electrode electrically connected to the fifth node N5, and a second electrode electrically connected to the seventh node N7.

[0089] The twenty-first transistor T21 has a gate electrically connected to the seventh node N7, a first electrode electrically connected to the fourth clock line CK4, and a second electrode electrically connected to the output terminal Out_i.

[0090] The twenty-second transistor T22 has a gate electrically connected to the sixth node N6 , a first electrode electrically connected to the high potential signal line VGH, and a second electrode electrically connected to the output terminal Out_i.

[0091] The fourth capacitor C4 has a first electrode plate electrically connected to the seventh node N7 and a second electrode plate electrically connected to the output terminal Out_i.

[0092] A fifth capacitor C5 , wherein a first plate of the fifth capacitor C5 is electrically connected to the sixth node N6 , and a second plate of the fifth capacitor C5 is electrically connected to the high potential signal line VGH.

[0093] It should be noted that Fig.12 This is only an example of a structure of the second shift unit 9. In other optional implementations of the present invention, second shift units 9 with other structures may also be used to output the signal waveform required by the second scan line Scan2.

[0094] In a possible implementation, Fig.14 and Fig.15 As shown, Fig.14 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Fig.15 In another timing diagram provided by an embodiment of the present invention, the display panel further includes a plurality of circuit rows 5 arranged along a first direction x, the circuit row 5 includes a plurality of pixel circuits 01 arranged along a second direction y, and the first direction x intersects the second direction y.

[0095] A first shift unit 7 is electrically connected to the first scan lines Scan1 corresponding to the m circuit rows 5 , and a third shift unit 11 is electrically connected to the light emitting control lines Emit corresponding to the m circuit rows 5 , where m≥2.

[0096] in, Fig.14 and Fig.15 The illustration is made by taking m=2 as an example. Fig.15 Emit_x~Emit_x+1 in the figure represent the light-emitting control signals corresponding to the x-th circuit row 5 and the x+1-th circuit row 5, Scan1_x~Scan1_x+1 represent the first scanning signals corresponding to the x-th circuit row 5 and the x+1-th circuit row 5, Scan2_x represents the second scanning signal corresponding to the x-th circuit row 5, and Scan2_x+1 represents the second scanning signal corresponding to the x+1-th circuit row 5.

[0097] In this structure, a first shift unit 7 is used to output a first scanning signal to m circuit rows 5, and a third shift unit 11 is used to output a light-emitting control signal to m circuit rows 5. This arrangement can reduce the number of shift units required to be set in the first shift register 6 and the third shift register 10, which is more conducive to realizing a narrow frame design, and can reduce the number of pulses output by the first shift register 6 and the third shift register 10, thereby reducing power consumption.

[0098] In addition, when one third shift unit 11 is electrically connected to the light emitting control lines Emit corresponding to m circuit rows 5, if one first shift unit 7 is electrically connected to only one first scanning line Scan1 corresponding to one circuit row 5, Fig.16 As shown, Fig.16 In another timing diagram provided by an embodiment of the present invention, a high level in the light-emitting control signal needs to cover the low levels of the m first scanning signals corresponding to the m circuit rows 5. Then, when the high level duration in the light-emitting control signal is constant, the low level duration of the first scanning signal corresponding to a single circuit row 5 will be relatively short. In the embodiment of the present invention, a first shift unit 7 is also electrically connected to the first scanning line Scan1 corresponding to the m circuit rows 5, and the m circuit rows 5 share a first scanning signal, so the time of a single low level in the first scanning signal can be extended, thereby increasing the reset time.

[0099] Furthermore, considering that too large a value of m may affect the load and voltage drop of the signal, in the embodiment of the present invention, m may be designed to be equal to 2.

[0100] In addition, in the embodiments of the present invention, see Fig.14 , one second shift unit 9 can be electrically connected to only one second scan line Scan2 corresponding to one circuit row 5, so that the pixel circuits 01 in each circuit row 5 can accurately receive the data voltage required by themselves, thereby ensuring display accuracy.

[0101] In one possible implementation, see Fig.14 The display panel includes two second shift registers 8, and the two second shift registers 8 are electrically connected to the second scan line Scan2 on both sides of the second scan line Scan2.

[0102] The second scan line Scan2 is used to control the data writing transistor M3 to write the data voltage, and the data voltage determines the magnitude of the driving current, so the driving force stability requirement of the second scan line Scan2 is higher. In this regard, the embodiment of the present invention uses two sets of second shift registers 8 to perform bilateral driving on the second scan line Scan2 to improve the writing stability and accuracy of the second scan signal.

[0103] In one possible implementation, see Fig.14 The display panel also includes a display area 12.

[0104] The display panel includes two second shift registers 8 , wherein the first shift register 6 and one of the second shift registers 8 are located on one side of the display area 12 , and the third shift register 10 and the other second shift register 8 are located on the other side of the display area 12 .

[0105] In this configuration, two of the four shift registers are located on one side of the display area 12, and the other two are located on the other side of the display area 12. The distribution of the shift registers is more reasonable, which helps to optimize the left and right frame design of the display panel.

[0106] In other optional embodiments of the present invention, the shift register may also adopt other designs. For example, in a display panel with a lower requirement for the frame width, such as a display panel of a vehicle-mounted display screen, a first shift unit 7 may be electrically connected to a first scan line Scan1 corresponding to a circuit row 5, a second shift unit 9 may be electrically connected to a second scan line Scan2 corresponding to a circuit row 5, and a third shift unit 11 may be electrically connected to a light-emitting control line Emit corresponding to a circuit row 5. Further, the display panel may include two groups of first shift registers 6, two groups of second shift registers 8, and two groups of third shift registers 10, the two groups of first shift registers 6 are respectively connected to the first scan line Scan1 on both sides of the first scan line Scan1, the two groups of second shift registers 8 are respectively connected to the second scan line Scan2 on both sides of the second scan line Scan2, and the two groups of third shift registers 10 are respectively connected to the light-emitting control line Emit on both sides of the light-emitting control line Emit.

[0107] See also Figure 5 The pixel circuit 01 further includes a threshold compensation module 13, a first end of the threshold compensation module 13 is electrically connected to the second end of the driving module 1, and a second end of the threshold compensation module 13 is electrically connected to the control end of the driving module 1. More specifically, the threshold compensation module 13 includes a threshold compensation transistor M5, a first electrode of the threshold compensation transistor M5 is electrically connected to the second electrode of the driving transistor M1, and a second electrode is electrically connected to the gate of the driving transistor M1.

[0108] In one structure, combined Figure 4 and Figure 5 , the control end of the threshold compensation module 13 is electrically connected to the second scan line Scan2, that is, the gate of the threshold compensation transistor M5 is electrically connected to the second scan line Scan2. At this time, the threshold compensation transistor M5 can be a transistor of the same type as the first reset transistor M2 and the data writing transistor M3, for example, an LTPS transistor. The threshold compensation transistor M5 is turned on in response to the low level of the second scan signal, and the data voltage written by the second electrode of the driving transistor M1 is further written into the gate of the driving transistor M1. This structure does not need to configure an additional scan line for the threshold compensation module 13, simplifying the structural design.

[0109] Or, in another structure, such as Fig.17 and Fig.18 As shown, Fig.17 Another structural schematic diagram of the pixel circuit 01 provided in an embodiment of the present invention is shown in FIG. Fig.18 Another timing diagram provided by an embodiment of the present invention, the control end of the threshold compensation module 13 is electrically connected to the fourth scan line Scan4 for providing the fourth scan signal, that is, the gate of the threshold compensation transistor M5 is electrically connected to the fourth scan line Scan4. The enable level of the fourth scan signal is a high level, and the non-enable level is a low level. In addition, the time covered by the high level in the fourth scan signal overlaps the time covered by the low level in the second scan signal. The threshold compensation transistor M5 is turned on in response to the high level of the fourth scan signal, and the data voltage written by the second electrode of the driving transistor M1 is further written into the gate of the driving transistor M1. At this time, the threshold compensation transistor M5 is an N-type transistor. For example, in order to reduce the influence of the off-state leakage current of the threshold compensation transistor M5 on the gate potential of the driving transistor M1, the threshold compensation transistor M5 can be an indium gallium zinc oxide (IGZO) transistor.

[0110] In one possible implementation, see Figure 5 The display panel further includes a second reset module 14, a first end of the second reset module 14 is electrically connected to the second reset line Ref2, and a second end of the second reset module 14 is electrically connected to the light emitting element 02, wherein the first reset line Ref1 and the second reset line Ref2 provide different reset voltages.

[0111] More specifically, the second reset module 14 includes a second reset transistor M6, a first electrode of which is electrically connected to the second reset line Ref2, and a second electrode of which is electrically connected to the light emitting element 02. When the second reset transistor M6 is turned on, the second reset voltage is written into the light emitting element 02 to reset the anode of the light emitting element 02.

[0112] Using different reset voltages to reset the driving transistor M1 and the light emitting element 02 can make the driving more flexible. For example, the second reset voltage can be designed to be lower to avoid the problem of sub-pixel stealing light to a greater extent.

[0113] Or, in another feasible implementation, as Fig.19 As shown, Fig.19 This is another structural diagram of the pixel circuit 01 provided in an embodiment of the present invention. The first end of the second reset module 14 can also be electrically connected to the first reset line Ref1, so that only one reset line is configured for the first reset module 2 and the second reset module 14, simplifying the structural design.

[0114] In one possible implementation, see Figure 5 and Figure 6The display panel further includes a second reset module 14 , a control end of the second reset module 14 receives a scan signal, a first end of the second reset module 14 receives a reset voltage, and a second end of the second reset module 14 is electrically connected to the light emitting element 02 .

[0115] Among them, within the time covered by a non-enable level in the light-emitting control signal, the total duration of the enable level in the scanning signal received by the second reset module 14 is greater than the duration of the enable level in the second scanning signal, thereby increasing the reset time of the light-emitting element 02 and resetting the anode potential of the light-emitting element 02 more thoroughly. Before emitting light, the anode voltages of the light-emitting elements 02 in different sub-pixels will be set to a consistent initial state, which helps to improve display uniformity.

[0116] In one possible implementation, see Figure 5 and Figure 6 The control end of the second reset module 14 is electrically connected to the first scan line Scan1, and the first scan signal is used to drive the second reset module 14 to increase the reset time of the light emitting element 02, without configuring an additional scan line for the second reset module 14.

[0117] Or, in another feasible implementation, as Fig. 20 As shown, Fig. 20 This is another structural diagram of the pixel circuit 01 provided in an embodiment of the present invention, in which the control end of the second reset module 14 is electrically connected to the third scan line Scan3 for providing a third scan signal.

[0118] The second reset module 14 is driven by a separate third scan line Scan3, and the reset time of the light emitting element 02 can be designed separately. Fig.21 As shown, Fig.21 In another timing diagram provided by an embodiment of the present invention, the waveform of the third scanning signal may be consistent with the waveform of the first scanning signal, or, as Fig. 22 As shown, Fig. 22Another timing diagram provided by an embodiment of the present invention, the waveform of the third scanning signal and the waveform of the first scanning signal may also be inconsistent. For example, during the operation of the pixel circuit 01, the on-time of the first reset transistor M2 and the on-time of the data writing transistor M3 and the threshold compensation transistor M5 need to be staggered, otherwise it will cause the gate potential of the driving transistor M1 to be disordered, therefore, the low level of the first scanning signal and the low level of the second scanning signal cannot overlap. However, the on-time of the second reset transistor M6 can overlap with the on-time of the data writing transistor M3 and the threshold compensation transistor M5. For this reason, when the second reset transistor M6 is connected to the third scanning line Scan3, the duration of the low level in the third scanning signal can be designed to be larger, and the low level in the third scanning signal can overlap with the low level in the first scanning signal and the low level in the second scanning signal, so that the reset time of the light-emitting element 02 is greater.

[0119] Furthermore, if Fig.23 and Fig.24 As shown, Fig.23 A schematic diagram of another structure of a display panel provided in an embodiment of the present invention is shown in FIG. Fig.24 Another timing diagram provided by an embodiment of the present invention, the display panel further includes a plurality of circuit rows 5 arranged along a first direction x, the circuit row 5 includes a plurality of pixel circuits 01 arranged along a second direction y, and the first direction x intersects the second direction y.

[0120] The display panel further includes a first shift register 6 , which includes a plurality of first shift units 7 arranged in cascade, and an output end of the first shift unit 7 is electrically connected to a first scan line Scan1 corresponding to at least one circuit row 5 .

[0121] The display panel further includes a fourth shift register 15 , which includes a plurality of fourth shift units 16 arranged in cascade, and an output terminal Out3 of the fourth shift unit 16 is electrically connected to a third scan line Scan3 corresponding to at least one circuit row 5 .

[0122] For the first shift unit 7 and the fourth shift unit 16 corresponding to the same circuit row 5 , the output terminal Out1 of the first shift unit 7 is also electrically connected to the shift control terminal Next of the fourth shift unit 16 .

[0123] In this driving mode, the third scan line Scan3 is driven by a separate fourth shift register 15, and the signals output by different shift registers only need to be transmitted to one scan line, so the voltage drop of the scan signal is small.

[0124] Generally, among the multiple shift units cascaded in the shift register, the signal outputted by the output terminal of the previous shift unit will also be used as the shift control signal of the shift control terminal of the next shift unit, so that the multiple shift units can sequentially output the enable level. In order to drive the first shift unit to work normally, the shift control terminal of the first shift unit needs to be electrically connected to a frame start signal line. After the frame start signal line outputs the signal, the first shift unit will start to output the signal under the action of the frame start signal, the clock signal, etc. The signal outputted by the first shift unit is used as the shift signal of the second shift unit, driving the second shift unit to work, so that the second shift unit sequentially outputs the signal, and then the third, fourth, ..., until the last shift unit sequentially outputs the signal.

[0125] In the above structure, the shift control signal of the fourth shift unit 16 is not provided by the output terminal Out3 of the fourth shift unit 16 of the previous level, but is provided by the output terminal Out1 of the first shift unit 7. With this arrangement, only the signal output by the first first shift unit 7 is needed as the frame start signal of the first fourth shift unit 16, and there is no need to configure an additional frame start signal line for the fourth shift register 15, thereby saving the number of wiring.

[0126] In other optional embodiments of the present invention, the control end of the second resetting module 14 may also be electrically connected to the second scanning line Scan2.

[0127] In the embodiments of the present invention, see Figure 5 The pixel circuit 01 also includes a second light-emitting control module 17, a control end of the second light-emitting control module 17 is electrically connected to the light-emitting control line Emit, a first end of the second light-emitting control module 17 is electrically connected to the power line PVDD, and a second end of the second light-emitting control module 17 is electrically connected to the first end of the driving module 1.

[0128] More specifically, the second light emitting control module 17 includes a second light emitting control transistor M7 , a gate of which is electrically connected to the light emitting control line Emit, a first electrode of which is electrically connected to the power line PVDD, and a second electrode of which is electrically connected to the first electrode of the driving transistor M1 .

[0129] The pixel circuit 01 further includes a storage capacitor Cst. A first plate of the storage capacitor Cst is electrically connected to the power line PVDD, and a second plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor M1.

[0130] In the embodiment of the present invention, in order to reduce the influence of the off-state leakage current of the first reset transistor M2 and the threshold compensation transistor M5 on the gate potential of the driving transistor M1, as shown in FIG. Fig.25 As shown, Fig.25Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention, the first reset transistor M2 includes a first sub-transistor M21 and a second sub-transistor M22, the gate of the first sub-transistor M21 and the gate of the second sub-transistor M22 are both electrically connected to the first scan line Scan1, the first electrode of the first sub-transistor M21 is electrically connected to the first reset line Ref1, the second electrode of the first sub-transistor M21 is electrically connected to the first electrode of the second sub-transistor M22, and the second electrode of the second sub-transistor M22 is electrically connected to the gate of the driving transistor M1. The threshold compensation transistor M5 includes a third sub-transistor M51 and a fourth sub-transistor M52, the gates of the third sub-transistor M51 and the fourth sub-transistor M52 are both electrically connected to the second scan line Scan2, the first electrode of the third sub-transistor M51 is electrically connected to the second electrode of the driving transistor M1, the second electrode of the third sub-transistor M51 is electrically connected to the first electrode of the fourth transistor, and the second electrode of the fourth sub-transistor M52 is electrically connected to the gate of the driving transistor M1.

[0131] Based on the same inventive concept, an embodiment of the present invention further provides a method for driving a display panel, Figure 4~Figure 6 The display panel includes a pixel circuit 01. The pixel circuit 01 includes a driving module 1, a first resetting module 2, a data writing module 3 and a first light emitting control module 4.

[0132] The control end of the first reset module 2 is electrically connected to the first scan line Scan1 for providing the first scan signal, the first end of the first reset module 2 is electrically connected to the first reset line Ref1 , and the second end of the first reset module 2 is electrically connected to the control end of the driving module 1 .

[0133] The control end of the data writing module 3 is electrically connected to the second scanning line Scan2 for providing a second scanning signal, the first end of the data writing module 3 is electrically connected to the data line Data, and the second end of the data writing module 3 is electrically connected to the first end of the driving module 1 .

[0134] The control end of the first light-emitting control module 4 is electrically connected to the light-emitting control line Emit for providing a light-emitting control signal, the first end of the first light-emitting control module 4 is electrically connected to the second end of the driving module 1 , and the second end of the first light-emitting control module 4 is electrically connected to the light-emitting element 02 .

[0135] The enable levels of the first scanning signal and the second scanning signal are both low level.

[0136] The driving method includes: controlling the second scanning signal to output an enable level within the time covered by a non-enable level in the light-emitting control signal, and controlling the total duration of the enable level in the first scanning signal to be greater than the duration of the enable level in the second scanning signal.

[0137] In an embodiment of the present invention, during the time covered by a single high level of the light-emitting control signal, the total duration of the low level in the first scanning signal is greater than the duration of the low level in the second scanning signal, and the first reset transistor M2 can reset the driving transistor M1 for a longer time, thereby improving the reset capability of the driving transistor M1, so that it is restored to its initial working state to a greater extent, and its threshold voltage returns to a normal level. Therefore, when grayscale switching is performed, the driving transistor M1 can quickly be in a normal state, effectively improving the problems of short-term image retention and brightness difference in the first frame. At the same time, during the time covered by a single high level of the light-emitting control signal, the second scanning signal has only a low level, that is, the driving transistor M1 will only write a voltage once, and the data voltage written is the data voltage required by itself. In this way, the node potential of the driving transistor M1 will not be affected by the display signal in the previous circuit row, thereby avoiding the problem of black text bright bars.

[0138] In addition, compared with the related art, the second scanning signal in the embodiment of the present invention has a smaller number of pulses output, and thus can reduce the power consumption of the panel to a certain extent.

[0139] In a possible implementation, combining Figure 5 and Figure 6 , within the time covered by a non-enable level in the light-emitting control signal, the first scanning signal is controlled to output an enable level, and the enable level in the first scanning signal is located before the enable level in the second scanning signal.

[0140] The duration of the enable level in the first scanning signal is t1, the duration of the enable level in the second scanning signal is t2, and t1>t2.

[0141] Based on this driving method, during the time covered by a non-enable level in the light-emitting control signal, both the first scanning signal and the second scanning signal are driven by a single pulse. Among them, the single low level in the first scanning signal has a long duration, and the first scanning signal drives the first reset transistor M2 to be turned on for a long time, and the driving transistor M1 is reset for a long time, so that the driving transistor M1 is restored to the initial working state to a greater extent, and the problem of afterimage and brightness difference in the first frame is effectively improved when grayscale is switched. Moreover, compared with the related art, the number of pulses output by the first scanning signal is also small, which can further reduce the power consumption of the panel.

[0142] Furthermore, 2 t2≤t1≤20 t2.

[0143] Combined with the above analysis, the minimum value of t1 is set to 2 t2 can ensure that the driving transistor M1 has sufficient reset time. The maximum value of t1 is further set to 20 t2 can ensure a better SVM and prevent the human eye from recognizing flicker.

[0144] In one possible implementation, see Figure 6 The moment when the light-emitting control signal jumps from the enable level to the non-enable level is the first moment p1, the moment when the first scanning signal jumps from the non-enable level to the enable level is the second moment p2, and the interval between the first moment p1 and the second moment p2 is ΔT1, 0<ΔT1≤1H.

[0145] The moment when the first scanning signal jumps from the enable level to the disable level is the third moment p3, the moment when the second scanning signal jumps from the disable level to the enable level is the fourth moment p4, and the interval between the third moment p3 and the fourth moment p4 is ΔT2, 0<ΔT2≤1H.

[0146] , n is the number of rows of the pixel circuit 01, and f is the basic frequency or the frequency at which the display panel is currently driven.

[0147] When ΔT1 and ΔT2 meet the above definition, the interval between the low edge of the first scanning signal and the high edge of the light-emitting control signal is at most 1H, and the interval between the two is relatively short. At the same time, the interval between the high edge of the first scanning signal and the low edge of the second scanning signal is also at most 1H, and the interval between the two is also relatively short. Then, under the condition that the high level duration of the light-emitting control signal is certain, the duration of the low level in the first scanning signal can be further extended to increase the reset time.

[0148] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.26 As shown, Fig.26 1 is a schematic diagram of a structure of a display device provided by an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. Of course, Fig.26 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0149] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: A pixel circuit is included, wherein the pixel circuit includes: Driver module; a first reset module, wherein a control end of the first reset module is electrically connected to a first scan line for providing a first scan signal, a first end of the first reset module is electrically connected to a first reset line, and a second end of the first reset module is electrically connected to a control end of the driving module; a data writing module, wherein a control end of the data writing module is electrically connected to a second scanning line for providing a second scanning signal, a first end of the data writing module is electrically connected to a data line, and a second end of the data writing module is electrically connected to a first end of the driving module; a first light-emitting control module, wherein a control end of the first light-emitting control module is electrically connected to a light-emitting control line for providing a light-emitting control signal, a first end of the first light-emitting control module is electrically connected to a second end of the driving module, and a second end of the first light-emitting control module is electrically connected to a light-emitting element; Among them, the enable levels of the first scanning signal and the second scanning signal are both low levels, the second scanning signal has an enable level within the time covered by a non-enable level in the light-emitting control signal, and the total duration of the enable level in the first scanning signal is greater than the duration of the enable level in the second scanning signal.

2. The display panel according to claim 1, characterized in that: During a time period covered by a non-enable level in the light emitting control signal, the first scanning signal has an enable level, and the enable level in the first scanning signal is before the enable level in the second scanning signal; The duration of the enable level in the first scanning signal is t1, the duration of the enable level in the second scanning signal is t2, and t1>t2.

3. The display panel according to claim 2, characterized in that: t1≥2 t2.

4. The display panel according to claim 3, characterized in that: t1≤20 t2.

5. The display panel according to claim 2, characterized in that: The moment when the light emitting control signal changes from the enable level to the disable level is the first moment, the moment when the first scanning signal changes from the disable level to the enable level is the second moment, and the interval between the first moment and the second moment is ΔT1, 0<ΔT1≤1H; The moment when the first scanning signal jumps from the enable level to the disable level is the third moment, the moment when the second scanning signal jumps from the disable level to the enable level is the fourth moment, and the interval between the third moment and the fourth moment is ΔT2, 0<ΔT2≤1H; in, , n is the number of rows of the pixel circuits in the display panel, and f is the basic frequency or the current driving frequency of the display panel.

6. The display panel according to claim 1, characterized in that: During a time period covered by a non-enable level in the light emitting control signal, the first scanning signal has at least two enable levels, and the enable level in the first scanning signal is located before the enable level in the second scanning signal.

7. The display panel according to claim 1, characterized in that: The display panel further includes: A first shift register, comprising a plurality of first shift units arranged in cascade, wherein the first shift units are electrically connected to the first scan lines; A second shift register, comprising a plurality of second shift units arranged in cascade, wherein the second shift units are electrically connected to the second scan lines; The third shift register includes a plurality of third shift units arranged in cascade connection, and the third shift units are electrically connected to the light emitting control line.

8. The display panel according to claim 7, characterized in that: The display panel further includes a plurality of circuit rows arranged along a first direction, the circuit rows including a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction; Among them, one of the first shift units is electrically connected to the first scan lines corresponding to m of the circuit rows, and one of the third shift units is electrically connected to the light emitting control lines corresponding to m of the circuit rows, and m≥2.

9. The display panel according to claim 7, characterized in that: The display panel includes two second shift registers, and the two second shift registers are electrically connected to the second scan line at two sides of the second scan line respectively.

10. The display panel according to claim 7, characterized in that: The display panel also includes a display area; The display panel further includes two second shift registers, the first shift register and one of the second shift registers are located on one side of the display area, and the third shift register and another of the second shift registers are located on the other side of the display area.

11. The display panel according to claim 1, characterized in that: The display panel further includes a second reset module, a first end of the second reset module is electrically connected to a second reset line, and a second end of the second reset module is electrically connected to the light emitting element, wherein the first reset line and the second reset line provide different reset voltages.

12. The display panel according to claim 1, characterized in that: The display panel further comprises a second reset module, a control end of the second reset module receives a scan signal, a first end of the second reset module receives a reset voltage, and a second end of the second reset module is electrically connected to the light emitting element; Among them, within the time covered by a non-enable level in the light-emitting control signal, the total duration of the enable level in the scanning signal received by the second reset module is greater than the duration of the enable level in the second scanning signal.

13. The display panel according to claim 12, characterized in that: The control end of the second reset module is electrically connected to the first scan line.

14. The display panel according to claim 12, characterized in that: The control end of the second reset module is electrically connected to the third scan line.

15. The display panel according to claim 14, characterized in that: The display panel further includes: A plurality of circuit rows arranged along a first direction, the circuit rows comprising a plurality of the pixel circuits arranged along a second direction, the first direction intersecting the second direction; A first shift register, comprising a plurality of first shift units arranged in cascade, wherein an output end of the first shift unit is electrically connected to the first scan line corresponding to at least one of the circuit rows; a fourth shift register, comprising a plurality of fourth shift units arranged in cascade, wherein an output end of the fourth shift unit is electrically connected to the third scan line corresponding to at least one of the circuit rows; Wherein, for the first shift unit and the fourth shift unit corresponding to the same circuit row, the output end of the first shift unit is also electrically connected to the shift control end of the fourth shift unit.

16. A method for driving a display panel, characterized in that: The display panel includes a pixel circuit, and the pixel circuit includes: Driver module; a first reset module, wherein a control end of the first reset module is electrically connected to a first scan line for providing a first scan signal, a first end of the first reset module is electrically connected to a first reset line, and a second end of the first reset module is electrically connected to a control end of the driving module; a data writing module, wherein a control end of the data writing module is electrically connected to a second scanning line for providing a second scanning signal, a first end of the data writing module is electrically connected to a data line, and a second end of the data writing module is electrically connected to a first end of the driving module; a first light-emitting control module, wherein a control end of the first light-emitting control module is electrically connected to a light-emitting control line for providing a light-emitting control signal, a first end of the first light-emitting control module is electrically connected to a second end of the driving module, and a second end of the first light-emitting control module is electrically connected to a light-emitting element; Wherein, the enable levels of the first scanning signal and the second scanning signal are both low levels; The driving method includes: controlling the second scanning signal to output an enable level within the time covered by a non-enable level in the light-emitting control signal, and controlling the total duration of the enable level in the first scanning signal to be greater than the duration of the enable level in the second scanning signal.

17. The driving method according to claim 16, characterized in that: During a time period covered by a non-enable level in the light emitting control signal, the first scanning signal is controlled to output an enable level, and the enable level in the first scanning signal is located before the enable level in the second scanning signal; The duration of the enable level in the first scanning signal is t1, the duration of the enable level in the second scanning signal is t2, and t1>t2.

18. The driving method according to claim 17, characterized in that: 2 t2≤t1≤20 t2.

19. The driving method according to claim 17, characterized in that: The moment when the light emitting control signal changes from the enable level to the disable level is the first moment, the moment when the first scanning signal changes from the disable level to the enable level is the second moment, and the interval between the first moment and the second moment is ΔT1, 0<ΔT1≤1H; The moment when the first scanning signal jumps from the enable level to the disable level is the third moment, the moment when the second scanning signal jumps from the disable level to the enable level is the fourth moment, and the interval between the third moment and the fourth moment is ΔT2, 0<ΔT2≤1H; in, , n is the number of rows of the pixel circuit, and f is the basic frequency or the frequency at which the display panel is currently driven.

20. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 15.

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