Zoned display driver circuit, display panel and display device

Abstract

A partitioned display driving circuit, a display panel, and a display device are disclosed. The partitioned display driving circuit drives a pixel array and includes multiple data lines, multiple gating modules, and a control module. Each data line connects to a column of pixel circuits. A first end of each gating module receives a data signal, and a second end of each gating module is connected to at least one data line. The gating module is used to turn on or off based on the received data signal upon receiving a periodic trigger signal. The pixel circuits are configured with a refresh rate based on the duty cycle of the received data signal. By controlling the on / off state of the gating modules, the duty cycle of the data signal output from the gating modules to the pixel circuits can be changed, thereby changing the refresh rate of the corresponding column of pixel circuits. By cooperating with multiple adjacent gating modules or configuring the data signals of multiple data lines through a single gating module, partitioned display of the pixel array can be achieved.

Description

Technical Field

[0001] This application belongs to the field of display device technology, and in particular relates to a zoned display driving circuit, a display panel, and a display device. Background Technology

[0002] Currently, organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used and have become the mainstream of display devices due to their advantages such as high image quality, power saving, thin body and wide range of applications. Summary of the Invention

[0003] The purpose of this application is to provide a partitioned display driving circuit, a display panel, and a display device to solve the problems existing in the prior art.

[0004] A first aspect of this application provides a partitioned display driving circuit for driving a pixel array, the pixel array including multiple pixel circuits arranged in an array, the partitioned display driving circuit including: multiple data lines, one of the data lines for connecting a column of pixel circuits; multiple gating modules, the first end of the gating module for receiving data signals, the second end of the gating module being connected to at least one of the data lines; and a control module connected to the first end of each of the gating modules for outputting the data signals; wherein, the gating module is used to turn on or off according to the received data signal when a periodic trigger signal is received, and the pixel circuit is used to configure a refresh rate according to the duty cycle of the received data signal.

[0005] In one embodiment, the data signal includes periodic gating control data bits, each corresponding to a trigger signal. The gating module is used to identify the level of the gating control data bits upon receiving the trigger signal, and to keep the signal on or off in the next cycle according to the level of the gating control data bits. Preferably, the data signal output by the control module is high except for the gating control data bits.

[0006] In one embodiment, the gating module includes a logic operation unit, a storage unit, and a switching unit. The logic operation unit is connected to a first end of the storage unit. Upon receiving the trigger signal, the logic operation unit sends a corresponding control signal to the storage unit according to the level of the gating control data bit, and controls the storage unit to store the control signal. The second end of the storage unit is connected to the control end of the switching unit, and is used to provide the stored control signal to the switching unit. The first end of the switching unit is connected to the control module, and the second end of the switching unit is connected to at least one data line. The switching unit is used to turn on or off according to the control signal.

[0007] In one embodiment, the logic operation unit includes a first switching device and a second switching device, the storage unit includes a first inverter and a second inverter, and the switching unit includes a third switching device; a first terminal of the first switching device is connected to the control module, a second terminal of the first switching device is connected to the input terminal of the first inverter, and a control terminal of the first switching device is used to receive the trigger signal; a first terminal of the second switching device is connected to the input terminal of the first inverter, a second terminal of the second switching device is connected to the output terminal of the second inverter, and a control terminal of the second switching device is used to receive the trigger signal; the output terminal of the first inverter is connected to the input terminal of the second inverter and the control terminal of the third switching device, a first terminal of the third switching device is connected to the control module, and a second terminal of the third switching device is connected to at least one data line; the conduction logic of the first switching device and the third switching device is the same, and the conduction logic of the first switching device and the third switching device is opposite to the conduction logic of the second switching device; preferably, the first switching device and the third switching device are configured to conduct at a low level, and the second switching device is configured to conduct at a high level.

[0008] In one embodiment, the switching unit further includes a fourth switching device, the first terminal of the fourth switching device being connected to the first terminal of the third switching device, the second terminal of the fourth switching device being connected to the second terminal of the third switching device, and the control terminal of the fourth switching device being connected to the second terminal of the second switching device; the conduction logic of the third switching device is opposite to that of the fourth switching device; preferably, the fourth switching device is configured to conduct at a high level.

[0009] In one embodiment, the trigger signal is a low-level signal, and the gating module is used to, upon receiving the trigger signal, to continuously conduct in the next cycle if the gating control data bit is high, and to continuously turn off in the next cycle if the gating control data bit is low.

[0010] In one embodiment, the system further includes multiple scanning circuits, one of which is connected to a row of pixel circuits. The scanning circuit is used to transmit a scanning signal, which is used to configure the maximum refresh rate of each pixel circuit. The refresh rate of a pixel circuit is equal to the product of the corresponding maximum refresh rate and the duty cycle of the corresponding data signal.

[0011] In one embodiment, the frequency at which the gating module receives the trigger signal is the same as the frequency of the scanning signal; preferably, the pixel array includes N rows of pixel circuits, the partition display driving circuit includes N+1 rows of scanning circuits, the scanning circuits in rows 1 to N correspond one-to-one with the pixel circuits in rows N, and the scanning circuit in row N+1 is used to provide the trigger signal; preferably, the control module is also used to provide the trigger signal.

[0012] A second aspect of this application provides a display panel including a pixel array and a partitioned display driving circuit as described above, wherein the partitioned display driving circuit is connected to the pixel array.

[0013] A third aspect of this application provides a display device, including the display panel as described above.

[0014] The beneficial effects of this application embodiment compared with the prior art are: by controlling the on and off of the gating module, the duty cycle of the data signal output by the gating module to the pixel circuit can be changed, thereby changing the refresh rate of the corresponding entire column of pixel circuits. By cooperating with multiple adjacent gating modules or by configuring the data signals of multiple data lines through one gating module, the pixel array can be partitioned for display. Attached Figure Description

[0015] Figure 1 A schematic diagram of a partitioned display driving circuit provided in an embodiment of this application;

[0016] Figure 2 A circuit diagram of a gating module provided in one embodiment of this application;

[0017] Figure 3 Another circuit diagram of a gating module provided in one embodiment of this application;

[0018] Figure 4 A schematic diagram of a pixel array provided in an embodiment of this application;

[0019] Figure 5 Waveforms of the trigger signal, data signal, and scan signal provided in an embodiment of this application;

[0020] Figure 6Another waveform diagram of the trigger signal, data signal and scan signal provided in an embodiment of this application;

[0021] Figure 7 Waveform diagrams of the data signals in columns 1 to 4 provided in an embodiment of this application;

[0022] Figure 8 Another waveform diagram of the data signals in columns 1 to 4 provided in an embodiment of this application;

[0023] Figure 9 Another waveform diagram of the data signals in columns 1 to 4 provided in an embodiment of this application;

[0024] Figure 10 A schematic diagram of a display panel provided in one embodiment of this application;

[0025] Figure 11 This is a schematic diagram of a display device provided in an embodiment of this application.

[0026] Explanation of reference numerals in the attached figures: 10, zone display driving circuit; 20, pixel array; 30, display panel; 40, display device; 100, pixel circuit; 200, gating module; 210, logic operation unit; 220, storage unit; 221, first inverter; 222, second inverter; 230, switching unit; 300, control module. Detailed Implementation

[0027] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0028] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0029] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0031] In existing technologies, common pixel arrays typically output multiple scan signals through a gate in panel (GIP), and frequency modulation is performed on a row of pixels.

[0032] By controlling the scanning signal output by the GIP, it is possible to determine whether the thin film transistor (TFT) of the corresponding row is turned on, and thus whether data is written to the corresponding row of pixels, thereby achieving control over the refresh rate of a row of pixels.

[0033] By controlling the refresh rate of multiple adjacent rows of pixels simultaneously, a certain pixel array partitioning display can be achieved.

[0034] Figure 1 A schematic diagram of a partitioned display driving circuit according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0035] A partitioned display driving circuit 10 is used to drive a pixel array 20. The pixel array 20 includes multiple pixel circuits 100 arranged in an array. The partitioned display driving circuit 10 includes multiple data lines, multiple gating modules 200, and a control module 300.

[0036] A data line is used to connect a column of pixel circuits 100. A first terminal of the gating module 200 is used to receive data signals, and a second terminal of the gating module 200 is connected to at least one data line. A control module 300 is connected to the first terminal of each gating module 200 and is used to output data signals.

[0037] The gating module 200 is used to turn on or off according to the received data signal when a periodic trigger signal is received, and the pixel circuit 100 is used to configure the refresh rate according to the duty cycle of the received data signal.

[0038] It should be noted that the pixel array 20 also includes multiple light-emitting signals, and a pixel circuit 100 can be connected to one or more light-emitting chips to control the brightness of each chip. The control module 300 may include a control chip. Due to limitations in the model and function of the control chip, a single control module 300 cannot individually adjust each data signal according to actual needs, and cannot adjust the refresh rate of the pixel circuits 100 in the pixel array 20 on a column-by-column basis.

[0039] When the second end of the gating module 200 is connected to only one data line, this embodiment can change the duty cycle of the data signal output from the gating module 200 to the pixel circuit 100 by controlling the on and off states of the gating module 200, thereby changing the refresh rate of the corresponding entire column of pixel circuits 100. By cooperating with multiple adjacent gating modules 200 or by configuring the data signals of multiple data lines through one gating module 200, partitioned display of the pixel array 20 can be achieved. Compared with existing technical solutions, this embodiment only needs to adjust the data bits corresponding to the trigger signal in the data signal to achieve column-by-column adjustment of the refresh rate of the pixel array 20.

[0040] In one embodiment, the data signal includes periodic gating control data bits, each corresponding to a trigger signal. The gating module 200 is used to identify the level of the gating control data bits upon receiving the trigger signal, and to keep the gating control data bits on or off in the next cycle according to their level.

[0041] It should be noted that a data signal can be considered as consisting of multiple level signals, and one strobe control data bit can correspond to one of these levels. A trigger signal can specifically be a pulse signal, for example, a low-level pulse signal.

[0042] In some embodiments, a trigger signal may specifically be a transition edge received by the gating module 200, which is used to identify the data signal at the same time as detecting the transition edge of the signal.

[0043] When the gating module 200 receives a trigger signal (for example, when the trigger signal is a low-level pulse signal and the level of the terminal of the gating module 200 used to receive the trigger signal is low), the gating module 200 can identify the level of the gating control data bit of the data signal received at the same time as the trigger signal. Before receiving the next trigger signal, the gating module 200 can be continuously controlled to be turned on according to the level of the gating control data bit.

[0044] Preferably, the data signals output by the control module 300, except for the strobe control data bits, are all at a high level.

[0045] Understandably, when the gating module 200 is off, the corresponding pixel circuit 100 cannot receive data signals and therefore cannot change the light emission parameters of the corresponding light-emitting chip (i.e., the corresponding pixel circuit 100 stops refreshing). However, when the gating module 200 is on, the corresponding pixel circuit 100 can change the light emission parameters of the corresponding light-emitting chip according to the data signals (i.e., the corresponding pixel circuit 100 can continuously refresh). Therefore, by changing the on / off state of the gating module 200, the refresh rate of the pixel circuit 100 can be adjusted. The longer the on / off time of a gating module 200, the larger the duty cycle of the data signal provided to the pixel circuit 100, and the higher the refresh rate of the corresponding column of pixel circuits 100.

[0046] In one embodiment, such as Figure 2 As shown, the gating module 200 includes a logic operation unit 210, a storage unit 220, and a switching unit 230. The logic operation unit 210 is connected to the first terminal of the storage unit 220. Upon receiving a trigger signal SCAN, the logic operation unit 210 sends a corresponding control signal to the storage unit 220 based on the level of the gating control data bit, and controls the storage unit 220 to store the control signal. The second terminal of the storage unit 220 is connected to the control terminal of the switching unit 230, and provides the stored control signal to the switching unit 230. The first terminal of the switching unit 230 is connected to the control module 300, and the second terminal of the switching unit 230 is connected to at least one data line. The switching unit 230 is used to turn on or off according to the control signal.

[0047] When the logic operation unit 210 receives the trigger signal SCAN, it will identify the level of the data signal DATA-IC (strobe control data bit) and output the corresponding control signal. Before receiving the next trigger signal SCAN (that is, in the next adjacent cycle), the storage unit 220 will save the control signal and continuously output it to the switching unit 230, thereby controlling the switching unit 230 to turn on and off, and finally achieving the effect of changing the duty cycle of the data signal DATA-AA provided to the pixel circuit 100.

[0048] In one embodiment, such as Figure 2As shown, the logic operation unit 210 includes a first switching device Q1 and a second switching device Q2, the storage unit 220 includes a first inverter 221 and a second inverter, and the switching unit 230 includes a third switching device Q3. The first terminal of the first switching device Q1 is connected to the control module 300, the second terminal of the first switching device Q1 is connected to the input terminal of the first inverter 221, and the control terminal of the first switching device Q1 is used to receive the trigger signal SCAN. The first terminal of the second switching device Q2 is connected to the input terminal of the first inverter 221, the second terminal of the second switching device Q2 is connected to the output terminal of the second inverter 222, and the control terminal of the second switching device Q2 is used to receive the trigger signal SCAN. The output terminal of the first inverter 221 is connected to the input terminal of the second inverter 222 and the control terminal of the third switching device Q3. The first terminal of the third switching device Q3 is connected to the control module 300, and the second terminal of the third switching device Q3 is connected to at least one data line. The first switching device Q1 and the third switching device Q3 have the same conduction logic, and the conduction logic of the first switching device Q1 and the third switching device Q3 is opposite to the conduction logic of the second switching device Q2.

[0049] Preferably, the first switching device Q1 and the third switching device Q3 are configured to be turned on at a low level, and the second switching device Q2 is configured to be turned on at a high level.

[0050] When the logic operation unit 210 receives the trigger signal SCAN, the trigger signal SCAN can turn on the first switching device Q1 and turn off the second switching device Q2. The logic operation unit 210 can output a corresponding control signal according to the level of the strobe control data bit of the data signal DATA-IC output by the control module 300. After the control signal passes through the first inverter 221, it is provided to the third switching device Q3 to control the turn-on and turn-off of the third switching device Q3.

[0051] When the selected control data bit is at a high level, the control signal after being inverted by the first inverter 221 can control the third switching device Q3 to turn on. The data signal DATA-AA can be transmitted to the corresponding pixel circuit 100 through the third switching device Q3, so that the light emission parameters of the light-emitting chip corresponding to the pixel circuit 100 are continuously refreshed.

[0052] When the level of the selected control data bit is low, the control signal after being inverted by the first inverter 221 can control the third switching device Q3 to turn off, and the data signal DATA-AA cannot be transmitted to the pixel circuit 100, causing the light emission parameters of the corresponding light-emitting chip of the pixel circuit 100 to stop refreshing.

[0053] Therefore, by reasonably configuring the level of the strobe control data bits of different data signals DATA-IC, the refresh rate of the pixel circuits 100 in different columns can be made different.

[0054] In the next cycle (before the next trigger signal SCAN arrives), the first switching device Q1 is turned off and the second switching device Q2 is turned on. The control signal provided to the third switching device Q3 will be transmitted to the input of the first inverter 221 through the second inverter 222, thereby achieving the effect of saving the control signal and keeping the switching state of the third control signal unchanged.

[0055] In one embodiment, such as Figure 3 As shown, the switching unit 230 further includes a fourth switching device Q4. The first terminal of the fourth switching device Q4 is connected to the first terminal of the third switching device Q3, the second terminal of the fourth switching device Q4 is connected to the second terminal of the third switching device Q3, and the control terminal of the fourth switching device Q4 is connected to the second terminal of the second switching device Q2. The conduction logic of the third switching device Q3 is opposite to the conduction logic of the fourth switching device Q4. Preferably, the fourth switching device Q4 is configured to be high-level turned on.

[0056] Since the conduction logic of the third switch Q3 is opposite to that of the fourth switch Q4, and the control signal provided to the fourth switch Q4 is inverted by the second inverter 222, the fourth switch Q4 will also conduct when the third switch Q3 is turned on, thereby increasing the current through the switching unit 230 and improving the charging effect of the data line.

[0057] In one embodiment, the trigger signal SCAN is a low-level signal. The gating module 200 is used to, upon receiving the trigger signal SCAN, either continue to conduct in the next cycle if the gating control data bit is high, or continue to turn off in the next cycle if the gating control data bit is low.

[0058] Specifically, in some embodiments, the first switching device Q1 and the third switching device Q3 can both be low-level conducting switching devices, and the second switching device Q2 and the fourth switching device Q4 can both be high-level conducting switching devices. The first switching device Q1, the second switching device Q2, the third switching device Q3, and the fourth switching device Q4 can specifically be a Metal-Oxide Semiconductor Field Effect Transistor (MOS) or an Insulated-Gate Bipolar Transistor (IGBT). The specific device types of the first switching device Q1, the second switching device Q2, the third switching device Q3, and the fourth switching device Q4 can be set according to actual needs, and this embodiment does not limit them.

[0059] Therefore, when the trigger signal SCAN is received, the first switching device Q1 is turned on and the second switching device Q2 is turned off, while when the trigger signal SCAN is not received, the first switching device Q1 is turned off and the second switching device Q2 is turned on.

[0060] When the turn-on control data bit is high, the third switch Q3 and the fourth switch Q4 are turned on during the cycle; when the turn-on control data bit is low, the third switch Q3 and the fourth switch Q4 are turned off during the cycle.

[0061] In one embodiment, the partition display driving circuit 10 further includes multiple scanning circuits. One scanning circuit is connected to a row of pixel circuits 100. The scanning circuit is used to transmit scanning signals, which are used to configure the maximum refresh rate of each pixel circuit 100. The actual refresh rate of a pixel circuit 100 is equal to the product of the corresponding maximum refresh rate and the duty cycle of the corresponding data signal DATA-AA.

[0062] It is understandable that the scan signal determines the maximum refresh rate of each pixel circuit 100. When all gating modules 200 are turned on, the refresh rate of each pixel circuit 100 is the maximum refresh rate. However, when some gating modules 200 are turned off for certain periods of time, the corresponding pixel circuit 100 will decrease as the duty cycle of the data signal DATA-AA decreases.

[0063] Exemplary, in some embodiments, such as Figure 4 As shown, the pixel array 20 includes a first region, a second region, a third region...a ninth region, and each of the first, second, third...ninth regions includes multiple pixel circuits 100. Specifically, the first, second, and third regions are arranged in the same row from left to right, the fourth, fifth, and sixth regions are arranged in the same row from left to right, and the seventh, eighth, and ninth regions are arranged in the same row from left to right.

[0064] When a high refresh rate is required for zone 5 and low refresh rates for the other zones, the maximum refresh rate of the pixel circuits 100 in zones 4, 5, and 6 can be set to 120Hz by configuring the various scan signals, while the maximum refresh rate of the pixel circuits 100 in zones 1, 2, 3, 7, 8, and 9 can be set to 60Hz. Furthermore, by keeping the gating module 200 corresponding to zone 5 on, the on-time of the gating modules 200 corresponding to zones 4 and 6 is halved (i.e., the duty cycle of the data signal DATA-AA output by the gating modules 200 corresponding to zones 4 and 6 is set to 50%). Ultimately, this results in a refresh rate of 120Hz for zone 5 and 60Hz for the other zones.

[0065] In one embodiment, such as Figure 5 , Figure 6 As shown, the frequency of the trigger signal received by the gating module 200 is the same as the frequency of the scan signal. Figure 5 , Figure 6 The scan signals shown include the third-to-last scan signal, the second-to-last scan signal, and the last scan signal. Figure 5 The strobe control data bit is high. Figure 6 The gating control data bit is at a low level. In some embodiments, when the gating control data bit is at a high level, the corresponding gating module 200 can be turned on, and when the gating control data bit is at a low level, the corresponding gating module 200 can be turned off.

[0066] It is understandable that the frequency of the scan signal specifically refers to the frequency of the pulses used for scanning any row of the scan signal. The trigger signal can be set according to the scan signal so that the gating module 200 has a sufficient switching frequency, which can make the minimum refresh rate of the pixel circuit 100 1Hz.

[0067] For example, in some embodiments, four data lines corresponding to four columns of data signals are used as an example. Figure 7 The waveforms of the data signals in columns 1 to 4 are shown. These data signals are used to supply the pixel circuits 100 in columns 1 to 4 of the pixel array 20, respectively, and the duty cycle of each data signal is 100%. With a maximum refresh rate of 120Hz, the refresh rate of the pixel circuits 100 in columns 1 to 4 is also 120Hz.

[0068] For example, in some embodiments, four data lines corresponding to four columns of data signals are used as an example. Figure 8 The diagram shows the waveforms of the data signals from columns 1 to 4, which are used to supply the pixel circuits 100 in the pixel array 20. The duty cycle of the data signals in columns 1 and 4 is 50%, and the duty cycle of the data signals in columns 2 and 3 is 100%. At a maximum refresh rate of 120Hz, the refresh rate of the pixel circuits 100 in columns 1 and 4 is 60Hz, and the refresh rate of the pixel circuits 100 in columns 2 and 3 is 120Hz.

[0069] For example, in some embodiments, four data lines corresponding to four columns of data signals are used as an example. Figure 9The diagram shows the waveforms of the data signals from columns 1 to 4, which are used to supply the pixel circuits 100 in the pixel array 20. The duty cycle of the data signals in columns 1 and 4 is 8.3%, and the duty cycle of the data signals in columns 2 and 3 is 100%. At a maximum refresh rate of 120Hz, the refresh rate of the pixel circuits 100 in columns 1 and 4 is 1Hz, and the refresh rate of the pixel circuits 100 in columns 2 and 3 is 120Hz.

[0070] Specifically, the phase of the signal can be changed based on the tail scan signal to obtain a periodic trigger signal.

[0071] In some embodiments, the pixel array 20 includes N rows of pixel circuits 100, and the partition display driving circuit 10 includes N+1 rows of scanning circuits. The first to Nth rows of scanning circuits correspond one-to-one with the N rows of pixel circuits 100, and the N+1th row of scanning circuits is used to provide the trigger signal.

[0072] It should be noted that a scan signal usually includes periodic pulse signals. Therefore, when a trigger signal is a pulse signal and the pulse signal parameters of the trigger signal and the scan signal are the same, when the frequency of the trigger signal received by the gating module 200 is the same as the frequency of the scan signal, a signal composed of periodic trigger signals can be generated based on the waveform of the tail scan signal (the scan signal corresponding to the Nth row scan circuit).

[0073] In some embodiments, the control module 300 is also used to output trigger signals to each gating module 200. It is understood that the control module 300 can be configured so that one port of the control module 300 outputs the required trigger signal, and the trigger signal can be adjusted according to actual needs.

[0074] Figure 10 A schematic diagram of a display panel according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0075] A display panel 30 includes a pixel array 20 and a partitioned display driving circuit 10 as described in any of the above embodiments, wherein the partitioned display driving circuit 10 is connected to the pixel array 20.

[0076] Since the display panel 30 includes the partition display driving circuit 10 of any of the above embodiments, the display panel 30 has the beneficial effects of the partition display driving circuit 10 of any of the above embodiments, which will not be described again here.

[0077] Figure 11A schematic diagram of a display device according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0078] A display device 40 includes a partitioned display driving circuit 10 as described in any of the above embodiments, or a display panel 30 as described in any of the above embodiments.

[0079] Since the display device 40 includes the display panel 30 of any of the above embodiments, the display device 40 has the beneficial effects of the display panel 30 of any of the above embodiments, which will not be repeated here.

[0080] The display device 40 in this application embodiment includes, but is not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0081] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0083] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A partitioned display driving circuit (10), characterized in that, For driving a pixel array (20), the pixel array (20) includes a plurality of pixel circuits (100) arranged in an array, and the partition display driving circuit (10) includes: Multiple data lines, one of which is used to connect a column of pixel circuits (100). Multiple gating modules (200), the first end of the gating module (200) is used to receive data signals, and the second end of the gating module (200) is connected to at least one of the data lines; A control module (300) is connected to the first end of each of the gating modules (200) and is used to output the data signal; The gating module (200) is used to turn on or off according to the received data signal when a periodic trigger signal is received, and the pixel circuit (100) is used to configure the refresh rate according to the duty cycle of the received data signal. The data signal includes periodic gating control data bits, each of which corresponds one-to-one with the trigger signal. The gating module (200) is used to identify the level of the gating control data bits when receiving the trigger signal, and to keep the gating control data bits on or off in the next cycle according to the level of the gating control data bits. The gating module (200) includes a logic operation unit (210), a storage unit (220), and a switching unit (230). The logic operation unit (210) is connected to the first end of the storage unit (220). The logic operation unit (210) is used to send a corresponding control signal to the storage unit (220) according to the level of the strobe control data bit when the trigger signal is received, and to control the storage unit (220) to store the control signal. The second end of the storage unit (220) is connected to the control end of the switch unit (230) for providing the stored control signal to the switch unit (230); The first end of the switch unit (230) is connected to the control module (300), and the second end of the switch unit (230) is connected to at least one of the data lines. The switch unit (230) is used to turn on or off according to the control signal. The logic operation unit (210) includes a first switching device and a second switching device, the storage unit (220) includes a first inverter (221) and a second inverter, and the switching unit (230) includes a third switching device; The first terminal of the first switching device is connected to the control module (300), the second terminal of the first switching device is connected to the input terminal of the first inverter (221), and the control terminal of the first switching device is used to receive the trigger signal. The first terminal of the second switching device is connected to the input terminal of the first inverter (221), the second terminal of the second switching device is connected to the output terminal of the second inverter (222), and the control terminal of the second switching device is used to receive the trigger signal; The output terminal of the first inverter (221) is connected to the input terminal of the second inverter (222) and the control terminal of the third switching device. The first terminal of the third switching device is connected to the control module (300), and the second terminal of the third switching device is connected to at least one of the data lines. The first switching device and the third switching device have the same conduction logic, and the conduction logic of the first switching device and the third switching device is opposite to that of the second switching device.

2. The partition display driving circuit (10) as described in claim 1, characterized in that, Except for the strobe control data bit, all data signals output by the control module (300) are at a high level.

3. The partition display driving circuit (10) as described in claim 1, characterized in that, The first and third switching devices are configured to be turned on at a low level, and the second switching device is configured to be turned on at a high level.

4. The partition display driving circuit (10) as described in claim 1, characterized in that, The switching unit (230) further includes a fourth switching device, the first end of the fourth switching device being connected to the first end of the third switching device, the second end of the fourth switching device being connected to the second end of the third switching device, and the control end of the fourth switching device being connected to the second end of the second switching device; The conduction logic of the third switching device is the opposite of that of the fourth switching device.

5. The partition display driving circuit (10) as described in claim 4, characterized in that, The fourth switching device is configured to be high-level on.

6. The partition display driving circuit (10) as described in claim 1, characterized in that, The trigger signal is a low-level signal. The gating module (200) is used to, when receiving the trigger signal, to continuously conduct in the next cycle if the gating control data bit is high, and to continuously turn off in the next cycle if the gating control data bit is low.

7. The partition display driving circuit (10) as described in claim 1, characterized in that, It also includes multiple scanning circuits, one of which is connected to a row of pixel circuits, the scanning circuit being used to transmit scanning signals, and the scanning signals being used to configure the maximum refresh rate of each pixel circuit; The refresh rate of one of the pixel circuits (100) is equal to the product of the corresponding maximum refresh rate and the duty cycle of the corresponding data signal.

8. The partition display driving circuit (10) as described in claim 1, characterized in that, The frequency at which the trigger signal is received by the gating module (200) is the same as the frequency of the scanning signal.

9. The partition display driving circuit (10) as described in claim 8, characterized in that, The pixel array (20) includes N rows of pixel circuits (100), and the partition display driving circuit (10) includes N+1 rows of scanning circuits. The scanning circuits in the first to Nth rows correspond one-to-one with the pixel circuits (100) in the Nth row. The scanning circuit in the N+1th row is used to provide the trigger signal.

10. The partition display driving circuit (10) as described in claim 8, characterized in that, The control module (300) is also used to provide the trigger signal.

11. A display panel (30), characterized in that, It includes a pixel array (20) and a partitioned display driving circuit (10) as described in any one of claims 1 to 10, wherein the partitioned display driving circuit (10) is connected to the pixel array (20).

12. A display device (40), characterized in that, Includes the display panel (30) as described in claim 11.

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