Shifting register, driving method, gate driving circuit and display device

Abstract

The embodiment of the invention provides a shifting register, a driving method, a gate driving circuit and a display device. Relates to the technical field of display, is used for improving the display effect of a display panel, and comprises a first input sub-circuit, a second input sub-circuit, a first output sub-circuit, a first storage sub-circuit and a first control sub-circuit. The first input sub-circuit is coupled with a signal input end, a first node and a first clock signal end; the second input sub-circuit is coupled with the first node, the second node and a first clock signal end; the first output sub-circuit is coupled with a second clock signal end, a second node and a cascade signal output end; the first control sub-circuit is coupled with a second clock signal end, a cascade signal output end and a first node; the first control sub-circuit is configured to transmit a working level received at the second clock signal end to the first node in response to the working level at the cascade signal output end in an output phase. The shift register is used for driving a pixel circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method, a gate driving circuit and a display device. Background Art

[0002] With the development of display technology, display devices (such as mobile phones, laptops or tablets) are increasingly used in people's lives. Among them, organic light-emitting diode (OLED) display devices have the advantages of active light emission, wide viewing angle, high contrast, fast response speed, low power consumption, and ultra-thinness, so they have attracted widespread attention. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide a shift register and a driving method, a gate driving circuit and a display device, so as to improve the display effect of a display panel.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] On the one hand, a shift register is provided. The shift register includes a first input subcircuit, a second input subcircuit, a first output subcircuit, a first storage subcircuit and a first control subcircuit. The first input subcircuit is coupled to a signal input terminal, a first node and a first clock signal terminal; the first input subcircuit is configured to, in an input stage, transfer the working level received at the signal input terminal to the first node in response to the first clock signal received at the first clock signal terminal; and in an output stage, cut off the signal input terminal and the first node in response to the first clock signal received at the first clock signal terminal; in an output stage, a non-working level is received at the signal input terminal; the first input subcircuit includes a first transistor, which is a low-temperature polysilicon transistor; the second input subcircuit is coupled to the first node, a second node and the first clock signal terminal; the second input subcircuit is configured to, in an input stage, transfer the voltage at the first node to the second node in response to the first clock signal received at the first clock signal terminal, and in an output stage, cut off the voltage at the first node in response to the first clock signal received at the first clock signal terminal. The first clock signal received by the first input subcircuit cuts off the first node and the second node; the second input subcircuit includes a second transistor, which is a low-temperature polysilicon transistor; the first output subcircuit is coupled to the second clock signal terminal, the second node and the cascade signal output terminal; the first output subcircuit is configured to, in the input stage, under the control of the voltage at the second node, transfer the non-working level received at the second clock signal terminal to the cascade signal output terminal; and in the output stage, under the control of the voltage at the second node, transfer the working level received at the second clock signal terminal to the cascade signal output terminal; the first control subcircuit is coupled to the second clock signal terminal, the cascade signal output terminal and the first node; the first control subcircuit is configured to, in the output stage, transfer the working level received at the second clock signal terminal to the first node in response to the working level at the cascade signal output terminal.

[0006] In the output stage, under the control of the signal at the cascade signal output terminal, the first control subcircuit transmits the signal received at the second clock signal terminal to the first node, so that the source-drain voltage difference of the transistor included in the second input subcircuit is small, and the leakage current of the transistor included in the second input subcircuit is small or non-existent, thereby reducing the risk of leakage from the first node to the second node, which is beneficial to improving the voltage stability at the second node, improving the stability of the conduction degree of the transistor included in the first output subcircuit, and improving the stability of the working level received at the cascade signal output terminal, thereby improving the display effect of the display panel.

[0007] In some embodiments, the first control subcircuit includes a third transistor. A first electrode of the third transistor is connected to the second clock signal terminal, a second electrode is connected to the first node, and a control electrode is connected to the cascade signal output terminal.

[0008] In some embodiments, the shift register further includes a third input sub-circuit, a second control sub-circuit, and a second output sub-circuit. The third input subcircuit is coupled to the first voltage signal terminal, the third node and the fourth node; the third input subcircuit is configured to, in the input stage, under the control of the voltage of the fourth node, transfer the first voltage signal received at the first voltage signal terminal to the third node; the first voltage signal is a non-working level; the second control subcircuit is coupled to the second node, the third node, the first voltage signal terminal, the second voltage signal terminal and the third clock signal terminal; the second control subcircuit is configured to, in the holding stage, in response to the third clock signal received at the third clock signal terminal, transfer the second voltage signal received at the second voltage signal terminal to the third node, and transfer the first voltage signal received at the first voltage signal terminal to the second node; the second voltage signal is a working level; the second output subcircuit is coupled to the third voltage signal terminal, the third node and the cascade signal output terminal; the second output subcircuit is configured to, in the holding stage, under the control of the voltage at the third node, transfer the third voltage signal received at the third voltage signal terminal to the cascade signal output terminal; the third voltage signal is a non-working level.

[0009] In some embodiments, the second control subcircuit includes a primary control subcircuit and a secondary control subcircuit. The primary control subcircuit is coupled to the third node, the second voltage signal terminal and the third clock signal terminal; the primary control subcircuit is configured to, in the holding phase, transmit the second voltage signal received at the second voltage signal terminal to the third node in response to the third clock signal received at the third clock signal terminal; the second voltage signal is a working level; the secondary control subcircuit is coupled to the second node, the third node and the first voltage signal terminal; the secondary control subcircuit is configured to, in the holding phase, transmit the first voltage signal received at the first voltage signal terminal to the second node under the control of the second voltage signal at the third node.

[0010] In some embodiments, the secondary control subcircuit includes a first subcircuit and a second subcircuit. The first subcircuit is coupled to the third node, the first voltage signal terminal and the fifth node; the first subcircuit is configured to, in the output stage, under the control of the voltage at the third node, turn off the first voltage signal terminal and the fifth node; the first subcircuit includes a fourth transistor, which is a low-temperature polysilicon transistor; the second subcircuit is coupled to the second node, the third node and the fifth node; the second subcircuit is configured to, in the output stage, under the control of the voltage at the third node, turn off the fifth node and the second node; the second subcircuit includes a fifth transistor, which is a low-temperature polysilicon transistor. The second control subcircuit also includes a three-level control subcircuit, the three-level control subcircuit is coupled to the fifth node, the second node and the second voltage signal terminal; the three-level control subcircuit is configured to, in the output stage, under the control of the voltage at the second node, transfer the second voltage signal received at the second voltage signal terminal to the fifth node.

[0011] In some embodiments, the primary control subcircuit includes a sixth transistor. A first electrode of the sixth transistor is connected to the second voltage signal terminal, a second electrode is connected to the third node, and a control electrode is connected to the third clock signal terminal.

[0012] In some embodiments, the fourth node is connected to the signal input terminal, or the fourth node is connected to the first node, or the fourth node is connected to the fifth node.

[0013] In some embodiments, the first output subcircuit includes a seventh transistor, a first electrode of the seventh transistor is connected to the second clock signal terminal, a second electrode is connected to the cascade signal output terminal, and a control electrode is connected to the second node; the third input subcircuit includes an eighth transistor, a first electrode of the eighth transistor is connected to the first voltage signal terminal, a second electrode is connected to the cascade signal output terminal, and a control electrode is connected to the fourth node; the second output subcircuit includes a ninth transistor, a first electrode of the ninth transistor is connected to the third voltage signal terminal, a second electrode is connected to the cascade signal output terminal, and a control electrode is connected to the third node; the three-level control subcircuit includes a tenth transistor, a first electrode of the tenth transistor is connected to the second voltage signal terminal, a second electrode is connected to the fifth node, and a control electrode is connected to the second node; the first storage subcircuit also includes a first storage capacitor, a first plate of the first storage capacitor is coupled to the second node, and a second plate is coupled to the cascade signal output terminal.

[0014] In another aspect, a gate driving circuit is provided, wherein the gate driving circuit comprises: a plurality of cascaded shift registers as described in any one of the above embodiments.

[0015] In some embodiments, the shift register is connected to a first clock signal terminal, a second clock signal terminal and a third clock signal terminal; the gate drive circuit also includes multiple clock signal lines, and the multiple clock signal lines are divided into multiple groups. In the same group, in adjacent bipolar shift registers, the clock signal line connected to the second clock signal terminal in the previous level shift register is the same as the clock signal line connected to the first clock signal terminal in the next level shift register, the clock signal line connected to the third clock signal terminal in the previous level shift register is the same as the clock signal line connected to the second clock signal terminal in the next level shift register, the clock signal line connected to the first clock signal terminal in the previous level shift register is different from the clock signal line connected to the third clock signal terminal in the next level shift register, and the clock signal lines connected to the same clock signal terminals in any two levels of shift registers are different.

[0016] In some embodiments, the gate drive circuit further includes a first voltage signal line and a second voltage signal line. The first voltage signal line is connected to the first voltage signal terminal and the shift register; the second voltage signal line is connected to the third voltage signal terminal and the shift register; the width of the first voltage signal line is smaller than the width of the second voltage signal line.

[0017] In some embodiments, the line width of the first voltage signal line is 3 μm to 10 μm; and / or the line width of the second voltage signal line is 10 μm to 20 μm.

[0018] In some embodiments, multiple shift registers are arranged at intervals along the second direction; the shift register includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; the first voltage signal line extends along the second direction, and along the first direction, the first voltage signal line is located between the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor and the tenth transistor, and the seventh transistor and the ninth transistor; the second voltage signal line extends along the second direction, and along the first direction, the second voltage signal line is located between the seventh transistor and the ninth transistor, away from the first voltage signal line; the second direction intersects with the first direction.

[0019] In some embodiments, the shift register also includes a first storage capacitor; the first storage capacitor is located on the side of the seventh transistor and the ninth transistor, away from the first voltage signal line, and the orthographic projection of the second voltage signal line on the reference plane overlaps with the orthographic projection of the first storage capacitor on the reference plane; along the first direction, both ends of the first storage capacitor exceed both ends of the second voltage signal line.

[0020] In some embodiments, the clock signal line extends along the second direction, and the clock signal line is located on a side of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor and the tenth transistor away from the first voltage signal line;

[0021] The gate driving circuit further includes a third voltage signal line, which is connected to the second voltage signal terminal and the shift register. The third voltage signal line extends along the second direction and is located between the clock signal line and the shift register.

[0022] In some embodiments, the fourth transistor and the fifth transistor are located between the first transistor, the second transistor, the third transistor, the sixth transistor, the eighth transistor and the tenth transistor and the first voltage signal line, and along the second direction, the fourth transistor is located on one side of the fifth transistor; and / or, the third transistor and the sixth transistor are located between the first transistor, the second transistor, the fourth transistor, the fifth transistor, the eighth transistor and the tenth transistor and the third voltage signal line, and along the second direction, the third transistor is located on one side of the sixth transistor.

[0023] In some embodiments, the eighth transistor is located between the fourth transistor and the fifth transistor, and the third transistor and the sixth transistor, and is located on the side of the first transistor, the second transistor and the tenth transistor away from the shift register of the next level; the fourth transistor is located on the side of the fifth transistor away from the shift register of the next level, and the ninth transistor is located on the side of the seventh transistor away from the shift register of the next level; the gate drive circuit also includes a first connecting line, which is connected to the gate of the third transistor, the second electrode of the seventh transistor and the first electrode of the first transistor of the next level; the first connecting line is located on the side of the first transistor, the second transistor, the fourth transistor, the fifth transistor and the tenth transistor close to the next electrode of the shift register.

[0024] In some embodiments, along the first direction, the channel portion of the first transistor is located on a side of the channel portion of the second transistor close to the shift register of the previous level, and along the second direction, the channel portion of the first transistor is located on a side of the channel portion of the second transistor away from the first voltage signal line; the channel portion of the third transistor is located on a side of the channel portion of the first transistor and the channel portion of the second transistor away from the first voltage signal line.

[0025] In another aspect, a display device is provided, comprising: the shift register as described in any one of the above embodiments, or the gate driving circuit as described in any one of the above embodiments.

[0026] On the other hand, a shift register driving method is provided, which is used to drive the shift register as described in any of the above embodiments. A display frame period includes an input stage and an output stage; in the input stage, the first input subcircuit transmits the working level received at the signal input terminal to the first node in response to the first clock signal received at the first clock signal terminal; the second input subcircuit transmits the working level at the first node to the second node in response to the first clock signal received at the first clock signal terminal; the first storage subcircuit stores the working level at the second node; under the control of the working level at the second node, the first output subcircuit transmits the non-working level received at the second clock signal terminal to the cascade signal output terminal; in the output stage, the first input subcircuit transmits the non-working level received at the second clock signal terminal to the cascade signal output terminal in response to the first clock signal received at the first clock signal terminal. The signal input terminal and the first node are cut off, and the signal received at the signal input terminal is a non-working level; the second input sub-circuit cuts off the first node and the second node in response to the first clock signal received at the first clock signal terminal; under the control of the working level at the second node, the first output sub-circuit transfers the working level received at the second clock signal terminal to the cascade signal output terminal; the first storage sub-circuit writes the difference between the working level and the non-working level received at the second clock signal terminal into the second node; under the control of the working level at the cascade signal output terminal, the first control sub-circuit transfers the working level received at the cascade signal output terminal to the first node.

[0027] In some embodiments, a display frame cycle also includes a holding phase, which is located after the output phase; in the input phase, under the control of the voltage of the fourth node, the third input subcircuit transmits the first voltage signal received at the first voltage signal terminal to the third node, and under the control of the first voltage signal at the third node, the second output subcircuit cuts off the third voltage signal terminal and the cascade signal output terminal; the second control subcircuit controls the third voltage signal terminal and the third node to be cut off in response to the third clock signal received at the third clock signal terminal, and under the control of the first voltage signal at the third node, the second control subcircuit cuts off the first voltage signal terminal and the second node; in the output phase, the second control subcircuit controls the second voltage signal terminal and the third node to be cut off in response to the third clock signal received at the third clock signal terminal, Under the control of the first voltage signal at the third node, the second output subcircuit cuts off the third voltage signal terminal and the cascade signal output terminal, and the second control subcircuit cuts off the first voltage signal terminal and the second node; in the holding phase, the second control subcircuit transmits the second voltage signal received at the second voltage signal terminal to the third node in response to the third clock signal received at the third clock signal terminal, and transmits the first voltage signal received at the first voltage signal terminal to the second node; under the control of the first voltage signal at the second node, the first output subcircuit cuts off the second clock signal terminal and the cascade signal output terminal; under the control of the second voltage signal at the third node, the second output subcircuit transmits the third voltage signal received at the third voltage signal terminal to the cascade signal output terminal.

[0028] In some embodiments, in the output stage, under the control of the second voltage signal at the third node, the first sub-circuit controls the second voltage signal terminal and the fifth node to be cut off, and the second sub-circuit controls the fifth node and the second node to be cut off; under the control of the voltage at the second node, the three-level control sub-circuit transmits the third voltage signal received at the third voltage signal terminal to the fifth node. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0030] Figure 1is a structural diagram of a display device according to some embodiments;

[0031] Figure 2 is another structural diagram of a display device according to some embodiments;

[0032] Figure 3 A display device according to some embodiments includes a structure diagram of a display panel;

[0033] Figure 4 is a structural diagram of a display panel according to some embodiments;

[0034] Figure 5 is a structural diagram of a gate driving circuit according to some embodiments;

[0035] Figure 6 is a structural diagram of an input circuit according to some embodiments;

[0036] Figure 7 is a structural diagram of an input circuit including a transistor and a capacitor according to some embodiments;

[0037] Figure 8 is a timing diagram of an input circuit according to some embodiments;

[0038] Fig. 9 is another structural diagram of an input circuit according to some embodiments;

[0039] Fig.10 is another structural diagram of an input circuit according to some embodiments;

[0040] Fig.11 for Figure 4 A partial enlarged view of middle C;

[0041] Fig.12 A structural diagram of a transistor turned on in an input circuit according to some embodiments;

[0042] Fig.13 Another structural diagram of a transistor turned on in an input circuit according to some embodiments;

[0043] Fig.14 is another structural diagram of a transistor turned on in an input circuit according to some embodiments;

[0044] Fig.15 is another structural diagram of a transistor turned on in an input circuit according to some embodiments;

[0045] Fig.16 FIG. 4 is another structural diagram of a transistor turned on in an input circuit according to some embodiments. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0050] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0053] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0057] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0058] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0059] In the embodiments of the present disclosure, the capacitor may be a capacitor device manufactured separately through a process, for example, a capacitor device is realized by manufacturing a special capacitor electrode, and each capacitor electrode of the capacitor may be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), etc. The capacitor may also be a parasitic capacitor between transistors, or realized by the transistor itself and other devices and circuits, or realized by utilizing the parasitic capacitor between the circuits of the circuit itself.

[0060] In the circuit provided in the embodiments of the present disclosure, the first node, the second node, the third node, the fourth node and the fifth node do not represent actually existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0061] The "working level" of the shift register provided in the embodiment of the present disclosure refers to a level that can turn on the operated transistor included therein, and correspondingly, the "non-working level" refers to a level that cannot turn on the operated transistor included therein (i.e., the transistor is turned off).

[0062] The control electrode of each transistor provided in the embodiments of the present disclosure is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0063] like Figure 1 As shown, some embodiments of the present disclosure provide a display device 1000 , which may be any device that displays either moving (eg, video) or fixed (eg, still image) content and either text or images.

[0064] Exemplarily, the display device 1000 can be a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle display, a flight display, a projection device, or any other product or component with a display function.

[0065] In some examples, such as Figure 1 As shown, the display device 1000 may be a portable display product. For example, the display device 1000 may be Figure 1 The phone shown.

[0066] In some other examples, such as Figure 2 As shown, the display device 1000 may be a wearable device. For example, the display device may be Figure 2 The watch shown in.

[0067] In some embodiments, Figure 3 As shown, the display device 1000 includes a display panel 100 , a driving circuit board 200 , a housing 300 and a cover plate 400 .

[0068] The display panel 100 has a light-emitting side 100A and a non-light-emitting side 100B opposite to each other. The light-emitting side 100A refers to a side of the display panel 100 that can emit light ( Figure 3 The non-luminous side 100B refers to the other side opposite to the luminous side 100A ( Figure 3 The lower side of the display panel 100).

[0069] The driving circuit board 200 is disposed on the non-luminous side of the display panel 100 and is connected to the display panel 100 to provide a luminous signal to the display panel 100 .

[0070] The housing 300 may be a box-shaped structure with an opening. The display panel 100 and the driving circuit board 200 may be disposed in the housing 300 . The cover plate 400 is disposed on the light emitting side of the display panel 100 and located at the opening of the housing 300 .

[0071] like Figure 3As shown, the longitudinal section of the housing 300 may be, for example, U-shaped, the display panel 100 and the driving circuit board 200 are disposed in the housing 300 , and the cover plate 400 is disposed at the opening of the housing 300 .

[0072] The display panel 100 may be of various types and may be selected according to actual needs.

[0073] Exemplarily, the above-mentioned display panel 100 can be: an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a liquid crystal display (LCD) display panel or a micro light-emitting (MLED) display panel, etc., and the embodiments of the present disclosure are not specifically limited herein.

[0074] For example, Micro LED refers to an LED with a size (such as length) less than 50 μm, and Mini LED refers to an LED with a size (such as length) of 50 μm to 200 μm.

[0075] like Figure 4 As shown, the display panel 100 has a display area AA and a peripheral area BB disposed on at least one side of the display area AA. Figure 3 In the example, the peripheral area BB is arranged around the display area AA.

[0076] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as an OLED display panel as an example.

[0077] In some embodiments, Figure 4 As shown, the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20 .

[0078] The material used for the substrate 10 may include polymer resin or glass. Exemplarily, the substrate 10 may be flexible, and the material used for the substrate 10 may include polymer resin, such as one of polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenyl sulfide (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). Illustratively, the substrate 10 may be rigid, including a glass material including SiO 2 as a main component.

[0079] like Figure 4 As shown, a plurality of sub-pixels 20 are disposed on the substrate 10 and located in the display area AA.

[0080] The plurality of sub-pixels 20 may include a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color. The first color, the second color, and the third color are three primary colors. For example, the first color is red, the second color is blue, and the third color is green, which is not specifically limited in the embodiments of the present disclosure.

[0081] In some examples, the plurality of sub-pixels 20 may be arranged in a plurality of rows and columns, each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

[0082] In some embodiments, Figure 4 As shown, the display panel 100 may further include a plurality of gate lines GL and a plurality of data lines DL.

[0083] The plurality of gate lines GL extend along the first direction X and are arranged at intervals along the second direction Y. One gate line GL is connected to at least one row of sub-pixels 20. For example, one gate line GL is connected to one row of sub-pixels 20.

[0084] The plurality of data lines DL extend along the second direction Y and are arranged at intervals along the first direction X. One data line DL is connected to at least one column of sub-pixels 20. For example, one data line DL is connected to one column of sub-pixels 20.

[0085] In some embodiments, Figure 4 As shown, the display panel 100 further includes a gate driving circuit 30. The gate driving circuit 30 is located on a side of the substrate 10 close to the sub-pixel 20 and is located in the peripheral area BB. The gate driving circuit 30 is connected to the gate line GL. In this way, the gate driving circuit 30 can transmit a signal to the sub-pixel 20 to drive the sub-pixel 20 to display normally.

[0086] In some examples, such as Figure 4 As shown, the display panel 100 is provided with a gate driving circuit 30 on one side of the peripheral area BB, and drives the gate lines GL row by row in sequence from one side, that is, the gate driving circuit is a one-side driving circuit.

[0087] In other examples, the display panel 100 can set gate driving circuits 30 on two sides along the extension direction of the gate line GL in the peripheral area BB, and drive each gate line GL row by row from both sides simultaneously through two gate driving circuits 30, that is, the gate driving circuit 30 is double-sided driven.

[0088] In some other examples, the display panel 100 may be provided with gate driving circuits 30 on two sides along the extension direction of the gate line GL in the peripheral area BB, and the two gate driving circuits 30 may drive the gate lines GL row by row in sequence from both sides alternately, that is, the gate driving circuits 30 are cross-driven.

[0089] In some embodiments, Figure 4 As shown, the gate driving circuit 30 includes N stages of cascaded shift registers RS. In this case, the display panel 100 includes N stages of cascaded shift registers RS connected to N gate lines GL in one-to-one correspondence, where N is a positive integer.

[0090] For the above shift register RS, in some embodiments, Figure 4 As shown, the shift register RS ​​of the gate driving circuit 30 includes a scan signal output terminal OUTPUT1, and the scan signal output terminal OUTPUT1 is connected to the gate line GL, so that the scan signal output terminal OUTPUT1 outputs a gate scan signal to the sub-pixel 20 through the gate line GL connected thereto.

[0091] In some implementations, on the basis that the shift register RS ​​includes the scan signal output terminal OUTPUT1, the scan signal output terminal OUTPUT1 can also be connected to the lower-level shift register RS ​​to transmit the cascade signal to the lower-level shift register RS ​​as the input signal of the lower-level shift register RS. That is, the scan signal output terminal OUTPUT1 also serves as the cascade signal output terminal OUTPUT2, and the scan signal output terminal OUTPUT1 and the cascade signal output terminal OUTPUT2 are the same signal output terminal.

[0092] In some other embodiments, the shift register RS ​​of the gate driving circuit 30 further includes a cascade signal output terminal OUTPUT2, which can be connected to the shift register RS ​​of the next stage to transmit the cascade signal to the shift register RS ​​of the next stage as the input signal of the shift register RS ​​of the next stage. That is, the scanning signal output terminal OUTPUT1 and the cascade signal output terminal OUTPUT2 are different signal output terminals.

[0093] In some embodiments, Figure 4 As shown, the shift register RS ​​of the gate driving circuit 30 also includes a signal input terminal INPUT. In two adjacent shift registers RS, the cascade signal output terminal OUTPUT2 in the previous stage shift register RS ​​is connected to the signal input terminal INPUT of the next stage, and the signal input terminal INPUT of the first stage shift register RS ​​is connected to the initialization signal terminal STV.

[0094] Based on the above structure, the cascade structure of each level of shift register RS ​​in the gate driving circuit 30 can be:

[0095] In every two adjacent shift registers RS, the signal input terminal INPUT of the next shift register RS ​​is connected to the cascade signal output terminal OUTPUT2 of the previous shift register RS, and the signal input terminal INPUT of the first shift register RS ​​is connected to the signal input terminal STV. The scan signal output terminal OUTPUT1 of each shift register RS ​​is connected to at least one gate line GL.

[0096] In some examples, along the second direction Y, N stages of cascaded shift registers RS are arranged at intervals.

[0097] In some embodiments, Figure 5 As shown, the shift register RS ​​includes an input circuit RS1, a noise removal control circuit RS2, a noise removal circuit RS3 and an output circuit RS4.

[0098] In some embodiments, Figure 6 and Figure 7As shown, the input circuit RS1 includes a first input sub-circuit 1 , a second input sub-circuit 2 , a first output sub-circuit 3 and a first storage sub-circuit 4 .

[0099] In some examples, such as Figure 6 and Figure 7 As shown, the first input subcircuit 1 is coupled to the signal input terminal INPUT, the first node N1 and the first clock signal terminal CK1. The first input subcircuit 1 is configured to, in the input stage P1, transmit the working level received at the signal input terminal INPUT to the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, and in the output stage P2, in response to the first clock signal received at the first clock signal terminal CK1, cut off the signal input terminal INPUT and the first node N1, and in the output stage P2, receive the non-working level at the signal input terminal INPUT.

[0100] For example, Figure 6 and Figure 7 As shown, the first input sub-circuit 1 includes a first transistor T1, a first electrode of the first transistor T1 is connected to the signal input terminal INPUT, a second electrode is connected to the first node N1, and a control electrode is connected to the first clock signal terminal CK1.

[0101] In some examples, such as Figure 6 and Figure 7 As shown, the second input subcircuit 2 is coupled to the first node N1, the second node N2 and the first clock signal terminal CK1. The second input subcircuit 2 is configured to, in the input phase P1, transmit the working level at the first node N1 to the second node N2 in response to the first clock signal received at the first clock signal terminal CK1, and in the output phase P2, cut off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1.

[0102] For example, Figure 6 and Figure 7 The second input sub-circuit 2 shown comprises a second transistor T2 , a first electrode of the second transistor T2 is connected to the first node N1 , a second electrode of the second transistor T2 is connected to the second node N2 , and a control electrode of the second transistor T2 is connected to the first clock signal terminal CK1 .

[0103] In this way, the first transistor T1 and the second transistor T2 form a double-gate transistor, which can reduce leakage current.

[0104] In some examples, such as Figure 6 and Figure 7As shown, the first output subcircuit 3 is coupled to the second clock signal terminal CK2, the second node N2 and the cascade signal output terminal OUTPUT2. The first output subcircuit 3 is configured to, in the input phase P1, under the control of the voltage at the second node N2, transfer the non-operating level received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2. And in the output phase P2, under the control of the voltage at the second node N2, transfer the operating level received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2.

[0105] For example, Figure 7 As shown, the first output sub-circuit 3 includes a seventh transistor T7, a first electrode of the seventh transistor T7 is connected to the second clock signal terminal CK2, a second electrode is connected to the cascade signal output terminal OUTPUT2, and a control electrode is connected to the second node N2.

[0106] In some examples, such as Figure 6 and Figure 7 As shown, the first storage sub-circuit 4 is coupled to the second node N2 and the cascade signal output terminal OUTPUT2. The first storage sub-circuit 4 is configured to store the voltage at the second node N2 in the input phase P1, and write the difference between the working level and the non-working level received at the second clock signal terminal CK2 into the second node N2 in the output phase P2.

[0107] For example, Figure 7 As shown, the first storage sub-circuit 4 includes a first storage capacitor C1, a first plate of the first storage capacitor C1 is connected to the second node N2, and a second plate of the first storage capacitor C1 is connected to the cascade signal output terminal OUTPUT2.

[0108] Based on the above structure, Figure 8 As shown, in the input stage P1, the first input sub-circuit 1 transmits the working level received at the signal input terminal INPUT to the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, the second input sub-circuit 2 transmits the working level at the first node N1 to the second node N2 in response to the first clock signal received at the first clock signal terminal CK1, the first storage sub-circuit 4 stores the working level at the second node N2, and under the control of the working level at the second node N2, the first output sub-circuit 3 transmits the non-working level received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2.

[0109] In the output stage P2, the first input subcircuit 1 cuts off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, and the signal received at the signal input terminal INPUT is at a non-working level. The second input subcircuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1, and under the control of the working level at the second node N2, the first output subcircuit 3 transfers the working level received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2, and the first storage subcircuit 4 writes the difference between the working level and the non-working level received at the second clock signal terminal CK2 into the second node N2.

[0110] In some examples, the working level received at the signal input terminal INPUT is a low level, for example, the working level received at the signal input terminal INPUT is Vss, and the non-working level received at the signal input terminal INPUT is a high level, for example, the non-working level received at the signal input terminal INPUT is Vdd. The working level received at the second clock signal terminal CK2 is a low level, for example, the working level received at the second clock signal terminal CK2 is Vss, and the non-working level received at the second clock signal terminal CK2 is a high level, for example, the non-working level received at the second clock signal terminal CK2 is Vdd.

[0111] At this time, in the input stage P1, the Vss signal received at the signal input terminal INPUT is transmitted to the first node N1 through the first input sub-circuit 1, the Vss signal received at the first node N1 is transmitted to the second node N2 and stored in the first storage sub-circuit 4, and under the control of the Vss signal received at the second node N2, the Vdd signal received at the second clock signal terminal CK2 is transmitted to the cascade signal output terminal OUTPUT2 through the first output sub-circuit 3.

[0112] In the output stage P2, the Vdd signal received at the signal input terminal INPUT cannot be transmitted to the first node N1 and the second node N2 through the first input sub-circuit 1, and the second node N2 is still a Vss signal. Under the control of the Vss signal at the second node N2, the Vss signal received at the second clock signal terminal CK2 is transmitted to the cascade signal output terminal OUTPUT2 through the first output sub-circuit 3. The signal received at the cascade signal output terminal OUTPUT2 changes from Vdd to Vss, that is, the voltage at the cascade signal output terminal OUTPUT2 drops by Vdd-Vss, and the first storage sub-circuit 4 causes the voltage at the second node N2 to also drop by Vdd-Vss, that is, the voltage at the second node N2 is 2Vss-Vdd.

[0113] In the related art, the display effect of the display panel is poor. The inventor has found through research that the material of the transistor of the first input subcircuit includes low-temperature polysilicon, that is, the transistor of the first input subcircuit is a low-temperature polysilicon transistor. The material of the transistor of the second input subcircuit includes low-temperature polysilicon, that is, the transistor of the second input subcircuit is a low-temperature polysilicon transistor. The low-temperature polysilicon transistor has a leakage tail characteristic, that is, when the low-temperature polysilicon transistor is cut off, the higher the source-drain voltage difference of the low-temperature polysilicon transistor, the greater the leakage current of the low-temperature polysilicon transistor.

[0114] According to the above, in the output stage, the voltage difference between the signal input terminal and the second node is Vdd-(2Vss-Vdd)=2Vdd-2Vss, that is, the voltage difference between the signal input terminal and the second node is large. This will cause the leakage current of the transistor of the first input sub-circuit and the transistor of the second input sub-circuit to be large, and the signal input terminal leaks to the second node. The voltage at the second node will change, that is, the voltage at the second node is unstable, which will cause the conduction degree of the transistor included in the first output sub-circuit to change, and the working level received at the cascade signal output terminal is unstable, resulting in poor display effect of the display panel.

[0115] In order to solve the above technical problems, Figure 6 and Figure 7 As shown, some embodiments of the present disclosure provide a shift register RS, and the shift register RS ​​further includes a first control subcircuit 5 .

[0116] In some examples, the first control subcircuit 5 is coupled to the second clock signal terminal CK2, the cascade signal output terminal OUTPUT2 (current stage) and the first node N1. The first control subcircuit 5 is configured to, in the output stage P2, in response to the working level at the cascade signal output terminal OUTPUT2, transmit the working level received at the second clock signal terminal CK2 to the first node N1.

[0117] Exemplarily, the first control subcircuit 5 includes a third transistor T3 , a first electrode of the third transistor T3 is connected to the second clock signal terminal CK2 , a second electrode is connected to the first node N1 , and a control electrode is connected to the cascade signal output terminal OUTPUT2 .

[0118] In some examples, the working level received at the second clock signal terminal CK2 is a low level, for example, the working level received at the second clock signal terminal CK2 is Vss, and the non-working level received at the second clock signal terminal CK2 is a high level, for example, the non-working level received at the second clock signal terminal CK2 is Vdd.

[0119] At this time, in the input stage P1, under the control of the Vdd signal received at the cascade signal output terminal OUTPUT2, the first control subcircuit 5 controls the second clock signal terminal CK2 and the first node N1 to be cut off. In the output stage P2, under the control of the VSS signal at the cascade signal output terminal OUTPUT2, the first control subcircuit 5 transfers the Vss signal received at the second clock signal terminal CK2 to the first node N1. At this time, the voltage difference between the first node N1 and the second node N2 is Vss-(2Vss-Vdd)=Vdd-Vss.

[0120] By configuring in this manner, the first control subcircuit 5 can make the voltage difference between the first node N1 and the second node N2 Vdd-Vss, that is, the source-drain voltage difference of the transistor included in the second input subcircuit 2 is Vdd-Vss. In this way, the source-drain voltage difference of the transistor included in the second input subcircuit 2 is smaller, and the leakage current of the transistor included in the second input subcircuit 2 is smaller or non-existent, thereby reducing the risk of leakage from the first node N1 to the second node N2, which is beneficial to improving the voltage stability at the second node N2, improving the stability of the conduction degree of the transistor included in the first output subcircuit 3, and improving the stability of the working level received at the cascade signal output terminal OUTPUT2, thereby improving the display effect of the display panel 100.

[0121] In some embodiments, Figure 6 and Figure 7 As shown, the shift register RS ​​further includes a third input sub-circuit 6 , a second control sub-circuit 7 and a second output sub-circuit 8 .

[0122] In some examples, such as Figure 6 and Figure 7 As shown, the third input subcircuit 6 is coupled to the first voltage signal terminal VDD1, the third node N3 and the fourth node N4. The third input subcircuit 6 is configured to, in the input phase P1, under the control of the voltage of the fourth node N4, transfer the first voltage signal received at the first voltage signal terminal VDD1 to the third node N3. The first voltage signal is a non-operating level.

[0123] For example, Figure 7 As shown, the third input sub-circuit 6 includes an eighth transistor T8, a first electrode of the eighth transistor T8 is connected to the second voltage signal terminal, a second electrode is connected to the third node N3, and a control electrode is connected to the fourth node N4.

[0124] In some examples, such as Figure 6 and Figure 7As shown, the second control subcircuit 7 is coupled to the second node N2, the third node N3, the first voltage signal terminal VDD1, the second voltage signal terminal VSS and the third clock signal terminal CK3. The second control subcircuit 7 is configured to, in the holding phase P3, in response to the third clock signal received at the third clock signal terminal CK3, transmit the second voltage signal received at the second voltage signal terminal VSS to the third node N3, and transmit the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. The second voltage signal is a working level.

[0125] In some examples, such as Figure 6 and Figure 7 As shown, the second output subcircuit 8 is coupled to the third voltage signal terminal VDD3, the third node N3 and the cascade signal output terminal OUTPUT2. The second output subcircuit 8 is configured to, in the holding phase, under the control of the voltage at the third node N3, transmit the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2, and the third voltage signal is a non-working level.

[0126] For example, Figure 7 As shown, the second output sub-circuit 8 includes a ninth transistor T9, a first electrode of the ninth transistor T9 is connected to the third voltage signal terminal VDD3, a second electrode is connected to the cascade signal output terminal OUTPUT2, and a control electrode is connected to the third node N3.

[0127] Based on the above structure, in the input stage P1, under the control of the voltage at the fourth node N4, the third input sub-circuit 6 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the third node N3, and under the control of the first voltage signal at the third node N3, the second output sub-circuit 8 turns off the third voltage signal terminal VDD3 and the cascade signal output terminal OUTPUT2. The second control sub-circuit 7 controls the second voltage signal terminal VSS and the third node N3 to be turned off in response to the third clock signal received at the third clock signal terminal CK3, and under the control of the first voltage signal at the third node N3, the second control sub-circuit 7 turns off the first voltage signal terminal VDD1 and the second node N2.

[0128] In the output stage P2, under the control of the first voltage signal at the third node N3, the second output sub-circuit 8 turns off the third voltage signal terminal VDD3 and the cascade signal output terminal OUTPUT2. The second control sub-circuit 7 controls the second voltage signal terminal VSS and the third node N3 to be turned off in response to the third clock signal received at the third clock signal terminal CK3, and under the control of the first voltage signal at the third node N3, the second control sub-circuit 7 turns off the first voltage signal terminal VDD1 and the second node N2.

[0129] In the holding phase P3, the second control subcircuit 7 transmits the second voltage signal received at the second voltage signal terminal VSS to the third node N3, and transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2 in response to the third clock signal received at the third clock signal terminal CK3. Under the control of the second voltage signal at the third node N3, the second output subcircuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2. Under the control of the third voltage signal at the second node N2, the first input subcircuit 1 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2.

[0130] In some examples, such as Figure 8 As shown, the holding phase P3 includes a first holding phase P31, a second holding phase P32 and a third holding phase P33.

[0131] In the first holding phase P31, the first input subcircuit 1 cuts off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, and the signal received at the signal input terminal INPUT is at a non-operating level. The second input subcircuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. Under the control of the voltage at the fourth node N4, the third input subcircuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3. The second control subcircuit 7 transmits the second voltage signal received at the second voltage signal terminal VSS to the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. Under the control of the second voltage signal at the third node N3, the second output subcircuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2. The second control subcircuit 7 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the first voltage signal at the second node N2, the first output subcircuit 3 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2. The level received at the second clock signal terminal CK2 is a non-working level. Under the control of the third voltage signal at the cascade signal output terminal OUTPUT2, the first control subcircuit 5 cuts off the second clock signal terminal CK2 and the first node N1.

[0132] In the second holding phase P32, the first input subcircuit 1 transmits the non-operating level received at the signal input terminal INPUT to the first node N1 in response to the first clock signal received at the first clock signal terminal CK1. The second input subcircuit 2 transmits the non-operating level at the first node N1 to the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. Under the control of the voltage of the fourth node N4, the third input subcircuit 6 turns off the second voltage signal terminal VSS and the third node N3. The second control subcircuit 7 turns off the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. Under the control of the second voltage signal at the third node N3, the second output subcircuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2, and transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the first voltage signal and / or the non-working level at the second node N2, the first output sub-circuit 3 turns off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is the non-working level. Under the control of the first voltage signal at the cascade signal output terminal OUTPUT2, the first control sub-circuit 5 turns off the cascade signal output terminal OUTPUT2 and the first node N1.

[0133] In the third holding phase P33, the first input subcircuit 1 cuts off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, and the signal received at the signal input terminal INPUT is at a non-operating level. The second input subcircuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. Under the control of the voltage of the fourth node N4, the third input subcircuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The second control subcircuit 7 cuts off the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. Under the control of the second voltage signal at the third node N3, the second output subcircuit 8 transfers the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2, and transfers the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the first voltage signal at the second node N2, the first output subcircuit 3 turns off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is the working level. Under the control of the first voltage signal at the cascade signal output terminal OUTPUT2, the first control subcircuit 5 turns off the cascade signal output terminal OUTPUT2 and the first node N1.

[0134] In some examples, the working level received at the signal input terminal INPUT is a low level, for example, the working level received at the signal input terminal INPUT is Vss, and the non-working level received at the signal input terminal INPUT is a high level, for example, the non-working level received at the signal input terminal INPUT is Vdd. The working level received at the second clock signal terminal CK2 is a low level, for example, the working level received at the second clock signal terminal CK2 is Vss, and the non-working level received at the second clock signal terminal CK2 is a high level, for example, the non-working level received at the second clock signal terminal CK2 is Vdd. The first voltage signal received at the first voltage signal terminal VDD1 is a high level, for example, the first voltage signal received at the first voltage signal terminal VDD1 is Vdd. The second voltage signal received at the second voltage signal terminal VSS is a low level, for example, the second voltage signal received at the second voltage signal terminal VSS is Vss. The third voltage signal received at the third voltage signal terminal VDD3 is a high level, for example, the third voltage signal received at the third voltage signal terminal VDD3 is Vdd.

[0135] At this time, in the input stage P1, the Vss signal received at the signal input terminal INPUT is transmitted to the second node N2 through the first input sub-circuit 1 and the second input sub-circuit 2. Under the control of the Vss signal at the second node N2, the first output sub-circuit 3 transmits the Vdd signal received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2.

[0136] Under the control of the voltage of the fourth node N4, the third input sub-circuit 6 transmits the Vdd signal received at the first voltage signal terminal VDD1 to the third node N3, and the second control sub-circuit 7 controls the second voltage signal terminal VSS and the third node N3 to be cut off in response to the third clock signal received at the third clock signal terminal CK3, and the Vss signal received at the second voltage signal terminal VSS cannot be transmitted to the third node N3 through the second control sub-circuit 7, so that the received signal at the third node N3 is the Vdd signal.

[0137] Under the control of the Vdd signal at the third node N3, the second control subcircuit 7 cuts off the first voltage signal terminal VDD1 and the second node N2, and the Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the second node N2 through the second control subcircuit 7, so that the received signal at the second node N2 is a Vss signal. Under the control of the Vdd signal at the third node N3, the second output subcircuit 8 cuts off the third voltage signal terminal VDD3 and the cascade signal output terminal OUTPUT2. The Vdd signal received at the third voltage signal terminal VDD3 cannot be transmitted to the cascade signal output terminal OUTPUT2 through the second output subcircuit 8.

[0138] In the output phase P2, the first input sub-circuit 1 controls the signal input terminal INPUT and the first node N1 to be turned off in response to the first clock signal received at the first clock signal terminal CK1, and the second input sub-circuit 2 controls the first node N1 and the second node N2 to be turned off in response to the first clock signal received at the first clock signal terminal CK1. The Vdd signal received at the signal input terminal INPUT cannot be transmitted to the second node N2.

[0139] The second control sub-circuit 7 controls the second voltage signal terminal VSS and the third node N3 to be cut off in response to the third clock signal received at the third clock signal terminal CK3, so that the Vss signal received at the second voltage signal terminal VSS cannot be transmitted to the third node N3 through the second control sub-circuit 7, so that the received signal at the third node N3 is a Vdd signal.

[0140] Under the control of the Vdd signal at the third node N3, the second control subcircuit 7 cuts off the first voltage signal terminal VDD1 and the second node N2, and the Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the second node N2. Under the control of the Vss signal at the second node N2, the first output subcircuit 3 transmits the Vss signal received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2. Under the control of the Vdd signal at the third node N3, the second output subcircuit 8 cuts off the first voltage signal terminal VDD1 and the cascade signal output terminal OUTPUT2, so that the signal at the cascade signal output terminal OUTPUT2 is a Vss signal. The first storage subcircuit 4 writes the difference between the Vdd signal and the Vss signal received at the second clock signal terminal into the second node, and the received signal at the second node N2 is 2Vss-Vdd.

[0141] In the first holding phase P31, the first input sub-circuit 1 cuts off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1. The second input sub-circuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. The Vdd signal received at the signal input terminal INPUT cannot be transmitted to the second node N2.

[0142] Under the control of the voltage of the fourth node N4 , the third input sub-circuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3 , and the Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the third node N3 .

[0143] The second control sub-circuit 7 transmits the Vss signal received at the second voltage signal terminal VSS to the third node N3 in response to the third clock signal received at the third clock signal terminal CK3 .

[0144] Under the control of the Vss signal at the third node N3, the second control subcircuit 7 transfers the Vdd signal received at the first voltage signal terminal VDD1 to the second node N2, and under the control of the Vdd signal at the second node N2, the first output subcircuit 3 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2, so that the Vdd signal received at the second clock signal terminal CK2 cannot be transferred to the cascade signal output terminal OUTPUT2. Under the control of the Vss signal at the third node N3, the second output subcircuit 8 transfers the Vdd signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2.

[0145] Under the control of the Vdd signal at the cascade signal output terminal OUTPUT2, the first control subcircuit 5 cuts off the second clock signal terminal CK2 and the first node N1, so that the Vdd signal received at the second clock signal terminal CK2 cannot be transmitted to the first node N1.

[0146] In the second holding stage P32, the first input sub-circuit 1 responds to the first clock signal received at the first clock signal terminal CK1, and transmits the Vdd signal received at the signal input terminal INPUT to the first node N1, and the second input sub-circuit 2 responds to the first clock signal received at the first clock signal terminal CK1, and transmits the Vdd signal received at the first node N1 to the second node N2.

[0147] Under the control of the voltage of the fourth node N4 , the third input sub-circuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3 , and the Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the third node N3 .

[0148] The second control subcircuit 7 cuts off the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. The Vss signal received at the second voltage signal terminal VSS cannot be transmitted to the third node N3, and the signal received at the third node N3 is the Vss signal received at the third node N3 in the first holding stage P31, that is, in the second holding stage P32, the signal received at the third node N3 is still the Vss signal.

[0149] Under the control of the Vss signal at the third node N3, the second control subcircuit 7 transfers the Vdd signal received at the first voltage signal terminal VDD1 to the second node N2, and under the control of the Vdd signal at the second node N2, the first output subcircuit 3 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2, so that the Vdd signal received at the second clock signal terminal CK2 cannot be transferred to the cascade signal output terminal OUTPUT2. Under the control of the Vss signal at the third node N3, the second output subcircuit 8 transfers the Vdd signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2.

[0150] Under the control of the Vdd signal at the cascade signal output terminal OUTPUT2, the first control subcircuit 5 turns off the second clock signal terminal CK2 and the first node N1. The Vdd signal received at the cascade signal output terminal OUTPUT2 cannot be transmitted to the first node N1.

[0151] In the third holding phase P33, the first input sub-circuit 1 cuts off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1. The second input sub-circuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. The Vdd signal received at the signal input terminal INPUT cannot be transmitted to the second node N2.

[0152] Under the control of the voltage of the fourth node N4 , the third input sub-circuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3 , and the Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the third node N3 .

[0153] The second control subcircuit 7 cuts off the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. The Vss signal received at the second voltage signal terminal VSS cannot be transmitted to the third node N3. The signal received at the third node N3 is the Vss signal received at the third node N3 in the second holding stage P32, that is, in the third holding stage P33, the signal received at the third node N3 is still the VSS signal.

[0154] Under the control of the Vss signal at the third node N3, the second control subcircuit 7 transfers the Vdd signal received at the second voltage signal terminal VSS to the second node N2, and under the control of the Vdd signal received at the second node N2, the first output subcircuit 3 cuts off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2, and the Vss signal received at the second clock signal terminal CK2 cannot be transferred to the cascade signal output terminal OUTPUT2. Under the control of the Vss signal at the third node N3, the second output subcircuit 8 transfers the Vdd signal received at the first voltage signal terminal VDD1 to the cascade signal output terminal OUTPUT2.

[0155] Under the control of the Vdd signal received at the cascade signal output terminal OUTPUT2, the first control subcircuit 5 cuts off the second clock signal terminal CK2 and the first node N1, so that the Vdd signal received at the cascade signal output terminal OUTPUT2 cannot be transmitted to the first node N1.

[0156] In some embodiments, Figure 6 and Figure 7 As shown, the second control subcircuit 7 includes a primary control subcircuit 71 and a secondary control subcircuit 72 .

[0157] In some examples, such as Figure 6 and Figure 7 As shown, the primary control subcircuit 71 is coupled to the third node N3, the second voltage signal terminal VSS and the third clock signal terminal CK3. The primary control subcircuit 71 is configured to, in the holding phase P3, transmit the second voltage signal received at the second voltage signal terminal VSS to the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. The second voltage signal is a working level.

[0158] For example, Figure 7 As shown, the first-level control subcircuit 71 includes a sixth transistor T6, a first electrode of the sixth transistor T6 is coupled to the second voltage signal terminal VSS, a second electrode is coupled to the third node N3, and a control electrode is coupled to the third clock signal terminal CK3.

[0159] In some examples, such as Figure 6 and Figure 7 As shown, the secondary control subcircuit 72 is coupled to the second node N2, the third node N3 and the first voltage signal terminal VDD1. The secondary control subcircuit 72 is configured to, in the holding phase P3, under the control of the voltage at the third node N3, transfer the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2.

[0160] In some embodiments, Figure 6 and Figure 7As shown, the secondary control subcircuit 72 includes a first subcircuit 721 and a second subcircuit 722 .

[0161] In some examples, such as Figure 6 and Figure 7 As shown, the first subcircuit 721 is coupled to the third node N3, the first voltage signal terminal VDD1 and the fifth node N5. The first subcircuit 721 is configured to cut off the first voltage signal terminal VDD1 and the fifth node N5 under the control of the second voltage signal at the third node N3 in the output phase P2.

[0162] For example, Figure 7 As shown, the first subcircuit 721 includes a fourth transistor T4, a first electrode of the fourth transistor T4 is connected to the first voltage signal terminal VDD1, a second electrode is connected to the fifth node N5, and a control is connected to the third node N3. For example, the fourth transistor T4 is a low temperature polysilicon transistor.

[0163] like Figure 6 and Figure 7 As shown, the second sub-circuit 722 is coupled to the second node N2, the third node N3 and the fifth node N5. The second sub-circuit 722 is configured to, in the output phase P2, under the control of the voltage at the third node N3, turn off the fifth node N5 and the second node N2.

[0164] For example, Figure 7 As shown, the second subcircuit 722 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is connected to the fifth node N5, a second electrode is connected to the second node N2, and a control electrode is connected to the third node N3. For example, the fifth transistor T5 is a low temperature polysilicon transistor.

[0165] On this basis, if Figure 6 and Figure 7 As shown, the second control subcircuit 7 further includes a three-level control subcircuit 73 .

[0166] In some examples, the three-level control subcircuit 73 is coupled to the fifth node N5, the second node N2, and the second voltage signal terminal VSS. The three-level control subcircuit 73 is configured to, in the output phase P2, under the control of the voltage of the second node N2, transmit the second voltage signal received at the second voltage signal terminal VSS to the fifth node N5.

[0167] For example, Figure 7 As shown, the three-stage control subcircuit 73 includes a tenth transistor T10, a first electrode of the tenth transistor T10 is connected to the second voltage signal terminal VSS, a second electrode is connected to the fifth node N5, and a control electrode is connected to the second node N2.

[0168] Based on the above structure, in the output stage P2, under the control of the voltage at the third node N3, the first sub-circuit 721 controls the first voltage signal terminal VDD1 and the fifth node N5 to be turned off, and the second sub-circuit 722 controls the fifth node N5 and the second node N2 to be turned off. Under the control of the voltage at the second node N2, the three-level control sub-circuit 73 transfers the second voltage signal received at the second voltage signal terminal VSS to the fifth node N5.

[0169] In some examples, the second voltage signal received at the second voltage signal terminal VSS is at a low level, for example, the second voltage signal received at the second voltage signal terminal VSS is Vss.

[0170] At this time, in the input stage P1, under the control of the Vss signal at the second node N2, the three-level control subcircuit 73 transmits the Vss signal received at the third voltage signal terminal VDD3 to the fifth node N5. In the output stage P2, under the control of the Vss signal or the 2Vss-Vdd signal at the second node N2, the three-level control subcircuit 73 transmits the Vss signal received at the second voltage signal terminal VSS to the fifth node N5. At this time, the voltage difference between the fifth node N5 and the second node N2 is Vss-(2Vss-Vdd)=Vdd-Vss.

[0171] Arranged in this way, the three-level control subcircuit 73 can make the voltage difference between the fifth node N5 and the second node N2 Vdd-Vss, that is, the source-drain voltage difference of the transistor included in the second subcircuit 722 is Vdd-Vss. In this way, the source-drain voltage difference of the transistor included in the second subcircuit 722 is smaller, and the leakage current of the transistor included in the second subcircuit 722 is smaller or non-existent, thereby reducing the risk of leakage from the fifth node N5 to the second node N2, which is beneficial to further improve the voltage stability at the second node N2, improve the stability of the conduction degree of the transistor of the first output subcircuit 3, and improve the stability of the working level received at the cascade signal output terminal OUTPUT2, thereby improving the display effect of the display panel 100.

[0172] In some embodiments, Figure 6 and Figure 7 As shown, the fourth node N4 is connected to the signal input terminal INPUT.

[0173] In other embodiments, Fig. 9 As shown, the fourth node N4 is connected to the first node N1.

[0174] In some other embodiments, Fig.10 As shown, the fourth node N4 and the fifth node N5 are connected.

[0175] In some implementations, such as Figure 6 and Figure 7As shown, the shift register RS ​​further includes a second storage subcircuit 9 .

[0176] In some examples, the second storage sub-circuit 9 is coupled to the third voltage signal terminal VDD3 and the third node N3. The second storage sub-circuit 9 is configured to store a voltage at the third node N3.

[0177] For example, Figure 7 As shown, the second storage sub-circuit 9 includes a second storage capacitor C2, a first plate of the second storage capacitor C2 is connected to the third node N3, and a second plate is connected to the third voltage signal terminal VDD3.

[0178] In some embodiments, Fig.11 As shown, the gate drive circuit 30 also includes a plurality of clock signal lines CL, and the plurality of clock signal lines CL are divided into a plurality of groups. In the same group, in adjacent bipolar shift registers RS, the clock signal line CL connected to the second clock signal terminal CK2 in the previous shift register RS ​​is the same as the clock signal line CL connected to the first clock signal terminal CK1 in the next shift register RS, the clock signal line CL connected to the third clock signal terminal CK3 in the previous shift register RS ​​is the same as the clock signal line CL connected to the second clock signal terminal CK2 in the next shift register RS, the clock signal line CL connected to the first clock signal terminal CK1 in the previous shift register RS ​​is different from the clock signal line CL connected to the third clock signal terminal CK3 in the next shift register RS, and the clock signal lines CL connected to the same clock signal terminals in any two shift registers RS are different.

[0179] In this way, the number of the clock signal lines CL is greater than three, so that the clock frequency on the clock signal lines CL can be reduced, which is beneficial to reducing the power consumption of the display panel 100 .

[0180] In some examples, the gate driving circuit 30 includes four clock signal lines CL. For the convenience of description, they are marked as the first clock signal line CL(1), the second clock signal line CL(2), the third clock signal line CL(3) and the fourth clock signal line CL(4) in the direction away from the display area AA, from the first clock signal line CL to the fourth clock signal line CL.

[0181] The plurality of shift registers RS are divided into a plurality of groups, and each group includes four shift registers RS. For the convenience of description, the four shift registers RS included in a group of shift registers RS are marked as a first-stage shift register RS ​​(1), a second-stage shift register RS ​​(2), a third-stage shift register RS ​​(3), and a fourth-stage first shift register RS ​​(4) in sequence according to the cascade order.

[0182] In some examples, such as Fig.11 As shown, the first clock signal terminal CK1 of the first-stage shift register RS(1) is connected to the first clock signal line CL(1), the second clock signal terminal CK2 is connected to the second clock signal line CL(2), and the third clock signal line CL is connected to the third clock signal line CL(3). The first clock signal terminal CK1 of the second-stage shift register RS(2) is connected to the second clock signal line CL(2), the second clock signal terminal CK2 is connected to the third clock signal line CL(3), and the third clock signal terminal CK3 is connected to the fourth clock signal line CL(4). The first clock signal terminal CK1 of the third-stage shift register RS(3) is connected to the third clock signal line CL(3), the second clock signal terminal CK2 is connected to the fourth clock signal line CL(4), and the third clock signal terminal CK3 is connected to the first clock signal line CL(1). The first clock signal terminal CK1 of the fourth stage shift register RS(4) is connected to the fourth clock signal line CL(4), the second clock signal terminal CK2 is connected to the first clock signal line CL(1), and the third clock signal terminal CK3 is connected to the second clock signal line CL(2).

[0183] In some embodiments, Fig.11 As shown, the gate driving circuit 30 further includes a first voltage signal line VL1 and a second voltage signal line VL2. The first voltage signal line VL1 is connected to the first voltage signal terminal VDD1 and the shift register RS. The second voltage signal line VL2 is connected to the third voltage signal terminal VDD3 and the shift register RS.

[0184] In this way, the first voltage signal terminal VDD1 and the third voltage signal terminal VDD3 are independent of each other, which can reduce the influence between the second control subcircuit 7 and the second output subcircuit 8 , and is beneficial to improving the display effect of the display panel 100 .

[0185] On this basis, the width of the first voltage signal line VL1 is smaller than the width of the second voltage signal line VL2.

[0186] In this way, the width of the second voltage signal line VL2 is larger, the resistance of the second voltage signal line VL2 is smaller, and the voltage drop on the second voltage signal line VL2 is smaller, which can improve the signal quality at the cascade signal output terminal OUTPUT2 and is beneficial to improving the display effect of the display panel 100.

[0187] In some examples, the line width of the first voltage signal line VL1 is 3 μm to 10 μm.

[0188] For example, the line width of the first voltage signal line VL1 is 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm.

[0189] In some examples, the line width of the second voltage signal line VL2 is 10 μm to 20 μm.

[0190] For example, the line width of the second voltage signal line VL2 is 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, or 20 μm.

[0191] In some embodiments, a plurality of shift registers RS are arranged at intervals along the second direction Y. The first voltage signal line VL1 extends along the second direction Y, and along the first direction X, the first voltage signal line VL1 is located between the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10, and the seventh transistor T7 and the ninth transistor T9. The second voltage signal line VL2 extends along the second direction, and along the first direction X, the second voltage signal line VL2 is located on the seventh transistor T7 and the ninth transistor T9, away from the first voltage signal line VL1.

[0192] In this way, the line width of the first voltage signal line VL1 is narrower, which can shorten the length of the connection line across the first voltage signal line VL1 and reduce the voltage drop of the connection line, which is beneficial to improving the signal quality on the connection line and improving the display effect of the display panel 100.

[0193] In some embodiments, Fig.11 As shown, the first storage capacitor C1 is located on the side of the seventh transistor T7 and the ninth transistor T9, away from the first voltage signal line VL1, the orthographic projection of the second voltage signal line VL2 on the reference plane overlaps with the orthographic projection of the first storage capacitor C1 on the reference plane, and along the first direction X, both ends of the first storage capacitor C1 exceed both ends of the second voltage signal line VL2. The reference plane is parallel to the surface of the substrate 10 close to the sub-pixel 20.

[0194] In this way, along the first direction X, the total width of the first storage capacitor C1, the first voltage signal line VL1 and the second voltage signal line VL2 is narrow, which can shorten the width of the peripheral area BB and help the display panel 100 achieve a narrow frame.

[0195] In some embodiments, Fig.11As shown, the second storage capacitor C2 is located on the side of the first storage capacitor C1 away from the next-stage shift register RS, and is located on the side of the seventh transistor T7 and the ninth transistor T9 away from the first voltage signal line VL1. The orthographic projection of the second storage capacitor C2 on the reference plane overlaps with the orthographic projection of the second voltage signal line VL2 on the reference plane, and along the first direction, both ends of the second storage capacitor C2 exceed both ends of the second voltage signal line VL2.

[0196] In some embodiments, Fig.11 As shown, the clock signal line CL extends along the second direction Y, and the clock signal line CL is located on the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10, away from the first voltage signal line VL1.

[0197] The gate driving circuit 30 further includes a third voltage signal line VL3 , which is connected to the second voltage signal terminal VSS and the shift register RS. The third voltage signal line VL3 extends along the second direction and is located between the clock signal line CL and the shift register RS.

[0198] In some embodiments, Fig.11 As shown, the fourth transistor T4 and the fifth transistor T5 are located between the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10 and the first voltage signal line VL1, and along the second direction, the fourth transistor T4 is located on one side of the fifth transistor T5.

[0199] By setting it in this way, the distance between the fourth transistor T4 and the first voltage signal line VL1 can be shortened, the length of the connecting line connecting the fourth transistor T4 and the first voltage signal line VL1 can be shortened, the voltage drop on the connecting line connecting the fourth transistor T4 and the first voltage signal line VL1 can be reduced, and the quality of the signal transmitted from the first voltage signal line VL1 to the fourth transistor T4 can be improved, which is beneficial to improving the display effect of the display panel 100.

[0200] In some embodiments, Fig.11 As shown, the third transistor T3 and the sixth transistor T6 are located between the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8 and the tenth transistor T10 and the third voltage signal line VL3, and along the second direction, the third transistor T3 is located on one side of the fifth transistor T5.

[0201] By setting it in this way, on the one hand, the distance between the third transistor T3 and the clock signal line CL can be shortened, the length of the connecting line connecting the third transistor T3 and the clock signal line CL can be shortened, the voltage drop on the connecting line connecting the third transistor T3 and the clock signal line CL can be reduced, and the quality of the signal transmitted from the clock signal line CL to the third transistor T3 can be improved, which is beneficial to improving the display effect of the display panel 100.

[0202] On the other hand, the distance between the sixth transistor T6 and the third voltage signal line VL3 can be made shorter, the length of the connecting line connecting the sixth transistor T6 and the third voltage signal line VL3 can be shortened, the voltage drop on the connecting line connecting the sixth transistor T6 and the third voltage signal line VL3 can be reduced, and the quality of the signal transmitted from the third voltage signal line VL3 to the sixth transistor T6 can be improved, which is beneficial to improving the display effect of the display panel 100.

[0203] In some embodiments, Fig.11 As shown, the eighth transistor T8 is located between the fourth transistor T4 and the fifth transistor T5, and between the third transistor T3 and the sixth transistor T6, and is located on the side of the first transistor T1, the second transistor T2 and the tenth transistor T10 away from the next-stage shift register RS; the fourth transistor T4 is located on the side of the fifth transistor T5 away from the next-stage shift register RS, and the ninth transistor T9 is located on the side of the seventh transistor T7 away from the next-stage shift register RS;

[0204] The gate drive circuit 30 further includes a first connection line 31, which is connected to the first electrode of the third transistor T3, the second electrode of the seventh transistor T7, and the gate of the eighth transistor T8 of the next stage. The first connection line 31 is located on a side of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the tenth transistor T10 close to the next electrode shift register RS.

[0205] By setting it in this way, the distance between the eighth transistor T8 and the first connecting line 31 can be shortened, the length of the connecting line connecting the eighth transistor T8 and the first connecting line 31 can be shortened, the voltage drop on the connecting line connecting the eighth transistor T8 and the first connecting line 31 can be reduced, and the quality of the signal transmitted from the first connecting line 31 to the eighth transistor T8 can be improved, which is beneficial to improving the display effect of the display panel 100.

[0206] In some embodiments, Fig.11As shown, along the second direction Y, the channel portion of the first transistor T1 is located on the side of the channel portion of the second transistor T2 close to the previous stage shift register RS, along the first direction X, the channel portion of the first transistor T1 is located on the side of the channel portion of the second transistor T2 away from the first voltage signal line VL1, and the channel portion of the third transistor T3 is located on the side of the channel portion of the first transistor T1 and the channel portion of the second transistor T2 away from the first voltage signal line VL1.

[0207] In this way, the distance between the first transistor T1 and the third transistor T3 is shorter, and the distance between the second transistor T2 and the third transistor T3 is shorter, which is beneficial to reducing the area occupied by the first transistor T1, the second transistor T2 and the third transistor T3, thereby facilitating the realization of a narrow frame of the display panel 100.

[0208] The following is a detailed description of the working process of the shift register RS ​​in a display frame period P in conjunction with the timing diagram. The following embodiments take the above-mentioned transistors as P-type as an example.

[0209] In some embodiments, Figure 7 and Figure 8 As shown, the fourth node N4 is connected to the signal input terminal INPUT. One display frame period P includes an input phase P1, an output phase P2, a first holding phase P31, a second holding phase P32 and a third holding phase P33.

[0210] like Figure 8 and Fig.12As shown, in the input phase P1, the first input subcircuit 1 transmits the working level received at the signal input terminal INPUT to the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, and the second input subcircuit 2 transmits the working level at the first node N1 to the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. The first storage subcircuit 4 stores the working level at the second node N2. Under the control of the working level at the second node N2, the first output subcircuit 3 transmits the non-working level received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2. The first control subcircuit 5 turns off the second clock signal terminal CK2 and the first node N1 in response to the non-working level at the cascade signal output terminal OUTPUT2. The third input subcircuit 6 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the third node N3 in response to the working level received at the second clock signal terminal CK2. The first-level control subcircuit 71 turns off the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. Under the control of the first voltage signal at the third node N3, the second output subcircuit 8 turns off the third voltage signal terminal VDD3 and the cascade signal output terminal OUTPUT2, and under the control of the first voltage signal at the third node N3, the first subcircuit 721 turns off the first voltage signal terminal VDD1 and the fifth node N5, and the second subcircuit 722 turns off the fifth node N5 and the second node N2. Under the control of the voltage at the second node N2, the three-stage control subcircuit 73 transmits the second voltage signal at the second voltage signal terminal VSS to the fifth node N5.

[0211] Exemplarily, each sub-circuit in the shift register RS ​​includes a transistor or a storage capacitor. Figure 8 As shown, in the input stage P1, the first input signal is 0, the first clock signal is 0, the second voltage signal is 0, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0212] In this case, if Figure 8 and Fig.12 As shown, the signal input terminal INPUT, the first clock signal terminal CK1 and the second voltage signal terminal VSS input low level, and the second clock signal terminal CK2, the third clock signal terminal CK3, the first voltage signal terminal VDD1 and the third voltage signal terminal VDD3 input high level. The first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are turned on. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the ninth transistor T9 are turned off.

[0213] At this time, the working level received at the signal input terminal INPUT is transmitted to the first node N1 through the first transistor T1, and is transmitted to the second node N2 through the first transistor T1 and the second transistor T2. The non-working level received at the second clock signal terminal CK2 is transmitted to the cascade signal output terminal OUTPUT2 through the seventh transistor T7, and the first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the third node N3 through the eighth transistor T8. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the fifth node N5 through the tenth transistor T10.

[0214] like Figure 8 and Fig.13 As shown, in the output stage P2, the first input subcircuit 1 cuts off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, and the signal received at the signal input terminal INPUT is a non-working level. The second input subcircuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. Under the control of the working level at the second node N2, the first output subcircuit 3 transfers the working level received at the second clock signal terminal CK2 to the cascade signal output terminal OUTPUT2, and the first storage subcircuit 4 writes the difference between the working level and the non-working level received at the second clock signal terminal CK2 to the second node N2. The first control subcircuit 5 transfers the working level received at the second clock signal terminal CK2 to the first node N1 in response to the working level at the cascade signal output terminal OUTPUT2. The third input subcircuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3 in response to the non-working level received at the second clock signal terminal CK2. The primary control subcircuit 71 cuts off the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. Under the control of the first voltage signal at the third node N3, the second output subcircuit 8 cuts off the third voltage signal terminal VDD3 and the cascade signal output terminal OUTPUT2, and under the control of the first voltage signal at the third node N3, the first subcircuit 721 cuts off the first voltage signal terminal VDD1 and the fifth node N5, and the second subcircuit 722 cuts off the fifth node N5 and the second node N2. Under the control of the voltage at the second node N2, the tertiary control subcircuit 73 transfers the second voltage signal at the second voltage signal terminal VSS to the fifth node N5.

[0215] Exemplarily, each sub-circuit in the shift register RS ​​includes a transistor or a storage capacitor. Figure 8 As shown, in the input stage P1, the second clock signal is 0, the second voltage signal is 0, the first input signal is 1, the first clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0216] like Figure 8 and Fig.13 As shown, in this case, the second clock signal terminal CK2 and the second voltage signal terminal VSS input a low level, and the signal input terminal INPUT, the first clock signal terminal CK1, the third clock signal terminal CK3, the first voltage signal terminal VDD1 and the third voltage signal terminal VDD3 input a high level. The third transistor T3, the seventh transistor T7 and the tenth transistor T10 are turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0217] At this time, the working level received at the second clock signal terminal CK2 is transmitted to the cascade signal output terminal OUTPUT2 through the seventh transistor T7, and the working level at the cascade signal output terminal OUTPUT2 is transmitted to the first node N1 through the third transistor T3. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the fifth node N5 through the tenth transistor T10.

[0218] like Figure 8 and Fig.14As shown, in the first holding phase P31, the first input subcircuit 1 cuts off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, and the signal received at the signal input terminal INPUT is a non-operating level. The second input subcircuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. Under the control of the non-operating level at the fourth node N4, the third input subcircuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The first-level control subcircuit 71 transfers the second voltage signal received at the second voltage signal terminal VSS to the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. Under the control of the second voltage signal at the third node N3, the first subcircuit 721 transfers the first voltage signal received at the first voltage signal terminal VDD1 to the fifth node N5, and the second subcircuit 722 transfers the first voltage signal at the fifth node N5 to the second node N2. Under the control of the second voltage signal at the second node N2, the first output subcircuit 3 turns off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is a non-working level. Under the control of the second voltage signal at the second node N2, the three-level control subcircuit 73 turns off the second voltage signal terminal VSS and the fifth node N5. Under the control of the second voltage signal at the third node N3, the second output subcircuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2, and under the control of the third voltage signal at the cascade signal output terminal OUTPUT2, the first control subcircuit 5 turns off the second clock signal terminal CK2 and the first node N1.

[0219] Exemplarily, each sub-circuit in the shift register RS ​​includes a transistor or a storage capacitor. Fig.14 As shown, in the input stage P1, the third clock signal is 0, the second voltage signal is 0, the first input signal is 1, the first clock signal is 1, the second clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0220] like Figure 8 and Fig.14 As shown, in this case, the third clock signal terminal CK3 and the second voltage signal terminal VSS input a low level, and the signal input terminal INPUT, the first clock signal terminal CK1, the second clock signal terminal CK2, the first voltage signal terminal VDD1 and the third voltage signal terminal VDD3 input a high level. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the ninth transistor T9 are turned on. The first transistor T1, the second transistor T2, the third transistor T3, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are turned off.

[0221] At this time, the first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the fifth node N5 through the fourth transistor T4, and is transmitted to the second node N2 through the fourth transistor T4 and the fifth transistor T5. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the third node N3 through the sixth transistor T6. The third voltage signal received at the third voltage signal terminal VDD3 is transmitted to the cascade signal output terminal OUTPUT2 through the ninth transistor T9.

[0222] like Figure 8 and Fig.15 As shown, in the second holding phase P32, the first input subcircuit 1 transmits the non-operating level received at the signal input terminal INPUT to the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, and the second input subcircuit 2 transmits the non-operating level at the first node N1 to the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. Under the control of the non-operating level at the fourth node N4, the third input subcircuit 6 turns off the second voltage signal terminal VSS and the third node N3. The first-level control subcircuit 71 turns off the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. Under the control of the second voltage signal at the third node N3, the first subcircuit 721 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the fifth node N5, and the second subcircuit 722 transmits the first voltage signal at the fifth node N5 to the second node N2. Under the control of the second voltage signal at the second node N2, and / or under the control of the non-operating level at the second node N2, the first output sub-circuit 3 turns off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is the non-operating level. Under the control of the second voltage signal at the second node N2, the three-level control sub-circuit 73 turns off the second voltage signal terminal VSS and the fifth node N5. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2, and under the control of the third voltage signal at the cascade signal output terminal OUTPUT2, the first control sub-circuit 5 turns off the second clock signal terminal CK2 and the first node N1.

[0223] Exemplarily, each sub-circuit in the shift register RS ​​includes a transistor or a storage capacitor. Figure 8 As shown, in the input stage P1, the first clock signal is 0, the second voltage signal is 0, the first input signal is 1, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0224] like Figure 8 and Fig.15 As shown, in this case, the first clock signal terminal CK1 and the second voltage signal terminal VSS input a low level, and the signal input terminal INPUT, the second clock signal terminal CK2, the third clock signal terminal CK3, the first voltage signal terminal VDD1 and the third voltage signal terminal VDD3 input a high level. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the ninth transistor T9 are turned on. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are turned off.

[0225] At this time, the working level received at the signal input terminal INPUT is transmitted to the first node N1 through the first transistor T1, and is transmitted to the second node N2 through the first transistor T1 and the second transistor T2, and the first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the fifth node N5 through the fourth transistor T4, and is transmitted to the second node N2 through the fourth transistor T4 and the fifth transistor T5. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the third node N3 through the sixth transistor T6. The third voltage signal received at the third voltage signal terminal VDD3 is transmitted to the cascade signal output terminal OUTPUT2 through the ninth transistor T9.

[0226] like Figure 8 and Fig.16As shown, in the third holding stage P33, the first input subcircuit 1 cuts off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1, and the signal received at the signal input terminal INPUT is at the working level. The second input subcircuit 2 cuts off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1. Under the control of the non-working level at the fourth node N4, the third input subcircuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The first-level control subcircuit 71 cuts off the second voltage signal terminal VSS and the third node N3 in response to the third clock signal received at the third clock signal terminal CK3. Under the control of the second voltage signal at the third node N3, the first subcircuit 721 transfers the first voltage signal received at the first voltage signal terminal VDD1 to the fifth node N5, and the second subcircuit 722 transfers the first voltage signal at the fifth node N5 to the second node N2. Under the control of the second voltage signal at the second node N2, the first output subcircuit 3 turns off the second clock signal terminal CK2 and the cascade signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is a non-working level. Under the control of the second voltage signal at the second node N2, the three-level control subcircuit 73 turns off the second voltage signal terminal VSS and the fifth node N5. Under the control of the second voltage signal at the third node N3, the second output subcircuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascade signal output terminal OUTPUT2, and under the control of the third voltage signal at the cascade signal output terminal OUTPUT2, the first control subcircuit 5 turns off the second clock signal terminal CK2 and the first node N1.

[0227] Exemplarily, each sub-circuit in the shift register RS ​​includes a transistor or a storage capacitor. Figure 8 As shown, in the input stage P1, the first clock signal is 0, the second voltage signal is 0, the first input signal is 1, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0228] like Figure 8 and Fig.16 As shown, in this case, the second clock signal terminal CK2 and the second voltage signal terminal VSS input a low level, and the first clock signal terminal CK1, the signal input terminal INPUT, the third clock signal terminal CK3, the first voltage signal terminal VDD1 and the third voltage signal terminal VDD3 input a high level. The fourth transistor T4, the fifth transistor T5 and the ninth transistor T9 are turned on. The first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are turned off.

[0229] At this time, the working level received at the signal input terminal INPUT is transmitted to the first node N1 through the first transistor T1, and is transmitted to the second node N2 through the first transistor T1 and the second transistor T2, and the first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the fifth node N5 through the fourth transistor T4, and is transmitted to the second node N2 through the fourth transistor T4 and the fifth transistor T5. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the third node N3 through the sixth transistor T6. The third voltage signal received at the third voltage signal terminal VDD3 is transmitted to the cascade signal output terminal OUTPUT2 through the ninth transistor T9.

[0230] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0231] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A shift register, characterized in that: include: A first input subcircuit is coupled to the signal input terminal, the first node and the first clock signal terminal; the first input subcircuit is configured to, in an input phase, transmit the working level received at the signal input terminal to the first node in response to the first clock signal received at the first clock signal terminal; and in the output stage, in response to a first clock signal received at the first clock signal terminal, turning off the signal input terminal and the first node; In the output stage, the signal input terminal receives a non-operating level; The first input subcircuit includes a first transistor, the first transistor being a low temperature polysilicon transistor; a second input subcircuit coupled to the first node, the second node and the first clock signal terminal; the second input subcircuit is configured to, in an input stage, transfer the voltage at the first node to the second node in response to the first clock signal received at the first clock signal terminal, and in an output stage, cut off the first node and the second node in response to the first clock signal received at the first clock signal terminal; the second input subcircuit includes a second transistor, which is a low temperature polysilicon transistor; A first output subcircuit is coupled to the second clock signal terminal, the second node and the cascade signal output terminal; the first output subcircuit is configured to, in the input stage, under the control of the voltage at the second node, transfer the non-operating level received at the second clock signal terminal to the cascade signal output terminal; and in the output stage, under the control of the voltage at the second node, transferring the working level received at the second clock signal terminal to the cascade signal output terminal; A first storage subcircuit is coupled to the second node and the cascade signal output terminal; the first storage subcircuit is configured to store the voltage at the second node in the input stage, and write the difference between the working level and the non-working level received at the second clock signal terminal into the second node in the output stage; a first control subcircuit coupled to the second clock signal terminal, the cascade signal output terminal and the first node; The first control subcircuit is configured to, in the output stage, transmit the operating level received at the second clock signal terminal to the first node in response to the operating level at the cascade signal output terminal.

2. The shift register according to claim 1, characterized in that: The first control subcircuit comprises: A third transistor, wherein a first electrode of the third transistor is connected to the second clock signal terminal, a second electrode of the third transistor is connected to the first node, and a control electrode of the third transistor is connected to the cascade signal output terminal.

3. The shift register according to claim 1 or 2, characterized in that: Also includes: A third input subcircuit is coupled to the first voltage signal terminal, the third node and the fourth node; the third input subcircuit is configured to, in the input stage, under the control of the voltage of the fourth node, transmit the first voltage signal received at the first voltage signal terminal to the third node; The first voltage signal is a non-working level; a second control subcircuit coupled to the second node, the third node, the first voltage signal terminal, the second voltage signal terminal and the third clock signal terminal; the second control subcircuit is configured to, in a holding phase, transmit the second voltage signal received at the second voltage signal terminal to the third node, and transmit the first voltage signal received at the first voltage signal terminal to the second node in response to the third clock signal received at the third clock signal terminal; The second voltage signal is a working level; The second output sub-circuit is coupled to the third voltage signal terminal, the third node and the cascade signal output terminal; the second output sub-circuit is configured to, in a holding phase, under the control of the voltage at the third node, transmit the third voltage signal received at the third voltage signal terminal to the cascade signal output terminal; the third voltage signal is a non-working level.

4. The shift register according to claim 3, characterized in that: The second control subcircuit comprises: a first-level control subcircuit coupled to the third node, the second voltage signal terminal and the third clock signal terminal; the first-level control subcircuit is configured to, in the holding phase, transmit the second voltage signal received at the second voltage signal terminal to the third node in response to the third clock signal received at the third clock signal terminal; the second voltage signal is a working level; A secondary control subcircuit is coupled to the second node, the third node and the first voltage signal terminal; the secondary control subcircuit is configured to, during the holding phase, transfer the first voltage signal received at the first voltage signal terminal to the second node under the control of the second voltage signal at the third node.

5. The shift register according to claim 4, characterized in that: The secondary control subcircuit comprises: A first subcircuit is coupled to the third node, the first voltage signal terminal and the fifth node; the first subcircuit is configured to, in the output stage, under the control of the voltage at the third node, cut off the first voltage signal terminal and the fifth node; the first subcircuit includes a fourth transistor, and the fourth transistor is a low temperature polysilicon transistor; A second subcircuit is coupled to the second node, the third node and the fifth node; the second subcircuit is configured to, in the output stage, under the control of the voltage at the third node, cut off the fifth node and the second node; the second subcircuit includes a fifth transistor, and the fifth transistor is a low temperature polysilicon transistor; The second control subcircuit further includes: A three-level control subcircuit is coupled to the fifth node, the second node and the second voltage signal terminal; the three-level control subcircuit is configured to, in the output stage, under the control of the voltage at the second node, transmit the second voltage signal received at the second voltage signal terminal to the fifth node.

6. The shift register according to claim 4 or 5, characterized in that: The primary control subcircuit comprises: A sixth transistor, wherein a first electrode of the sixth transistor is connected to the second voltage signal terminal, a second electrode is connected to the third node, and a control electrode is connected to the third clock signal terminal.

7. The shift register according to any one of claims 4 to 6, characterized in that: The fourth node is connected to the signal input terminal, or the fourth node is connected to the first node, or the fourth node is connected to the fifth node.

8. The shift register according to claim 6 or 7, characterized in that: The first output subcircuit comprises a seventh transistor, a first electrode of the seventh transistor is connected to the second clock signal terminal, a second electrode is connected to the cascade signal output terminal, and a control electrode is connected to the second node; The third input subcircuit comprises an eighth transistor, a first electrode of the eighth transistor is connected to the first voltage signal terminal, a second electrode is connected to the cascade signal output terminal, and a control electrode is connected to the fourth node; The second output subcircuit comprises a ninth transistor, wherein a first electrode of the ninth transistor is connected to the third voltage signal terminal, a second electrode is connected to the cascade signal output terminal, and a control electrode is connected to the third node; The three-stage control subcircuit comprises a tenth transistor, a first electrode of the tenth transistor is connected to the second voltage signal terminal, a second electrode is connected to the fifth node, and a control electrode is connected to the second node; The first storage sub-circuit further includes a first storage capacitor, wherein a first plate of the first storage capacitor is coupled to the second node, and a second plate of the first storage capacitor is coupled to the cascade signal output terminal.

9. A gate drive circuit, characterized in that: include: A plurality of cascaded shift registers according to any one of claims 1 to 8.

10. The gate driving circuit according to claim 9, characterized in that: The shift register is connected to the first clock signal terminal, the second clock signal terminal and the third clock signal terminal; The gate drive circuit further includes: Multiple clock signal lines are divided into multiple groups. In the same group, in adjacent two-pole shift registers, the clock signal line connected to the second clock signal terminal in the previous shift register is the same as the clock signal line connected to the first clock signal terminal in the next shift register, the clock signal line connected to the third clock signal terminal in the previous shift register is the same as the clock signal line connected to the second clock signal terminal in the next shift register, the clock signal line connected to the first clock signal terminal in the previous shift register is different from the clock signal line connected to the third clock signal terminal in the next shift register, and the clock signal lines connected to the same clock signal terminals in any two shift registers are different.

11. The gate drive circuit according to claim 9 or 10, characterized in that: Also includes: A first voltage signal line connected to the first voltage signal terminal and the shift register; The second voltage signal line is connected to the third voltage signal terminal and the shift register; the width of the first voltage signal line is smaller than the width of the second voltage signal line.

12. The gate driving circuit according to claim 11, characterized in that: The line width of the first voltage signal line is 3 μm to 10 μm; and / or the line width of the second voltage signal line is 10 μm to 20 μm.

13. The gate driving circuit according to claim 11 or 12, characterized in that: Along the second direction, a plurality of the shift registers are arranged at intervals; the shift registers include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The first voltage signal line extends along the second direction, and along the first direction, the first voltage signal line is located between the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor and the tenth transistor, and the seventh transistor and the ninth transistor; The second voltage signal line extends along the second direction, and along the first direction, the second voltage signal line is located on a side of the seventh transistor and the ninth transistor away from the first voltage signal line; the second direction intersects the first direction.

14. The gate driving circuit according to claim 13, characterized in that: The shift register also includes a first storage capacitor; the first storage capacitor is located on the side of the seventh transistor and the ninth transistor, away from the first voltage signal line, and the orthographic projection of the second voltage signal line on the reference plane overlaps with the orthographic projection of the first storage capacitor on the reference plane; along the first direction, both ends of the first storage capacitor exceed both ends of the second voltage signal line.

15. The gate driving circuit according to claim 13 or 14, characterized in that: The clock signal line extends along the second direction, and the clock signal line is located at a side of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor and the tenth transistor away from the first voltage signal line; The gate drive circuit further includes: The third voltage signal line is connected to the second voltage signal terminal and the shift register. The third voltage signal line extends along the second direction and is located between the clock signal line and the shift register.

16. The gate driving circuit according to claim 15, characterized in that: The fourth transistor and the fifth transistor are located between the first transistor, the second transistor, the third transistor, the sixth transistor, the eighth transistor and the tenth transistor and the first voltage signal line, and along the second direction, the fourth transistor is located on one side of the fifth transistor; and / or, The third transistor and the sixth transistor are located between the first transistor, the second transistor, the fourth transistor, the fifth transistor, the eighth transistor and the tenth transistor and the third voltage signal line, and along the second direction, the third transistor is located on one side of the sixth transistor.

17. The gate driving circuit according to claim 16, characterized in that: The eighth transistor is located between the fourth transistor and the fifth transistor, and between the third transistor and the sixth transistor, and is located on a side of the first transistor, the second transistor and the tenth transistor away from the shift register of the next stage; the fourth transistor is located on a side of the fifth transistor away from the shift register of the next stage, and the ninth transistor is located on a side of the seventh transistor away from the shift register of the next stage; The gate drive circuit further includes: A first connecting line is connected to the gate of the third transistor, the second electrode of the seventh transistor and the first electrode of the first transistor of the next level; the first connecting line is located on the side of the shift register close to the next electrode of the first transistor, the second transistor, the fourth transistor, the fifth transistor and the tenth transistor.

18. The gate driving circuit according to claim 17, characterized in that: Along the first direction, the channel portion of the first transistor is located on a side of the channel portion of the second transistor close to the shift register of the previous level, and along the second direction, the channel portion of the first transistor is located on a side of the channel portion of the second transistor away from the first voltage signal line; the channel portion of the third transistor is located on a side of the channel portion of the first transistor and the channel portion of the second transistor away from the first voltage signal line.

19. A display device, characterized in that: It comprises the shift register according to any one of claims 1 to 8, or the gate drive circuit according to any one of claims 9 to 18.

20. A shift register driving method, characterized in that: Used to drive the shift register as claimed in any one of claims 1 to 8; a display frame period includes an input stage and an output stage; In the input stage, the first input subcircuit transmits the working level received at the signal input terminal to the first node in response to the first clock signal received at the first clock signal terminal; The second input subcircuit transmits the operating level at the first node to the second node in response to the first clock signal received at the first clock signal terminal; The first storage sub-circuit stores the working level at the second node; Under the control of the working level at the second node, the first output subcircuit transmits the non-working level received at the second clock signal terminal to the cascade signal output terminal; In the output stage, the first input subcircuit cuts off the signal input terminal and the first node in response to the first clock signal received at the first clock signal terminal, and the signal received at the signal input terminal is a non-working level; the second input subcircuit cuts off the first node and the second node in response to the first clock signal received at the first clock signal terminal; Under the control of the working level at the second node, the first output subcircuit transmits the working level received at the second clock signal terminal to the cascade signal output terminal; The first storage sub-circuit writes the difference between the working level and the non-working level received at the second clock signal terminal into the second node; Under the control of the working level at the cascade signal output terminal, the first control subcircuit transmits the working level received at the cascade signal output terminal to the first node.

21. The register driving method according to claim 20, characterized in that: A display frame cycle also includes a holding phase, and the holding phase is located after the output phase; In the input stage, under the control of the voltage of the fourth node, the third input subcircuit transmits the first voltage signal received at the first voltage signal terminal to the third node, and under the control of the first voltage signal at the third node, the second output subcircuit cuts off the third voltage signal terminal and the cascade signal output terminal; The second control subcircuit controls the third voltage signal terminal and the third node to be turned off in response to the third clock signal received at the third clock signal terminal, and the second control subcircuit turns off the first voltage signal terminal and the second node under the control of the first voltage signal at the third node; In the output stage, the second control subcircuit controls the second voltage signal terminal and the third node to be turned off in response to the third clock signal received at the third clock signal terminal, and under the control of the first voltage signal at the third node, the second output subcircuit turns off the third voltage signal terminal and the cascade signal output terminal, and the second control subcircuit turns off the first voltage signal terminal and the second node; In the holding phase, the second control subcircuit transmits the second voltage signal received at the second voltage signal terminal to the third node and transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the third clock signal received at the third clock signal terminal; Under the control of the first voltage signal at the second node, the first output sub-circuit cuts off the second clock signal terminal and the cascade signal output terminal; under the control of the second voltage signal at the third node, the second output sub-circuit transmits the third voltage signal received at the third voltage signal terminal to the cascade signal output terminal.

22. The register driving method according to claim 21, characterized in that: In the output stage, under the control of the second voltage signal at the third node, the first sub-circuit controls the second voltage signal terminal and the fifth node to be cut off, and the second sub-circuit controls the fifth node and the second node to be cut off; under the control of the voltage at the second node, the three-level control sub-circuit transmits the third voltage signal received at the third voltage signal terminal to the fifth node.

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