Epilepsy detection hardware implementation method and system based on machine learning

Abstract

The invention relates to the technical field of biomedical signal processing, in particular to an epilepsy detection hardware implementation method and system based on machine learning, and the method comprises the steps: firstly, obtaining a data set, and constructing a classification detection model based on an SVM; the classification detection model comprises a preprocessing module, a feature extraction module, a normalization processing module and a classification module; secondly, the classification detection model is simulated through Vitis HLS, and an RTL calculation model is generated; and finally, packaging the RTL calculation model into a single IP core which can be called, forming a data path by the single IP core through an AXI-4 protocol CPU, and realizing data transmission from a PC end to a chip end at a high speed so as to realize real-time detection of epilepsy signals. According to the epilepsy detection hardware implementation method based on machine learning, the problems that a traditional epilepsy detection system is difficult to balance in the aspects of calculation speed and resource consumption and the precision loss is too large due to a calculation mode and hardware characteristics in the process of migrating a software end model to a hardware end are solved.

Description

Technical Field

[0001] The present application relates to the field of biomedical signal processing technology, and in particular to a method and system for realizing hardware implementation of epilepsy detection based on machine learning. Background Art

[0002] Epilepsy is a common neurological disease that usually manifests as sudden onset of abnormal electrical activity in the brain. Early warning and detection of epileptic seizures are crucial for the treatment and management of patients. Traditional epilepsy detection methods rely on monitoring and analysis of electroencephalogram (EEG) signals. However, due to the complexity of EEG signals, manual analysis is often time-consuming and susceptible to noise interference. Therefore, automated epilepsy detection methods have become a hot topic of research.

[0003] With the development of machine learning and deep learning technologies, epilepsy detection methods based on signal processing and data mining have made significant progress. Traditional machine learning methods, such as support vector machines (SVM), random forests, and K nearest neighbors (KNN), achieve epilepsy detection by extracting features from EEG signals and training classification models. SVM has become a common method in epilepsy detection due to its high efficiency and good generalization ability under small sample data. In order to improve the accuracy of detection, signal processing techniques such as wavelet transform are usually combined to extract features from EEG signals.

[0004] In terms of hardware implementation, with the continuous development of high-performance computing platforms, especially the rise of field programmable gate arrays (FPGAs) and high-level synthesis (Vitis HLS) tools, the use of hardware acceleration to achieve hardware acceleration of machine learning algorithms has become a trend. Hardware implementation can not only significantly improve the computing speed, but also realize real-time epilepsy monitoring on edge computing devices, providing instant detection and early warning services for epilepsy patients.

[0005] Existing epilepsy detection systems usually have the following shortcomings in hardware implementation: (1) Insufficient resource utilization: When using a central processing unit (CPU) or a graphics processing unit (GPU) for epilepsy detection, the algorithm is usually executed according to a general computing process, lacking hardware optimization, resulting in low utilization of hardware resources, especially when processing large amounts of data. In particular, for the two computationally intensive tasks of signal feature extraction and classification, it is difficult to achieve efficient parallel processing on hardware. (2) Low energy efficiency: Due to the lack of hardware-level optimization, existing epilepsy detection systems often consume a lot of energy when processing large-scale EEG data. This is particularly disadvantageous for real-time monitoring equipment because it requires long-term stable operation and low power consumption. (3) Lack of hardware acceleration support: Traditional systems usually do not fully utilize the advantages of hardware accelerators such as FPGAs, resulting in the signal processing and classification calculation process being too dependent on software, with large bottlenecks in implementation and unable to fully utilize the advantages of FPGA parallel processing. Summary of the invention

[0006] The embodiments of the present application provide a hardware implementation method and system for epilepsy detection based on machine learning, which solves the problem that traditional epilepsy detection systems are difficult to balance in terms of computing speed and resource consumption, and the problem that the accuracy loss is too large due to the computing method and hardware characteristics during the migration of the software-side model to the hardware-side.

[0007] To solve the above technical problems, in the first aspect, an embodiment of the present application provides a hardware implementation method for epilepsy detection based on machine learning, comprising the following steps: first, obtaining a data set and constructing a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; then, simulating the classification detection model through VitisHLS to generate a register transfer level (RTL) calculation model; finally, packaging the RTL calculation model into a single integrated circuit intellectual property core (referred to as IP core) that can be called, and the single IP core forms a data path through the Advanced Extensible Interface (AXI-4) protocol CPU, and realizes high-speed data transmission from a personal computer end (referred to as PC end) to a chip end, so as to realize real-time detection of epilepsy signals.

[0008] In some exemplary embodiments, the classification detection model obtains optimal training parameters by training on the software side, and transmits the optimal training parameters to the hardware side, and only implements the classification test task on the hardware side.

[0009] In some exemplary embodiments, a single IP core receives data to be classified stored by a CPU and outputs a classification result.

[0010] In some exemplary embodiments, the data set includes epilepsy raw data samples and non-epileptic raw data samples; after obtaining the data set and before building the SVM-based classification detection model, it also includes: dividing the data set into a test set and a training set, and labeling the epilepsy signal and the non-epileptic signal with 1 and -1 respectively, and sending the labeled raw data to a preprocessing module for preprocessing.

[0011] In some exemplary embodiments, the preprocessing module includes a bandpass filter of 0.5 Hz to 32 Hz, and the bandpass filter is used to filter the original EEG signal.

[0012] In some exemplary embodiments, the feature extraction module is used to extract features from the filtered signal to obtain a fused feature formed by a two-dimensional array combination of the maximum value and the standard deviation, and the fused feature is sent as input data to the classification detection model for training.

[0013] In some exemplary embodiments, the feature extraction module uses discrete wavelet transform to extract features from the filtered signal; the feature extraction process includes: first performing mirror filling to expand the boundary and using one-dimensional convolution to reduce the amount of calculation; then performing downsampling processing to retain only the data under the odd index to further reduce the amount of data; calculating and obtaining multiple feature combinations, and testing the multiple feature combinations to obtain the best feature combination as a fusion feature; the fusion feature is a two-dimensional array combination of the maximum value and standard deviation obtained by the data sample through the feature extraction process.

[0014] In some exemplary embodiments, the normalization module is used to perform a feature normalization process on the fused features; the normalization process includes: subtracting the mean value from the fused features and then dividing by the standard deviation of the fused features to complete the feature extraction normalization process and eliminate the offset and scale differences between different features.

[0015] In some exemplary embodiments, the classification module is used to perform SVM classification on the normalized features; the SVM classification process includes RBF (radial basis function) kernel function calculation and a decision process; the RBF kernel function calculation includes: subtracting the support vector from the normalized feature vector and finding the square sum to obtain the square value of the Euclidean distance, and then calculating the Gaussian radial basis function to obtain the RBF kernel value; each RBF kernel value is multiplied by the corresponding weight coefficient and accumulated, that is, the weighted summation process is completed; finally, the bias term is added to generate the final decision value; the decision process includes: setting the decision boundary to 0, if it is greater than 0, it is assigned to category 1, corresponding to the decision result between epileptic seizures; if it is less than 0, it is assigned to category -1, corresponding to the decision result before the epileptic seizure.

[0016] In the second aspect, the embodiment of the present application also provides an epilepsy detection hardware implementation system based on machine learning, which adopts the epilepsy detection hardware implementation method based on machine learning described in the above embodiment to perform real-time detection of epilepsy signals, including: a classification detection model module and an RTL calculation model module; wherein the classification detection model module includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; the RTL calculation model module is used to simulate the classification detection model through Vitis HLS to generate an RTL calculation model; and the RTL calculation model is packaged into a single IP core that can be called, and the single IP core forms a data path through the AXI-4 protocol CPU, and realizes high-speed data transmission from the PC end to the chip end to achieve real-time detection of epilepsy signals.

[0017] The technical solution provided by the embodiments of the present application has at least the following advantages: The embodiment of the present application provides a hardware implementation method and system for epilepsy detection based on machine learning, which includes the following steps: first, obtain a data set and build a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; then, simulate the classification detection model through Vitis HLS to generate an RTL calculation model; finally, package the RTL calculation model into a single IP core that can be called, and the single IP core forms a data path through the AXI-4 protocol CPU to achieve high-speed data transmission from the PC end to the chip end, so as to achieve real-time detection of epilepsy signals. The hardware implementation method for epilepsy detection based on machine learning provided by the present application solves the problem that the traditional epilepsy detection system is difficult to balance in terms of computing speed and resource consumption, and the excessive loss of accuracy caused by the calculation method and hardware characteristics during the migration of the software-side model to the hardware end. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0019] Figure 1 A flowchart of a method for implementing epilepsy detection hardware based on machine learning is provided in one embodiment of the present application.

[0020] Figure 2 A comparison diagram of the software and hardware structures of the epilepsy classification model provided in one embodiment of the present application.

[0021] Figure 3 A feature extraction and normalization flow chart provided for an embodiment of the present application.

[0022] Figure 4This is a flow chart of SVM classification provided in one embodiment of the present application.

[0023] Figure 5 This is a hardware structure diagram of epilepsy signal classification provided in one embodiment of the present application. DETAILED DESCRIPTION

[0024] As can be seen from the background technology, the existing epilepsy detection systems usually have technical problems in hardware implementation, such as insufficient resource utilization, low energy efficiency and lack of hardware acceleration support.

[0025] In terms of hardware implementation, with the continuous development of high-performance computing platforms, especially the rise of FPGA and Vitis HLS tools, the use of hardware acceleration to achieve hardware acceleration of machine learning algorithms has become a trend. Hardware implementation can not only significantly improve the computing speed, but also realize real-time epilepsy monitoring on edge computing devices, providing instant detection and early warning services for epilepsy patients. The process of developing an epilepsy detection system with Vitis HLS is as follows: 1. Model design. When developing an epilepsy detection system in Vitis HLS, you first need to perform system requirements analysis and model design. Epilepsy detection systems usually include steps such as signal acquisition, preprocessing, feature extraction, and classification. Developers need to select appropriate algorithms and models based on the specific needs of epilepsy monitoring. For example, select feature extraction methods suitable for EEG (electroencephalogram) signal processing, such as wavelet transform, Fourier transform, etc., and select appropriate classification algorithms (such as SVM, neural network) to detect epileptic seizures. At this stage, the overall architecture of the system and the requirements for hardware acceleration will be determined.

[0026] 2. Algorithm mapping. After designing appropriate epilepsy detection algorithms, the next step is to map these algorithms to the hardware resources of the FPGA. In traditional Vitis HLS development, developers need to consider data types (such as floating-point numbers, fixed-point numbers) and their representation in hardware, select appropriate data storage and transmission methods, such as double data rate synchronous dynamic random access memory (DDR storage), on-chip storage, etc., and allocate computing resources. This process includes analyzing the hardware acceleration requirements of the algorithm and converting algorithms such as feature extraction and classification calculations into hardware modules for parallel computing and pipeline processing on the FPGA.

[0027] 3. Circuit design. Based on Vitis HLS, developers will use high-level languages ​​(such as C / C++) to write hardware circuits and describe each module in the system. In an epilepsy detection system, hardware design usually includes feature extraction modules (such as wavelet transform modules), classifier modules (such as SVM classifiers), data transmission modules, etc. Vitis HLS uses automated tools to convert these high-level designs into hardware description languages ​​(HDL) suitable for FPGA implementation. The key to this stage is to ensure that each module in the design can achieve parallel computing, reduce data transmission delays, and maximize the use of FPGA hardware resources.

[0028] 4. Functional simulation. After the hardware circuit design is completed, the developer needs to perform functional simulation and verification on the design to ensure that the logical functions of the hardware module are correctly implemented. In the traditional Vitis HLS development process, this step is crucial and is mainly performed through simulation tools. Developers need to use actual epileptic EEG signals for testing to evaluate the running results of the hardware circuit on the FPGA platform. This includes testing of key computing processes such as feature extraction modules and classification modules to verify their accuracy, stability, and real-time processing capabilities. Performance evaluation can also be performed after functional simulation to ensure that the hardware design can meet the requirements of real-time and classification accuracy.

[0029] In order to solve the technical problems of insufficient resource utilization, low energy efficiency and lack of hardware acceleration support in the hardware implementation of epilepsy detection system, the embodiment of the present application provides a method and system for hardware implementation of epilepsy detection based on machine learning, which includes the following steps: first, obtain a data set and build a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; then, simulate the classification detection model through Vitis HLS to generate an RTL calculation model; finally, package the RTL calculation model into a single IP core that can be called, and the single IP core forms a data path through the AXI-4 protocol CPU to realize high-speed data transmission from the PC end to the chip end, so as to realize real-time detection of epilepsy signals. The present application provides a method and system for hardware implementation of epilepsy detection based on machine learning, which solves the problem that the traditional epilepsy detection system is difficult to balance in terms of computing speed and resource consumption, and the excessive loss of accuracy caused by the calculation method and hardware characteristics during the migration of the software end model to the hardware end.

[0030] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0031] See also Figure 1 The present application embodiment provides a hardware implementation method for epilepsy detection based on machine learning, comprising the following steps: Step S101, obtain a data set and build a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module.

[0032] Step S102: Simulate the classification detection model through Vitis HLS to generate an RTL calculation model.

[0033] Step S103: Pack the RTL calculation model into a single IP core that can be called. The single IP core forms a data path through the AXI-4 protocol CPU to achieve high-speed data transmission from the PC end to the chip end, so as to achieve real-time detection of epilepsy signals.

[0034] In order to detect abnormal EEG signals during epileptic seizures, this application designs a classification detection model based on SVM, which includes a full set of processes for preprocessing, feature extraction and classification of epileptic EEG signals. Through Vitis HLS simulation and synthesis, a complete RTL calculation model is generated and packaged into a single IP core that can be called. With the AXI-4 protocol, high-speed data interaction with the CPU is realized to achieve timely detection of epileptic signals.

[0035] The SVM-based classification detection model is first implemented in software form: for 700 epilepsy and 700 non-epileptic original data samples, they are divided into test sets and training sets in a ratio of 2:8, and the epilepsy and non-epileptic signals are labeled 1 and -1 respectively. The labeled original data is sent to the filtering module for preprocessing. Usually, the EEG signal frequency of epilepsy patients is lower than 32Hz, and the 0Hz frequency EEG signal brings a large number of noise artifacts. Therefore, this application uses a 0.5Hz~32Hz bandpass filter to complete the filtering of the original EEG signal. After that, this application extracts features from the filtered signal. Considering the balance between resource utilization and classification accuracy, it has been tested that the classification under the combination of the two features of maximum value and variance value can achieve better classification accuracy while saving computing resources. This application uses wavelet transform to complete feature extraction of the filtered signal. In order to ensure that the dimensions of different features are consistent and the numerical range is close, this application normalizes the extracted features, thereby greatly improving the training efficiency of the model. The normalized features are sent to the SVM training module to obtain the model training parameters, and then the classification task of the test set is completed on the software side. Figure 2As shown in the figure. After the software divides the training set and the test set, it outputs the test set data to the hardware. The hardware also completes the data filtering preprocessing, feature extraction and normalization. Unlike the software, when performing the SVM classification task, the hardware receives the training parameters from the software without the need for self-training. Using the existing training parameters, the hardware completes the classification task of epileptic and non-epileptic signals, and also obtains the classification accuracy. On the basis of accuracy to 0.01, there is no difference in the calculation results of the software and hardware.

[0036] In some embodiments, the classification detection model obtains optimal training parameters by training on the software side, and transmits the optimal training parameters to the hardware side, and only implements the classification test task on the hardware side.

[0037] In some embodiments, a single IP core receives data to be classified stored by a CPU and outputs a classification result.

[0038] In some embodiments, the data set includes epilepsy raw data samples and non-epileptic raw data samples; after obtaining the data set and before building a classification detection model based on SVM, it also includes: dividing the data set into a test set and a training set, and labeling the epilepsy signal and the non-epileptic signal with 1 and -1 respectively, and sending the labeled raw data to a preprocessing module for preprocessing.

[0039] In some embodiments, the preprocessing module includes a bandpass filter of 0.5 Hz to 32 Hz, and the bandpass filter is used to filter the original EEG signal.

[0040] In some embodiments, the feature extraction module is used to extract features from the filtered signal to obtain a fused feature formed by a two-dimensional array combination of the maximum value and the standard deviation, and send the fused feature as input data to the classification detection model for training.

[0041] In some embodiments, the feature extraction module uses discrete wavelet transform to extract features from the filtered signal; the feature extraction process includes: first performing mirror filling to expand the boundary and using one-dimensional convolution to reduce the amount of calculation; then performing downsampling to retain only the data under the odd index to further reduce the amount of data; calculating and obtaining multiple feature combinations, and testing the multiple feature combinations to obtain the best feature combination as a fusion feature; the fusion feature is a two-dimensional array combination of the maximum value and standard deviation obtained by the data sample through the feature extraction process.

[0042] In some embodiments, the normalization module is used to perform a feature normalization process on the fused features; the normalization process includes: subtracting the mean M from the fused features and then dividing them by the standard deviation of the fused features to complete the feature extraction normalization process, thereby eliminating the offset and scale differences between different features.

[0043] In some embodiments, the classification module is used to perform SVM classification on the normalized features; the SVM classification process includes RBF kernel function calculation and a decision process; the RBF kernel function calculation includes: subtracting the support vector from the normalized feature vector and finding the square sum to obtain the square value of the Euclidean distance, and then calculating the Gaussian radial basis function to obtain the RBF kernel value; each RBF kernel value is multiplied by the corresponding weight coefficient and accumulated to complete the weighted summation process; finally, the bias term is added to generate the final decision value; the decision process includes: setting the decision boundary to 0, if it is greater than 0, it is assigned to category 1, corresponding to the decision result between epileptic seizures; if it is less than 0, it is assigned to category -1, corresponding to the decision result before the epileptic seizure.

[0044] The following is a detailed introduction to the hardware implementation method of epilepsy detection based on machine learning provided by the present application through specific embodiments.

[0045] This application aims to provide an efficient and low-energy epilepsy classification method by combining hardware acceleration with machine learning algorithms. A complete SVM machine learning model for the classification of epileptic EEG signals in the pre-ictal and interictal stages is built on FPGA, including the preprocessing, feature extraction, normalization and classification of epileptic EEG signals. The pre-trained model can be used on the hardware side to perform efficient classification and detection of EEG signals during epileptic seizures.

[0046] The training and test data used in this application are from the CHB-MIT (Children's Hospital Boston Branch-Massachusetts Institute of Technology) epilepsy data set, which has a sampling rate of 256Hz. Through preliminary processing, this application uses 1024 sampling data points at a sampling time of 5s as a sample. A total of 1400 data samples (700 for epilepsy and non-epileptic) are sent to the software model to realize the division of training set and test set and label them. After that, they are sent to the finite impulse response (FIR) filter to perform the filtering process with a filtering range of 0.5~32Hz, where the filter coefficients are generated by FDA (FDAtools, the built-in toolbox in matlab). The filtering process is the preprocessing of the data. The filtered data is transformed by discrete wavelet transform to obtain the best feature combination of 2 quantities: maximum value and variance value. The feature combination is normalized, and the SVM training process is carried out on the software side to obtain the support vector SV, support vector weight Wt and bias term Bias. The three together constitute the parameters generated by the training, which will be passed to the software and hardware ends for classification tasks. The SVM test module, also known as the classification module, receives the labeled test set data and the parameters obtained from the training set training, completes the judgment of the test sample, and outputs the judgment result. The judgment result is compared with the label result, and the final test accuracy is accumulated. Different from the software side, the hardware side does not need to perform the model training process, and directly uses the parameters obtained from the software model training to perform the classification task, which greatly reduces the waste of storage resources and computing resources. The classifier model of this design is trained on the PC side, and tested on both the FPGA and PC sides to compare its classification accuracy.

[0047] After testing multiple feature combinations, we determined the best feature combination: maximum value and standard deviation. A single 1024-point data sample was extracted through the feature extraction process to obtain a two-dimensional array combination of maximum value and standard deviation, called fusion feature, which was sent as input data to the machine learning model to complete the training. This feature ensures the minimum computing resource usage under the premise of model training efficiency. A small number of features also ensures the simplicity of calculations during training and testing. Figure 3 As shown, this embodiment uses discrete wavelet transform to complete the feature extraction process: first, mirror filling is performed to expand the boundary. Since the calculation of the maximum value and standard deviation usually requires traversing the signal data, one-dimensional convolution is used to reduce the amount of calculation. If the feature scale required by the model changes, the one-dimensional convolution method can also effectively decompose the signal into high-frequency components and low-frequency components. After that, downsampling is performed, and only the data under the odd index is retained to further reduce the amount of data. After the calculation is obtained, the feature normalization process is executed: after the combined feature is subtracted from the average value, it is divided by the standard deviation of the combined feature to complete the feature extraction normalization process, eliminating the offset and scale differences between different features.

[0048] like Figure 4 The normalized features shown in the figure still contain the feature information required for SVM classification within a small numerical fluctuation range. The support vector SV, weight coefficient Wt and bias term Bias trained by the software are used for SVM classification. The SVM classification process on the hardware side includes the RBF kernel function calculation and the decision process: the use of the RBF kernel function avoids the mapping of features in high-dimensional space and increases the generalization of the model to a certain extent. The normalized feature vector is subtracted from the support vector and the square sum is calculated to obtain the square value of the Euclidean distance, and then the Gaussian radial basis function is calculated to obtain the final RBF kernel value. Each RBF kernel needs to be multiplied and accumulated with the corresponding weight coefficient, that is, the weighted summation process is completed, and finally the bias term is added to generate the final decision value. The decision process is similar to the boundary judgment in SVM. The routine sets the decision boundary to 0. If it is greater than 0, it is assigned to category 1, otherwise it is -1, corresponding to the judgment results of the epileptic seizure interval and the pre-epileptic seizure period, respectively.

[0049] The design process of the traditional FPGA signal processing module is completed by writing RTL code, connecting the hardware modules through the hardware description language, and obtaining good resource utilization and acceleration performance with the lowest code description. Considering the complexity of the complete epilepsy signal classification module and the large amount of data processing, the writing of RTL code is very difficult, which prolongs the development cycle on the one hand, and makes the maintenance of the overall code model full of challenges on the other hand. This embodiment uses C++ language to develop a complete epilepsy signal classification model on Vivado HLS under Xilinx, including a filtering module for the data preprocessing part, a feature extraction and normalization module implemented by the discrete wavelet transform method, and a classification judgment module using the SVM method with the RBF kernel. In order to maximize the reduction of computing resources and storage resource consumption on the FPGA development board, we deploy the SVM training model on the software side, and obtain the optimal parameters through training on the software side, which are passed to the hardware module, and the classification test task is only implemented on the hardware side. Figure 5 The hardware structure diagram of epilepsy signal classification is shown. The overall epilepsy classification module is integrated into a single IP core, which can form a data path with the CPU through the AXI-4 protocol to achieve high-speed data transmission from the PC end to the chip end. Since only a single IP core is generated, the long data link and complex Block Design are avoided, which greatly improves the simplicity of the hardware structure.

[0050] The present application provides a hardware implementation method for epilepsy detection based on machine learning. On the one hand, the present application provides a modular implementation method for a complete epilepsy signal classification solution, and only uses a single IP core to encapsulate the three-part calculation process including data preprocessing, feature extraction and normalization, and SVM classification, thereby avoiding the hidden danger of long data transmission paths existing in multiple IP cores, and the IP core can be conveniently parameterized. Different from the complex block design structure formed by multiple IPs in other epilepsy signal classification hardware models, this classification module is integrated into a single IP core, which directly receives the raw data to be classified stored by the CPU and transmitted via the AXI bus, and outputs the classification results.

[0051] On the other hand, this application uses a CPU-FPGA combination of hardware and software to achieve epilepsy signal classification, avoiding the consumption of storage resources and computing resources caused by the training of machine learning models on the hardware side. The on-chip random access memory (RAM) only needs to store the parameters and classification data obtained from CPU training. The SVM training part is completed on the software side, and the hardware side only needs to store parameters and data to be classified, without saving training data, reducing register and computing resource overhead.

[0052] In addition, the present application completes the SVM model training and classification tasks with a two-dimensional fusion feature composed of the maximum value and the standard deviation, which ensures the classification accuracy while greatly reducing the computational complexity and resource loss with a small number of features. In other words, the two-dimensional fusion feature composed of the maximum value and the standard deviation in the present application maintains a high SVM classification accuracy with a minimum number of features. Other SVM classification models require a large number of features. This method reduces the amount of calculation required for training and classification, saving computing resources. It should be noted that the highly integrated epilepsy signal classification calculation module of the present application adopts Vitis HLS under Xilinx, uses C++ language for development and completes simulation synthesis, and outputs RTL level code.

[0053] The hardware resource utilization of the epilepsy detection model is shown in Table 1, where the resources in the first column of Table 1 are all FPGA on-chip resources.

[0054] Table 1 Hardware resource utilization of epilepsy detection model

[0055] In addition, an embodiment of the present application also provides an epilepsy detection hardware implementation system based on machine learning, which uses the epilepsy detection hardware implementation method based on machine learning described in the above embodiment to perform real-time detection of epilepsy signals, including: a classification detection model module and an RTL calculation model module; wherein the classification detection model module includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; the RTL calculation model module is used to simulate the classification detection model through Vitis HLS to generate an RTL calculation model; and the RTL calculation model is packaged into a single IP core that can be called, and the single IP core forms a data path through the AXI-4 protocol CPU, and realizes high-speed data transmission from the PC end to the chip end, so as to realize real-time detection of epilepsy signals.

[0056] Compared with the prior art, the hardware implementation method for epilepsy detection based on machine learning provided by the present application has the following advantages: (1) Efficient acceleration and low power consumption; the present application uses FPGA for hardware acceleration. While ensuring computing efficiency, the present application significantly reduces power consumption by optimizing hardware design and fixed-point operations. In addition, the parallel computing capability of FPGA can maximize the use of hardware resources, while reducing power consumption and maintaining efficient computing performance. This solution is particularly suitable for running on embedded devices or mobile devices, and has better energy efficiency. (2) Flexible hardware programmability and scalability; the present application adopts FPGA platform and Vitis HLS tool, and the present application can flexibly adjust the design of hardware modules. For example, feature extraction algorithm, SVM classification algorithm, etc. can be optimized according to actual application requirements, and algorithm parameters can even be adjusted through configuration files or firmware updates. The FPGA platform also supports later expansion, such as adding more functional modules or adjusting computing resource configuration, which greatly improves the flexibility and scalability of the system. (3) Seamless collaboration between hardware and software; the present application realizes the deep integration of hardware and software through Vitis HLS tool, and the hardware and software ends realize high-speed data transmission and shared training parameters through AXI-4 protocol. The hardware side directly performs classification tasks by receiving the training model parameters transmitted by the software side without retraining, thereby saving computing resources and improving the overall system efficiency.

[0057] This application completes C simulation, synthesis and joint simulation in Vitis HLS software. The program runs correctly. The classification results are compared with the software side synchronously. The absolute error is less than 0.01, which can be ignored. The resource usage results after synthesis are shown in Table 1. Taking the X7Z035FFG676-2 model development board used in this experiment as an example: the resource usage of block random access memory (BRAM), lookup table (LUT) and digital signal processing unit (DSP) is less than 10%, showing a good resource utilization rate.

[0058] Based on the above technical scheme, the embodiment of the present application provides a hardware implementation method and system for epilepsy detection based on machine learning, which includes the following steps: first, obtain a data set and build a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; then, simulate the classification detection model through Vitis HLS to generate an RTL calculation model; finally, package the RTL calculation model into a single IP core that can be called, and the single IP core forms a data path through the AXI-4 protocol CPU to realize high-speed data transmission from the PC end to the chip end, so as to realize real-time detection of epilepsy signals. The hardware implementation method for epilepsy detection based on machine learning provided by the present application solves the problem that the traditional epilepsy detection system is difficult to balance in terms of computing speed and resource consumption, and the excessive loss of accuracy caused by the calculation method and hardware characteristics during the migration of the software-side model to the hardware end.

[0059] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application, so the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A hardware implementation method for epilepsy detection based on machine learning, characterized in that: The following steps are involved: Acquire a data set and construct a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; The classification detection model is simulated by Vitis HLS to generate an RTL calculation model; The RTL calculation model is packaged into a single IP core that can be called. The single IP core forms a data path through the AXI-4 protocol CPU to achieve high-speed data transmission from the PC end to the chip end, so as to realize real-time detection of epilepsy signals.

2. The method for realizing epilepsy detection hardware based on machine learning according to claim 1, characterized in that: The classification detection model obtains optimal training parameters by training on the software side, and transmits the optimal training parameters to the hardware side, and only implements the classification test task on the hardware side.

3. The method for realizing epilepsy detection hardware based on machine learning according to claim 1, characterized in that: The single IP core receives the data to be classified stored by the CPU and outputs the classification result.

4. The method for realizing epilepsy detection hardware based on machine learning according to claim 1, characterized in that: The data set includes epilepsy raw data samples and non-epilepsy raw data samples; After obtaining the dataset and before building the SVM-based classification detection model, it also includes: The data set is divided into a test set and a training set, and the epileptic signal and the non-epileptic signal are labeled with 1 and -1 respectively, and the raw data with the labels are sent to the preprocessing module for preprocessing.

5. The method for realizing epilepsy detection hardware based on machine learning according to claim 1, characterized in that: The preprocessing module includes a bandpass filter of 0.5 Hz to 32 Hz, and the bandpass filter is used to filter the original EEG signal.

6. The method for realizing epilepsy detection hardware based on machine learning according to claim 1, characterized in that: The feature extraction module is used to extract features from the filtered signal to obtain a fusion feature formed by a two-dimensional array combination of the maximum value and the standard deviation, and send the fusion feature as input data to the classification detection model for training.

7. The method for realizing hardware implementation of epilepsy detection based on machine learning according to claim 6, characterized in that: The feature extraction module uses discrete wavelet transform method to extract features from the filtered signal; The feature extraction process includes: First, mirror padding is performed to expand the boundary, and one-dimensional convolution is used to reduce the amount of calculation; Then downsampling is performed to retain only the data under odd indexes, further reducing the amount of data; A plurality of feature combinations are calculated and tested to obtain the best feature combination as a fusion feature; the fusion feature is a two-dimensional array combination of the maximum value and the standard deviation obtained by the feature extraction process of the data sample.

8. The method for realizing hardware implementation of epilepsy detection based on machine learning according to claim 6, characterized in that: The normalization module is used to perform a feature normalization process on the fused features; The normalization process includes: subtracting the average value from the fused feature and dividing it by the standard deviation of the fused feature to complete the feature extraction normalization process, thereby eliminating the offset and scale differences between different features.

9. The method for realizing hardware implementation of epilepsy detection based on machine learning according to claim 1, characterized in that: The classification module is used to perform SVM classification on the normalized features; The SVM classification process includes RBF kernel function calculation and decision process; The calculation of RBF kernel function includes: subtracting the support vector from the normalized feature vector and calculating the square sum to get the square value of the Euclidean distance, and then calculating the Gaussian radial basis function to get the RBF kernel value; multiplying each RBF kernel value with the corresponding weight coefficient and accumulating them to complete the weighted summation process; finally, adding the bias term to generate the final decision value; The judgment process includes: setting the judgment boundary to 0, if it is greater than 0, it is assigned to category 1, which corresponds to the judgment result between epileptic seizures; if it is less than 0, it is assigned to category -1, which corresponds to the judgment result before the epileptic seizure.

10. A system for realizing epilepsy detection hardware based on machine learning, using the method for realizing epilepsy detection hardware based on machine learning as claimed in any one of claims 1 to 9 to detect epilepsy signals in real time, characterized in that: include: Classification detection model module and RTL calculation model module; among them, The classification detection model module includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; The RTL computing model module is used to simulate the classification detection model through Vitis HLS to generate an RTL computing model; and package the RTL computing model into a single IP core that can be called. The single IP core forms a data path through the AXI-4 protocol CPU to realize high-speed data transmission from the PC end to the chip end, so as to realize real-time detection of epilepsy signals.

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