Semiconductor wafer fabrication with polyimide to graphene conversion

Abstract

The invention relates to semiconductor wafer fabrication using polyimide to graphene conversion. A back-end-process integrated circuit interconnect device is formed on an integrated circuit structure having a first dielectric layer formed over a first conductive contact layer by forming an interconnect opening in the first dielectric layer that exposes at least a portion of the first conductive contact layer; filling the interconnect openings in the first dielectric layer with one or more polyimide layers in contact with the first conductive contact layer; and applying a laser light source to directly convert the one or more polyimide layers to form a graphene interconnect structure in the first dielectric layer that is directly electrically connected to the first conductive contact layer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices. In one aspect, the present disclosure relates to an inter-level interconnect structure formed on a semiconductor device. Background Art

[0002] Modern integrated circuits typically have conductors formed on multiple interconnect layers or levels to accommodate dense circuit systems. These conductors can be used to transmit information in the form of signals that are sent to and from the integrated circuit system formed on the underlying substrate. After the integrated circuit system is formed on the substrate during the front-end process (FEOL) processing, the existing semiconductor wafer manufacturing technology forms the inter-level interconnect structure by repeatedly performing deposition, etching, plating and polishing steps with various different layers and materials, all of which make the interconnect manufacturing process complex, time-consuming and expensive. In recent years, copper has been used to form inter-layer interconnects, but as semiconductor manufacturing processes move towards future nodes that shrink the interconnect stack, the resistance and capacitance problems of the materials used to form the interconnects are increasing. In addition, as performance requirements increase, the signals passing through the interconnect conductors operate at very high frequencies, but the smaller spacing between the interconnect geometries may lead to increased parasitic capacitance, which adversely affects the speed and power of the integrated circuit. Another negative aspect of the increase in parasitic capacitance may be the increase in signal crosstalk between adjacent and parallel conductors. Therefore, the existing interconnect manufacturing process cannot provide the cost, speed and electrical performance required for cutting-edge integrated circuit devices. Other limitations and disadvantages of conventional processes and techniques will become apparent to those skilled in the art after reviewing the remainder of the present application with reference to the accompanying drawings and detailed description. Summary of the invention

[0003] It should be appreciated that an integrated circuit interconnect device and an associated manufacturing method are provided. In the disclosed method, an integrated circuit structure is provided, the integrated circuit structure including a first dielectric layer formed above a first conductive contact layer. In selected embodiments, the integrated circuit structure is provided with a semiconductor substrate having a plurality of integrated circuit elements covered by the first dielectric layer formed thereon. In selected embodiments, the first dielectric layer includes an ultra-low-k dielectric layer, and the first conductive contact layer includes a graphene contact layer. The disclosed method also includes forming an interconnect opening in the first dielectric layer that exposes at least a portion of the first conductive contact layer. In selected embodiments, the interconnect opening is formed in the first dielectric layer by: patterning a first resist material on the first dielectric layer to form a first resist mask having a via opening above the first dielectric layer; selectively etching the via opening in the first dielectric layer using the first resist mask; patterning a second resist material on the first dielectric layer to form a second resist mask having a metal line opening above the first dielectric layer; and selectively etching the metal line opening in the first dielectric layer using the second resist mask. In addition, the disclosed method includes filling the interconnect openings in the first dielectric layer with polyimide in contact with the first conductive contact layer. In selected embodiments, the interconnect openings are filled by filling the via openings in the first dielectric layer with polyimide using a first deposition process before patterning the second resist material, and then filling the metal line openings in the first dielectric layer with polyimide using a second deposition process after selectively etching the metal line openings. In other embodiments, the interconnect openings are filled by filling the via openings and metal line openings in the first dielectric layer with polyimide using a deposition process after selectively etching the metal line openings. The disclosed method also includes applying a laser light source to directly convert the polyimide, thereby forming a graphene interconnect structure in the first dielectric layer that is directly electrically connected to the first conductive contact layer. In selected embodiments, a laser irradiation source is applied to one or more first polyimide layers located in the via openings to form a graphene via structure in the first dielectric layer in direct electrical contact with the first conductive contact layer, and a laser irradiation source is applied to one or more second polyimide layers located in the metal line openings to form a graphene wiring structure in the first dielectric layer in direct electrical contact with the graphene via structure.

[0004] In another form, a graphene interconnect structure and associated manufacturing method are provided. In the disclosed method, a first conductive layer is formed above a first dielectric layer. In selected embodiments, the first conductive layer is formed with a first graphene layer on the first dielectric layer, the first graphene layer covering a plurality of integrated circuit components formed on a semiconductor substrate. The disclosed method also includes forming a second dielectric layer above the first conductive layer. In selected embodiments, the second dielectric layer is formed by depositing an ultra-low-k dielectric layer above the first conductive layer and planarizing the ultra-low-k dielectric layer. In other selected embodiments, the second dielectric layer is formed of amorphous fluorinated diamond-like carbon (aC:F). In selected embodiments, the ultra-low-k dielectric layer is fluorinated amorphous diamond-like carbon. In addition, the disclosed method includes forming a through-hole etching opening in the second dielectric layer that exposes at least a portion of the first conductive layer. In selected embodiments, a via etch opening is formed in the second dielectric layer by patterning a first resist material on the second dielectric layer to form a first resist mask having a via opening above the second dielectric layer; and selectively etching the via etch opening in the second dielectric layer using the via opening in the first resist mask. The disclosed method also includes forming a wiring etch opening having a portion overlapping the via etch opening in an upper portion of the second dielectric layer. In selected embodiments, a wiring etch opening is formed in the upper portion of the second dielectric layer by patterning a second resist material on the second dielectric layer to form a second resist mask having a wiring opening above the second dielectric layer; and selectively etching the wiring etch opening in the second dielectric layer using the wiring opening in the second resist mask. In addition, the disclosed method includes forming one or more polyimide layers to fill the via etch opening and the wiring etch opening in the second dielectric layer. In selected embodiments, the one or more polyimide layers are formed by: filling the via etch openings and the wiring etch openings in the second dielectric layer with one or more first polyimide layers using a first deposition process; and planarizing the top surfaces of the one or more first polyimide layers and the second dielectric layer. The disclosed method also includes applying irradiation from a laser source to directly convert the one or more polyimide layers into a graphene interconnect structure, the graphene interconnect structure including graphene wiring formed in the wiring etch opening and graphene via structures formed in the via etch opening to directly electrically connect the graphene wiring to the first conductive layer. In selected embodiments, irradiation from a laser source is applied by: applying a laser irradiation source to one or more first polyimide layers located in the via etch opening to form a graphene via structure in the second dielectric layer that is in direct electrical contact with the first conductive layer; and applying a laser irradiation source to one or more second polyimide layers located in the wiring etch opening to form a graphene wiring structure in the second dielectric layer that is in direct electrical contact with the graphene via structure.In other embodiments, irradiation from a femtosecond UV laser source is applied to convert the one or more polyimide layers directly into a graphene interconnect structure. In selected embodiments, the disclosed method further comprises planarizing a top surface of the graphene wiring and the second dielectric layer.

[0005] In yet another form, an integrated circuit and associated manufacturing method have been provided. As disclosed, the integrated circuit includes a substrate having one or more semiconductor devices formed therein. In addition, the semiconductor device includes a multi-layer interconnect stack formed above the substrate to include a plurality of stacked wirings, the plurality of stacked wirings being vertically separated from each other by a corresponding plurality of interlayer dielectric (ILD) layers. Specifically, the multi-layer interconnect stack includes: a first graphene wiring in a first conductor layer; a second graphene wiring in a second conductor layer, the second graphene wiring being separated from the first graphene wiring by a first ILD layer; and a first graphene via structure formed in the first ILD layer to electrically connect the first graphene wiring to the second graphene wiring. Each of the first graphene wiring, the second graphene wiring, and the first graphene via structure is formed as an irradiation-induced graphene structure that does not include an underlying metal layer. In selected embodiments, the first graphene wiring, the second graphene wiring, and the first graphene via structure are each formed as a laser-induced graphene foam structure. In other selected embodiments, the first ILD layer is formed of amorphous fluorinated diamond-like carbon (aC:F). BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention can be understood and many of its objects, features and advantages can be achieved when the following detailed description of the preferred embodiments is considered in conjunction with the following drawings.

[0007] Figure 1-8 Cross-sectional views of various stages of fabrication of a semiconductor structure having a graphene interconnect structure formed using a single intercalation selective polyimide to graphene conversion process according to selected embodiments of the present disclosure are shown.

[0008] Fig. 9 A simplified process flow for fabricating a graphene interconnect structure according to selected embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0009] An integrated circuit manufacturing process for manufacturing a graphene interconnect structure and the resulting integrated circuit are described. In selected embodiments, a graphene interconnect structure is formed using a selective polyimide to graphene conversion process. For example, a semiconductor wafer can be processed to form a plurality of integrated circuits on a substrate and then covered with a protective interlayer dielectric (ILD) layer and a first level metal or graphene layer (M1). After a planarized ultra-low-k (ULK) dielectric layer is formed above the first level metal or graphene layer (M1), a via etch opening and a next level metal line opening are sequentially etched into the upper surface of the planarized ULK dielectric layer to expose the first level metal or graphene layer (M1), and then filled with one or more planarized polyimide layers. By selectively applying a laser beam with an appropriate energy dose and intensity, the one or more planarized polyimide layers can be converted into a graphene foam interconnect structure. For example, a polyimide (PI) plastic film can be directly laser irradiated into a 3D porous graphene material using a laser in the infrared, ultraviolet or visible range as a one-step process without the need for high temperature reaction conditions, solvents or subsequent processing. By using a laser energy source to directly form a graphene foam interconnect structure from a polyimide layer, no additional barrier or liner layers, such as those used with nickel or copper-based interconnects, are required.

[0010] In the present disclosure, an improved integrated circuit design, structure and manufacturing method are described for forming a graphene interconnect structure as part of a mid-way process or a back-end process, thereby solving various problems in the art, wherein after reviewing the rest of the application with reference to the drawings and detailed description provided herein, the various limitations and disadvantages of conventional solutions and techniques will become apparent to those skilled in the art. Various illustrative embodiments of the present invention will now be described in detail with reference to the drawings. Although various details are set forth in the following description, it should be understood that the present invention can be practiced without these specific details, and many implementation-specific decisions can be made for the present invention described herein to achieve the specific goals of the device designer, such as compliance with process technology or design-related constraints, which vary from implementation to implementation. Although such research and development work may be complex and time-consuming, the work is nothing more than routine work for those of ordinary skill in the art who benefit from the present disclosure. For example, a simplified cross-sectional view of a reference semiconductor device is used to depict selected aspects, but not including every device feature or geometric structure, so as not to limit or obscure the present invention. Such descriptions and representations are used by those skilled in the art to describe and convey the gist of their work to other persons skilled in the art. It should also be noted that throughout this detailed description, certain elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. In addition, the sizes of some elements in the various figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present disclosure. In addition, the figure numbers have been repeated in the drawings to represent corresponding or similar elements. In addition, the depicted device layers shown as being deposited and / or etched are represented by simplified line drawings, but it should be understood that in practice, for example, when the described etching processes are applied to different materials at different rates, or when the described deposition or growth processes generate each layer based on the underlying material, the actual profile or size of the device layer will be non-linear.

[0011] Now refer to Figure 1-9 Various illustrative embodiments of the present invention are described in detail. In addition, although specific example materials, thicknesses and processes are described herein, it will be appreciated by those skilled in the art that other materials, thicknesses and processes with similar properties or characteristics can be substituted without loss of function. It should be noted that throughout this specific embodiment, certain material layers will be deposited and removed to form semiconductor structures. In the case of specific procedures for processing such layers or the thickness of such layers not described in detail below, it is expected that conventional techniques known to those skilled in the art will be used to deposit, remove, form or otherwise process such layers with appropriate thicknesses. Such details are well known and are not considered to be necessary to teach those skilled in the art how to make or use the present invention.

[0012] Now go to Figure 1, a portion of a semiconductor structure 1 is shown in cross-section, the semiconductor structure having a first interlayer dielectric (ILD1) layer 12 and a first metal line conductor layer 11 formed above a substrate 10, wherein one or more integrated circuit elements (not shown) are formed therein. As will be appreciated, the integrated circuit elements may include one or more transistors, resistors, capacitors, diodes, or other semiconductor components formed on or in a semiconductor substrate, the semiconductor substrate being formed of any suitable semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, semiconductor on insulator (SOI), silicon, single crystal silicon, and the like. To protect the integrated circuit elements, the substrate 10 also includes an initial insulating layer (not shown) that may be formed of any suitable insulating material. For example, a planarized tetraethyl borophosphosilicate (BPTEOS) layer may form all or part of an initial interlayer dielectric (ILD0) layer, the ILD0 layer providing a gettering function to help protect the integrated circuit elements and control field leakage between semiconductor transistors.

[0013] After forming the initial ILD0 layer, the first metal line (M1) conductor layer 11 can be formed of any suitable material, such as a copper material, a silver material, an aluminum material, a graphene material, etc. For example, the M1 conductor layer 11 can be formed as a graphene layer surrounding a patterned metal layer, the patterned metal layer being formed of nickel or other suitable metal material, the patterned metal layer being exposed to a growth process of a carbon-containing film using, for example, acetylene or other carbon-containing gases. The carbon-containing gas can be part of a plasma, a remote plasma, or a chemical reaction process, so that elemental carbon or carbon ions interact with nickel. As carbon diffuses through nickel, it forms graphene on the outer surface of nickel until the carbon reaches its solid solubility limit in nickel. For example, by using plasma etching, excess carbon, such as graphite, which may not be in the form of graphene, can be chemically removed. Alternatively, in order to form the graphene layer 11, the patterned metal layer can be exposed to a plasma with some hydrogen and a controlled amount of methane, or can be exposed to a carbon-containing paste. Alternatively, the graphene layer 11 may be formed by converting the polyimide layer directly into a graphene foam structure without the need for patterning the metal layer using laser induced graphene technology as described more fully below.

[0014] After forming the M1 conductor layer 11, a first ILD1 layer 12 may be formed over the semiconductor structure to a predetermined thickness using any suitable deposition technique, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), atmospheric pressure CVD (AP-CVD), chemical bath deposition (CBD), or any combination thereof. For example, the first ILD1 layer 12 may be formed of an ultra-low-k (ULK) dielectric material having a dielectric constant k value of less than about 2.5. Example ULK materials include, but are not limited to, fluorinated amorphous diamond-like carbon (aC:F), carbon-doped SiO2, parylene-F, benzocyclobutane (BCB), Teflon AF, or another similar ultra-low-k dielectric.

[0015] Figure 2 1 shows a subsequent process after forming a first patterned photoresist or hard mask layer 13 on a semiconductor structure according to selected embodiments of the present disclosure. Figure 1 After processing of the semiconductor structure 2. Although any suitable photoresist patterning process can be used, a first patterned photoresist mask 13 can be formed on the first ILD1 layer 12 by depositing, patterning, etching, or developing a photoresist layer formed of any material suitable for photolithography. As depicted, the first patterned photoresist or hard mask layer 13 includes a defined opening 13A that exposes the underlying first ILD1 layer 12 at an intended etching location for forming a through-hole etch opening above the depicted graphene layer 11.

[0016] Figure 3 1 shows the subsequent steps after applying one or more etching processes 14 to form a via etch opening 15 according to selected embodiments of the present disclosure. Figure 2 Afterwards, the semiconductor structure 3 is processed. Although any suitable etching process may be used, the etching process 14 may include performing a reactive ion etching (RIE) step with a suitable etching chemistry using the first patterned photoresist mask 13 to remove the exposed portion of the underlying first ILD1 layer 12. For example, a controlled photoetching process 14 such as timed anisotropic dry etching may be used to remove a portion of the exposed portion of the underlying first ILD1 layer 12 to a predetermined depth that exposes the underlying graphene layer 11. Although the sidewalls of the via etch opening 15 are substantially vertical, it should be understood that slight deviations in the sidewall profile may occur due to etching process variations.

[0017] Figure 4 1 shows the subsequent steps after forming the first polyimide layer 16 in the defined through-hole etching opening 15 according to selected embodiments of the present disclosure. Figure 3Processing of the semiconductor structure 4 thereafter. Although any suitable formation process may be used, the first polyimide layer 16 may be formed after stripping or removing the first patterned photoresist layer 13 and then forming the first polyimide layer 16 using a damascene or embedding process to directly contact the underlying graphene layer 11. For example, the first polyimide layer 16 may be deposited or otherwise formed over the semiconductor structure using a spin coating process to completely fill the through-hole etch opening 15 and the upper horizontal surface of the first ILD1 layer 12. Example polyimide materials include, but are not limited to, fluorinated polyimide (PI-FP, PI-FO, and PI-FH) films, which may be prepared using a polycondensation reaction method by doping p-phenylenediamine (PDA), 4-40-diaminodiphenyl ether (ODA), and 4,40-(hexafluoroisopropylidene)bis(p-phenyleneoxy)diphenylamine (HFPBDA) into 4,40-(hexafluoroisopropylidene)diphthalic anhydride (6FDA), respectively. In other embodiments, the first polyimide layer 16 is formed of a material having a chemical property that interacts with the laser irradiation to directly form graphene. After depositing the first polyimide layer 16 to fill the via etch opening 15, a planarization process such as chemical mechanical polishing (CMP) is applied to remove excess polyimide material from the upper horizontal surface of the first ILD1 layer 12, thereby planarizing the first polyimide layer 16.

[0018] Figure 5 1 and 2. The following diagram shows a subsequent step after forming a second patterned photoresist or hard mask layer 17 on the semiconductor structure according to selected embodiments of the present disclosure. Figure 4 Thereafter, the semiconductor structure 5 is processed. Although any suitable photoresist patterning process may be used, a second patterned photoresist mask 17 may be formed on the first ILD1 layer 12 by depositing, patterning, etching, or developing a suitable photoresist material to define openings 17A that expose intended etching locations for forming metal lines in the underlying polyimide layer 16 and the first ILD1 layer 12.

[0019] Figure 6 1 shows the subsequent steps after applying one or more etching processes 18 to form metal line openings 18 according to selected embodiments of the present disclosure. Figure 5Afterwards, the semiconductor structure 6 is processed. Although any suitable etching process may be used, the etching process 18 may include performing a reactive ion etching (RIE) step with a suitable etching chemistry using the second patterned photoresist mask 17 to remove the underlying polyimide layer 16 and the exposed portion of the first ILD1 layer 12. For example, a controlled photoetching process 18 such as a timed anisotropic dry etch may be used to remove a portion of the polyimide layer 16 and the exposed portion of the first ILD1 layer 12 to a predetermined depth that exposes the underlying first polyimide layer 16. Although the sidewalls of the metal line openings 19 are substantially vertical, it should be understood that slight deviations in the sidewall profile may occur due to etching process variations.

[0020] Figure 7 1 shows the subsequent steps after forming the second polyimide layer 20 in the defined metal line opening 19 according to the selected embodiment of the present disclosure. Figure 6 Afterwards, the semiconductor structure 7 is processed. Although any suitable formation process may be used, the second polyimide layer 20 may be formed after stripping or removing the second patterned photoresist layer 17 and then forming the second polyimide layer 20 using a damascene or embedding process to directly contact the underlying first polyimide layer 16. For example, the second polyimide layer 20 may be formed by depositing or otherwise forming any suitable polyimide material over the semiconductor structure using a spin coating process to completely fill the metal line opening 19 and the upper horizontal surface of the first ILD1 layer 12. After depositing the second polyimide layer 20 to fill the metal line opening 19, a planarization process is applied to remove excess polyimide material from the upper horizontal surface of the first ILD1 layer 12, thereby planarizing the second polyimide layer 20.

[0021] Figure 8 2 shows the subsequent steps after applying a laser irradiation source 21 to directly convert the first and second polyimide layers 16, 20 into graphene via structures 22 and graphene wirings 23, respectively, thereby forming graphene interconnect structures 22-23 according to selected embodiments of the present disclosure. Figure 7Afterwards, the semiconductor structure 8 is processed. Although any suitable laser irradiation source 21 process can be used, lasers in the infrared, ultraviolet and visible ranges can be used to provide a laser-induced graphene process that synthesizes graphene interconnect structures 22-23. For example, a polyimide (PI) plastic film can be directly laser-irradiated into a 3D porous graphene material using an ultraviolet laser as a one-step method without the need for high temperature reaction conditions, solvents or subsequent treatments. Since the first and second polyimide layers 16, 20 have different depth profiles in the first ILD1 layer 12, the application of the laser irradiation source 21 should be controlled to selectively apply the energy dose required to convert both the first and second polyimide layers 16, 20 into graphene. For example, the laser scanning operation can be controlled to apply a first group of laser pulses, which are positioned to have sufficient energy to convert the entire first polyimide layer 16 into a graphene through-hole structure 22, and apply a second group of laser pulses, which are positioned to have sufficient energy to convert the entire second polyimide layer 20 into a graphene wiring structure 23. By appropriately constructing the first ILD1 layer 12 with a material non-reactive to the laser radiation source 21, graphene interconnect structures 22-23 are selectively formed in the semiconductor structure 8 to reduce resistivity and processing complexity compared to the prior art of forming conductive interconnect structures using metal conductors (eg, copper or nickel).

[0022] As disclosed above, a single embedded interconnect process may be used to separately form and fill the via etch openings 15 and the metal line openings 19. However, other embodiments of the present disclosure may use a dual embedded interconnect process, whereby the via etch openings and the metal line openings are sequentially formed in the first ILD1 layer 12, and then subsequently filled with one or more polyimide layers using a single deposition step, followed by a planarization or CMP step to planarize the deposited polyimide layer. In still other embodiments, the planarization or CMP step may occur after forming the graphene interconnect structure.

[0023] As will be appreciated, the graphene interconnect fabrication sequence described above may be repeated one or more times to form multiple graphene interconnect layers or levels over the substrate 10. For example, a second graphene interconnect structure may be formed in a second interlayer dielectric (ILD2) layer formed on the first ILD ILD1 layer by selectively etching through-hole etch openings and next-level metal line openings that expose the graphene interconnect structures 22-23 in the second ILD2 layer, filling the through-hole etch openings and next-level metal line openings with one or more polyimide layers, and then selectively applying a laser beam of appropriate energy dose and intensity to directly convert the one or more polyimide layers into a second graphene interconnect structure.

[0024] The last or topmost metal layer in the semiconductor structure can be formed of any conductive material, such as laser-induced graphene, aluminum, copper, tantalum, tungsten, tantalum nitride, tungsten nitride, titanium, titanium nitride, etc., and combinations thereof. When formed, each of the last metal layers is coupled to one or more integrated circuit elements (not shown) in the substrate 10 via an intermediate graphene interconnect structure (e.g., 22, 23) formed within an ILD layer of an interconnect stack, which can be formed of any insulating material. Although the specific arrangement, construction, and connection of the different conductive interconnect layers are not important, each conductive interconnect layer can be constructed within a constituent ILD layer in the interconnect stack by forming a polyimide structure using a damascene process, which is converted into a graphene structure as disclosed herein using a laser irradiation pulse.

[0025] Now go to Fig. 9 , showing a simplified process flow for manufacturing a graphene interconnect structure according to selected embodiments of the present disclosure 9. Although selected embodiments of the graphene interconnect manufacturing method are described with reference to an example back-end manufacturing process, those skilled in the art will appreciate that the sequence of steps shown can be used at any suitable stage of the device manufacturing process and can be modified, reduced or amplified according to the disclosure of the present invention. Therefore, it should be understood that the method of the present disclosure can be viewed as a method according to Fig. 9 The identified sequence of steps is performed in the order described in the specification, but the steps may also be performed in parallel, in a different order, or as combined independent operations.

[0026] After starting at step 91, the disclosed manufacturing method begins with one or more front-end-of-line (FEOL) processing steps 92 for fabricating one or more integrated circuit elements (e.g., transistors, capacitors, resistors, diodes, etc.) in a wafer substrate. Generally speaking, FEOL processing is the first part of IC manufacturing, where individual components (transistors, capacitors, resistors, etc.) are patterned in the semiconductor, and generally covers everything up to (but not including) the deposition of metal interconnect layers.

[0027] At step 93, one or more first ILD interconnects with attached first metal (M1) lines are formed over the wafer substrate. Example first ILD interconnects may include an initial interlayer dielectric (ILD0) layer formed over the integrated circuit element by depositing, spin coating, or otherwise forming a silicon dioxide layer. In the initial ILD0 layer, contacts may be formed to extend through the initial ILD0 layer to one end of the integrated circuit element (e.g., a source / drain region of a transistor device), for example by selectively etching a contact opening and then filling the opening with one or more conductive via layers. In contact with the contacts, a first metal (M1) layer may be selectively formed over the initial ILD0 layer, for example by depositing a conductive metal layer over the wafer substrate, which is then patterned and etched to leave an M1 layer. In other embodiments, the M1 layer may be formed by selectively etching metal line etch openings in an initial ILD0 layer, filling the metal line etch openings with one or more polyimide layers, and then selectively applying a laser beam of appropriate energy dose and intensity to directly convert the one or more polyimide layers into a graphene M1 metal line layer.

[0028] At step 94, an ultra low k (ULK) dielectric layer is deposited over the wafer substrate and planarized. An example ULK dielectric layer may be formed of a dielectric material having a dielectric constant k value less than about 2.5, formed to a predetermined thickness using any suitable deposition technique, such as CVD, PECVD, PVD, ALD, AP-CVD, CBD, or any combination thereof. Example ULK materials include, but are not limited to, fluorinated amorphous diamond-like carbon (aC:F), carbon-doped SiO2, parylene-F, benzocyclobutane (BCB), Teflon AF, or another similar ultra low k dielectric. In other embodiments, the ULK dielectric layer may be replaced by a dielectric material having a dielectric constant k value less than about 3.9.

[0029] At step 95, a first photoresist mask having patterned via etch openings is formed over the ultra low k dielectric layer. In selected embodiments, the first photoresist mask is formed by coating the ULK dielectric layer with a photosensitive organic material; applying a light source having a patterned mask over the surface of the wafer substrate, the patterned mask blocking the light so that only unmasked areas of the material will be exposed to the light; and applying a solvent to develop the material so that the photosensitive material, which is degraded by the light and the developer, will dissolve away the areas exposed to the light, leaving behind the coating in which the mask is placed and leaving behind via etch openings over the ULK dielectric layer from which the coating was removed.

[0030] At step 96, via openings are selectively etched into the ultra low k dielectric layer using the first photoresist mask. In selected embodiments, the ULK dielectric layer is selectively etched by performing a reactive ion etch (RIE) step with a suitable etch chemistry using the first photoresist mask to selectively etch the via openings by removing exposed portions of the underlying ULK dielectric layer to a predetermined depth that exposes the underlying M1 layer.

[0031] At step 97, after removing the first photoresist mask, a first polyimide layer is formed in the through-hole opening formed in the ultra-low-k dielectric layer. The example first polyimide layer can be formed with any suitable high-performance polymer material having optical and dielectric properties, such that the polymer material is directly converted into a graphene material in response to laser irradiation, and can be deposited using any suitable deposition technique (e.g., CVD, PECVD, PVD, ALD, AP-CVD, CBD, or any combination of the above) to completely fill the through-hole opening. Example polyimide materials include, but are not limited to, fluorinated polyimide (PI-FP, PI-FO, and PI-FH) films, which can be prepared using a polycondensation reaction method by doping p-phenylenediamine (PDA), 4-40-diaminodiphenyl ether (ODA), and 4,40-(hexafluoroisopropylidene)bis(p-phenyleneoxy)diphenylamine (HFPBDA) into 4,40-(hexafluoroisopropylidene)diphthalic anhydride (6FDA), respectively. As understood by those skilled in the art, PI-FP represents 6FDA-PDA, PI-FO represents 6FDA-ODA, and PI-FH represents 6FDA-HFBAPP, respectively. After depositing the first polyimide layer to fill the via opening, a CMP or other planarization step may be applied to the first polyimide layer with the ULK dielectric layer directly after forming the first polyimide layer or at a subsequent stage of the manufacturing process.

[0032] At step 98, a second photoresist mask having patterned metal line etch openings is formed over the ultra low k dielectric layer. In selected embodiments, the second photoresist mask is formed by coating the ULK dielectric layer with a photosensitive organic material; applying a light source having a patterned mask over the surface of the wafer substrate that selectively blocks the light; and developing the material to leave the coating in which the mask is placed and leaving metal line etch openings over the ULK dielectric layer in which the coating is removed.

[0033] At step 99, metal line openings are selectively etched into the ultra low k dielectric layer using the second photoresist mask. In selected embodiments, the ULK dielectric layer is selectively etched by performing a reactive ion etch (RIE) step with a suitable etch chemistry using the second photoresist mask to selectively etch the metal line openings by removing exposed portions of the underlying ULK dielectric layer to a predetermined depth that exposes the underlying first polyimide layer.

[0034] At step 100, after removing the second photoresist mask, a second polyimide layer is formed in the metal line opening formed in the ultra-low-k dielectric layer. In selected embodiments, the second polyimide layer can be formed using any suitable deposition technique, such as CVD, PECVD, PVD, ALD, AP-CVD, CBD, or any combination of the foregoing, to deposit any suitable high-performance polymer material having optical and dielectric properties, such that the polymer material is directly converted into a graphene material in response to laser irradiation. Example polyimide materials include, but are not limited to, fluorinated polyimide (PI-FP, PI-FO, and PI-FH) films, which can be prepared using a polycondensation reaction method by doping p-phenylenediamine (PDA), 4-40-diaminodiphenyl ether (ODA), and 4,40-(hexafluoroisopropylidene)bis(p-phenyleneoxy)diphenylamine (HFPBDA) into 4,40-(hexafluoroisopropylidene)diphthalic anhydride (6FDA), respectively. After depositing the second polyimide layer to fill the metal line openings, a CMP or other planarization step may be applied to the first polyimide layer with the ULK dielectric layer directly after forming the second polyimide layer or at a later stage of the manufacturing process. In other embodiments, the formation of the first and second polyimide layers may be performed in a single polyimide deposition step.

[0035] At step 101, a laser is applied to the first and second polyimide layers to form graphene vias and metal lines. In selected embodiments, the first and second polyimide layers can be directly laser-irradiated into 3D porous graphene materials using a laser irradiation source such as an ultraviolet laser. In the case where the first and second polyimide layers have different depth profiles, the application of the laser irradiation source should be controlled to selectively apply the energy dose required to convert both the first and second polyimide layers into graphene. In other embodiments, a single embedded flow can be used to decouple the laser parameters of the via from the metal line. For example, a first polyimide layer can be deposited and laser-irradiated to form a conductive graphene via structure, followed by deposition and laser-irradiation of a second polyimide layer to form a conductive graphene wiring structure. In other embodiments, planarization of the graphene wiring structure can occur after the second polyimide layer is laser-irradiated to form the graphene wiring structure. In yet other embodiments, the graphene wiring structure can be planarized by depositing a photoimageable polyimide and controlling the exposure so that the upper polyimide is exposed and then selectively removed by a development process, leaving the polyimide coplanar with the top of the ILD, so that CMP planarization is not required.

[0036] At step 102 , the manufacturing process flow ends, but it should be understood that additional back-end processing may be performed to complete the manufacturing of the integrated circuit structure, such as packaging, scribing, die separation, testing, etc.

[0037] As described above, the present disclosure provides a mechanism for integrating graphene interconnects into ultra-low-k dielectric layers using an unusually planar BEOL process that does not require special metal, barrier or liner layers for graphene contact and avoids the most complex and expensive BEOL operations while providing the highest known conductivity. In addition to reducing manufacturing cost and complexity, the disclosed mechanism for integrating graphene interconnects also provides reliability and yield advantages by reducing or eliminating stress migration, electromigration or plasma-induced damage.

[0038] Although the described exemplary embodiments disclosed herein are directed to various semiconductor and integrated circuit device structures and methods of manufacturing the same, the present invention is not necessarily limited to exemplary embodiments illustrating inventive aspects of the present invention applicable to a wide variety of semiconductor processes and / or devices. Therefore, the specific embodiments disclosed above are merely illustrative and should not be considered as limitations on the present invention, as the present invention may be modified and practiced in different but equivalent ways that are apparent to those skilled in the art having benefited from the teachings herein. Therefore, the foregoing description is not intended to limit the present invention to the specific forms set forth, but rather, is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the present invention as defined by the appended claims, so that those skilled in the art should understand that they may make various changes, substitutions and modifications without departing from the spirit and scope of the present invention in its broadest form.

[0039] Benefits, other advantages, and solutions to problems are described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and any elements that may cause any benefit, advantage, or solution to appear or become more apparent should not be construed as essential, necessary, or essential features or elements of any or all claims. As used herein, the terms "comprises" or "comprising" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A method for manufacturing an integrated circuit interconnection device, characterized in that: include: Providing an integrated circuit structure, the integrated circuit structure comprising a first dielectric layer formed over a first conductive contact layer; forming an interconnect opening in the first dielectric layer exposing at least a portion of the first conductive contact layer; filling the interconnect opening in the first dielectric layer with polyimide in contact with the first conductive contact layer; as well as A laser light source is applied to directly convert the polyimide to form a graphene interconnect structure in the first dielectric layer that is directly electrically connected to the first conductive contact layer.

2. The method according to claim 1, characterized in that Forming the interconnect opening in the first dielectric layer includes: patterning a first resist material on the first dielectric layer to form a first resist mask having a via opening over the first dielectric layer; selectively etching the via opening in the first dielectric layer using the first resist mask; patterning a second resist material on the first dielectric layer to form a second resist mask having metal line openings over the first dielectric layer; and The metal line opening is selectively etched in the first dielectric layer using the second resist mask.

3. The method according to claim 2, characterized in that Filling the interconnect opening comprises: filling the via openings in the first dielectric layer with polyimide using a first deposition process prior to patterning the second resist material; and After selectively etching the metal line openings, the metal line openings in the first dielectric layer are filled with polyimide using a second deposition process.

4. The method according to claim 2, characterized in that: Application of the laser light source includes: applying a laser radiation source to the polyimide in the via opening to form a graphene via structure in the first dielectric layer in direct electrical contact with the first conductive contact layer; and A laser radiation source is applied to the polyimide in the metal line opening to form a graphene wiring structure in the first dielectric layer in direct electrical contact with the graphene via structure.

5. A method for forming a graphene interconnect structure, characterized in that: include: forming a first conductive layer over the first dielectric layer; forming a second dielectric layer over the first conductive layer; forming a via etch opening in the second dielectric layer exposing at least a portion of the first conductive layer; forming a wiring etch opening in an upper portion of the second dielectric layer having a portion overlapping the via etch opening; forming polyimide to fill the via etch opening and the wiring etch opening in the second dielectric layer; as well as Irradiation from a laser source is applied to convert the polyimide directly into the graphene interconnect structure, thereby directly electrically connecting the graphene wiring formed in the wiring etch opening to the first conductive layer, the graphene interconnect structure including the graphene wiring and the graphene via structure formed in the via etch opening.

6. The method according to claim 5, characterized in that Forming the via etch opening in the second dielectric layer includes: patterning the first resist material on the second dielectric layer to form a first resist mask having a via opening over the second dielectric layer; and The via etch opening is selectively etched in the second dielectric layer using the via opening in the first resist mask.

7. The method according to claim 5, characterized in that Forming the wiring etch opening in the upper portion of the second dielectric layer includes: patterning a second resist material on the second dielectric layer to form a second resist mask having wiring openings over the second dielectric layer; and The wiring etch openings are selectively etched in the second dielectric layer using the wiring openings in the second resist mask.

8. The method according to claim 5, characterized in that Forming a polyimide includes: filling the via etch openings and the wiring etch openings in the second dielectric layer with one or more first polyimide layers using a first deposition process; and Top surfaces of the one or more first polyimide layers and the second dielectric layer are planarized.

9. The method according to claim 5, characterized in that Applications of radiation from laser sources include: applying a laser radiation source to the one or more first polyimide layers located in the via etch openings to form the graphene via structure in the second dielectric layer in direct electrical contact with the first conductive layer; and A laser radiation source is applied to the one or more second polyimide layers located in the wiring etch openings to form the graphene wiring structure in the second dielectric layer in direct electrical contact with the graphene via structure.

10. An integrated circuit, characterized in that: include: a substrate including one or more semiconductor devices formed therein; as well as a multi-layer interconnect stack formed above the substrate, comprising a plurality of stacked wirings, the plurality of stacked wirings being vertically separated from each other by a corresponding plurality of inter-layer dielectric (ILD) layers, the multi-layer interconnect stack comprising: a first graphene wiring in a first conductor layer, a second graphene wiring in a second conductor layer, the second graphene wiring being separated from the first graphene wiring by a first ILD layer, and a first graphene via structure formed in the first ILD layer to electrically connect the first graphene wiring to the second graphene wiring; The first graphene wiring, the second graphene wiring and the first graphene via structure each include an irradiation-induced graphene structure, and the irradiation-induced graphene structure does not include an underlying metal layer.

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