Novel integrated circuit interconnection packaging method

Through low profile wire bonding technology and magnetic field heating operation, copper wires are efficiently stretched and plasticized in integrated circuit packaging, solving the problem of inappropriate copper column ratios and difficult to achieve high package thickness interconnection in traditional processes, and achieving high-performance integrated circuit interconnection.

CN120109028APending Publication Date: 2025-06-06RESEARCH ON RIYUE NEW ADVANCED TECHNOLOGY (KUNSHAN) CO LTD
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Patent Information

Application Number
CN202510181532.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-02-19
Publication Date
2025-06-06

AI Technical Summary

Technical Problem

In traditional integrated circuit packaging processes, the electroplating copper process leads to inappropriate ratios of copper column diameter to height, affecting packaging performance and production efficiency; while wire bonding technology is difficult to achieve effective interconnection under high packaging thickness.

Method used

Low-profile wire bonding and wire drawing technology is used, combined with magnetic field action and heating operation, so that the copper wire is softened and stretched to an ideal height, and then plastic sealed and grinded to achieve stable electrical interconnection between the upper and lower layers.

Benefits of technology

The aspect ratio of integrated circuit interconnection is improved, the interconnection performance is enhanced, and the high-performance integrated circuit packaging needs at different package thicknesses are met, which improves production efficiency and reduces costs.

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Abstract

The invention discloses a novel integrated circuit interconnection packaging method, and belongs to the technical field of integrated circuits. According to the invention, the traditional method of realizing up-down interconnection through copper electroplating and the conventional lead bonding method are abandoned, the low-profile lead bonding routing technology is adopted, the copper wire is acted by virtue of a magnetic field in the packaging process, and meanwhile, the heating operation is carried out, so that the copper wire is softened to a free deformation state. And then cooling and carrying out plastic package molding treatment, removing the epoxy resin wrapping the copper wire through a grinding process to expose the copper wire, and finally successfully realizing stable and reliable electrical interconnection between the upper layer and the lower layer. According to the invention, the copper wire can be stretched and positioned to an ideal height, the packaging design requirement is perfectly met, the aspect ratio is greatly improved, the limitation of 1: 2 of electroplating copper and 1: 7 of traditional lead bonding is broken through, nearly unlimited proportion optimization is realized, the interconnection performance of an integrated circuit is comprehensively improved, and the production cost is reduced. And powerful technical support is provided for packaging and manufacturing of high-performance electronic products.
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Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a novel integrated circuit interconnection packaging method. Background Art

[0002] In the traditional integrated circuit packaging process, when it comes to achieving electrical interconnection between the upper and lower layers, the conventional practice is to use electroplating copper. However, this method has many disadvantages. The copper pillars formed by electroplating copper usually have a diameter-to-height ratio of 1:2, which means that if effective upper and lower interconnection is to be achieved, a very thick copper layer must be plated. On the one hand, it will cause the chip surface to become rough, affecting subsequent processes and product performance; on the other hand, an overly thick copper plating layer is prone to uneven thickness, which not only wastes a lot of process materials, but also consumes too much time and costs, reducing production efficiency.

[0003] The use of wire bonding technology to build upper and lower interconnections has the limitation of an aspect ratio of only 1:7, which is 60:420 after conversion. This makes it possible to achieve products with a package thickness of 300-4000μm in practical applications, but once the package thickness reaches 500μm and above, traditional wire bonding technology is difficult to achieve and cannot meet the growing demand for high-performance integrated circuit packaging. Summary of the invention

[0004] In view of the above situation, in order to overcome the defects of the prior art, the present invention adopts copper electroplating process and wire bonding technology to realize the many problems existing in the electrical interconnection of the upper and lower layers. Through unique process steps and operating methods, while ensuring the interconnection effect, it improves production efficiency, reduces costs, and meets the packaging requirements of high-performance integrated circuits under different packaging thicknesses.

[0005] In order to achieve the above object, the following technical solution is adopted: The present invention provides a novel integrated circuit interconnect packaging method, comprising the following steps:

[0006] Stick the die on the substrate, exposing the pads;

[0007] Solder the copper wire to the pad;

[0008] Use a sticky material containing magnetic substance to stick the substance pulled by the magnetic field to the copper wire;

[0009] Cut the copper wire;

[0010] The environment is heated up until the copper wire softens, and the copper wire is stretched upward under a magnetic field;

[0011] Under the action of the magnetic field, the softened copper wire is pulled to a vertical state;

[0012] After the temperature drops to room temperature, plastic seal;

[0013] Grind to remove the epoxy resin containing iron powder and expose the copper wire;

[0014] Complete the packaging.

[0015] Furthermore, the sticky material containing magnetic substance is iron powder / nickel powder / cobalt powder.

[0016] Further, the environment is heated to soften the copper wire, and the temperature rise range is 250° C. to 500° C.

[0017] Furthermore, the copper wire is welded to the pad, including using a wire welding machine to perform arc discharge at the bottom of the copper wire to melt the copper wire and weld it to the pad.

[0018] Further, cutting the copper wire includes cutting the drawn copper wire by using a wire bonding machine.

[0019] Furthermore, the material attracted by the magnetic field includes iron powder, nickel powder or cobalt powder.

[0020] The beneficial effects of the present invention are:

[0021] (1) The present invention abandons the traditional copper electroplating to achieve upper and lower interconnection and conventional wire bonding practices, and adopts low-profile wire bonding technology. During the packaging process, the copper wire is acted on by a magnetic field and heated at the same time, so that the copper wire softens to a state where it can deform freely. It is then cooled and plastic-sealed, and then the epoxy resin wrapped around the copper wire is removed through a grinding process to expose the copper wire, and finally a stable and reliable electrical interconnection between the upper and lower layers is successfully achieved.

[0022] (2) The present invention can stretch and position the copper wire to an ideal height, perfectly meeting the requirements of packaging design. The aspect ratio is greatly improved, breaking through the limitations of 1:2 for electroplated copper and 1:7 for traditional wire bonding, achieving nearly unlimited ratio optimization, and comprehensively improving the interconnection performance of integrated circuits, providing strong technical support for the packaging and manufacturing of high-performance electronic products. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The steps of the novel integrated circuit interconnect packaging method of the present invention are schematically shown in FIG. Figure 1 ;

[0024] Figure 2 The steps of the novel integrated circuit interconnect packaging method of the present invention are schematically shown in FIG. Figure 2 ;

[0025] Figure 3 The steps of the novel integrated circuit interconnect packaging method of the present invention are schematically shown in FIG. Figure 3 ;

[0026] Figure 4The steps of the novel integrated circuit interconnect packaging method of the present invention are schematically shown in FIG. Figure 4 ;

[0027] Figure 5 The steps of the novel integrated circuit interconnect packaging method of the present invention are schematically shown in FIG. Figure 5 ;

[0028] Figure 6 The steps of the novel integrated circuit interconnect packaging method of the present invention are schematically shown in FIG. Figure 6 ;

[0029] Figure 7 The steps of the novel integrated circuit interconnect packaging method of the present invention are schematically shown in FIG. Figure 7 .

[0030] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0031] Legend: 1. Substrate; 2. Crystal grain; 3. Pad; 4. Copper wire; 5. Material pulled by magnetic field; 6. Epoxy resin. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0033] Unless otherwise defined, all professional and scientific terms used herein have the same meanings as those familiar to those skilled in the art. In addition, any methods and materials similar or equivalent to those described herein may be applied to the present invention. The preferred implementation methods and materials described herein are for demonstration purposes only and are not intended to limit the content of this application.

[0034] The experimental methods in the following examples are conventional methods unless otherwise specified, and the experimental materials used in the following examples are purchased from commercial channels unless otherwise specified.

[0035] Example

[0036] A novel integrated circuit interconnect packaging method comprises the following steps:

[0037] like Figure 1 As described above, taking a product of 1P1M RDL circuit on a substrate as an example, a die 2 is attached to a substrate 1, and a metal pad 3 is exposed.

[0038] like Figure 2 As described above, the copper wire 4 is clamped by a wire bonding machine, arc discharge is performed at the bottom to melt the copper wire 4 and weld it to the metal pad 3 (pad), and the copper wire 4 is clamped and cut after being pulled out to a desired distance.

[0039] like Figure 3 As described above, before the copper wire 4 is cut, the iron powder is adhered to the front end area (a section of the area facing forward from the end) of the copper wire 4 by using a sticky material containing magnetic substance.

[0040] like Figure 4 As described above, the environment is heated to 250-500° C. until the copper wire 4 softens, and the copper wire 4 is stretched upward under a magnetic field.

[0041] like Figure 5 As described above, under the action of the magnetic field, the softened copper wire is pulled to a vertical state. At this time, the aspect ratio of the copper wire is significantly optimized, far exceeding the 1:2 limitations of traditional copper electroplating technology and the 1:7 limitations of conventional wire bonding technology, laying a solid foundation for achieving high-performance interconnection.

[0042] like Figure 6 After the temperature drops to room temperature, epoxy resin 6 is used for plastic sealing. This epoxy resin has excellent insulation performance, mechanical strength and temperature resistance. During the plastic sealing process, it can tightly wrap the chip and interconnection structure, and effectively protect the internal circuit from interference from external environmental factors, such as moisture, dust, mechanical impact, etc. At the same time, its good fluidity ensures uniformity when filling tiny gaps and wrapping complex structures, avoiding defects such as bubbles and voids.

[0043] like Figure 7 As described above, after the plastic encapsulation is completed, grinding is performed to remove the epoxy resin containing iron powder until the copper wire 4 is exposed for the purpose of subsequent upper and lower interconnection.

[0044] This patented technology is applicable to the process flow that requires wire bonding process to achieve upper and lower interconnection.

[0045] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

[0046] The present invention and its implementation methods are described above, which is not restrictive. The drawings are only one of the implementation methods of the present invention, and the actual application is not limited thereto. In short, if ordinary technicians in the field are inspired by it and design methods and embodiments similar to the technical solution without creativity without departing from the purpose of the invention, they should all fall within the protection scope of the present invention.

Claims

1. A novel integrated circuit interconnect packaging method, characterized in that: The following steps are involved: Stick the die on the substrate, exposing the pads; Solder the copper wire to the pad; Use a sticky material containing magnetic substance to stick the substance pulled by the magnetic field to the copper wire; Cut the copper wire; The environment is heated up until the copper wire softens, and the copper wire is stretched upward under a magnetic field; Under the action of the magnetic field, the softened copper wire is pulled to a vertical state; After the temperature drops to room temperature, plastic seal it; Grind to remove the epoxy resin containing iron powder and expose the copper wire; Complete the packaging.

2. The novel integrated circuit interconnect packaging method according to claim 1, characterized in that: The sticky material containing magnetic substance is iron powder / nickel powder / cobalt powder.

3. The novel integrated circuit interconnect packaging method according to claim 1, characterized in that: The environment is heated up until the copper wire softens, and the temperature rise range is: 250℃ to 500℃.

4. The novel integrated circuit interconnect packaging method according to claim 1, characterized in that: The copper wire is welded to the welding pad, including using a wire welding machine to perform arc discharge at the bottom of the copper wire to melt the copper wire and weld it to the welding pad.

5. The novel integrated circuit interconnect packaging method according to claim 1, characterized in that: Cut the copper wire, Including using a wire bonding machine to cut the pulled copper wire.

6. The novel integrated circuit interconnect packaging method according to claim 1, characterized in that: The material attracted by the magnetic field includes iron powder, nickel powder or cobalt powder.