Integrated circuit interconnect shape optimizer

Abstract

To disclose systems, devices, and methods for optimization of conducting interconnects.SOLUTION: A method includes steps of: receiving an integrated circuit layout including a plurality of terminals and an interconnect, the interconnect representing a conductive coupling between the plurality of terminals; receiving terminal information describing operating parameters of the plurality of terminals; receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect; generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information; determining an individual contribution of a cell included in the three-dimensional representation to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information; and generating an updated integrated circuit layout based at least in part on the individual contribution.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Provisional Application No. 63 / 310,750, filed on February 16, 2022, which is hereby incorporated by reference in its entirety.

[0002] The present disclosure generally relates to integrated circuits, and more particularly, to first principles electronic design automation for optimizing the shape and generating the layout of integrated circuits.

Background Art

[0003] Routing is a fundamental problem in electronic design and automation for generating wiring to interconnect pins of common signals while following manufacturing design rules. For very large - scale integrated circuit (VLSI) designs where there may be billions of transistors within a single chip, routing optimization is particularly difficult due to the complexity of the integrated circuit. Typically, routing is divided into at least a global routing stage and a detailed routing stage, where the global routing plan generates routing paths without considering the manufacturing design rules of a given vendor process node, and the detailed routing determines the exact routes.

[0004] Conventional routing algorithms may be generated using multi - dimensional grid - based graph search techniques (e.g., a 2 - D grid with a third dimension corresponding to a routing layer), and routing resources are modeled as a graph where the graph topology can represent the structure of an integrated circuit. At that time, global routing can partition the graph into tiles and find inter - tile paths to guide a detailed router. Then, the detailed router overlays a grid on the graph where each unit of the grid is larger than the sum of the minimum width and spacing of the wiring of a given vendor process node to find a precise wiring route. A typical router sequentially generates detailed routes and has preferred routing directions (i.e., metal wiring arranged horizontally or vertically with respect to different metallization layers of the integrated circuit), and thus may be restricted in both efficiency and shape (e.g., restricted to the convention of Manhattan routing with vertical and horizontal straight lines). SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0005] Unless otherwise specified, non - limiting and non - exhaustive embodiments of the present invention are described with reference to the following figures in which like reference numerals refer to like parts throughout the various figures. Where appropriate, not all instances of elements are labeled to avoid cluttering the drawings. The drawings are not necessarily to scale; instead, emphasis is placed on showing the principles being described. BRIEF DESCRIPTION OF THE DRAWINGS

[0006]

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DETAILED DESCRIPTION

[0007] Embodiments of a system and method for detailed interconnect routing based on RC simulation at the cell level are described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. However, one of ordinary skill in the art will recognize that the techniques described herein may be practiced without one or more of the specific details, or in other ways, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown in detail or described to avoid obscuring certain aspects.

[0008] Throughout this specification, references to "one embodiment" or "an embodiment" mean that the particular features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0009] Most of the basic characteristics of integrated circuits are related to resistance and capacitance. The delay in charging and discharging the elements of an integrated circuit with each clock cycle is directly given by the RC time constant. Capacitance is related to the amount of charge flowing into and out of the circuit, and thus current can be derived and the power required to drive the integrated circuit subsequently results. Furthermore, the Joule heat generated during operation also immediately results from resistance and current. As a result of miniaturization, phenomena such as electromigration and dielectric breakdown affect the reliability of integrated circuits, and those phenomena are also related to the electric field strength in conductors (e.g., metals such as Au, Ag, Al, Cu, Ti, combinations thereof to form metal alloys) and between conductors (e.g., oxides such as SiO2, SiO x such as other insulators).

[0010] Described herein are embodiments of an iterative cell-based integrated circuit (IC) optimizer that implements first-principles techniques for modifying the detailed interconnect shape of an integrated circuit layout. In this context, an integrated circuit layout describes a graphical and / or numerical representation of at least a portion of an integrated circuit, such as a layer of the integrated circuit that includes one or more interconnects between one or more terminals. In this context, a terminal is a contact coupled to an IC element, also referred to as a port, and an interconnect is a conductive material that electrically couples two or more terminals. An interconnect is also referred to as a "net" or "wiring" according to the terminology used in the field of IC layout routing.

[0011] An integrated circuit layout can describe the positions and dimensions of multiple interconnects and multiple types of terminals. For example, an interconnect can electrically couple multiple input terminals to a single output terminal (referred to as a "fan-in" configuration). In another example, an interconnect can electrically couple a single input terminal to multiple output terminals (referred to as a "fan-out" configuration). In yet another example, an interconnect can electrically couple multiple input terminals to multiple output terminals (referred to as a "fan-in-out" configuration). In some embodiments, an interconnect electrically couples one or more drivers to one or more loads, for example, as part of powering one or more transistors.

[0012] An analytical solution of the RC value of an interconnect incorporating physically meaningful terms is virtually impossible with the dimensions and shapes employed in an IC layout. Therefore, a finite volume method, a finite element method, or other types of 3D full-field numerical simulation methods can be used to determine the RC value. In particular, a three-dimensional representation of the IC layout can be generated to discretize the layout into an array of volumetric elements called cells or voxels. A cell is characterized by uniform material properties corresponding to the cell's position in the IC layout. As an example, a cell at the position of an interconnect in the IC layout can be defined as a conductor (e.g., metal). In another example, a cell at a position outside the interconnect can be defined as a dielectric or insulator (e.g., oxide). The materials can include those used in a multi-layer CMOS process applied to IC manufacturing.

[0013] The three-dimensional representation can show at least a part of an integrated circuit including interconnects and terminals that can be used for simulation of the contribution of individual cells to the RC time constant of the interconnect. The RC time constant of the interconnect can be simulated from the material properties of individual cells and the operating parameters of the terminals. Simulation of the capacitive and conductive contributions of each cell to the overall electrical properties (e.g., conductance and capacitance) of the interconnect and / or dielectric can be used to re-form the interconnect, including re-assigning the materials of individual cells, as a technique for optimizing the RC time constant of the interconnect.

[0014] Advantageously, the techniques described herein facilitate a departure from the convention of linear interconnect layouts. Current vendor process nodes are approaching the threshold of the optical resolution of semiconductor manufacturing systems. Linear routing, along with an emphasis on edge-placement error as a performance metric for manufacturability and process optimization, constrains normal layout design and leads to inefficiencies in the operation of integrated circuits. Accordingly, the curvilinear layouts shown in the figures herein represent a significant step toward improved integrated circuit design associated with nanometer process nodes. For example, the techniques described herein enable function retention, rather than edge-placement error, to guide the determination of manufacturability and enable the physically meaningful RC values of the IC layout to serve as optimization metrics. Modifications can be made to the interconnects to optimize the RC values and improve the overall performance and robustness of the IC interconnects in ways not possible with current linear routing conventions.

[0015] FIG. 1 is a schematic diagram of an exemplary system 100 for modifying conductive interconnects of an integrated circuit layout according to an embodiment of the present disclosure. The exemplary system 100 includes one or more servers 105, one or more client computing devices 110, one or more semiconductor manufacturing systems 115, and a network 120. The server 105 includes a first database 125 of training data 130, a second database 135 of process data 137, a shape optimizer 140, and one or more machine learning models 150 encoded by software 155. As part of the software 155, the server 105 includes instructions for training and / or deploying the shape optimizer 140 and / or the model 150 using the computer circuit 160. In some embodiments, the server 105 further includes a third database 165 that stores a design file 170, also referred to as an integrated circuit layout file, which may be stored in one or more database file formats including, but not limited to, GDSII or OASIS.

[0016] The following description focuses on embodiments of the present disclosure that implement a networked system for deploying a shape optimizer 140 as part of a detailed routing platform for the optimization of an integrated circuit layout 170. However, some embodiments of the present disclosure are contemplated to include some or all of a process implemented on a client computing device 110, such as a laptop or personal computer. For example, training of an untrained model 150 can be performed using a server 105, while the trained model 150 can be transferred to the client computing device 110 via a network 120 and directly deployed thereon. Similarly, the components of the exemplary system 100 can be hosted and / or stored on a distributed computing system (e.g., a cloud system) rather than a single system. For example, the first database 125, the second database 135, the third database 165, and / or the computer circuitry 160 can be implemented in a distributed system such that portions of the training data 130, the process data 137, the software 155, and / or the design file 170 can be stored or executed by a distributed computing system at one or more physical locations.

[0017] In an example for explaining the operation of the exemplary system 100, a user of the client computing device 110 prepares a layout 170 (in connection with FIG. 2) that describes an integrated circuit manufactured using the manufacturing system 115. In a normal system, the layout 170 is routed based on design rules that can be encoded in software that can be stored and / or hosted on the server 105 and / or the client computing device 110. Design rule checking software can generate a boolean result indicating whether the design is manufacturable and can also provide boolean values for "mandatory" or "recommended" rules. Using the design rule checking software, the layout 170 can be easily identified as compliant or non-compliant, but is manually corrected.

[0018] For that purpose, the layout 170 can be processed using the software 155 of the shape optimizer 140 stored in the server 105 and / or the client computing device 110 to generate an updated layout 270 that is optimized with respect to physically meaningful parameters including but not limited to RC time constants. In some embodiments, the layout 170 is transferred to the server 105 via the network 120 where the shape optimizer 140 processes the layout 170. In some embodiments, the shape optimizer 140 is implemented as part of an interactive design environment hosted on the client computing device 110 and / or the server 105, such as a browser environment or a graphical user interface that presents the layout information and one or more tools for designing the layout file 170.

[0019] The optimization criteria can also include target values regarding power consumption, integrated circuit area, processing power, and design and / or wafer-scale yield, which can be specific to the application. In this way, the aggregated effects of multiple detailed routing optimizations can be determined and evaluated against the global optimization goal. Further, composite optimization factors can be used to guide the detailed routing. In an example for illustration, for designs used in highly specialized applications with space or power constraints or where defects are not tolerated, a lower yield can be tolerated in favor of other goals. For high-volume applications where defects are tolerated or there are no size limitations, yield can be prioritized at the expense of area or processing power. Similarly, indirect quantities can be adapted for use as optimization goals. For example, the total cost of ownership of an application-specific integrated circuit used in a data center business can be applied as an optimization function.

[0020] Manufacturing system 115 is an example of a complex system in the pipeline between layout design and semiconductor foundry that processes integrated circuit layouts and converts design data into mask data. The mask data is then used to generate a photomask used in the photolithography process for manufacturing physical semiconductor devices. In the context of the exemplary system 100, manufacturing system 115 is represented by a network interface computer (e.g., a server) for simplicity of visual explanation. Typically, multiple processes (e.g., inverse lithography, optical proximity effect correction, process correction code) are completed between "tape out," which refers to the point when a design compliant with the integrated circuit design rules is sent to the foundry, and the manufacture of the compliant integrated circuit on the wafer.

[0021] In some embodiments, software 155 implements shape optimizer 140 in a manner that generates one or more updated layouts 270 from layout 170. Optionally, the updated layout 270 is combined to generate an updated layout 270 that includes multiple layers, and the updated layout 270 is output for the user, for example, as part of an interactive design environment. Outputting may include, but is not limited to, transfer to client computing device 110 via network 120 and / or storing the updated layout 270 and / or optimization data in a third database 165. When exemplary system 100 operates as part of an interactive design environment, output of manufacturability data may include generation and transmission of user interface data that causes client computing device 110 to present data of manufacturability parameters on display 111.

[0022] In some embodiments, updated process data 137 and / or new process data 137 is received from manufacturing system 115. Semiconductor processing technology is constantly improving as new devices and technologies are developed, and thus exemplary system 100 is contemplated to support retraining of shape optimizer 140 and preparation of new models 145-150 in response to changes to process data 137 or when new process data 137 is received.

[0023] In the illustrated embodiment, the shape optimizer 140 includes functional subunits described as modules 141-149 that are used to generate an updated integrated circuit layout 270. In some embodiments, the shape optimizer 140 includes a discretization module 141 configured to (in connection with FIG. 2) capture layout data 215 used to generate a three-dimensional representation of a layout file 170 that includes a number of cells. The shape optimizer 140 may include a physical simulation module 143 configured to solve electromagnetic equations as part of an electromagnetic simulation of the integrated circuit layout 170. The physical simulation module 143 can enable an exemplary system 100 to determine a local contribution of cells to at least some performance metrics of the layout 170, which may include, but is not limited to, RC values of the interconnects. A shape optimization module 145 configured to implement physically meaningful heuristics based on one or more outputs of the physical simulation module 143 may be included. For example, the shape optimization module 145 can include in software 155 routines for modifying the definition of one or more cells of the three-dimensional representation of the layout 170 according to relationships between the contributions of individual cells near the boundaries of the interconnects.

[0024] In some embodiments, the operation of the physical simulation module 143 may be supplemented and / or implemented by one or more machine learning models 144 trained to generate at least a portion of the updated layout 270 using the layout file 170 as an input. In an example for illustration, the machine learning model 144 may be or include a deep convolutional neural network model trained using the updated layout 270 generated using the physical simulation module 143. For example, a database 146 of training data may be generated by optimizing a plurality of layout files 170 using physics-based simulations. The training data may include paired layout files 170 with corresponding updated layouts 270 that enable the machine learning model 144 to be trained by supervised learning. In some embodiments, the shape optimizer 140 generates the updated layout 270 by first generating the output layout of the machine learning model 144 that is later optimized by the physical simulation module 143. Advantageously, thus complementing the physical simulation module 143 with the machine learning model 144 can reduce the number of iterations of the physical simulation module 143 used to generate the updated layout 270.

[0025] In some embodiments, the shape optimizer 140 includes a process simulator 147 configured to perform a manufacturability simulation of the updated layout 270. In some embodiments, the process simulator 147 can perform a manufacturability analysis based on process node design rules and / or functionality retention criteria. In light of the output returned by the process simulator 147, a modification module 149 can be provided that is configured to modify the updated layout 270. For example, if the process simulator 147 indicates that the updated layout 270 is not manufacturable by the semiconductor manufacturing system 115, the modification module 149 can modify the updated layout to satisfy the manufacturability constraints of the semiconductor manufacturing system 115. The techniques described herein can be applied at multiple distinct scales. For example, the routing of interconnects can be performed at a first scale, while the optimization of the shape of individual interconnects can be performed using a smaller scale, and each scale can correspond to a particular size of the cells that make up the three-dimensional representation.

[0026] It is understood that the techniques described herein can be iterative such that the output of a given iteration can serve as the input for subsequent iterations. In this way, the initial layout file 170 can be repeatedly modified towards an optimization goal such as minimizing the RC value of the interconnects. For that purpose, the exemplary processes described with reference to the figures ahead are understood to represent individual iterations of an optimization technique that can include multiple iterations. Individual iterations can include additional operations, omit one or more operations, and can interchange the order of the operations that are the components.

[0027] FIG. 2 is a schematic diagram showing an exemplary process 200 for generating an updated layout 270 of the interconnects of an integrated circuit according to an embodiment of the present disclosure. The exemplary process 200 may be implemented by a system (e.g., system 100 of FIG. 1) that performs operations for performing iterative optimization of performance metrics to generate a manufacturable integrated circuit layout that may be stored as a layout file 170 (e.g., in database 165 of FIG. 1). The exemplary process 200 may be implemented by a computer encoded in software 155 provided on a storage medium (e.g., non-transitory memory) accessible by at least one machine that, when executed by the machine (e.g., server 150 and / or client computing device 110), causes the machine to perform operations for generating the updated layout 270. The updated layout 270 refers to the updated integrated circuit layout in the previous description in the form of a layout file 170 that includes or otherwise incorporates at least a subset of a plurality of shape modifications made to the interconnects and / or terminals.

[0028] It is further understood that the order in which some or all of the process blocks appear in the exemplary process 200 should not be considered limiting. Rather, those skilled in the art benefiting from the present disclosure will understand that some of the process blocks may be executed in various orders not shown or in parallel. Further, although the exemplary process 200 is described as a sequence of operations performed by modules 141-149 of a shape optimizer 140, it is also contemplated that non-modular software 155 may be provided. Alternatively, as part of the optimization of the load, one or more modules may be segmented into sub-modules, for example, as part of the parallelization of software 155 or as part of the execution on a distributed system.

[0029] In operation 201, exemplary process 200 includes receiving layout data 215. As described in more detail with reference to FIG. 1, layout file 170 may be or include a numerical description of one or more interconnects between terminals associated with an integrated circuit. The description may correspond to a netlist, layout, schematic, diagram, or any other representation of an integrated circuit in which the location, quantity, and connectivity of terminals are described. In some embodiments, layout file 170 includes information regarding wiring route information (e.g., unoptimized or unmanufacturable wiring routes), the number of metallization layers, the physical dimensions of the integrated circuit, wiring routes, and the like. The integrated circuit can include many components (e.g., resistors, transistors, capacitors, diodes, transistors, or other electronic sub-components), and it is understood that the specific or relative spatial arrangement of the components is provided by the description. Thus, layout file 170 indicates how individual terminals among a plurality of terminals are electrically coupled. In some embodiments, layout file 170 also describes information related to terminals that are not placed directly on the integrated circuit (e.g., ground connections).

[0030] In operations 203 and 205, exemplary process 200 includes receiving terminal information 220 and layer information 225. Terminal information 220 refers to data that describes one or more operating parameters of at least a subset of the terminals included in layout file 170. In an example for illustration, layout file 170 may include a description of interconnects that couple driver terminals to load terminals, as described in more detail with reference to FIG. 4A. In this example, terminal information 220 can describe operating parameters for a portion of layout file 170, including but not limited to driver impedance, operating frequency, and / or load capacitance. In some embodiments, terminal information 220 includes metadata that identifies each terminal in relation to layout file 170 such that the terminals included in the layout file are correctly associated with the terminal operating parameters.

[0031] Layer information 225 may include, but is not limited to, material property information of the layers corresponding to the layout file 170. For example, the layout file 170 may describe via layers, metal layers, or other layers that may be included in a multilayer integrated circuit manufactured by a CMOS process. In this way, the layer information 225 may include material property information including electronic properties, thermal properties, elemental composition, phase / structure information, etc. Examples of electronic properties include, but are not limited to, conductivity, permittivity, and breakdown voltage. An example of a thermal property includes, but is not limited to, conductivity. In an example for illustration, the layer information 225 can define a layer as a metal layer and can define two or more materials for a layer including a dielectric oxide and a conductive metal. The layer information 225 may be associated with the layout file 170, for example, by spatial coding of the layout file 170 where interconnects are encoded as metal and regions outside the interconnects are encoded as dielectrics. In some embodiments, the layout file 170 can include a plurality of interconnects and / or terminals within a given region such that a plurality of regions of the layout are represented as conductive materials, as will be described in more detail with reference to FIGS. 4A - 12.

[0032] In operation 207, exemplary process 200 includes discretizing the layout file 170 as part of generating a three - dimensional representation 235 of at least a portion of the layout file 170. The three - dimensional representation 235 can include a plurality of cells, where each cell corresponds to a discrete volume element that describes a portion of the layout file 170. As described above, a cell is a volume element having a specific size, shape, and volume. In some embodiments, the cells share a common size, a common shape, and / or a common volume. In some embodiments, the cells may have various sizes, shapes, and / or volumes such that the layout file 170 can be discretized into a more general set of cells of various sizes and shapes.

[0033] For example, in one embodiment, a plurality of cells may include a first cell having a first volume and a second cell having a second volume different from the first volume. Having cells of different sizes may have certain computational advantages. For example, regions of the simulated environment that are farther from the interconnect boundary may be generated with a larger size compared to cells on or near the interconnect boundary. Advantageously, dynamic cell sizing can reduce the computational resource requirements of the electromagnetic simulation techniques described herein, thereby improving the operation of the exemplary process 200 on the exemplary system 100. It is understood that the individual cells are not necessarily limited to a particular shape that includes any one or combination of a cube, rectangular prism, triangular prism, sphere, cylinder, tetrahedron, hexagonal prism, pyramid, or other shape not explicitly listed. Rather, it is understood that the cells can be sized, shaped, and / or positioned to facilitate any resolution of the 3D representation 235. For example, a cell can be defined as any volume between the arranged nodes mapped on the layout file 170. The arrangement of the nodes among the arranged nodes can be guided by the geometric aspects of the layout file 170. For example, regions of high density of corners or other features of the layout file 170 may correspond to a higher node density, while regions of low feature density may correspond to a lower node density. In some embodiments, each of the individual cells is small enough such that a given terminal included in a plurality of terminals of an integrated circuit is represented by two or more cells included in the plurality of cells.

[0034] In some embodiments, generating the three-dimensional representation 235 may include configuring a coordinate system (e.g., Cartesian, cylindrical, spherical, etc.), cell size, shape, and / or number. The configuration may include assigning material properties to the cells to match or otherwise represent the integrated circuit description (e.g., based on the placement and location of multiple terminals associated with the integrated circuit). For example, cells representing terminals of a given net may be assigned material properties corresponding to a conductor (e.g., a metal such as Au, Ag, Al, Cu, Ti, a combination thereof to form a metal alloy, or other suitable material). Conversely, cells outside of interconnects, terminals, or other conductors may be assigned material properties of an insulator or dielectric (e.g., an oxide such as SiO2, SiO x , SiN, etc., a high-k dielectric, a low-k dielectric, etc.).

[0035] As part of the shape optimization, the initial three-dimensional representation 235 may be generated from a routed layout file 170 that includes interconnects routed according to a straight-through routing convention (e.g., a "Manhattan-type routing"). In subsequent iterations of the exemplary process 200, operations 201-207 may be omitted, and the updated layout 270 may be stored as the three-dimensional representation 235.

[0036] In operation 209, exemplary process 200 includes generating the individual contributions of cells that make up the three-dimensional representation 235 of one or more electrical characteristics of the interconnect. The individual contributions can include capacitive contribution 250 and conductive contribution 255 to characteristic metric 260. Characteristic metric 260 can be based on an objective function that defines one or more parameters of the interconnect. Characteristic metric 260 can include any electrical characteristic or parameter that can be derived from or otherwise inferred from a first principles simulation of a given net and / or integrated circuit based on a simulated environment, such as, but not limited to, resistance, capacitance, admittance, admittance density, impedance, or RC time constant. In an example for illustration, characteristic metric 260 can correspond to the RC time constant of the interconnect that can be used as a convergence target for multiple iterations of exemplary process 200. Individual contributions 250 and 255 can be used as part of a physically meaningful heuristic or other model approach in the optimization of the shape that characteristic metric 260 can be modified as part of the optimization of layout file 170. For example, the convergence of a physical simulation to an optimal RC value can correspond to an iteration of about 20 or less, about 19 or less, about 18 or less, about 17 or less, about 16 or less, about 15 or less, about 14 or less, about 13 or less, about 12 or less, about 11 or less, about 10 or less, about 9 or less, about 8 or less, about 7 or less, about 6 or less, about 5 or less, about 4 or less, about 3 or less, about 2 or less, or 1 iteration. However, as layout 170 becomes more complex, the number of iterations can exceed 20.

[0037] In one or more embodiments, the electromagnetic simulation used to determine the individual contributions 250 and 255 corresponds to the simulation of a given interconnect. The electromagnetic simulation can generate electrostatic field values and / or electromagnetic field values for at least a subset of the cells included in the 3D representation 235, based at least in part on the layer information 225 and the terminal information 220. In some embodiments, the local contribution to the figure of merit is calculated based on the field values obtained via the electromagnetic simulation (e.g., the physical simulation module 143). For example, a current density, an admittance density, or more generally, a flux of parameters related to the resistance or capacitance of the interconnect can be calculated for individual cells. In this way, the spatially localized cell-level simulation results can be used to determine how current flows in the environment simulated in response to the bias signal, and in turn, how current flows in the environment simulated in response to the bias signal can be used to calculate the local contribution of individual cells to the figure of merit 260.

[0038] It is further understood that since the field values from the electromagnetic simulation are based on the material properties of the individual cells, the local contributions are calculated based at least in part on the material properties. In some embodiments, the admittance density of at least a subset of the cells is calculated based at least in part on the field values to determine how the cells affect the admittance matrix of the interconnect. In some embodiments, the admittance density corresponds to a scalar field of the simulated environment at the location discretized using the cells. The admittance density can be understood to indicate the local contribution to the overall conductance and capacitance of the interconnect. As will be described in more detail with reference to FIGS. 3A - 4B, it is understood that the admittance density can be derived in part from the field values of the electromagnetic simulation of the 3D representation 235.

[0039] In operation 211, an exemplary process includes modifying the 3D representation 235 using the output of the physical simulation module 143 and / or the machine learning model 144. As will be described in more detail with reference to FIGS. 3A-4B and 7, the local contribution of a cell to a metric (e.g., a convergence goal or an optimization criterion) can be used to reform interconnects by reallocating the material property information of one or more cells of the 3D representation 235 or by deforming one or more cells of the 3D representation 235. In an example for illustration, the capacitive and conductive contributions of at least a subset of the cells of the 3D representation 235 to the overall RC value of the interconnect can be determined using the layer information 225 and the terminal information 220. In this example, the material identifier of one or more cells of the subset of cells can be modified based at least in part on a comparison of the relative magnitudes of the respective contributions of each cell. Exemplary embodiments of the 3D representation 235 generated in operation 211 are described in more detail with reference to FIGS. 4A-7C, FIGS. 8-10, and FIG. 11.

[0040] In some embodiments, the exemplary process 200 includes one or more sub-operations for modifying the modification of operation 211. For example, modules 147 and / or 149 can verify the manufacturability of a 3D representation through process simulation to generate a predicted manufactured state of a modified 3D representation 235 for the semiconductor manufacturing system 115, as described in more detail with reference to FIG. 1. If the manufactured state fails to reproduce one or more functional aspects of the modification to the 3D representation 235, the manufacturability check implemented as module 147 can return a simple boolean false, or indicate which modifications are likely to result in defects in the manufactured layout. Advantageously, at least in part, since heuristic and / or rule-based manufacturability verification tools (e.g., design rule checker algorithms) are generally assembled for normal straight-through routing, using a physically meaningful process to complete the manufacturability check can facilitate curved routing.

[0041] Based on the output of the manufacturability analysis, the exemplary process 200 may include modifying the modifications to the 3D representation 235 to maintain the functionality of the interconnects in the context of the layout file 170. In some embodiments, the machine learning model 144 may be trained to modify the modifications to the 3D representation 235 to maintain manufacturability, for example, by supervised training using a set of paired manufacturable layouts 170 and non-manufacturable layouts 170. In this context, the training data may be generated from a number of layout files 170 that are verified using a physics-based process model. Such physical simulations may use, for example, a process model developed for the operation of components included as part of the manufacture of integrated circuits using the semiconductor manufacturing system 115, and may include elements configured to identify cells and / or regions of the 3D representation 235 that are likely to be manufactured incorrectly. By using functionality retention rather than other performance metrics (e.g., edge placement error) as the criterion for determining manufacturability, advantageously, operation 211 can generate a physically meaningful manufacturability score that facilitates the transition to a curved interconnect shape. As shown, the iteration of the exemplary process 200 can occur over a subset of the operations that are components. For example, the iteration can include operations 209 and 211, and the layer information 225 and terminal information 220 are maintained for each iteration based on the layout data 215 received in operations 201-205. Similarly, it is possible to modify the 3D representation 235 at the cell level (e.g., as a transformation of one or more polygons or vertices of the layout file 170) rather than at the layout file level. Therefore, encoding the layout file 170 with the modifications from the 3D representation 235 and operation 211 may include one or more image processing techniques applied to the 3D representation 235 to convert the quantized regions described by the cells into smooth regions with lines. In doing so, it is possible to reallocate a portion of the conductive material of a subset of the cells to the dielectric material, and it is possible to reallocate a portion of the dielectric material of a subset of the cells to the conductive material.However, in some embodiments, if the cells have specific dimensions below the lower limit of the resolution of one or more processes of the semiconductor manufacturing system 115, the updated layout can retain the quantized boundaries that are smoothed during manufacturing.

[0042] In operation 213, exemplary process 200 includes outputting an updated layout 270. Outputting the updated layout 270 can include, but is not limited to, generating a layout file 170 using a three-dimensional representation 235 that incorporates the modifications made over one or more iterations of operations 209 and 211. In some embodiments, the updated layout 270 can be encoded as a layout file 170 such as GDSII or OASIS, a mask set, or any other data format used in integrated circuit design. In some embodiments, the updated layout 270 can be encoded as visualization data that is distributed or otherwise accessible by the client computing device 110 as part of an interactive design environment. In this way, one or more users of the interactive design environment can access and / or modify the layout file 170 and / or the updated layout 270 simultaneously or in parallel.

[0043] Detailed Consideration of Interconnect Shape Modification With the routes properly established between the terminals, the capacitance between the nets can be determined and used to optimize the shape of the interconnects to improve RC, but other optimization goals including, but not limited to, reducing electromigration and avoiding dielectric breakdown are also envisioned. For that purpose, the admittance density of Equation (1) repeated below

[0044]

Equation

[0045] can be applied to understand which regions contribute to RC and then assemble heuristics for reforming the interconnect to improve RC.

[0046]

Number

[0047] Here, the fundamental solution f k is the solution of the complex Laplace equation with Dirichlet boundary conditions of 1 at terminal k and 0 at all other terminals

[0048]

Number

[0049] and Neumann boundary conditions are applied everywhere else. Here, the complex material parameters are given by

[0050]

Number

[0051] where the permittivity is “ε”, the conductivity is “σ”, and the angular frequency is “ω”. Then, the admittance matrix of a system with N ports can be determined as a volume integral over the admittance density

[0052]

Number

[0053] as follows.

[0054] Without being bound by a specific physical mechanism, it is understood that the RC depends on the load attached to the output terminal of the interconnect representing the transistor gate node of CMOS logic. When the gate capacitance of the transistor gate is large, the interconnect capacitance can be ignored or substantially ignored, while the optimization of the interconnect shape can include reducing the interconnect resistance. Such scenarios were typical for older vendor process nodes, but in the latest technology nodes such as FinFET technology, the interconnect capacitance is comparable to the gate capacitance of the transistor. Therefore, modifying the interconnect shape can depend on the ratio between the wiring capacitance and the attached load.

[0055] Input admittance and RC: The RC can be calculated from the admittance, at least in part, based on deriving the effect of the admittance density of a single interconnect on the overall RC of the routed IC layout. As part of generating the overall RC time constant, the admittance matrix

[0056]

Number

[0057] can be determined for a fully routed system of N ports using the following equation.

[0058]

Number

[0059] Furthermore, the regions of the three-dimensional representation of the layout file 170 can be assigned to the terminals belonging to either the transistors or the external pins. The input admittance of input i

[0060]

Number

[0061] is

[0062]

Number

[0063] capable of being defined by and determined from a system underlying interconnects and transistors.

[0064] Since the attached load (e.g., a transistor) is a non-linear component, the resistance and capacitance of the transistor are evaluated based on the instantaneously applied voltage signal. As a simplifying assumption, the gate capacitance can be bounded by assuming the maximum capacitance of all operating points of each transistor t as follows.

[0065]

Number

[0066] However, in practice, an effective capacitance with respect to a particular voltage ramp or slew may be selected according to embodiments of the present disclosure.

[0067] For the purpose of RC calculations, the low-frequency component of the capacitance is important. Since the capacitance is independent of frequency up to near the cut-off frequency, in some embodiments, it is assumed that the frequency dependence can be ignored. The input admittance at terminal i

[0068]

Number

[0069] To calculate it, it is necessary to assume the load admittance at all other input terminals j≠i. For simplicity, an ideal ohmic contact, i.e.,

[0070]

Number

[0071] can be assumed. Finally, the input admittance of terminal i is

[0072]

Number

[0073] calculated as, and considering the load Y at all terminals other than the input terminal i, the current is set to their appropriate values. Thus, the following linear equation that can be directly solved is obtained,

[0074]

Number

[0075] where δ kl is the Kronecker delta.

[0076] The input admittance defined in Equation (6)

[0077]

Number

[0078] can be determined from Equation (9). For l≠i

[0079]

Number

[0080] The value of can be calculated and used in the upper equation of Equation (9), while the lower equation

[0081]

Number

[0082] for all

[0083]

Number

[0084] contains that information exactly by expressing it as a function of.

[0085] Input admittance

[0086]

Number

[0087] Using, the RC at terminal i i can be calculated using the equation

[0088]

Number

[0089] as follows.

[0090] RC iConsiders other phenomena including, but not limited to, capacitance effects, resistance effects, and coupling efficiency based on crosstalk and / or loads attached to other wiring. However, Equation (10) describes the instantaneous RC time constant. For non-linear elements such as transistors, the instantaneous RC time constant is different from the RC measured in large-signal operation. Therefore, the following discussion assumes the worst-case gate capacitance for all operating states. In this way, it is understood that the objective function for optimizing the interconnect shape with respect to the RC value is bounded by the worst-case RC.

[0091] RC improvement heuristic: Equation (10) shows that it is not obvious how to optimize the wiring with respect to RC. First, the input admittance

[0092]

Number

[0093] is an admittance matrix for which there is no analytical solution

[0094]

Number

[0095] is a complex function of the elements. Second, RC is determined by the quotient of Equation (10), which means that its value is determined non-locally. Thus, an algorithm for optimizing RC cannot easily determine whether local changes to the interconnect structure (e.g., widening and / or narrowing the interconnect width at one or more locations of the interconnect) will improve or degrade the output of the objective function. Third, the transistor load that appears in the implicit input admittance system of Equation (9) is an important factor in determining how the interconnect structure should be optimized due to the nature of how RC is calculated. In some embodiments, the magnitude of the load at the terminals can be made such that the interconnect capacitance can be substantially ignored, resulting in a wide optimal interconnect for increasing conductivity. This was the case for old vendor process nodes, but for current and future expected process nodes, the interconnect capacitance and the gate capacitance can be comparable. In such cases, the width of the interconnect can depend on the length of the interconnect. For example, relatively short interconnects can be relatively wide, while longer interconnects can be characterized by a capacitance that shows an improvement in RC by narrowing the width.

[0096] In short, interconnect optimization is a significant computational challenge. Advantageously, the numerical techniques described herein can be complemented by simple heuristics for improving circuit timing, such as widening interconnects, inserting vias to reduce resistance, and / or widening the spacing between adjacent wires or shortening the parallel run-length of adjacent wires to reduce cross-coupling capacitance. Thus, it can be understood that the RC-optimization landscape enables the algorithm to follow the gradient towards a local optimum. Such a hybrid approach, including the finite volume method and simple heuristics, can result in improved IC performance by modifying the layout file 170 while also reducing the computational resource requirements of the optimization process.

[0097] This structure of capacitance is shown by algorithms such as FasterCap, which represent interconnect capacitance with the Green's function of the Laplace equation since the strength of the electric field between interconnects is an equivalent measure of capacitance. Similarly, the current density within an interconnect is an equivalent measure of conductance by Ohm's law. Thus, the admittance density of Equation (1) can be used to determine the measure of the local conductance and capacitance contributions to the overall admittance of Equation (5). In this way, the spatial contribution from the admittance density

[0098] [Number]

[0099] can serve as the basis for determining the RC of Equation (10).

[0100] As a prelude, heuristics for improving interconnect design without using numerical or analytical methods are described. Equation

[0101]

Number

[0102] Start with a layout 170 that includes interconnects and one or more terminals, each described by a material parameter field κ(r) defined using . In this way, the layout file 170 can be updated based at least in part on a determination of whether the spatial coordinate r should have the material parameters of the metal of the interconnect or the material parameters of the insulator and / or dielectric.

[0103] Single load: Attached load

[0104]

Number

[0105] , ∀k≠a is RC a As part of optimizing a , it greatly affects the optimization of the wiring shape at the input terminal a, which at least partially determines whether the interconnect can be widened to carry more current or narrowed to avoid capacitive cross - coupling. In some cases, the net connects two terminals a and b with a single load

[0106]

Number

[0107] connects two terminals a and b with , while all other terminals are

[0108]

Number

[0109] For all \(k\neq a, b\), it can be assumed that they are short - circuited. Inserting these loads into Equation (9) gives the following equation.

[0110]

Number

[0111] In the equation which is the second component of Equation (12), for example, terms of relatively small magnitude other than the load at the short - circuited terminals can be ignored.

[0112]

Number

[0113] Since \(\cdots\) is non - zero, the applied bias at the short - circuited port \(k\) is understood as the applied voltage approaches zero

[0114]

Number

[0115] and can be understood as such. Inserting this into the equation which are the first two components results in the following equation.

[0116]

Number

[0117] Solving the equation which is the second component for \(\cdots\)

[0118]

Number

[0119] and inserting the result into the equation which is the first component makes it possible to derive the following equation for the input admittance.

[0120] [Number]

[0121] This equation is understood to be an equation for an interconnect that connects two terminals with a single load.

[0122] For the RC of Equation (10) a When the equation regarding it is expanded into real and imaginary components, Equation (14) can be used to derive the following equation regarding RC. a

[0123] [Number]

[0124] For a single interconnect that connects terminal a to terminal b, the admittance matrix can be expressed as

[0125] [Number]

[0126] and can be represented as

[0127] Regarding CMOS technology, terminal b can be assumed to correspond to a gate acting as a capacitive load. Therefore,

[0128] [Number]

[0129] is a complex number value

[0130] [Number]

[0131] and can be represented as such, whereby the RC of Equation (13) a is

[0132] [Number]

[0133] can be rewritten as.

[0134] In Equation (17), the structure of the RC time constant is shown as the ratio of the capacitive contribution to the conductive contribution. Therefore, the conductivity of the interconnect can be compared with the load and the capacitance of the interconnect. From the perspective of input a, it can be understood that it is physically impossible to distinguish whether the capacitance at the output is part of the interconnect structure or part of the load. Thus, the output capacitance C is, at least in part, the load capacitance C L combined with.

[0135] Fixed-width Toy Model Optimization: FIG. 3A is a schematic diagram showing a toy model 300 of a two-port interconnect 310 according to an embodiment of the present disclosure. FIG. 3A shows an interconnect 310 electrically coupled to two terminals 305 (e.g., "ports") having an equivalent circuit with physical size, conductance G, and capacitance C. In the following procedure, the interconnect 310 is optimized to drive the load C L FIG. 3A shows a toy model 300 in which transmission line effects, such as the effect of capacitance being distributed over the length "L" of the interconnect 310, are ignored. Thus, the following simple analytical models for conductance and capacitance are applied,

[0136] [Number]

[0137] where x w , L, and W are the dimensions shown in FIG. 3A, and H is the height in the remaining direction. σ and ε are the conductance and permittivity, respectively. Inserting the terms of Equation (18) into Equation (17) results in the following equation.

[0138]

Number

[0139] Equation (16) reveals that when the capacitance of interconnect 310 is equal to or greater than the load capacitance, RC can scale with L 2 Accordingly, it can be understood that short wiring driving a large load scales with L. As described in more detail with reference to FIG. 2, in some embodiments, the local width of interconnect 310 is a variable that is operated in an optimization scheme to improve the performance of interconnect 310 (e.g., by a minimizing RC). In such a technique, the width x w of interconnect 310 is understood to depend at least in part on the operating parameters of the load represented by terminal information 220. In the two-port scenario shown in FIG. 3A using a uniform width x w , for a given load capacitance C L , the optimal width is given by the equation

[0140]

Number

[0141] described by

[0142] In Equation (20), C0 is the capacitance of interconnect 310 at the full width L, i.e.,

[0143]

Number

[0144] defined as. The minimum RC aValue location x opt Note that it can be determined from the ratio of the intrinsic capacitance of the interconnect 310 to the external load capacitance, independent of the conductivity. For a small load, the interconnect 310 mainly drives the capacitance of the interconnect 310 itself, and the optimal width x opt ≒ W / 2. However, as the load increases, the delay due to charging of the load capacitance becomes significant. As a result, x opt increases. Note that due to the interdependence of the capacitance of the interconnect 310 with the dielectric width, the intrinsic wiring capacitance can be balanced against the capacitive load. Therefore, as the capacitive load approaches infinity (C L →∞), x opt gradually approaches the limit of W.

[0145] Regarding the optimization of the RC-based shape, the position of one or more interfaces between the conductive material and the dielectric material can be modified based at least in part on the relative magnitudes of the electric fields accumulated in the conductor and the dielectric. For that purpose, the admittance density of Equation (1) is in both the metal M of the interconnect and the dielectric OX (example of an oxide),

[0146]

Number

[0147] can be expressed as.

[0148] In contrast, the RC equation is,

[0149]

Number

[0150] becomes.

[0151] Equation (22) qualitatively reveals a technique for locally optimizing the interconnect 310. At the interface between the metal and the oxide, when the imaginary part of the admittance density contributes more to the overall capacitance than the real part of the admittance density contributes to the overall conductance within the conductor, the interconnect boundary 311 is moved to increase the distance between the capacitor plates (e.g., by shrinking the interconnect 310). On the other hand, when the real part within the conductor contributes more, the interconnect boundary 311 is moved to increase the conductor cross-section.

[0152] Regarding gradient-based optimization, a differentiable function of RC is derived, and the optimal value can correspond to a stationary point where the

[0153]

Number

[0154] derivative is zero. Solving Equation (22) for the stationary point results in an equation that holds for all values of r0

[0155]

Number

[0156] as shown below.

[0157] As revealed by Equation (23), in the optimal configuration, the local capacitive contribution and the conductive contribution balance each other, and each contribution is defined as

[0158]

Number

[0159]

Number

[0160] as follows.

[0161] Equation (24) describes the local capacitive contribution at position r, and Equation (25) describes the local conductive contribution at position r. From these equations, inspired by the qualitative approach shown in Equation (22), a heuristic for improving the RC of the interconnect is at the position r on the interface 311 between the interconnect 310 and the dielectric inter can be assembled as follows.

[0162] C C (r inter ) > C G (r inter ), reduce the width of the interconnect.

[0163] C C (r inter ) < C G (r inter ), increase the width of the interconnect.

[0164] C C (r inter ) = C G (r inter ), maintain the width of the interconnect.

[0165] To generalize the previous treatment of the RC circuit, a voltage generator

[0166]

Number

[0167] can be included along with the associated generator admittance

[0168]

Number

[0169] In a digital circuit, the generator is generally the power grid, and the generator admittance

[0170] [Number]

[0171] is associated with the resistance and capacitance of interconnect 310 and the channel of the MOSFET. The real part of the generator admittance can be associated with the conductance of the channel of the MOSFET in the on state, and thus can be interpreted as the driving strength of interconnect 310. Similar to what has already been shown for the load admittance, different driving strengths can lead to different optimal interconnect 310 designs.

[0172] To determine RC, the input admittance

[0173] [Number]

[0174] is from an ideal voltage source

[0175] [Number]

[0176] and the relationship

[0177] [Number]

[0178] can be obtained using.

[0179] Here, the generator current

[0180] [Number]

[0181] is the admittance value of the 2-port interconnect 310

[0182] [Number]

[0183] and

[0184] [Number]

[0185] to which the formula

[0186] [Number]

[0187] can be associated using.

[0188] Equation (27) is combined with Equation (26) and

[0189] [Number]

[0190] to obtain the equation of, can be rearranged as follows.

[0191] [Number]

[0192] Equation (28) is combined with Equation (25) to yield the equation of RC as

[0193] [Number]

[0194] possible.

[0195] Figure 3B is a schematic diagram showing an exemplary variable-width interconnect 310 that couples two terminals 305, according to an embodiment of the present disclosure. To derive the corresponding two-port admittance matrix, an approximation based on the solution of the Laplace equation for the fundamental solution can be used to reduce the complexity of the description using an equivalent circuit. For that purpose, an assumption can be made that the potential in the highly conductive interconnect is constant in the x direction. In Figure 3B, the x direction is defined as shown.

[0196] Assuming a constant conductivity, the Laplace equations for the fundamental solutions f a and f b can be understood as a description of current conservation as a function of the position of y between the terminals 305. More specifically, for the metal region, a metal fundamental

[0197]

Number

[0198] can be defined. In this context, an integration over a control volume that includes two slices of the interconnect 310 at y = 0 and an arbitrary internal point y0, using the Gaussian integration theorem, results in the equation

[0199]

Number

[0200] which yields.

[0201] Since Equation (30) is a general equation for any y0, current conservation is determined by assuming that I0 is constant and the metal fundamental solution

[0202]

Number

[0203] can be defined using the formula

[0204]

Number

[0205] as described above, the subscript "a" is assigned to one of the terminals 305 connected by the interconnect 310. In this way, for the terminal "b", the fundamental solution for the metal is

[0206]

[0207]

Number

[0208] can be defined by

[0209] For equations (31) and (32), the boundary conditions are, respectively

[0210]

Number

[0211] and

[0212]

Number

[0213] defined as

[0214] The equations for the fundamental solutions in the dielectric are their respective values in the metal

[0215]

Number

[0216] ​It can be represented as a simple linear function that decays from [value at x = 0] to zero at the electrode position x = W shown in Figure 3B. The resulting dielectric fundamental function is, with respect to the dielectric

[0217]

Number

[0218] can be defined as.

[0219]

Number

[0220] Under the simplifying assumption that it is [value], Equation (28) can be used together with Equation (29) to derive the constraints on the admittance density resulting from the RC stationary points. Once determined, the stationary points can be defined as fixpoints for modifying the shape of the interconnect 310 (for example, by displacing at least a part of the interface 311). Using the general form of the RC equation including the generator admittance and the load admittance shown in Equation (29),

[0221]

Number

[0222] is.

[0223] The stationary points are

[0224]

Number

[0225] given by.

[0226] The functional derivative of the generator input admittance is

[0227]

Number

[0228] is given by.

[0229] From this equation, the complete equation of the functional derivative of equation (35) can be derived for the two-terminal 305 interconnect 310

[0230]

Number

[0231] can be derived as.

[0232]

Number

[0233] is,

[0234]

Number

[0235] is.

[0236] From equations (37) to (39), for any point r0 on the interface 311, the equation of the fixed point is

[0237]

Number

[0238] can be defined as.

[0239] Detailed consideration of any fanout The derivation regarding the variation of RC can be extended to the interconnect that couples the driver (input terminal 305) to multiple output terminals 305, as will be described in more detail with reference to FIG. 8. In the RC formula given in Equation (34), the output terminal 305 forms part of the generator input admittance, the input admittance

[0240] [Number]

[0241] affects the value. Therefore, RC and its variation for any fan-out can be determined, at least in part, by calculating the input admittance and its derivative with respect to different admittances.

[0242] For this purpose, consider an interconnect 310 characterized by an N×N admittance matrix

[0243] [Number]

[0244] for input terminals 305 a∈{1, 2, ..., N} and the load of all terminals 305 for i = 1, 2, ..., N

[0245] [Number]

[0246] To determine the input admittance in this case, first Ohm's law

[0247] [Number]

[0248] Starting from this, which uses a simplified notation, it is understood that both I and V refer to vectors of complex phasors. To calculate the input admittance with respect to terminal 305a, the influence of the load on all ports other than a can be determined. For this purpose, the reduced (N - 1)×(N - 1) matrix

[0249] [Number]

[0250] is equal to that obtained by deleting the row and column corresponding to terminal 305a, except that

[0251] [Number]

[0252] is equal to. Similarly, the vectors

[0253] [Number]

[0254] and

[0255] [Number]

[0256] are defined to be equal to I and V respectively, but without the element a.

[0257] [Number]

[0258] Regarding this, Ohm's law states that

[0259] [Number]

[0260] can be represented as,

[0261]

Number

[0262] is an (N - 1)×(N - 1) diagonal matrix that all loads except terminal 305a have on its diagonal. Further, H is an element

[0263]

Number

[0264] , including k∈{1, ..., N}\{a}.

[0265] Equation (41) can be simplified to an equation of the relationship between the voltage ratio (V r ) and H,

[0266]

Number

[0267] where Vr = V~ / Va is the voltage ratio with respect to the input.

[0268] Equation (42) can be used to determine the input admittance as a function of the voltage ratio and the elements of the admittance matrix.

[0269]

Number

[0270] Using these equations, a system of linear equations can be defined and solved to define the derivative of the input admittance.

[0271] [Number]

[0272] Detailed Examination of the RC Contribution of Cells As described in more detail with reference to FIG. 2, the following examination details an example for the description of a computational technique for optimizing the RC of the interconnect 310 of a layout file 170 that includes one or more nets. Each has T n Starting from a fully routed layout 170 that includes N interconnects 310 each having a set of T terminals 305, where n ∈ {1, 2, ..., N}. Further, each interconnect 310n has one or more inputs derived from a pull-up network and / or a pull-down network, and one or more outputs that terminate at a load (e.g., a gate in CMOS technology). The set of inputs to interconnect 310n is

[0273] [Number]

[0274] is denoted as, and the set of outputs is

[0275] [Number]

[0276] is denoted as,

[0277] [Number]

[0278] indicates the set of terminals 305 (e.g., the interconnect 310 can connect inputs to outputs without dead terminals or null terminals).

[0279] The optimization of the shape of the interconnect 310 involves defining the local contribution δRC(r) of each interconnect 310. When RC is at a minimum, RC is stationary and the variation δRC is zero, which occurs by the cancellation of its conductive component inside the interconnect and its capacitive component outside the interconnect. See the two terms of Equation (40).

[0280] Detailed Consideration of Shape Modification Therefore, if the interconnect is not RC-optimal, an imbalance in components can be found at the interface "r inter " of the interconnect. The conductive contribution

[0281]

Number

[0282] indicates the value of δRC inside the interconnect, and the capacitive contribution

[0283]

Number

[0284] indicates the value of δRC outside the interconnect. Then, the heuristic for improving RC is given by the following.

[0285]

Number

[0286] If it is, reduce the width of the interconnect.

[0287]

Number

[0288] If it is, increase the width of the interconnect.

[0289]

Number

[0290] If so, maintain the width of the interconnect.

[0291] In the context of the above heuristic, equality can be understood to be approximate within the range of values. For example,

[0292]

Number

[0293] is within a given tolerance

[0294]

Number

[0295] and is substantially equal, the interconnect boundary 311 can be maintained. Similarly,

[0296]

Number

[0297] is outside a given tolerance

[0298]

Number

[0299] and is larger, the width of the interconnect 310 can be reduced. In some embodiments, the tolerance is

[0300]

Number

[0301] and

[0302]

Number

[0303] can be given as a ratio of the values of. For example, about 1.5 or less, about 1.4 or less, about 1.3 or less, about 1.2 or less, about 1.1 or less, about 1.05 or less, about 1.01 or less of

[0304]

Number

[0305] and

[0306]

Number

[0307] the ratio to can be considered equal within an acceptable range, including their interpolation and parts thereof.

[0308] The implementation of the algorithm is in the boundary region 313 near the interconnect boundary 311

[0309]

Number

[0310] and

[0311]

Number

[0312] It is complicated by the geometric dependence of local modifications to the interconnect boundary 311 on the value of. As will be described in more detail with reference to FIG. 7, allocating material to cells in the 3D representation 235 can involve determining the differential contribution of the cells in the discretized space and comparing the corresponding contributions of adjacent discretized volumes (e.g., cells) within the boundary region 313.

[0313] In some embodiments, the relative effects of the conductive and dielectric materials within the boundary region 313 on the differential RC contribution at a given position r of the interconnect 310 are

[0314]

Number

[0315] and

[0316]

Number

[0317] can be explained by extrapolating the value to adjacent cells of the 3D representation 235. In some embodiments, the extrapolation can involve applying a 3D smoothing operation to the cells. Examples of 3D smoothing include

[0318]

Number

[0319] including a Gaussian smoothing function defined as, where σ is a 3D standard deviation vector of values defined in Cartesian space, σ = (σ x , σ y , σ z) It is understood that σ can be defined in other coordinate spaces so as to correspond to the coordinate space used to define the three-dimensional representation 235. The value of σ affects the range of smoothing, with smaller values resulting in more restricted smoothing and larger values resulting in broader smoothing. In some embodiments, to limit the possibility that the opposing boundary 311 affects the field contribution of the vector quantity, the value of σ can be less than the width X W (Y) of the interconnect 310. Thus, σ can be a function of the position within the three-dimensional representation 235 or can be a consistent value with respect to the layout 170. In some embodiments, an initial value of σ greater than the initial width of the interconnect 310 is selected (for example, in a straight routing, the width can be a single value).

[0320] For the Gaussian smoothing function of Equation (45), the smoothed contributions to the conductance and capacitance at a given position r can be expressed as a three-dimensional convolution.

[0321]

Number

[0322]

Number

[0323] and

[0324]

Number

[0325] represent, respectively, the smoothed capacitive contribution and the smoothed conductive contribution at a position r within the three-dimensional representation 235. Advantageously, extrapolation such as by the smoothing shown in equations (45) and (46) allows the relative contribution of the cell to the conductance and capacitance of the interconnect 310 (e.g., the real and imaginary components of the RC) to be determined with less influence from the relative position of the cell to the interconnect boundary 311. In this way, for a position r within the interconnect 310, within a given tolerance ε

[0326] [Number]

[0327] if so, the material of the interconnect 310 within the cell corresponding to the position r can be reallocated from a conductor to a dielectric (e.g., from a metal to an oxide). Otherwise, the material of the interconnect 310 within the cell corresponding to the position r can be maintained as a conductor. Similarly, for a position r outside the interconnect 310, within a given tolerance ε

[0328] [Number]

[0329] if so, the material can be reallocated from a dielectric to a conductor (e.g., from an oxide to a metal). Otherwise, the material of the interconnect 310 within the cell corresponding to the position r can be maintained as a dielectric.

[0330] In some embodiments, the simulation mesh is unstructured and, instead of reallocating materials to cells, the walls of the interconnect can be moved by a mesh movement operation.

[0331] As will be described in more detail with reference to FIG. 7, in some embodiments, manufacturability checks may be included as part of the operation of an exemplary process 200 that includes, but is not limited to, generating an updated layout 270. If a process function P(M, θ) that depends on the mask set M and the fab parameter θ is available, a material parameter field that describes the interconnect 310 may be determined. For an interconnect 310 structure with a given M0 and θ, the material parameters of the interconnect 310 structure and other quantities of interest can be determined using the process function P(M0, θ) = {σ(r), ε(r),...} =: S0, and the wafer state S0 of the first iteration 0 is defined as a set of physical quantities that describe the layout 170. By the above-described method, it is possible to determine the admittance of the interconnect 310, and from the generator admittance and the load admittance, a smoothed contribution can be determined for the interconnect 310.

[0332] Using the updated layout 270, the target design D1 can be defined as the next iteration (e.g., iteration 1 after the initial state 0) that includes the updated material parameters of the cells that make up the 3D representation 235. Using the process data that describes the fab parameter θ, a process simulation can be performed to simulate the manufacturing result of D1, and it can be used to modify D1 to a new wafer state S1. In some embodiments, D1 is manufacturable based on physical simulation, but at the same time, it also violates the Boolean design rule of the process. In this way, the manufacturability checks described here are based on a linear routing, but may not be relatively applicable to a curved routing, and may be developed to minimize other performance metrics such as edge placement errors, rather than to meet the design rules provided by the manufacturer, and may be targeted at function retention.

[0333] In one or more iterations (``i'') of the above-described operations, the wafer state Si The RC value can converge to an optimal value that is also manufacturable based on a physically meaningful process simulation. Advantageously, the manufacturability verification based at least in part on process data can provide a differentiable manufacturability revision where a small change in the design D leads to a small change in the wafer state S. In contrast, the Boolean design rules are not smooth or differentiable and do not allow modifications based on the manufacturability of the updated layout 270 with the gradient-based optimization techniques described above.

[0334] The mask set M, described in more detail with reference to FIG. 7 with respect to the layout file 170 IN and the process data θ are taken in, and an exemplary algorithm for performing the optimization described above to output a modified mask set M OUT includes the following operations that can be parallelized or otherwise reordered. 1. Use a process model (``P'') to calculate the wafer state S0. 2. Use Equation (37) to calculate the net contribution of the wafer state S i with respect to the interconnect 310

[0335]

Number

[0336] and

[0337]

Number

[0338] are calculated. 3. For the interconnect 310, the Gaussian smoothing of Equation (46)

[0339]

Number

[0340] and

[0341]

Number

[0342] Calculate 4. Use the above heuristic to generate a new target design D i+1 Generate. 5. Using at least partially the process simulation P(D i+1 , θ), calculate the mask set M i+1 that is closest to D i+1 and manufacturable. 6. Calculate a new wafer state S i+1 using P(Mi+1, θ) = Si+1. 7. Using the new wafer state S i+1 calculate the optimization objective (e.g., RC value). If the optimization objective value does not meet the target value or criterion (e.g., delta or convergence metric), increment i and return to step 2. 8. Once converged, return the final mask set M F Return.

[0343] Figures 4A - 4D are schematic diagrams showing a two - dimensional planar projection onto the "x - y" plane of a three - dimensional representation 235 of a portion of the layout file 170 and the updated layout 270 according to an embodiment of the present disclosure. The projection represents a two - port interconnect that can be and / or has been completed as described with reference to FIGS. 2 and 3A - 3B, where the optimization of the shape including one or more iterations is completed. Thus, FIGS. 4A - 4D are provided to show the influence of the shape optimization and the layer information 225 and terminal information 220 on the updated layout 225. Although representing exemplary simulation and optimization results, FIGS. 4A - 4D are not intended to be limiting, but rather are intended to be exemplary. For example, the results of the shape optimization may differ from the examples provided in FIGS. 4B - 4D, at least in part, based on the layer information 225, terminal information 220, and layout file 170 used to generate the three - dimensional representation 235. Additionally or alternatively, the figure of merit used to guide the shape optimization, as well as the physical effects such as breakdown or other electric - field effects that can become prominent at small length scales on the order of nanometers or less, can also affect the results of the shape optimization. Thus, an optimization using the same layout file 170, the same layer information 225, and the same terminal information 220 can result in a modified layout 270 that is different from that shown. Advantageously, a realistic interconnect structure can include layer - specific material parameters for each of the plurality of layers. Further, physical parameters such as conductivity can vary within a single interconnect 310, for example, as a function of wall - distance. Such variations can be easily captured by the techniques described herein, but can introduce a great deal of complexity to a rule - based system, which may include adding new rule - based models for each layer and each interconnect 310.

[0344] FIG. 4A is a schematic diagram showing an exemplary plan view 400 of a simplified three-dimensional representation 235 of at least a portion of a layout file 170 that depicts an interconnect 310 (e.g., a two-port interconnect) that couples two terminals 305, according to an embodiment of the present disclosure. The exemplary plan view 400 also includes additional conductive features 415, such as a conducting backplate, vias, or other terminals that are not coupled to the interconnect 310, but are not limited thereto. As described in more detail with reference to FIG. 2, the three-dimensional representation 235 defines the interconnect 310, the terminals 305, the conductive elements 415, and the dielectric material cells 401 that surround the interconnect 310. As described in more detail with reference to FIGS. 3A-3B, the boundary region 313 near the surface of the interconnect 310 can be modified as part of the shape optimization. The exemplary plan view 400 omits the dielectric material cells 401 for visual clarity, but the boundary region 313 is shown in an inset view that places the conductive cells 411 of the interconnect 310 and the dielectric cells 413 outside the interconnect 310 (e.g., corresponding to an oxide or nitride material). Associated with the layout file 170 used to generate the three-dimensional representation, layer information 225 is used to identify the conductive cells 411 and the dielectric cells 413 based on the spatial information from the layout file 170.

[0345] The exemplary plan view 400 follows the convention of a straight routing, but characteristics including but not limited to the RC time constant of the interconnect 310 can indicate that the interconnect 310 can be quasi-optimal in terms of its shape. For example, the electromagnetic interaction between the interconnect 310 and one or more conductive elements 415 can increase the RC time constant for a given set of terminal information 220. As part of reforming the interconnect 310, the terminal information 220 can be used with the 3D representation 235 of the exemplary plan view 400 to determine the individual contribution of cells 401, such as cell 401 near the boundary region 313, to the RC value of the interconnect under specific operating conditions defined in the terminal information 220. Thus, as described in more detail with reference to FIGS. 4B-4D, different terminal information 220 can result in different updated layouts 270.

[0346] FIG. 4B is an exemplary plan view 425 of an updated layout 270 generated from the exemplary plan view 400 of FIG. 4A according to a first set of terminal information 220, according to an embodiment of the present disclosure. Without being bound to a particular set of terminal information 220 and layer information 225, the exemplary plan view 425 represents the output of one or more iterations of an exemplary process 200 that uses the exemplary plan view 400 as an input to the physical simulation module 143.

[0347] Exemplary plan view 425 corresponds to an embodiment of exemplary process 200 where terminal information 220 includes input frequency, driver impedance, and load capacitance. For simplicity, specific values are omitted to focus on the relative impact of the parameters that are components of terminal information 220. It is understood that in practice, the terminal information may include values of parameters corresponding to values used during operation of the integrated circuit. For example, the driver impedance can be or include values of about 0 ohms or more, about 10 ohms or more, about 100 ohms or more, about 1000 ohms or more, about 5000 ohms or more, about 10,000 ohms or more, about 100,000 ohms or more, about 1,000,000 ohms or more, or about 10,000,000 ohms or more, including some and interpolations of the following values. Similarly, the input frequency can be or include frequencies in the kHz range, MHz range, or GHz range, including some and interpolations of the following frequencies. Similarly, the load capacitance can be or include values of about 0.0001 fF or more, about 0.001 fF or more, about 0.01 fF or more, about 0.1 fF or more, about 1.0 fF or more, about 10 fF or more, or about 100 fF or more, including some and interpolations of the following values. In the example for illustration, exemplary plan view 425 can correspond to terminal information specifying a driver impedance of about 1 M ohm, a load capacitance of about 1 fF, and an input frequency of about 100 GHz.

[0348] As shown in FIG. 4B, the shape of interconnect 310 is significantly different in exemplary plan view 425 compared to the straight shape of interconnect 310 in exemplary plan view 400. In particular, the width of interconnect 310 is greater and a non-uniform width expansion of interconnect 310 as a function of its lateral position relative to terminal 305 is applied. As described with reference to FIGS. 2 through 3B, the width that depends on the position of interconnect 310 (the "X" W(Y) is determined using the contribution of cell 401 to the capacitive and conductive terms of the RC time constant of interconnect 310. Without being bound to a particular physical phenomenon, the shape of interconnect 310 of the updated layout 270 shown in exemplary plan view 425 is understood to exhibit a capacitance contribution that is greater than the conductance contribution to the RC value of interconnect 310.

[0349] Advantageously, the techniques described herein enable an exemplary system 100 to generate an updated layout 270 corresponding to an exemplary plan view 425 using physically meaningful information rather than a physics-naive heuristic, by one or more iterations of an exemplary process 200. For example, an exemplary plan view 425 might appear to have been generated by a rule-based model that was instructed to widen the width of interconnect 310 while maintaining a minimum distance between interconnect 310 and conductive element 415. However, such a physics-naive model does not generate an updated layout 270 that results in an RC value optimized with respect to terminal information 220 and layer information 225.

[0350] However, as described in more detail with reference to FIG. 1, the physical simulation module 143 can be enhanced by one or more machine learning models 144 trained to reform at least a portion of the interconnect 310. For example, a convolutional neural network can be trained to accept a layout file 170 or a three-dimensional representation 235 as input along with terminal information 220 and / or layer information 225 and output a reformed interconnect 310. The output of the machine learning model 144 can be or include, for example, the material identifier of one or more cells 401, a portion of the interface 311, etc. Unlike a physically naive rule-based model, the machine learning model 144 can be trained with respect to a particular set of terminal information 220 and / or layer information 225, for example, using a labeled training set of a linear layout file 170 and an updated layout 270 (e.g., as a supervised training technique). In this way, the machine learning model 144 can approximate the physical simulation described with reference to FIGS. 3A-3B.

[0351] Figure 4C is another exemplary plan view 450 of an updated layout 270 generated from the exemplary plan view 400 of FIG. 4A using a second set of terminal information 220 according to an embodiment of the present disclosure. Similar to the exemplary plan view 425 of FIG. 4B, the exemplary plan view 450 is generated by the operation of the exemplary process 200 of FIG. 2 as described in more detail with reference to FIGS. 3A-3B. Compared to the exemplary plan view 425, the exemplary plan view 450 includes relatively narrow interconnects and has a wider spacing between the interconnect surface 311 and the conductive element 415. The exemplary plan view 450 shows the effect of different terminal information 220 on the modification of the shape of the interconnect 310, based at least in part on the operating parameters of the terminals 305 and interconnects 310, such as driver impedance, load capacitance, or frequency. In the example of FIG. 4C, the driver impedance is a relatively higher value than the corresponding driver impedance used to generate the exemplary plan view 425. From this, it can be seen that as the impedance increases, the conductive contribution of the interconnect cell 401 decreases relative to the capacitive contribution of the adjacent cell 401 in the boundary region 313, resulting in relatively narrow interconnects 310. However, it is noted that the interconnect 310 of the exemplary plan view 450 is wider than the interconnect 310 of the exemplary plan view 400, indicating that the typical straight "shortest path" route of the normal routing algorithm is not optimized with respect to the RC time constant. This, in turn, indicates that imposing the convention of straight routing can lead to a performance degradation of the integrated circuit that scales with the number of interconnects.

[0352] Figure 4D is an exemplary plan view 460 of an updated layout 270 generated from the exemplary plan view 400 of FIG. 4A according to a third set of terminal information 220 according to an embodiment of the present disclosure.

[0353] Similar to exemplary plan view 425 of FIG. 4B and exemplary plan view 450 of FIG. 4C, exemplary plan view 460 is generated by the operation of exemplary process 200 of FIG. 2, as described in more detail with reference to FIGS. 3A-3B. Compared to exemplary plan view 425, exemplary plan view 460 includes relatively narrow interconnects and there is a wider spacing between interconnect surface 311 and conductive element 415. Exemplary plan view 460 shows the effect of different terminal information 220 on the modification of the shape of interconnect 310, based at least in part on the operating parameters of terminals 305 and interconnect 310, such as driver impedance, load capacitance, or frequency. In the example of FIG. 4C, the driver impedance is a relatively higher value than the corresponding driver impedance used to generate exemplary plan view 425. From this, it can be seen that as the impedance increases, the conductive contribution of interconnect cell 401 decreases relative to the capacitive contribution of adjacent cell 401 in boundary region 313, resulting in relatively narrow interconnects 310.

[0354] It is noted that interconnect 310 of exemplary plan view 460 is substantially the same width as interconnect 310 of exemplary plan view 400, except that the position of cell 401 of interconnect 310, and thus interface 311, is relatively repositioned with respect to the position of terminal 305. From this, it is shown that reforming interconnect 310 as part of exemplary process 200 can include translating, displacing, and / or redirecting interconnect 310 relative to one or more conductive elements 415 in layout file 170, as well as widening or narrowing the width of interconnect 310.

[0355] Figures 5A - 5B are schematic diagrams showing exemplary three - dimensional representations 535 of a layout file 170 and an updated layout 270, respectively. As shown, a three - dimensional representation 235 including the exemplary three - dimensional representation 535 includes three - dimensional information that is discretized into cells 401 with material properties assigned using layer information 225. Elements of the layout file 170 can be at different three - dimensional positions labeled using the Cartesian "x", "y", and "z" axes of FIGS. 5A - 5B. In some embodiments, the optimization of the interconnect 310 can be limited to the interconnect 310 or can also include the terminals 305. Similarly, one or more boundaries 311 can be constrained as part of the operation of the exemplary process 200. In this way, the modification of the shape of the interconnect 310 can be guided away from non - physical solutions.

[0356] FIG. 5A is a schematic diagram showing an exemplary three - dimensional representation 235 of a layout file 170 according to an embodiment of the present disclosure. The layout file 170 includes an interconnect 310, terminals 305, a conductive element 415 at substantially the same "z" position as the interconnect 310, and an additional conductive element 515 at a different "z" position from the interconnect 310. In some embodiments, the conductive element 515 can be or can include the terminal 305. The layout file 170 represents an exemplary input to the exemplary process 200. Thus, the interconnect 310, the conductive element 515, and the conductive element 415 follow the convention of a straight routing. The three - dimensional representation 235 is discretized into cells 501, and it is understood that the straight routing enables each boundary 311 of the interconnect 310 to be represented as a smooth unitary surface as opposed to the quantized curvilinear boundaries 311 shown in FIG. 5B.

[0357] FIG. 5B is a schematic diagram showing an exemplary three - dimensional representation 575 of an updated layout file 270 according to an embodiment of the present disclosure. The exemplary three - dimensional representation 575 represents an optimized interconnect 310 that is reformed according to the exemplary process 200 as described in more detail with reference to FIG. 2. As described above, one or more interface surfaces 311 of the interconnect 310 can be constrained such that the interconnect 310 is reformed while maintaining at least a portion of the electrical contacts to the conductive element 515 while improving RC, as described in more detail with reference to FIGS. 3A - 3B. In connection with FIGS. 3A - 3B, FIG. 5B shows that a modification of the physically - based shape of the interconnect 310 is widened at one or more positions, narrowed at one or more positions, redirected, translated, displaced, or otherwise deformed based at least in part on an electromagnetic field simulation that describes the interaction between the interconnect 310 and the conductive element 415 or the conductive element 515, resulting in a curvilinear interconnect 310. As described in more detail with reference to FIGS. 4A - 4D, the final shape of the interconnect 310 is based at least in part on the terminal information 220 and the material information 225, and thus the shape of the interconnect shown in FIG. 5B is intended as an example and not a limiting embodiment. In some embodiments, differences in the terminal information 220 and / or the layer information 225 can result in different shape modifications in the exemplary three - dimensional representation 575.

[0358] FIGS. 6A - 6C are schematic diagrams showing exemplary plan views of the layout file 170 and the updated layout 270 for intermediate and final iterations of the exemplary process 200, respectively. FIGS. 6A - 6C are provided to show the progressive shape modification of the interconnect 310 over multiple iterations of the exemplary process 200 as described in more detail with reference to FIG. 2.

[0359] FIG. 6A is a schematic diagram showing an exemplary plan view 600 of a layout file 170 according to an embodiment of the present disclosure. The exemplary plan view 600 corresponds to an exemplary three-dimensional representation 535 of FIG. 5A projected onto the “x-y” plane at a “z” position of the interconnect 310 to facilitate visual interpretation. The exemplary plan view 600 shows that the interconnect 315, the conductive element 415, and the conductive element 515 follow the convention of a straight routing after routing but before the first iteration of the exemplary process 200. However, in some embodiments, the layout file 170 is received after at least one iteration of the exemplary process 200. For example, the updated layout 270 may be encoded as the layout file 170 and stored in the third database 165. An example of such a process is where a first set of one or more iterations of the exemplary process 200 is completed and then the updated layout 270 is stored as the layout file 170 so as to be accessed for additional iterations of the exemplary process 200 if shown.

[0360] FIG. 6B is a schematic diagram showing an exemplary plan view 630 of an updated layout 270 in an intermediate state according to an embodiment of the present disclosure. The exemplary plan view 630 represents the "x-y" projection of the three-dimensional representation 235 after one or more iterations of the exemplary process 200 have applied one or more shape modifications to the interconnect 310, as compared to the exemplary plan view 600. As shown, the interconnect 310 no longer follows the convention of a straight routing, but rather includes one or more curved surfaces. The three-dimensional representation 235 is discretized into cells 401, while FIG. 6B includes a smoothed interface surface 311 for ease of visual interpretation. In some embodiments, however, the three-dimensional representation 235 may be smoothed as part of generating the updated layout 270 (e.g., a smoothed updated layout 270 may be used to generate a mask that is transmitted to the manufacturing system 115). One or more shape constraints can be seen in that the interconnect 310 is constrained to maintain contact with the conductive element 515 at one or more positions corresponding to the contact points with the terminal 305. The interconnect 310 is shown with three contact points, but it is understood that the interconnect 310 can represent the "two-port" configuration described in connection with FIGS. 3A-3B.

[0361] FIG. 6C is a schematic diagram showing an exemplary plan view 650 of an updated layout 270 in an advanced state according to an embodiment of the present disclosure. The exemplary plan view 650 represents the "x-y" projection of the three-dimensional representation 235 after one or more additional iterations of the exemplary process 200 have applied one or more shape modifications to the interconnect 310, as compared to the exemplary plan view 630 of FIG. 6B. The exemplary plan view 650, in response to the local contribution of the cell 401 to the RC time constant based at least in part on the terminal information 220 and the layer information 225, (i) increases the distance between the interconnect 310 and the conductive element 415, (ii) constrains the interconnect 310 to maintain contact with the terminal 305, and (iii) the local width "W X(Y) variations are incorporated as a function of the lateral position on interconnect 310, showing multiple shape modifications to interconnect 310. In some embodiments, the exemplary plan view 650 is the result of iterations applied to the updated layout 270. In some embodiments, the exemplary plan view 650 is generated from operations applied to the 3D representation 235 prior to generating the updated layout 270. In this way, the heuristics described with reference to FIGS. 3A - 3B can be applied to the 3D representation 235, for example, by reallocating the material property information of one or more cells 401.

[0362] FIG. 7 is a block diagram showing an exemplary flow 700 of operations applied to a 3D representation as part of the exemplary process 200 of FIG. 2 according to an embodiment of the present disclosure. Similar to the operations that are components of the exemplary process 200, the exemplary flow 700 represents operations that can be performed locally and / or distributedly by a computer system (e.g., server 105, client computing device 110, etc.). Accordingly, the blocks that are components of the exemplary flow 700 can be understood to represent machine-readable instructions encoded in software (e.g., software 155 of FIG. 1) that enable a computer system to modify the shape of interconnect 310, terminal 305, etc., as part of a physical-based optimization of layout file 170 that can introduce curved features to the routed elements of layout file 170. The blocks that are components of the exemplary flow 700 are shown as proceeding in order, but it is understood that one or more blocks can be omitted, repeated, rearranged, or subdivided as part of the iterations of the exemplary process 200 and / or the implementation on a particular computer system. For example, in the context of a distributed system, blocks can be subdivided into processes with multiple components to facilitate parallelization. In this way, two or more blocks can be executed in parallel rather than in order.

[0363] In block 705, the exemplary flow 700 includes generating a 3D representation 235 that corresponds to operation 207 of the exemplary process 200. Operations 201 - 205 of the exemplary process 200 are omitted from the exemplary flow 700 to focus the description on the components of operations 207 - 211. As described in more detail with reference to FIG. 2, block 705 may include discretizing the layout file 170 or the modified layout 270 to generate the 3D representation 235.

[0364] In blocks 710 - 715, the exemplary flow 700 includes generating a conductive contribution of at least a subset of the cells 401 of the 3D representation 235 to the RC time constant of the interconnect 310. As described in more detail with reference to FIGS. 3A - 3B, in some cases, at least some of the contributions for the cells 401 of the 3D representation 235 may be ignored, for example, if that part of the cell 401 is relatively far from the interface 311 and thus material information reallocation is unlikely to occur. The individual contributions

[0365]

Number

[0366] and

[0367]

Number

[0368] The detailed physical simulation information for determining and is considered above with reference to FIGS. 3A - 3B.

[0369] In block 720, one or more smoothing operations are applied to each cell to the contributions generated in blocks 710-715. The smoothing operation can be or can include a three-dimensional smoothing function such as a Gaussian smoothing function using the standard deviation parameter σ. As described in more detail with reference to FIG. 3B, the smoothing enables the relative contributions of adjacent cells 401 to be extrapolated, thereby facilitating a heuristic for determining the reallocation of materials described in connection with blocks 721-730 that can be performed for each cell.

[0370] In decision block 721, for a given cell 401, the position of the given cell 401 within the three-dimensional representation 235 and / or the material property metadata of the given cell 401 are used to determine whether the given cell 401 forms part of the interconnect 310 or part of the surrounding oxide. In some embodiments, cells 401 corresponding to the terminals 305 and / or the conductive elements 415 and 515 are omitted from the operation of the exemplary flow 700. In some embodiments, for example, at least a subset of the cells 401 corresponding to the interconnect 310 are similarly omitted as a technique for imposing one or more shape constraints on the interconnect 310.

[0371] In decision blocks 723 and 724, as described in more detail with reference to FIGS. 3A-3B, an appropriate comparison of the individual contributions generated in blocks 710 and 715 is applied to determine whether the material information of a given cell 401 should be reallocated in block 725 or retained in block 730. Block 730 is shown as two blocks, but the instructions are understood to be equivalent regardless of whether a given cell 401 forms part of the interconnect 310 or part of the surrounding oxide.

[0372] In block 735, the modifications shown for the subset of cells 501 by blocks 721 - 730 are encoded into the updated layout 270. As described in more detail with reference to FIG. 2, the updated layout 270 can be generated by applying a reallocation of one or more materials to the 3D representation 235 to generate an updated 3D representation 235 (e.g., the exemplary 3D representation 575 of FIG. 5B). And then, the updated representation can be converted into a layout file 170 (e.g., OASIS or GDSII format) for use in the manufacture of the integrated circuit.

[0373] In some embodiments, the exemplary flow 700 each includes a manufacturability determination at blocks 740 and 745 and a modification as a result for the updated layout 270. As described in more detail with reference to FIGS. 2 and 3A - 3B, the verification of the manufacturability of the updated layout 270 can include performing a process simulation using process data that describes the semiconductor manufacturing system 115 that enables one or more manufacturability criteria to be evaluated. For example, a normal Boolean design rule checker may return false values for the updated layout 270, at least in part due to curved routing, while a physics - based process simulation may enable functionality preservation to guide the manufacturability verification. Thus, the manufacturability verification can include determining whether the updated layout 270 represents a non - physical solution, whether the updated layout 270 will function according to the design when manufactured, and / or whether the updated layout 270 violates any Boolean design rules applied to the linear portions of the updated layout 270.

[0374] In some cases, the updated layout 270 may include portions that conform to a linear routing standard. For example, the interconnect 310 can include a curved boundary surface 311 in the "x-z" and "y-z" planes and can include a flat or substantially flat boundary surface 311 in the "x-y" plane. Similarly, the interconnect 310 can be constrained by a minimum thickness in the "z" axis such that a Boolean design rule check, which can be of relatively lower computational load than a physics-based process simulation, can verify whether the updated layout 270 is manufacturable. For that purpose, such a minimum thickness constraint can be encoded as part of the operation of the exemplary process 200. For example, modifying the 3D representation 235 as part of the operation 211 of the exemplary process 200 can include the constraint that the minimum number of cells 401 (e.g., assigned conductive material properties) attributable to the interconnect 310 is maintained in the "z" direction at all positions within the interconnect 310 (e.g., defined by the boundary surface 311).

[0375] Advantageously, the operations of the exemplary process 200 and the exemplary flow 700 can be performed for various combinations of input and output terminals 305, as described by the terminal information 220. So-called "fan-out", "fan-in", and "fan-in-out" layouts 170 include at least one input terminal and at least one output terminal, but can include multiple of either or both.

[0376] FIG. 8 is a schematic diagram showing an exemplary three-dimensional representation 835 of an updated layout file 270 including a fan-out configuration according to an embodiment of the present disclosure. The exemplary three-dimensional representation 835 represents a modified interconnect 310 having a shape that is reformed according to the exemplary process 200, as described in more detail with reference to FIG. 2. As shown, and as described in more detail in connection with FIGS. 3A-3B and, in particular, the detailed consideration of the fan-out optimization including equations (39)-(42), the first terminal 305-1 of the terminals 305 represents a single input terminal, while the second terminal 305-2, the third terminal 305-3, and the fourth terminal 305-4 represent output terminals. The interconnect 310 exhibits a curved feature discretized as a function of position (r) and a tee shape with non-uniform width such that output terminals 305-2 to 305-3 are in different quadrants of the three-dimensional representation 835. In that regard, the interconnect 310 of the three-dimensional representation 835 narrows at the split point into a plurality of branches each coupling the input terminal 305-1 to a different output terminal 305-2, 305-3, or 305-4. It is also shown that the interconnect 310 has a substantially uniform thickness in the "z" direction, but each branch has a different width in the "x" or "y" direction. In this way, the influence of the different terminal information 220 describing each terminal 305 is shown as a result of the different operating parameters of the different terminals 305.

[0377] FIG. 9 is a schematic diagram showing an exemplary three - dimensional representation 935 of an updated layout file 270 including a fan - in - out configuration according to an embodiment of the present disclosure. The exemplary three - dimensional representation 935 represents a modified interconnect 310 in a shape that is reformed according to the exemplary process 200 as described in more detail with reference to FIG. 2. The exemplary three - dimensional representation 935 can be understood as a modification of the exemplary three - dimensional representation 835, with a fifth terminal 305 - 5 representing a second input terminal added. Similar to the first terminal 305 - 1, the fifth terminal 305 - 5 is conductively coupled to the output terminals 305 - 2, 305 - 3, and 305 - 4 via the interconnect 310. Similar to FIG. 8, the interconnect 310 branches near a split point that is substantially aligned with the output terminals 305 - 3 and 305 - 4. The interconnect 310 of the three - dimensional representation 935 also shows a wider region between the split point and the input terminals 305 - 1 and 305 - 5, along with a relative narrowing of the conductive paths after splitting. In contrast to the operations described as part of fan - out optimization, fan - in optimization can proceed by segmenting the layout file into a plurality of partial layouts that are modified by the operations of the exemplary process 200. After modifying the shape of the partial layouts, an updated layout is generated by merging the partial layouts. Thus, fan - in - out modification can include parallel instances of the exemplary process 200 and one or more preliminary operations applied to the layout file, for example, as part of a discretization operation.

[0378] FIG. 10 is a block diagram showing an exemplary flow 1000 for modifying the shape of a fan-in or fan-in / out layout file 170 according to an embodiment of the present disclosure. Similar to exemplary process 200 and exemplary flow 700, exemplary flow 1000 represents operations that can be performed locally and / or distributedly by a computer system (e.g., server 105, client computing device 110, etc.). Thus, the blocks that are components of exemplary flow 1000 can be understood to represent machine-readable instructions encoded in software (e.g., software 155 of FIG. 1) that enable a computer system to modify the shape of interconnect 310, terminal 305, etc. as part of a physical-based optimization of layout file 170 that can introduce curvilinear features into the routed elements of layout file 170. The blocks that are components of exemplary flow 1000 are shown as proceeding in order, but it is understood that one or more blocks can be omitted, repeated, rearranged, or subdivided as part of the iteration of exemplary process 200 and / or the implementation on a particular computer system. For example, in the context of a distributed system, blocks can be subdivided into processes with multiple components to facilitate parallelization. In this way, two or more blocks can be executed in parallel rather than in order.

[0379] In block 1005, exemplary flow 1000 includes receiving layout data 215 that includes terminals 305 and interconnect 310. Similar to exemplary process 200, layout data 215 includes terminal information 220 and layer information 225. Terminal information 220 encodes whether terminal 305 is an input terminal or an output terminal. Thus, block 1010 includes generating a separate conductive path for each input terminal. For example, in the exemplary three-dimensional layout 1035 of FIG. 9, interconnect 310 couples two input terminals to three output terminals. Thus, block 1010 includes defining a first conductive path between a first input terminal 305-1 and output terminals 305-2, 305-3, and 305-4, and defining a second conductive path between a second input terminal 305-5 and the output terminals. In this way, a fan-in / fan-out configuration can be modified by the operation of exemplary process 200 by defining a number of separate conductive paths equal to the number of input terminals. Advantageously, implementing exemplary flow 1000 enables a complex layout file 170 to be segmented into a relatively simple configuration for parallel processing. In this way, a physically based shape modification can be applied to a layout file 170 that would otherwise not pass design rule-based manufacturability verification. Further, integrated circuit layouts often incorporate many repeated instances of basic layout elements associated with circuit components (e.g., fin-FETs). Thus, segmentation can be used to enable layout data 215 to be entered into a database of partial layouts indexed by layer information 225 and terminal information 220, thereby further improving the performance of exemplary system 100.

[0380] In block 1015, the first conductive path defined from the layout data 215 is repeated using at least a subset of the operations of the exemplary process 200. As described with reference to FIGS. 3A - 8, one or more repetitions of the exemplary process 200 can generate an updated layout 270. However, in the context of the exemplary flow 1000, the repetition of the first path provides a partial update of the layout file 170. At the same time, in parallel, sequentially, or otherwise, block 1020 includes repeating a second conductive path using at least a subset of the operations of the exemplary process 200. As described above, the exemplary flow 1000 is described with respect to a layout file 170 that includes two input terminals 305. For that purpose, blocks 1000 and 1015 may involve additional instances of the exemplary process 200 for additional conductive paths corresponding to a third input terminal 305, a fourth input terminal 305, and so on.

[0381] In block 1025, the exemplary flow 1000 includes merging paths with modified shapes to generate an updated three - dimensional representation 235 for a fan - in or fan - in - out configuration. In some embodiments, it includes applying a Boolean function to each cell to determine whether a given cell 401 should be assigned to a conductive material or a dielectric or insulating material. Examples of Boolean functions include AND, OR, INCLUSIVE OR, EXCLUSIVE OR, etc. In an example for illustration, an INCLUSIVE OR function can be defined such that cell 401 is assigned to a conductive material (e.g., metal) when cell 401 is assigned as metal of either the first conductive path or the second conductive path, in order to avoid removing both portions of an interconnect 310 that connects to only one of the input terminals 305.

[0382] FIG. 11 is a schematic diagram showing an exemplary three - dimensional representation 1175 of a multilayer layout file 170 including a plurality of interconnects 310 that couple a plurality of terminals. The exemplary three - dimensional representation 1175 represents an optimized layout file 170 that includes a first interconnect 310 - 1 and a second interconnect 310 - 2 that are reformed according to an exemplary process 200 as described in more detail with reference to FIG. 2. In the example of FIG. 11, both the first interconnect 310 - 1 and the second interconnect 310 - 2 are fan - in - outs configured to couple a plurality of input terminals to a plurality of output terminals on two different “z” layers of an integrated circuit layout. For such a multilayer layout 170, the exemplary process 200 may include a plurality of parallel optimization processes that subdivide the optimization operation and then incorporate the operations of exemplary flow 700 and exemplary flow 1000 to merge the components of the exemplary three - dimensional representation 1175 into an updated layout 270.

[0383] In the example for illustration shown in the exemplary three - dimensional representation 1175, the first interconnect 310 - 1 may be modified as described in more detail with reference to FIGS. 8 - 11. During the optimization of the first interconnect 310 - 1, the second interconnect 310 - 2 may be kept static. After the convergence of the first interconnect 310 - 1, the second interconnect 310 - 2 can be optimized as described in more detail with reference to FIGS. 8 - 11, and the first interconnect 310 - 1 is kept static. By repeating this process, as described in more detail with reference to FIG. 2, both the first interconnect 310 - 1 and the second interconnect 310 - 2 can be modified to optimize their respective RC values or other optimization metrics. Additionally or alternatively, the first interconnect 310 - 1 and the second interconnect 310 - 2 can be optimized in parallel, and thus, in each iteration of the exemplary process 200, a plurality of interconnects 310 are modified together. Advantageously, such an approach allows for fewer iterations of the exemplary process 200.

[0384] The processes described above are described from the perspectives of computer software and hardware. The described technology may comprise instructions executable by a machine embodied in a tangible or non-transitory machine (e.g., a computer) readable storage medium, and those instructions executable by the machine, when executed by the machine, cause the machine to perform the described operations. Additionally, the process may be embodied in hardware such as an application specific integrated circuit ("ASIC") or otherwise.

[0385] A tangible machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a non-transitory form that is accessible by a machine (e.g., a computer, a network device, a portable information terminal, a manufacturing tool, any device having a set of one or more processors, etc.). For example, the machine-readable storage medium includes recordable / non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0386] The foregoing description of the illustrated embodiments of the invention, including what is set forth in the "Summary," is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Specific embodiments and examples of the invention are described herein for illustrative purposes, but as will be recognized by those of ordinary skill in the art, various modifications are possible within the scope of the invention.

[0387] Such modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed as limiting the invention to the specific embodiments disclosed herein. Rather, the scope of the invention should be determined by all of the following claims, and the claims should be construed in accordance with established principles of claim interpretation.

Description of the Reference Numerals

[0388] 100 System 105 Server 110 Client Computing Device 111 Display 115 Semiconductor Manufacturing System 120 Network 125 First Database 130 Training Data 135 Second Database 137 Process Data 140 Shape Optimizer 141 Discretization Module 143 Physical Simulation Module 144 Machine Learning Model 145 Shape Optimization Module, Model 146 Database 147 Process Simulator 149 Modification Module 150 Machine Learning Model 155 Software 160 Computer Circuit 165 Third Database 170 Design File, Integrated Circuit Layout 200 Process 215 Layout Data 220 Terminal Information 225 Layer Information, Material Information 235 3D Representation 250 Capacitive Contribution 255 Conductive Contribution 260 Characteristic Index 270 Updated Layout 300 Toy Model 305 Terminal 305-1 First Terminal 305-2 Second Terminal 305-3 Third Terminal 305-4 Fourth Terminal 305-5 Fifth Terminal 310 Interconnect 310-1 First interconnect 310-2 Second interconnect 311 Interconnect boundary, interface surface, interconnect surface 313 Boundary region 400 Plan view 401 Cell 411 Conductive cell 413 Dielectric cell 415 Conductive feature, conductive element 425 Plan view 450 Plan view 460 Plan view 501 Cell 515 Additional conductive element 535 Three-dimensional representation 575 Three-dimensional representation 600 Plan view 630 Plan view 650 Plan view 700 Flow 835 Three-dimensional representation 935 Three-dimensional representation 1000 Flow 1035 Three-dimensional layout 1175 Three-dimensional representation

Claims

1. A method implemented by a computer for optimizing conductive interconnects, comprising: receiving an integrated circuit layout including a plurality of terminals and interconnects, wherein the interconnects represent conductive couplings between the plurality of terminals; receiving terminal information describing operating parameters of the plurality of terminals; receiving layer information describing material compositions and material property information of the plurality of terminals and the interconnects; generating a three-dimensional representation of the integrated circuit using the integrated circuit layout and the layer information, the three-dimensional representation including cells corresponding to discrete volume elements of the three-dimensional representation, the cells representing at least a portion of the interconnects or at least a portion of non-conductive material outside the interconnects; using the three-dimensional representation and the terminal information to determine individual contributions of the cells to resistance-capacitance (RC) values of the interconnects; generating an updated integrated circuit layout based at least in part on the individual contributions A method implemented by a computer, comprising:

2. The step of generating the individual contributions of the elements to the RC values includes: determining generator admittance and load admittance of the cells based at least in part on the layer information and the terminal information; determining input admittance using the generator admittance and the load admittance; determining admittance density of the cells using the input admittance, the admittance density describing a local contribution of the cells to the admittance of the interconnects; generating differential RC values of the cells based at least in part on the admittance density The method implemented by a computer according to claim 1, comprising:

3. wherein the cell is a first cell, the three-dimensional representation further includes a second cell, and the step of generating the updated integrated circuit layout includes: determining conductive contributions of the first cell and the second cell to the conductance of the interconnect; determining capacitive contributions of the first cell and the second cell to the capacitance of the interconnect; Using the respective contributions of the first cell and the second cell to generate a smoothed conductive contribution and a smoothed capacitive contribution of the first cell; Determining a material composition of the first cell based at least in part on the smoothed contribution of the first cell; The method implemented by a computer according to claim 1, comprising:

4. Determining the material composition includes: When the cell represents a part of the interconnect, if the smoothed capacitive contribution of the first cell exceeds the smoothed conductive contribution of the first cell, reassigning the cell to represent the non-conductive material, or When the cell represents a part of the non-conductive material, if the smoothed conductive contribution of the first cell exceeds the smoothed capacitive contribution of the first cell, reassigning the cell to represent the interconnect; The method implemented by a computer according to claim 3, comprising:

5. The method implemented by a computer according to claim 4, wherein generating the smoothed contribution of the first cell includes three-dimensional smoothing of the respective contributions of the first cell and the second cell.

6. The method implemented by a computer according to claim 4, wherein generating the smoothed contribution of the first cell includes Gaussian smoothing using a standard deviation parameter σ less than the width of the interconnect in the integrated circuit layout.

7. Inputting the updated integrated circuit layout into a process model configured to output a simulated manufactured integrated circuit produced by a semiconductor manufacturing system using the updated integrated circuit layout; Generating the simulated manufactured integrated circuit as an output of the process model; Determining the manufacturability of the updated integrated circuit layout with respect to the semiconductor manufacturing system using the output of the process model; The method implemented by a computer according to claim 1, further comprising:

8. The manufacturability indicates that the updated integrated circuit layout cannot be manufactured by the semiconductor manufacturing system, and the method includes: A step of generating a modified layout using the updated integrated circuit layout and the process model, wherein the modified layout is manufacturable by the semiconductor manufacturing system, further comprising the method according to claim 7, implemented by a computer.

9. The method according to claim 1, wherein the plurality of terminals includes an input terminal and two output terminals, implemented by a computer.

10. The plurality of terminals includes a plurality of input terminals and at least one output terminal, the three-dimensional representation is a first representation, and the method includes Generating the corresponding first representation when a first input terminal included in the input terminals is active and the remaining input terminals are inactive; Generating a second representation using the integrated circuit layout and the layer information, wherein the second representation corresponds when a second input terminal included in the input terminals is active and the remaining input terminals are inactive, and both the first representation and the second representation include the cell; Generating a first partial update using the first representation; Generating a second partial update using the second representation; Generating the updated integrated circuit layout using the first partial update and the second partial update The method according to claim 1, further comprising.

11. The method according to claim 10, wherein the step of generating the updated integrated circuit layout includes combining the first partial update and the second partial update using an inclusive OR operator, implemented by a computer.

12. A step of outputting the updated integrated circuit layout, Generating an updated integrated circuit layout file using the updated integrated circuit layout, and Storing the updated integrated circuit layout file in a data store The method according to claim 1, further comprising the step of including.

13. A non-transitory computer-readable memory device storing machine-executable instructions, wherein when the machine-executable instructions are executed by the machine, the machine Receiving an integrated circuit layout including a plurality of terminals and interconnects, wherein the interconnects represent conductive couplings between the plurality of terminals; Receiving terminal information describing operating parameters of the plurality of terminals; Receiving layer information describing material compositions and material property information of the plurality of terminals and the interconnects; Generating a three-dimensional representation of the integrated circuit using the integrated circuit layout and the layer information, wherein the three-dimensional representation includes cells corresponding to discrete volume elements of the three-dimensional representation, and the cells represent at least a portion of the interconnects or at least a portion of a non-conductive material outside the interconnects; Using the three-dimensional representation and the terminal information to determine individual contributions of the cells to resistance-capacitance (RC) values of the interconnects; and Generating an updated integrated circuit layout based at least in part on the individual contributions A non-transitory computer-readable memory device that causes an operation including the above to be executed.

14. Generating the individual contribution of the element to the RC value includes Determining generator admittance and load admittance of the cell based at least in part on the layer information and the terminal information; Determining input admittance using the generator admittance and the load admittance; Determining admittance density of the cell using the input admittance, wherein the admittance density describes a local contribution of the cell to the admittance of the interconnect; Generating a differential RC value of the cell based at least in part on the admittance density; The non-transitory computer-readable memory device according to claim 13, comprising the above.

15. The three-dimensional representation further includes a second cell, and generating the updated integrated circuit layout includes Determining conductive contributions of the first cell and the second cell to the conductance of the interconnect; Determining capacitive contributions of the first cell and the second cell to the capacitance of the interconnect; Generating a smoothed conductive contribution and a smoothed capacitive contribution of the first cell using the respective contributions of the first cell and the second cell; Determining the material composition of the first cell based at least in part on the smoothed contribution of the first cell The non-transitory computer-readable memory device of claim 13, comprising: **Claim 16** Determining the material composition comprises When the cell represents a part of the interconnect, if the smoothed capacitive contribution of the first cell exceeds the smoothed conductive contribution of the first cell, reassigning the cell to represent the non-conductive material, or When the cell represents a part of the non-conductive material, if the smoothed conductive contribution of the first cell exceeds the smoothed capacitive contribution of the first cell, reassigning the cell to represent the interconnect The non-transitory computer-readable memory device of claim 15, comprising: **Claim 17** Generating the smoothed contribution of the first cell includes Gaussian smoothing using a standard deviation parameter σ less than the initial width of the interconnect in the integrated circuit layout. The non-transitory computer-readable memory device of claim 13 **Claim 18** When the instructions are executed by the machine, cause the machine to Input the updated integrated circuit layout into a process model configured to output a simulated manufactured integrated circuit produced by a semiconductor manufacturing system using the updated integrated circuit layout Generate the simulated manufactured integrated circuit as an output of the process model Determine the manufacturability of the updated integrated circuit layout with respect to the semiconductor manufacturing system based at least in part on the output of the process model The non-transitory computer-readable memory device of claim 13, causing the machine to perform further operations including: **Claim 19** Wherein the manufacturability indicates that the updated integrated circuit layout is not manufacturable by the semiconductor manufacturing system, and the instructions, when executed by the machine, cause the machine to Generate a modified layout based at least in part on the updated integrated circuit layout and the process model, wherein the modified layout is manufacturable by the semiconductor manufacturing system The non-transitory computer-readable memory device of claim 18, causing further operations to be performed that include [

20. ] wherein the plurality of terminals include a plurality of input terminals and at least one output terminal, the three-dimensional representation is a first representation, and the instructions, when executed by the machine, cause the machine to generate the corresponding first representation when a first input terminal included in the input terminals is active and the remaining input terminals are inactive; generate a second representation using the integrated circuit layout and the layer information, the second representation corresponding when a second input terminal included in the input terminals is active and the remaining input terminals are inactive, and both the first representation and the second representation include the cell; generate a first partial update using the first representation; generate a second partial update using the second representation; and generate the updated integrated circuit layout using the first partial update and the second partial update. The non-transitory computer-readable memory device of claim 13, causing further operations to be performed that include

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