Semiconductor structure preparation method and semiconductor structure

Abstract

The present disclosure relates to a method for preparing a semiconductor structure and a semiconductor structure. The method forms a first sacrificial layer on a first metal layer structure, forms a plurality of step-type first grooves spaced apart by etching the first sacrificial layer, and forms a second metal conductor and a metal through hole with a width smaller than the second metal conductor in the first groove. Next, the first sacrificial layer between adjacent second metal conductors is removed to form a second groove, and a dielectric layer material is filled in the second groove to form a first dielectric layer. After etching the first dielectric layer to expose a portion of the first sacrificial layer on the side wall of the metal through hole, the first sacrificial layer on the side wall of the metal through hole is removed to form a first air gap between the first dielectric layer and the metal through hole, and finally the dielectric layer material is continued to be filled in the second groove to make the top surface of the first dielectric layer flush with the top surface of the second metal conductor. Since the dielectric constant of air is much lower, the formation of the first air gap reduces the capacitance between metal interconnect structures, improves RC delay, and improves semiconductor performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] As semiconductor process technology continues to shrink, the density of the back-end metal interconnect structure in integrated circuit chips is getting higher and higher. As the semiconductor structure shrinks, the parasitic capacitance between metal interconnects increases, and the RC (Resistance-Capacitance) delay between metal interconnects becomes more and more serious, affecting semiconductor performance.

[0003] The existing technology widely uses low-k materials to make dielectric layers in metal interconnect structures to reduce the capacitance between metal interconnects and improve RC delay. However, traditional low-k materials can no longer meet the ever-changing preparation requirements. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure preparation method and a semiconductor structure that can reduce parasitic capacitance between metal interconnects.

[0005] In order to achieve the above objectives, on the one hand, the present disclosure provides a method for preparing a semiconductor structure, the method comprising:

[0006] Providing a first metal layer structure, forming a first sacrificial layer on the first metal layer structure, etching the first sacrificial layer to form a plurality of step-shaped first grooves arranged at intervals; forming a metal through hole and a second metal wire in the first groove, wherein the metal through hole is located between the first metal layer and the second metal wire in the first metal layer structure, and the width of the metal through hole is smaller than that of the second metal wire;

[0007] Removing the first sacrificial layer between adjacent second metal wires to form a second trench, and filling the second trench with a dielectric layer material to form a first dielectric layer;

[0008] Etching the first dielectric layer until a portion of the first sacrificial layer on the side wall of the metal through hole is exposed, removing the first sacrificial layer on the side wall of the metal through hole, and forming a first air gap between the first dielectric layer and the metal through hole;

[0009] The dielectric layer material is continuously filled in the second trench to make the top surface of the first dielectric layer flush with the top surface of the second metal wire.

[0010] In some embodiments, etching the first dielectric layer to expose a portion of the first sacrificial layer on the sidewall of the metal through hole includes:

[0011] The first dielectric layer is self-aligned and etched for multiple times, and the thickness of the first dielectric layer is measured until an opening is formed between the first dielectric layer and the side wall of the metal through hole, and the first sacrificial layer is exposed in the opening.

[0012] In some embodiments, removing the first sacrificial layer on the sidewall of the metal via comprises:

[0013] A reaction gas is introduced into the opening through a plasma process, and the first sacrificial layer is removed through the reaction between the reaction gas and the first sacrificial layer.

[0014] In some embodiments, a first sacrificial layer is formed on the first metal layer structure, and the first sacrificial layer is etched to form a plurality of step-shaped first trenches arranged at intervals, including:

[0015] forming a first sacrificial layer and a first mask layer on the first metal layer structure at one time, and etching the first mask layer toward the substrate to form a third trench;

[0016] A second mask layer is formed on the third trench and the first sacrificial layer, and the second mask layer and the first sacrificial layer are etched at once toward the substrate to form a first trench.

[0017] In some embodiments, forming a metal via and a second metal conductive line in the first trench includes:

[0018] A first metal barrier layer is formed on the sidewall and bottom of the first trench, and a metal through hole and a second metal wire are sequentially formed on the first metal barrier layer.

[0019] In some embodiments, a first metal layer structure is provided, comprising:

[0020] providing a substrate;

[0021] Forming a first metal layer on the substrate, the first metal layer comprising a plurality of first metal wires spaced apart;

[0022] forming a first sidewall sacrificial layer on the sidewall of each first metal wire so that there is a gap between the first sidewall sacrificial layers formed on the sidewalls of adjacent first metal wires;

[0023] A second dielectric layer is formed in each gap; the first sidewall sacrificial layer is removed, and a second air gap is formed between the second dielectric layer and the first metal wire; wherein the second dielectric layer and the first metal wire are alternately arranged.

[0024] In some embodiments, forming a first metal layer on a substrate includes:

[0025] A first barrier layer, a second sacrificial layer and a third mask layer are sequentially formed on the substrate, and the third mask layer, the second sacrificial layer and the first barrier layer are sequentially etched toward the substrate and the first barrier layer is etched through to form a fourth trench;

[0026] forming a first metal layer in the fourth trench;

[0027] The second sacrificial layer is removed to expose each first metal wire in the first metal layer.

[0028] In some embodiments, before forming the first metal layer in the fourth trench, the method further includes:

[0029] A second metal barrier layer is formed on the sidewalls and the bottom of the fourth trench.

[0030] In some embodiments, forming a first sidewall sacrificial layer on the sidewall of each first metal wire includes:

[0031] Depositing a first covering layer on the first metal layer to cover the first metal wire and the substrate;

[0032] The first covering layer is removed by etching in a horizontal direction to obtain a first sidewall sacrificial layer.

[0033] In a second aspect, the present disclosure further provides a semiconductor structure, which is prepared using the method for preparing a semiconductor structure provided in the first aspect above.

[0034] The semiconductor structure preparation method and semiconductor structure of the above scheme, when preparing the semiconductor structure, a first sacrificial layer is formed on the provided first metal layer structure, a plurality of step-type first grooves arranged at intervals are formed by etching the first sacrificial layer, and a metal through hole and a second metal wire are formed in the first groove. Wherein, the metal through hole is located between the first metal layer and the second metal wire in the first metal layer structure, and the width of the metal through hole is smaller than the second metal wire. Then, the first sacrificial layer between adjacent second metal wires is removed to form a second groove, and a dielectric layer material is filled in the second groove to form a first dielectric layer. After etching the first dielectric layer to expose the first sacrificial layer of the side wall of the metal through hole, the first sacrificial layer of the side wall of the metal through hole is removed to form a first air gap between the first dielectric layer and the metal through hole, and finally the dielectric layer material is continued to be filled in the second groove to make the top surface of the first dielectric layer flush with the top surface of the second metal wire. The present application gradually etches the first dielectric layer so that the first sacrificial layer of the side wall of the metal through hole is exposed after etching, and the first air gap is formed between the first dielectric layer and the metal through hole by removing the first sacrificial layer. Compared with the conventional method of forming a first dielectric layer entirely between adjacent metal through holes, the present invention sets an air gap in the first dielectric layer. Since the dielectric constant of air is much lower than other low dielectric constant materials, the capacitance between metal interconnect structures can be reduced, the RC delay between metal interconnect structures can be improved, and the semiconductor performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0037] Figures 2 to 11 It is a schematic diagram of a method for manufacturing a first metal layer structure having a second air gap in a semiconductor structure according to an embodiment of the present disclosure;

[0038] Figures 12 to 21 It is a schematic diagram of a method for manufacturing a second metal layer and a via layer having a first air gap in a semiconductor structure according to an embodiment of the present disclosure;

[0039] Fig. 22 Schematic diagram of a process for preparing a first metal layer structure in an embodiment of the present disclosure.

[0040] Description of reference numerals:

[0041] 100, substrate; 110, first metal wire; 120, second metal barrier layer; 130, first cap layer; 132, first sidewall sacrificial layer; 140, gap; 150, second dielectric layer; 160, second air gap; 210, first barrier layer; 220, second sacrificial layer; 230, third mask layer; 231, third metal hard mask; 232, third dielectric hard mask; 240, second oxide layer; 250, second anti-reflective layer; 260, third photoresist layer; 270, fourth trench; 310, first sacrificial layer; 320, gold 30, a metal through hole; 330, a second metal wire; 340, a first metal barrier layer; 350, a first dielectric layer; 360, a first air gap; 410, a second barrier layer; 420, a first mask layer; 421, a first metal hard mask; 422, a first dielectric hard mask; 430, a first oxide layer; 440, a first anti-reflective layer; 450, a first photoresist layer; 460, a third trench; 470, a second mask layer; 471, a blocking layer; 472, a blocking mask layer; 480, a second photoresist layer; 490, a first trench; 500, a second trench. DETAILED DESCRIPTION

[0042] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0044] It should be understood that when an element or layer is referred to as being "on, "adjacent to, "connected to, or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on, "directly adjacent to, "directly connected to, or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various regions, layers, and / or portions, these regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one region, layer, or portion from another region, layer, or portion. Therefore, without departing from the teachings of the present invention, the first region, layer, or portion discussed below may be represented as the second region, layer, or portion.

[0045] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0046] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of idealized embodiments (and intermediate structures) of the invention, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0048] As mentioned in the background technology, in metal interconnect structures, due to the continuous reduction in size, the parasitic capacitance of the dielectric layer currently formed by low dielectric constant materials increases, affecting the semiconductor performance. Based on this, the present disclosure provides a method for preparing a semiconductor structure, and an air gap is set in the dielectric layer. Since the dielectric constant of air is much lower than that of other low dielectric constant materials, the capacitance between metal interconnect structures can be reduced, the RC delay between metal interconnect structures can be improved, and the semiconductor performance can be improved.

[0049] In the present application, the metal interconnect structure includes a first metal layer structure and a second metal layer structure, and a metal via layer disposed between the first metal layer structure and the second metal layer structure. In order to improve the RC delay between the metal interconnect structures and improve the semiconductor performance, in one embodiment, Figure 1 As shown, a method for preparing a semiconductor structure is provided, comprising steps S100 to S400.

[0050] S100, providing a first metal layer structure, forming a first sacrificial layer on the first metal layer structure, etching the first sacrificial layer to form a plurality of step-shaped first grooves arranged at intervals; forming a metal through hole and a second metal wire in the first groove, wherein the metal through hole is located between the first metal layer and the second metal wire in the first metal layer structure, and the width of the metal through hole is smaller than the second metal wire;

[0051] S200, removing the first sacrificial layer between adjacent second metal wires to form a second trench, and filling the second trench with a dielectric layer material to form a first dielectric layer;

[0052] S300, etching the first dielectric layer until a portion of the first sacrificial layer on the side wall of the metal through hole is exposed, removing the first sacrificial layer on the side wall of the metal through hole, and forming a first air gap between the first dielectric layer and the metal through hole;

[0053] S400 , continue to fill the second trench with dielectric layer material, so that the top surface of the first dielectric layer is flush with the top surface of the second metal wire.

[0054] The second metal wire 330 is a second layer of metal interconnection wires in the metal interconnection structure. The second metal wire 330 is used to connect different functional units to achieve logic operations and data processing. A plurality of second metal wires 330 arranged at intervals form a second metal layer. The second metal wire 330 is formed of metal, such as aluminum, tungsten, ruthenium, or copper.

[0055] Please refer to Figure 12-Figure 21 When preparing the semiconductor structure of this embodiment, the first metal layer structure in the metal interconnect structure is first formed, and then the first sacrificial layer 310 is deposited on the formed first metal layer structure, and the first step-type first grooves 490 arranged at intervals are etched at one time on the first sacrificial layer 310. A metal through hole 320 and a second metal wire 330 are formed in each first groove 490. The metal through hole 320 is located between the first metal layer and the second metal layer in the first metal layer structure, and is used to connect the first metal layer and the second metal layer. The width of the metal through hole 320 is less than the width of the second metal wire 330. Optionally, the first sacrificial layer 310 can be aC amorphous carbon.

[0056] Since a plurality of first grooves 490 are arranged at intervals on the first sacrificial layer 310, and each first groove 490 is provided with a metal through hole 320 and a second metal conductive line 330, it can be understood that a plurality of second metal conductive lines 330 arranged at intervals form a second metal layer structure, and a plurality of metal through holes 320 arranged at intervals form a connecting metal through hole layer, which is used to connect the first metal layer structure and the second metal layer.

[0057] Please continue to refer to Figures 16 to 21 After the metal via layer and the second metal layer are formed, the first sacrificial layer 310 between adjacent second metal wires 330 is removed by etching in this embodiment. Fig.17 Specifically, when etching the first sacrificial layer 310 between adjacent second metal wires 330, the first sacrificial layer 310 is etched along the sidewall of the second metal wire 330 toward the substrate 100 to form the second groove 500. Since the width of the metal through hole 320 is smaller than the second metal wire 330, the distance between adjacent second metal wires 330 is smaller than the distance between adjacent metal through holes 320. Therefore, please continue to refer to Fig.17, the first sacrificial layer 310 is etched along the sidewall of the second metal conductive line 330 , and the first sacrificial layer 310 on the sidewall of the metal via 320 is retained. Here, the first sacrificial layer 310 retained on the sidewall of the metal via 320 is used to form the first air gap 360 .

[0058] like Fig.18 As shown, a dielectric layer material is filled in the second trench 500 to form a first dielectric layer 350. A higher etching selectivity ratio may be selected for etching the first sacrificial layer 310 to ensure that other structures are not damaged.

[0059] The first dielectric layer 350 can be formed by depositing a dielectric layer material in the second groove 500. The deposited dielectric layer material may include but is not limited to silicon dioxide, silicon nitride or silicon oxynitride. In order to reduce the capacitance of the metal interconnect structure, the first dielectric layer 350 may also use low dielectric constant (referred to as low-K) and ultra-low dielectric constant (referred to as ultralow-K) materials to replace traditional insulating media such as silicon dioxide. In this embodiment, the material of the first dielectric layer 350 is preferably a low-K material SICOH. After the first dielectric layer 350 is formed, a vapor deposition reaction may be used to form a thin film on the surface of the first dielectric layer 350 to fill the depression and achieve smoothing, providing a good foundation for subsequent processes.

[0060] Please refer to Fig.18 As shown, the first dielectric layer 350 is formed by removing the first sacrificial layer 310 between adjacent second metal wires 330. Since the width of the second metal wire 330 is greater than the metal through hole 320, the first sacrificial layer 310 still exists on the side wall of the metal through hole 320. In this embodiment, the first sacrificial layer 310 on the side wall of the metal through hole 320 is further used to form the first air gap 360.

[0061] The first dielectric layer 350 is etched to expose a portion of the first sacrificial layer 310 on the sidewall of the metal through hole 320, and then the first sacrificial layer 310 on the sidewall of the metal through hole 320 is removed based on the exposed opening. After the first sacrificial layer 310 on the sidewall of the metal through hole 320 is removed, a first air gap 360 is formed between the first dielectric layer 350 and the metal through hole. Then, the first dielectric layer 350 removed by etching is restored by depositing a filling dielectric layer material in the second trench 500 to form a first dielectric layer 350 flush with the top surface of the second metal wire 330. Optionally, chemical mechanical polishing (CMP) can be used to flatten the deposited surface of the deposited first dielectric layer 350.

[0062] It can be understood that when etching the first dielectric layer 350, the present embodiment has a very high requirement for etching accuracy. To ensure the etching accuracy of the first dielectric layer 350, the present embodiment etches the first dielectric layer 350 by dry etching. For example, thin film etching is performed by plasma, and the etching gas is used to form active radicals in the plasma under the acceleration of the electric field, and chemically reacts with the etched material, and the by-products are taken away with the gas flow. Since dry etching methods such as plasma etching can accurately control the etching thickness, when etching the first dielectric layer 350, the first sacrificial layer 310 can be controlled to be etched to expose part of the side wall of the metal through hole 320, and the first sacrificial layer 310 is removed through the opening that exposes the first sacrificial layer 310 to form the first air gap 360. Although the wet etching method can theoretically control the etching thickness by adjusting the etching time and the concentration of the etching liquid, the wet etching method has a low precision and is not suitable for etching the first dielectric layer 350 here. It should be noted that, after the first sacrificial layer 310 on the side wall of the metal through hole 320 is removed to form the first air gap 360, there is an opening on the first air gap 360. Therefore, when the filling dielectric layer material is continuously deposited on the first dielectric layer 350, a rapid sealing deposition process is adopted, and the process parameters of the deposition process are controlled so that the material growth rate at the opening of the first air gap 360 is faster than that at other positions.

[0063] This embodiment utilizes the width difference between the second metal wires 330 and the metal through-holes 320, first removes the first sacrificial layer 310 between the adjacent second metal wires 330 to form a first dielectric layer 350 with a low dielectric constant, then gradually etches the first dielectric layer 350 until the first sacrificial layer 310 on the sidewalls of the metal through-holes 320 is exposed, and forms a first air gap 360 between the first dielectric layer 350 and the metal through-holes 320 by removing the first sacrificial layer 310 on the sidewalls of the metal through-holes 320. Since the dielectric constant of air is much smaller than that of the first dielectric layer 350, the dielectric constant of the first dielectric layer 350 and the first air gap 360 as a whole is reduced, thereby reducing the capacitance between the metal wires and improving the performance of the semiconductor.

[0064] In some specific embodiments, in step S100, a first sacrificial layer is formed on the first metal layer structure, and the first sacrificial layer is etched to form a plurality of step-shaped first grooves arranged at intervals, including the following steps S110 to S120. Among them:

[0065] S110, forming a first sacrificial layer and a first mask layer on the first metal layer structure, and etching the first mask layer toward the substrate to form a third trench;

[0066] S120, forming a second mask layer on the third trench and the first sacrificial layer, and etching the second mask layer and the first sacrificial layer at once toward the substrate to form a first trench.

[0067] Please continue to refer to Fig.12 When etching the first sacrificial layer 310, a first mask layer 420 is first deposited on the first sacrificial layer 310, and the first mask layer 420 may include a stacked first metal hard mask 421 and a first dielectric hard mask 422. A first oxide layer 430 and a first anti-reflection layer 440 are then deposited on the first mask layer 420, a photoresist is coated on the first anti-reflection layer 440, and the photoresist is exposed and developed to obtain a patterned first photoresist layer 450, which is used to etch the second metal layer. Please continue to refer to Fig.12 and Fig.13 , the first mask layer 420 is etched using the first photoresist layer 450 as a mask, and the etching stops when the first sacrificial layer 310 is reached. Fig.13 A third trench 460 is shown formed.

[0068] The first metal hard mask 421 may include, for example, aluminum, titanium, gold or a corresponding alloy, and the first metal hard mask 421 has good conductivity and mechanical strength. The first dielectric hard mask 422 may include, for example, insulating materials such as silicon dioxide and silicon nitride, and is mainly used for insulation and isolation. The first oxide layer 430 is used to protect the first mask layer 420. Preferably, the first metal hard mask 421 of this embodiment is TiN, and the first dielectric hard mask 422 is SiON.

[0069] Please continue to refer to Fig.14 , deposit a second mask layer 470 on the third trench 460 and the first sacrificial layer 310, the second mask layer 470 may include a stacked shielding layer 471 and a shielding mask layer 472, coat a photoresist on the shielding mask layer 472, and expose and develop the photoresist to obtain a patterned second photoresist layer 480, the second photoresist layer 480 is used to implement the etching of the metal via layer. The material of the shielding layer 471 may be ODL (Organic Dielectric layer). The material of the shielding mask layer 472 may be SHB (Si-O-Based hardmask).

[0070] Please continue to refer to Fig.15 In this embodiment, the second metal layer and the metal through hole layer are formed by one-time etching. That is, under the action of the first mask layer 420 and the second mask layer 470, the grooves for forming the metal through holes 320 of the metal through hole layer are first etched in the first sacrificial layer 310, and then the grooves for forming the second metal wires 330 of the second metal layer are etched back, and finally the step-shaped first grooves 490 are formed.

[0071] Please continue to refer to Fig.16, metal is filled in the first trench 490, and a metal through-hole layer and a second metal layer are formed at the same time. The filled metal may be aluminum, tungsten, ruthenium, or copper, etc. Filling the metal in the first trench 490 may be achieved by an electrochemical deposition process. After the metal is deposited, chemical mechanical polishing (CMP) may be used to flatten the deposited metal surface.

[0072] like Fig.16 As shown, the metal through hole layer includes a plurality of metal through holes 320 arranged at intervals, and the second metal layer includes a plurality of second metal wires 330 arranged at intervals. The metal through hole layer is arranged between the first metal layer and the second metal layer, and the width of each metal through hole 320 is smaller than the corresponding first metal wire 110 and the second metal wire 330. The second metal layer and the first metal layer are both used for interconnection of local signals.

[0073] In some further embodiments, a metal via and a second metal conductive line are formed in the first trench 490 in step S100, including: forming a first metal barrier layer 340 on the sidewall and bottom of the first trench 490, and sequentially forming a metal via 320 and a second metal conductive line 330 on the first metal barrier layer 340.

[0074] A first metal barrier layer 340 is formed on the sidewall and bottom of the first trench 490 to prevent metal diffusion between the metal in the metal via layer and the second metal layer and the first dielectric layer 350. Optionally, the first metal barrier layer 340 may be titanium, titanium alloy, tantalum, tantalum alloy, aluminum, aluminum alloy, silicon, or other materials that can prevent diffusion of the metal via 320 and the second metal wire 330. Preferably, the first metal barrier layer 340 is tantalum Ta or tantalum alloy TaN.

[0075] The specific method of etching the first dielectric layer 350 to form the first air gap 360 is described in detail below. In some embodiments, etching the first dielectric layer 350 to expose a portion of the first sacrificial layer 310 on the sidewall of the metal through hole 320 in step S300 includes: performing multiple self-aligned etching on the first dielectric layer 350, and measuring the thickness of the first dielectric layer 350 until an opening is formed between the first dielectric layer 350 and the sidewall of the metal through hole 320, and the first sacrificial layer 310 is exposed in the opening.

[0076] As shown in the above embodiment, the first dielectric layer 350 is etched by dry etching in this embodiment to ensure the etching accuracy of the first dielectric layer 350. Figure 18 to Figure 19 , the first dielectric layer 350 is etched by a self-aligned etching process, and when a gap is formed between the first dielectric layer 350 and the sidewall of the metal through hole 320, as shown in FIG. Fig.19 The opening is as shown, and the opening ends at exposing a portion of the first sacrificial layer 310 on the side wall of the metal through hole 320 .

[0077] Dry etching can achieve control of etching by controlling parameters such as etching time, gas flow and pressure, gas type and ratio, plasma density or energy. Exemplarily, this embodiment can ensure that the first dielectric layer 350 is removed uniformly and accurately by accurately controlling the time of dry etching operation. The thickness of etching is strictly controlled by using a quality control (QC) measurement station. Etching process parameters such as etching rate are determined based on QC data, and then the etching time corresponding to a certain thickness of etching is calculated based on the determined etching process parameters, so as to obtain accurate etching results by accurately controlling the etching time.

[0078] In some embodiments, removing the first sacrificial layer 310 on the sidewall of the metal through hole in step S300 includes: introducing a reaction gas into the opening by a plasma process, and removing the first sacrificial layer 310 by reaction between the reaction gas and the first sacrificial layer 310 .

[0079] After etching the first dielectric layer 350 to a certain thickness, a portion of the first sacrificial layer 310 on the side wall of the metal through hole 320 is exposed. Fig. 20 , a reaction gas is introduced into the opening through a plasma process to remove the first sacrificial layer 310 on the side wall of the metal through hole 320. For example, in the case where the first sacrificial layer 310 is aC amorphous carbon, the reaction gas is ozone, and volatile byproducts such as carbon dioxide are formed through the oxidation reaction of ozone on the amorphous carbon. Optionally, the removal efficiency can be optimized by adjusting the plasma power, gas flow rate and processing time to ensure that the amorphous carbon is completely removed without damaging the underlying material. The method of this embodiment can selectively remove amorphous carbon without damaging other materials, and the high energy state of the plasma can accelerate the reaction rate and improve the cleaning efficiency.

[0080] The preparation method of the first metal layer structure is described in detail below. Fig. 22 As shown, in some other embodiments, the method for preparing the first metal layer structure includes the following steps S500 to S800. Wherein:

[0081] S500, providing a substrate;

[0082] S600, forming a first metal layer on a substrate, wherein the first metal layer includes a plurality of first metal wires arranged at intervals;

[0083] S700, forming a first sidewall sacrificial layer on the sidewall of each first metal wire, so that there is a gap between the first sidewall sacrificial layers formed on the sidewalls of adjacent first metal wires;

[0084] S800, forming a second dielectric layer in each gap; removing the first sidewall sacrificial layer, and forming a second air gap between the second dielectric layer and the first metal wire; wherein the second dielectric layer and the first metal wire are alternately arranged.

[0085] Please refer to Figures 7 to 11 The material of the substrate 100 can be any suitable substrate material known in the art. The first metal layer is the first layer of metal interconnection wires, which are used to connect different functional units to achieve logical operations and data processing. Generally speaking, the first metal layer is used for interconnection of local signals, and the connections are dense and small. The first metal layer includes a plurality of first metal wires 110 arranged at intervals. The first metal wires 110 are the same as the second metal wires 330 and are formed of metals such as aluminum, tungsten, ruthenium, or copper.

[0086] Please refer to Fig. 9 In order to improve semiconductor performance, in this embodiment, a first sidewall sacrificial layer 132 is formed on the sidewall of the first metal wire 110 , so that a gap 140 exists between the first sidewall sacrificial layers 132 formed on the sidewalls of adjacent first metal wires 110 .

[0087] Please refer to Fig.10 , a second dielectric layer 150 is formed in the gap 140 by a deposition process. The material of the second dielectric layer 150 may include but is not limited to silicon dioxide, silicon nitride or silicon oxynitride. In order to reduce the capacitance of the metal interconnect structure, the second dielectric layer 150 may also use low dielectric constant and ultra-low dielectric constant materials to replace traditional insulating media such as silicon dioxide. In this embodiment, the material of the second dielectric layer 150 is preferably a low-K material SICOH.

[0088] Please continue to refer to Fig.10 and Fig.11 After forming the second dielectric layer 150 in the gap 140, the first sidewall sacrificial layer 132 is removed, so that a second air gap 160 is formed between the second dielectric layer 150 and the first metal wire 110. Fig.10 As shown, in the first metal layer and the second dielectric layer 150 corresponding to the first metal layer, the second dielectric layers 150 and the first metal wires 110 are alternately arranged, and second air gaps 160 exist between adjacent second dielectric layers 150 and first metal wires 110 .

[0089] In this embodiment, an air gap is set in the dielectric layer of the metal interconnect structure. Since the dielectric constant of air is approximately 1, that is, the dielectric constant of air is smaller than the dielectric constant of the second dielectric layer 150 formed by the low dielectric constant material, the overall dielectric constant between the metal interconnect structures is reduced, the capacitance between the metal wires is reduced, the RC delay between the metal interconnect structures is improved, and the performance of the semiconductor is improved.

[0090] In this embodiment, a first sidewall sacrificial layer 132 is first formed on the sidewall of the first metal wire 110, and then a second dielectric layer 150 is formed between the first sidewall sacrificial layer 132 and the first metal wire 110. Then, the first sidewall sacrificial layer 132 is removed to form a second air gap 160 between the second dielectric layer 150 and the first metal wire 110. The air gap can be formed without a photomask, thereby improving semiconductor performance while saving process costs.

[0091] In some specific embodiments, the above step S600: forming a first metal layer on the substrate includes the following steps S610-S630. Among them:

[0092] S610, forming a first barrier layer, a second sacrificial layer, and a third mask layer on the substrate in sequence, and etching the third mask layer, the second sacrificial layer, and the first barrier layer in sequence toward the substrate and etching through the first barrier layer to form a fourth trench;

[0093] S620, forming a first metal layer in the fourth trench;

[0094] S630, removing the second sacrificial layer to expose each first metal wire in the first metal layer.

[0095] Please refer to Figures 2 to 7 , this embodiment provides a substrate 100, a second sacrificial layer 220 is formed on the substrate 100, and a fourth groove 270 is formed in the second sacrificial layer 220 by etching. A first barrier layer 210 is also formed between the substrate 100 and the second sacrificial layer 220. The first barrier layer 210, for example, nitrogen-doped silicon carbide SiCN (Nitrogen doped Silicon Carbide, NDC), is used to prevent the metal in the first metal layer from diffusing. At the same time, the first barrier layer 210 also helps in the subsequent process of forming the groove by etching process, so that the corresponding etching process can be stopped in time and accurately without damaging other structures. The second sacrificial layer 220 is, for example, aC amorphous carbon.

[0096] Please continue to refer to Figure 2, when etching the second sacrificial layer 220, a third mask layer 230 is sequentially formed on the second sacrificial layer 220. The third mask layer 230 may include a stacked third metal hard mask 231 and a third dielectric hard mask 232. Then, a second oxide layer 240 and a second anti-reflection layer 250 are sequentially stacked on the third mask layer 230, and a photoresist is formed on the second anti-reflection layer 250, and a patterned third photoresist layer 260 is obtained by exposing and developing the photoresist. Among them, the third metal hard mask 231 may include, for example, aluminum, titanium, gold or a corresponding alloy, and has good electrical conductivity and mechanical strength. The third dielectric hard mask 232 may include, for example, insulating materials such as silicon dioxide and silicon nitride for insulation and isolation. The second oxide layer 240 is used to protect the third mask layer 230. Preferably, the third metal hard mask 231 of this embodiment is TiN, and the third dielectric hard mask 232 is SiON.

[0097] Please continue to refer to Figure 3 and Figure 4 ,like Figure 3 As shown, the third mask layer 230 is first etched using the third photoresist layer 260 as a mask, and the etching stops when the second sacrificial layer 220 is reached. Figure 4 As shown, the second sacrificial layer 220 is continuously etched using the third mask layer 230 as a mask, the first barrier layer 210 is etched through and then stopped, thereby forming a fourth trench 270 .

[0098] Please continue to refer to Figure 5 and Figure 6 , a metal is filled in the fourth trench 270 to form a first metal layer, and the filled metal may be aluminum, tungsten, ruthenium, or copper. Filling the fourth trench 270 with metal may be achieved by an electrochemical deposition process, that is, using an electric current to achieve deposition of metal ions. After the deposition is completed, chemical mechanical polishing (CMP) may be used to smooth the deposited metal surface.

[0099] Optionally, before forming the first metal layer in the fourth trench 270, a second metal barrier layer 120 is first formed on the sidewall and bottom of the fourth trench 270 to prevent metal diffusion between the metal in the first metal layer and the dielectric layer. Optionally, the second metal barrier layer 120 may be titanium, titanium alloy, tantalum, tantalum alloy, aluminum, aluminum alloy, silicon, or other materials that can prevent the diffusion of the first metal wire 110. Preferably, the second metal barrier layer 120 is tantalum Ta or tantalum alloy TaN.

[0100] Please continue to refer to Figure 7After forming the first metal layer, the second sacrificial layer 220 is removed, so that each first metal wire 110 in the first metal layer is exposed. Taking the second sacrificial layer 220 as aC amorphous carbon as an example, the second sacrificial layer 220 can also be removed by passing ozone through a plasma process, or can be removed by a specific chemical solvent. This embodiment has no limitation on the removal method of the second sacrificial layer 220, and the second sacrificial layer 220 can be removed without affecting other structures.

[0101] In some embodiments, the step S700 forms a first sidewall sacrificial layer on the sidewall of each first metal wire so that there is a gap between the first sidewall sacrificial layers formed on the sidewalls of adjacent first metal wires, including the following steps S710-S720. Among them:

[0102] S710, depositing a first covering layer on the first metal layer to cover the first metal wire and the substrate;

[0103] S720, etching to remove the first covering layer in the horizontal direction to obtain a first sidewall sacrificial layer.

[0104] Please refer to Figure 8 and Fig. 9 , first deposit a first covering layer 130 of a certain thickness on the first metal layer. Figure 8 As shown, the first covering layer 130 covers the first metal wire 110 and the substrate 100. The first covering layer 130 is etched to remove the first covering layer 130 in the horizontal direction to obtain a first sidewall sacrificial layer 132. Figure 8 As shown, since the thickness of the first covering layer 130 formed on the first metal layer in the horizontal direction is small, the first covering layer 130 can be etched using a non-blocking dry etching process to remove the first covering layer 130 in the horizontal direction, and make the upper surface of the first covering layer 130 retained on the sidewall of the first metal wire 110 flush with the upper surface of the first metal wire 110. Optionally, the first covering layer 130 can be amorphous carbon or other thin film structures.

[0105] The barrier-free dry etching process refers to a process that directly performs etching without a mask. The barrier-free process can reduce the thickness of the first covering layer 130 at the same removal rate, and the etching is stopped when the first covering layer 130 covering the first metal wire 110 is removed until the first metal wire 110 is exposed.

[0106] In some other embodiments, before forming the first sacrificial layer 310 on the first metal layer structure, the method further includes: forming a second barrier layer 410 on the first metal layer structure. Here, forming the first sacrificial layer 310 on the first metal layer structure includes forming the first sacrificial layer 310 on the second barrier layer 410.

[0107] Please continue to refer to Fig.12 When forming the first sacrificial layer 310 on the provided first metal layer structure, the second barrier layer 410 is first deposited on the first metal layer structure, and then the first sacrificial layer 310 is deposited on the second barrier layer 410. The second barrier layer 410 may also be NDC, which is used to prevent the metal in the metal via layer from diffusing, and the subsequent etching process can be stopped in time and accurately without damaging other structures.

[0108] Since there is a second air gap 160 between the second dielectric layer 150 and the first metal wire 110, the second barrier layer 410 still adopts a fast-sealing thin film deposition process, and by controlling the process parameters of the thin film deposition process, the material growth rate at the opening of the second air gap 160 is faster than the growth rate at other positions, so that the second air gap 160 is quickly closed to obtain the second barrier layer 410. It can be understood that the process parameters of the thin film deposition process here include but are not limited to one of temperature, gas flow, gas pressure or gas composition.

[0109] In some embodiments, a semiconductor structure is provided, which may be a metal interconnect structure. When the semiconductor structure is a metal interconnect structure including two metal layers, such as Fig.21 As shown, it includes a first metal layer and a second metal layer, and a metal through hole layer arranged between the first metal layer and the second metal layer. The first metal layer includes a plurality of first metal wires 110 arranged at intervals, the second metal layer includes a plurality of second metal wires 330 arranged at intervals, and the metal through hole layer includes a plurality of metal through holes 320 arranged at intervals.

[0110] Please refer to Fig.21 , a second dielectric layer 150 is formed between adjacent first metal wires 110, and a second air gap 160 exists between the first metal wires 110 of the first metal layer and the second dielectric layer 150. A first dielectric layer 350 is formed between adjacent second metal wires 330, and since the width of the metal via 320 is smaller than the second metal wire 330, a first air gap 360 exists between the metal via 320 and the first dielectric layer 350. The semiconductor structure shown in this embodiment is obtained by the method for preparing the semiconductor structure provided in the above embodiment, which will not be described in detail here.

[0111] The present invention sets an air gap in the dielectric layer of the metal interconnect structure. Since the dielectric constant of air is much lower than other low dielectric constant materials, the capacitance between the metal interconnect structures is reduced, the RC delay between the metal interconnect structures is improved, and the semiconductor performance is improved. Since the present invention does not require a mask to form the air gap, the process cost is saved while improving the semiconductor performance.

[0112] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0113] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: Providing a first metal layer structure, forming a first sacrificial layer on the first metal layer structure, etching the first sacrificial layer to form a plurality of step-shaped first grooves arranged at intervals; forming a metal through hole and a second metal wire in the first groove, wherein the metal through hole is located between the first metal layer and the second metal wire in the first metal layer structure, and the width of the metal through hole is smaller than that of the second metal wire; Removing the first sacrificial layer between adjacent second metal wires by etching to form a second groove, and filling the second groove with a dielectric layer material to form a first dielectric layer, wherein when etching the first sacrificial layer between adjacent second metal wires, the first sacrificial layer is etched along the sidewall of the second metal wire toward the substrate; Performing multiple self-aligned etchings on the first dielectric layer, and measuring the thickness of the first dielectric layer, until an opening is formed between the first dielectric layer and the side wall of the metal through hole, the first sacrificial layer is exposed in the opening, and removing the first sacrificial layer on the side wall of the metal through hole, so that a first air gap is formed between the first dielectric layer and the metal through hole; The dielectric layer material continues to be filled in the second trench, so that the top surface of the first dielectric layer is flush with the top surface of the second metal wire.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Removing the first sacrificial layer from the sidewall of the metal through hole includes: A reaction gas is introduced into the opening through a plasma process, and the first sacrificial layer is removed through the reaction between the reaction gas and the first sacrificial layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of forming a first sacrificial layer on the first metal layer structure and etching the first sacrificial layer to form a plurality of step-shaped first grooves arranged at intervals comprises: forming the first sacrificial layer and the first mask layer on the first metal layer structure at the same time, and etching the first mask layer toward the substrate to form a third trench; A second mask layer is formed on the third trench and the first sacrificial layer, and the second mask layer and the first sacrificial layer are etched at once toward the substrate to form the first trench.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The forming of a metal via and a second metal conductive line in the first trench comprises: A first metal barrier layer is formed on the sidewall and the bottom of the first trench, and the metal through hole and the second metal conductive line are sequentially formed on the first metal barrier layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The providing of a first metal layer structure comprises: providing a substrate; forming the first metal layer on the substrate, wherein the first metal layer comprises a plurality of first metal wires spaced apart from each other; forming a first sidewall sacrificial layer on the sidewall of each of the first metal wires, so that there is a gap between the first sidewall sacrificial layers formed on the sidewalls of adjacent first metal wires; A second dielectric layer is formed in each of the gaps; the first sidewall sacrificial layer is removed, and a second air gap is formed between the second dielectric layer and the first metal wire; wherein the second dielectric layer and the first metal wire are alternately arranged.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The step of forming a first metal layer on the substrate comprises: forming a first barrier layer, a second sacrificial layer and a third mask layer in sequence on the substrate, and etching the third mask layer, the second sacrificial layer and the first barrier layer in sequence towards the substrate and etching through the first barrier layer to form a fourth trench; forming the first metal layer in the fourth trench; The second sacrificial layer is removed to expose each of the first metal wires in the first metal layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: Before forming the first metal layer in the fourth trench, the method further includes: A second metal barrier layer is formed on the sidewalls and the bottom of the fourth trench.

8. The method for preparing a semiconductor structure according to claim 5, characterized in that: The forming of a first sidewall sacrificial layer on the sidewall of each of the first metal wires comprises: Depositing a first covering layer on the first metal layer to cover the first metal wire and the substrate; Etching is performed to remove the first covering layer in a horizontal direction to obtain the first sidewall sacrificial layer.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first sacrificial layer is aC amorphous carbon.

10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 9.

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