Design method of power divider with low phase noise

Abstract

The invention relates to a design method of a power divider with low phase noise. Signals of the power divider are clock signals and synchronization signals of the millimeter wave cascade board. Comprising a signal input end via hole, an impedance matching control wire, a port isolation part and a ground wire protection isolation part. The sizes of stacked apertures of signal input end ground holes are different, the impedance matching control input end and the impedance matching control output end are 50 ohms, signal reflection is prevented, and insertion loss is reduced. The port isolation and the ground wire protection isolation reduce the coupling between the ports and the influence of an external circuit on a power divider signal. The phase noise can be controlled within-153dBc / Hz at 1MHz, and the phase noise can be controlled within-152dBc / Hz at 100KHz. And when the frequency is 10KHz and 1KHz, the frequency can be controlled within-143dBc / Hz. And the jitter can be controlled within 1.75 ps rms.

Description

Technical Field

[0001] The present invention designs a power divider for reducing phase noise and signal jitter. Background Art

[0002] At present, PCB design is widely used in the fields of communication, computer, graphics and image processing. All high-tech value-added electronic and product designs are pursuing low power consumption, low electromagnetic radiation, high reliability, miniaturization, lightweight and other characteristics. In order to achieve the above goals, via design is an important factor in PCB design. A via is mainly composed of three parts: one is the hole; the second is the pad area around the hole; and the third is the POWER layer isolation area. The process of vias is to plate a layer of metal on the cylindrical surface of the via wall by chemical deposition to connect the copper foils that need to be connected in the middle layers, and the upper and lower sides of the via are made into ordinary pad shapes, which can be directly connected to the upper and lower lines, or not. Vias can play the role of electrical connection, fixing or positioning devices.

[0003] Broadband, multi-channel power splitters are widely used in microwave and millimeter wave systems. Currently, one-to-eight power splitters are mostly used in microstrip or stripline circuits. The topology is a three-level (7 identical) one-to-two power splitter connected by a 50Ω transmission line. This structure of power splitter has a narrow working bandwidth and requires the use of multi-section impedance transformers for cascading to increase the bandwidth. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a power divider that reduces phase noise and signal jitter. The power divider includes four parts: a signal input via, an impedance matching control routing, port isolation, and ground wire protection isolation. The stacked aperture sizes of the ground holes at the signal input end are designed differently, and the impedance matching control input and output ends are both 50 ohms to prevent signal reflection and reduce insertion loss. Port isolation and ground wire protection isolation reduce the coupling between ports and the influence of external circuits on the power divider signal. The influence of phase noise can be controlled. While setting the signal via, a return ground hole is added near the signal hole to reduce interference with the signal. Signal quality is guaranteed. Finally, the power divider is surrounded by protection using ground holes and ground wires. S11 can reach -15.30dB, and the insertion loss is about -12dB. The power divider operates in the 19GHz to 20GHz frequency band. The circuit design isolation is controlled below -20dB, the phase noise can be controlled within -153dBc / Hz at 1MHz, within -152dBc / Hz at 100KHz, and within -143dBc / Hz at 10KHz and 1KHz. The time jitter can be controlled within 1.75ps rms.

[0005] The technical solution adopted by the present invention to solve the above technical problems is: the circuit is designed to be equivalent to a multi-section converter with an impedance ratio of 8:1, the first stage 8 channels are merged into 2 channels, the second stage 8 channels are merged into 4 channels, and the third stage is still 8 channels. The connecting line between the two-stage power dividers is also used as one of the impedance transformation sections of the cascaded power divider and is also designed to be merged accordingly. In this way, the cascaded three-stage single-section power divider becomes a one-to-eight power divider with five impedance transformation sections.

[0006] During the design simulation, all branch line circuits and connecting circuits use microstrip line circuits, and the output 50 ohm circuit uses microstrip line circuits; when used in high-frequency PCBs, all branch line circuits and connecting circuits can use coplanar waveguide (CPW) circuits, and the output 50 ohm circuit uses grounded coplanar waveguide (CPW) circuits. The circuit design can reduce the loss by about 10%; the isolation is improved by about 2dB based on the 20dB of the traditional power divider; at the same time, the phase noise of all frequency points during signal transmission can still be maintained within -153dBc / Hz.

[0007] The material of the dielectric substrate used in the power divider of the present invention is Rogers 4350B, the thickness of the dielectric material is h = 0.1016mm, and its dielectric constant ε r is 3.66, the tangent loss value is 0.0037, and the copper thickness used for the microstrip line is 0.035mm. By calculation, when the microstrip line width is w = 0.18mm, the characteristic impedance of the microstrip line in the above dielectric material is 50Ω, the minimum processable line width of the existing process is 0.1mm, and the corresponding characteristic impedance is 66.7Ω. The width of all impedance matching lines should be greater than or equal to 0.1mm.

[0008] In the present invention, the structure is changed and the cavity size is reduced. The output ports of the two one-to-two power dividers are designed to be far apart, and the distance between the port transmission lines is designed to be more than twice that of the feeder. In addition, the one-to-eight power divider has the property of low transmission loss. In this way, the loss amplitude difference of each transmission port can be controlled within a certain range and the isolation of each port can reach below -22dB. At the same time, there is no peak problem in isolation and transmission parameters.

[0009] The present invention uses a ground wire isolation solution. Because this design will be used in the transmission of 20GHz local oscillator signals in high-frequency PCBs, the ground wire surrounding the signal can effectively form a shielding layer to reduce the impact of external electromagnetic interference on the signal line. This interference may come from other electrical equipment, RF signals or power supply noise. In the case of 20GHz, the distance between the ground wire and the power divider structure should be controlled within a quarter of the waveguide wavelength λ g Above, according to Let c = 3 × 10 8m / s, f = 20GHz, we can get the air wavelength λ0 = 15mm, according to the waveguide wavelength Effective dielectric constant It can be calculated that the waveguide wavelength is 9.89mm, and the distance between the ground wire and the power divider should be controlled above 2.45mm. While using the ground wire to surround, add a row of ground holes. By surrounding the signal line in the ground layer, the noise coupling on the signal line can be reduced, thereby improving the integrity of data transmission. In terms of the selection of via size, 0.25mm / 0.51mm / 0.91mm (drilling / pad / POWER isolation area) vias are selected. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a structural diagram of a single one-to-two power divider of the present invention.

[0011] Figure 2 It is a structural diagram of the one-to-eight power divider of the present invention.

[0012] Figure 3 It is a structural diagram of the power divider plus ground wire protection of the present invention.

[0013] Figure 4a This is the S parameter isolation simulation result of the power divider of the present invention.

[0014] Figure 4b These are the S parameter insertion loss and isolation loss simulation results of the power divider of the present invention.

[0015] Figure 5 This is the simulation result of the phase noise in the power divider of the present invention.

[0016] Figure 6a This is the S parameter phase jitter simulation result of the power divider of the present invention.

[0017] Figure 6b This is the S parameter phase jitter simulation result of the power divider of the present invention.

[0018] Figure 6c This is the S parameter phase jitter simulation result of the power divider of the present invention.

[0019] Figure 6d This is the S parameter phase jitter simulation result of the power divider of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, content and advantages of the present invention more clear, the implementation mode of the present invention is further described in detail below in conjunction with the drawings and embodiments.

[0021] like Figure 1 and Figure 2 As shown, Figure 2 yes Figure 1A circuit design is equivalent to a multi-section converter with an impedance ratio of 8:1. The first stage 8 channels are merged into 2 channels, the second stage 8 channels are merged into 4 channels, and the third stage is still 8 channels. The connecting line between the two stages of the power divider is also designed as one of the impedance transformation sections of the cascaded power divider. In this way, the cascaded three-stage single-section power divider becomes a one-to-eight power divider with five impedance transformation sections.

[0022] In the above specific example, Figure 2 1 is the signal input port of the power divider, 2-9 are the signal output ports of the power divider. Figure 1 L2 is the cut corner at the T-type of the power divider, and its length is twice the square root of W2. By designing the cut corner, the signal transmission performance can be improved and the return loss can be reduced. The size and angle of the cut corner are optimized according to the selected Rogers material and the operating frequency to reduce the loss. At the same time, it can also ensure the impedance matching of the input and output ports to a certain extent to avoid reflection. During the processing, the appropriate size of the cut corner can also ensure the processing accuracy to avoid unnecessary radiation loss.

[0023] In the above specific example, Figure 1 The thickness of the medium green board Rogers 4350B is 0.1016mm, the copper thickness is 0.035mm, the length L1 of the input and output ports is not required, and it can be easily processed. The width is calculated by the microstrip line calculation tool to get W1 = 0.18mm, the width of the middle microstrip line W2 is 0.1mm, and the middle isolation resistor is 100 ohms. The return loss of the simulation result is -15.3dB. Under the ideal condition without any loss at each port, the insertion loss of the one-to-eight power divider is -9dB, and the insertion loss of each port of this design is about -12dB. The isolation is higher than that of the general traditional microstrip line power divider. The slightly worse port is -22.83dB, and the higher isolation can reach -30dB and -40dB.

[0024] The simulation of phase noise in the above specific example is -151.6dBc / Hz at 100kHz, -142.9dBc / Hz at 10kHz, and -152.5dBc / Hz at 1.0Mhz. The time jitter can be calculated by the formula 2πfΔt=phase angle difference. The phase angle difference of the S parameter is about 3°, and the time jitter calculated according to the formula is less than 1.75psrms.

Claims

1. A method for designing a power divider with low phase noise, characterized in that: The power divider consists of four parts: signal input via, impedance matching control routing, port isolation, and ground protection isolation; the impedance matching control input and output are both 50 ohms.

2. The design method according to claim 1, characterized in that: While setting the signal vias, add a return ground via near the signal vias, and use ground vias and ground wires around the power divider for surrounding protection.

3. The design method according to claim 1, characterized in that: The circuit is designed to contain a multi-section converter with an impedance ratio of 8:

1. The 8 channels in the first stage are merged into 2 channels, the 8 channels in the second stage are merged into 4 channels, and the third stage is still 8 channels. The connecting line between the two stages of the power divider also serves as one of the impedance transformation sections of the cascade power divider, that is, a one-to-eight power divider with five impedance transformation sections.

4. The design method according to claim 1, characterized in that: All branch line circuits and connecting circuits use microstrip line circuits, and the output 50 ohm circuit uses microstrip line circuits; when applied in PCB, all branch line circuits and connecting circuits use coplanar waveguide circuits, and the output 50 ohm circuit uses grounded coplanar waveguide circuits.

5. The design method according to claim 1, characterized in that: The dielectric substrate material used in the power divider is Rogers 4350B, the dielectric material thickness is h = 0.1016mm, and its dielectric constant is ε r It is 3.66, the tangent loss value is 0.0037, and the copper thickness used for the microstrip line is 0.035mm.

6. The design method according to claim 1, characterized in that: The distance between the ground wire and the power divider structure should be controlled within one quarter of the waveguide wavelength λ g As shown above, the waveguide wavelength is 9.89 mm, and the distance between the ground wire and the power divider should be controlled above 2.45 mm.

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