Power supply device and method of controlling the same
By dispersing the power supply to multiple power management chips and achieving synchronous control, the size and reliability problems caused by excessive channels are solved for a single chip, and the timing control accuracy of complex power supply systems is improved.
Patent Information
- Application Number
- CN202411724336.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-03-18
AI Technical Summary
In complex power supply systems, a single power management chip needs to deal with too many channels, resulting in too large chip size and difficult to optimize the layout, affecting reliability and economy, and cannot be applied to complex power supply systems.
The power supply is integrated on multiple power management chips, and the target voltage of each chip is detected through the detection module to generate a level signal; the synchronization signal is determined through the judgment circuit, and all chips are controlled to achieve synchronous power on or off.
This avoids the problem of too many integrated channels of a single power management chip, ensures the power-on safety of each chip, reduces the start-up timing difference between different chips, and improves the power timing control accuracy.
Smart Images
Figure CN119652070A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic technology, and in particular to a power supply device and a method for controlling the power supply device. Background Art
[0002] With the development of integrated circuits, the process integration of SOC (System on Chip) is getting higher and higher, and the demand for the number of power supplies is also increasing. In some complex power supply systems, dozens of independent power supply devices are usually required.
[0003] At present, the scheme for multi-power on / off timing control is usually aimed at the application scenario of a single power management chip controlling multiple parallel power supplies. If a single power management chip is used to control the timing of a complex power system, the number of channels required for the single power management chip is too large, which will cause the size of the power management chip to be too large, and the internal layout of the chip is difficult to optimize, which will affect the reliability and economy of the chip. Therefore, the control scheme of a single power management chip cannot be applied to complex power systems. Summary of the invention
[0004] The present invention provides a power supply device and a method for controlling the power supply device, which integrates power supplies on multiple power management chips respectively, avoiding excessive number of integrated channels of a single power management chip, and ensuring synchronous control between different power management chips.
[0005] In one aspect of the present invention, a power supply device is provided. The power supply device includes: a plurality of power management chips, each including: a detection module configured to compare a target voltage based on an input power supply voltage with a reference voltage to generate a level signal at a first output terminal; a control module configured to receive a synchronization signal at a control input terminal and generate a switch control signal based on the synchronization signal; at least one power supply module configured to output a supply voltage at at least one second output terminal respectively based on the switch control signal; and a judgment circuit configured to judge whether the level signals generated at each of the first output terminals all have a first value, and send the synchronization signal corresponding to the judgment result to each of the control input terminals.
[0006] In another aspect of the present invention, a method for controlling a power supply device is provided. The method includes: comparing a target voltage based on an input power supply voltage with a reference voltage in each power management chip to generate a level signal at a first output terminal; receiving a synchronization signal at a control input terminal in each power management chip, and generating a switch control signal based on the synchronization signal; outputting a supply voltage at at least one second output terminal in each power management chip based on the switch control signal; and judging whether the level signals generated at each of the first output terminals have a first value, and sending the synchronization signal corresponding to the judgment result to each of the control input terminals.
[0007] According to the technical solution of the present invention, a plurality of power management chips are provided to respectively control different power modules, so that different power modules are respectively integrated on different power management chips, thereby avoiding the problem of too many integrated channels of a single power management chip. The present invention detects whether the target voltage of each power management chip meets the power-on condition through a detection module to generate a corresponding level signal, thereby ensuring the power-on safety of each power management chip. Then, the judgment circuit determines the synchronization signal corresponding to each power management chip according to the level signal of the detection module, and finally generates a switch control signal according to the synchronization signal through the control module, so that all power management chips can be turned on or off synchronously, thereby reducing the startup timing differences between different power management chips, ensuring that all power management chips can be turned on and off synchronously, and avoiding the problem of poor power timing control accuracy due to differences in startup timing between different power management chips. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 is a block diagram of a power supply device according to an embodiment of the present invention;
[0009] Figure 2 is a circuit diagram of a power supply device according to an embodiment of the present invention;
[0010] Figure 3 FIG. 4 is a flow chart of a method for controlling a multi-power supply device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0011] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.
[0012] In the prior art, the scheme for the timing control of multi-power on / off is usually for the application scenario of a single power management chip controlling multiple parallel power supplies. For example, in a power supply system, the parallel power supply power-on indication signal of its parallel power supply power-on indication signal line is synthesized by the single power supply power-on indication signal of the power supply power-on indication signal processing unit in each of the power supply devices by line-and logic. When the power supply device meets the preset power-on condition, the start control signal processing unit of the power supply device receives a specified level signal to control the power supply device to start. In addition, in another power supply system, its physical wires are electrically coupled to each power supply device to form a synchronization signal line. The logic level of the synchronization signal line is the result of the logic level of the signal pin of the power supply device and the logic operation. When any power supply device is started, the control unit in the power supply device adjusts the start and close setting of the power output unit according to the logic level of the synchronization signal line.
[0013] If a single power management chip is used to control the timing of a complex power system, the number of channels required for the single power management chip is too large, which will cause the size of the power management chip to be too large, and the internal layout of the chip is difficult to optimize, which will affect the reliability and economy of the chip. Therefore, the control solution of a single power management chip cannot be applied to complex power systems.
[0014] In order to solve at least the above technical problems, the present disclosure provides a power supply device. According to the present disclosure, a plurality of power management chips are provided to control different power modules respectively, so that different power modules are integrated on different power management chips respectively. At the same time, the detection module detects whether the target voltage of each power management chip meets the power-on condition to generate a corresponding level signal, and then the judgment circuit determines the synchronization signal corresponding to each power management chip according to the level signal of the detection module, and finally the control module generates a switch control signal according to the synchronization signal, so that all power management chips can be turned on or off synchronously. In this way, according to the embodiment of the present disclosure, the problem of too many integrated channels of a single power management chip can be avoided, and the power-on safety of each power management chip can be guaranteed. In addition, the startup timing difference between different power management chips is reduced, ensuring that all power management chips can be turned on and off synchronously, and avoiding the problem of poor power timing control accuracy due to differences in startup timing between different power management chips.
[0015] According to the disclosed embodiment, a synchronization signal SYNC is short-circuited outside each power management chip to form a judgment circuit to achieve synchronous control of all power management chips. As long as the target voltage VCC_DIV (signal after VCC voltage division) of one power management chip is lower than the reference voltage REF, the detection module of the power management chip will pull down its internal transistor to output a low level, resulting in the synchronization signal SYNC of other power management chips connected to the same judgment circuit being low. At this time, the digital control logic inside the power management chip detects that the synchronization signal SYNC is low, and the power management chip will not start up. Only when the target voltage VCC_DIV (signal after VCC voltage division) of all power management chips in the same judgment circuit is higher than the reference voltage REF, that is, the input power supply voltage of all power management chips meets the power-on condition, the synchronization signal SYNC of the judgment circuit will be released and present a high level state. At the moment when the synchronization signal SYNC of the judgment circuit jumps from a low level to a high level, the digital control logic signal of each power management chip synchronously detects the rising edge jump, so all power management chips are turned on at the same time, so that the output voltages of different channels between different chips can be synchronized.
[0016] The same is true for shutdown. As long as one power management chip detects that the target voltage VCC_DIV (the signal after VCC voltage division) is lower than the reference voltage REF, the synchronization signal SYNC of the judgment circuit will be pulled low, and all power management chips will detect the falling edge at the same time to control them to shut down synchronously.
[0017] Hereinafter, the technical solution according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.
[0018] Figure 1 is a block diagram showing a power supply device 100 according to an embodiment of the present disclosure. Figure 1 The method 100 includes a plurality of power management chips 102 and a determination circuit 104 .
[0019] Each power management chip 102 includes a detection module 1022, a control module 1024, and at least one power module 1026. The detection module 1022 is configured to compare a target voltage based on an input power supply voltage with a reference voltage to generate a level signal at a first output terminal. The control module 1024 is configured to receive a synchronization signal at a control input terminal and generate a switch control signal based on the synchronization signal. At least one power module 1026 is configured to output a supply voltage at at least one second output terminal based on the switch control signal.
[0020] In some embodiments, the detection module 1022 is configured to receive the input power supply voltage and divide the input power supply voltage to obtain the target voltage. The detection module 1022 is configured to generate the level signal having the first value at the first output terminal when the target voltage is greater than or equal to the reference voltage. In addition, the detection module 1022 is configured to generate the level signal having a second value relative to the first value at the first output terminal when the target voltage is less than the reference voltage. In this way, it is detected whether the target voltage of the power management chip is greater than a preset reference voltage, so that different types of level signals are generated respectively according to the comparison results to distinguish the power-on states of different power management chips.
[0021] In some embodiments, the control module 1024 is configured to generate the switch control signal when the synchronization signal has the valid level so that the at least one power module 1026 outputs the supply voltage. In addition, the control module 1024 is configured to generate the switch control signal when the synchronization signal has the invalid level so that the at least one power module 1026 stops outputting the supply voltage. In this way, the power management chip is controlled based on the level state of the synchronization signal to start the power module to output power or to shut down the power module to stop supplying power, thereby effectively controlling the power-on timing or power-off timing of each power module.
[0022] In some embodiments, the control module 1024 is further configured to receive a clock signal, and further generate the switch control signal according to a set timing based on the clock signal. In this way, multiple power management chips generate switch control signals based on the same clock signal to ensure that the time after each power management chip is started is consistent, thereby achieving precise control of the timing of multiple power on / off.
[0023] In addition, the determination circuit 104 is configured to determine whether the level signals generated at the first output terminals all have the first value, and send the synchronization signal corresponding to the determination result to the control input terminals.
[0024] In some embodiments, the judgment circuit 104 is configured to send the synchronization signal with a valid level to each of the control input terminals when the level signal generated at each of the first output terminals has the first value. In addition, the judgment circuit 104 is configured to send the synchronization signal with an invalid level to each of the control input terminals when the level signal generated at any of the first output terminals has a second value relative to the first value. In this way, the level states of all power management chips are coupled to each other, and only when the level states of all power management chips are in the same state can the corresponding synchronization operation be performed, effectively ensuring the consistency of the power management chips.
[0025] Figure 2 is a circuit diagram showing a power supply device 100 according to an embodiment of the present disclosure. Figure 2 In some embodiments, the detection module 1022 may include a comparator 2202, a transistor 2204, and a resistor 2206. The comparator 2202 includes a first input terminal for receiving the target voltage, a second input terminal for receiving the reference voltage, and a comparison output terminal for outputting a comparison result signal. The transistor 2204 includes a control terminal for receiving the comparison result signal, a first terminal electrically coupled to the first output terminal, and a second terminal grounded. The resistor 2206 includes a first terminal electrically coupled to the input power supply voltage, and a second terminal electrically coupled to the first output terminal. In this way, the target signal is received by the comparator for voltage comparison, so that the conduction state of the transistor is controlled according to the comparison result, thereby generating different level states to input the judgment circuit for synchronous state coupling.
[0026] In some embodiments, the detection module 1022 is configured to turn off the transistor 2204 when the target voltage is greater than or equal to the reference voltage, so that the level signal at the first output terminal has a high level. In addition, the detection module 1022 is configured to turn on the transistor 2204 when the target voltage is less than the reference voltage, so that the level signal at the first output terminal has a low level. In this way, when the level signal is at a high level, it indicates that the target voltage of the power management chip meets the power-on condition. When the level signal is at a low level, it indicates that the target voltage of the power management chip does not meet the power-on condition.
[0027] In some embodiments, transistor 2204 is specifically a MOS tube. In a specific application scenario, transistor 2204 is an NMOS tube. The first input terminal of comparator 2202 is the inverting input terminal of the voltage comparator, and the second input terminal of comparator 2202 is the non-inverting input terminal of the voltage comparator. The control terminal of transistor 2204 is the gate G of the NMOS tube, the first terminal of transistor 2204 is the source S of the NMOS tube, and the second terminal of transistor 2204 is the drain D of the NMOS tube. That is, the inverting input terminal of the voltage comparator receives the target voltage VCC_DIV, the non-inverting input terminal of the voltage comparator receives the reference voltage REF, the output terminal of the voltage comparator is connected to the gate G of the NMOS tube, the drain D of the NMOS tube is grounded, and the source S of the NMOS tube is connected to the judgment circuit 104.
[0028] In some embodiments, the power module 1026 includes a converter 2602 and a power supply channel 2604. The converter 2602 is configured to receive the input power supply voltage and convert the input power supply voltage into the power supply voltage according to the switch control signal. The power supply channel 2604 is configured to output the power supply voltage via the second output terminal. In this way, different power modules under the same power management chip are independently operated and controlled.
[0029] In a specific application scenario, the converter 2602 is a DC-DC (direct current power supply) module, and the power supply channel 2604 is CHn.
[0030] In some embodiments, the judgment circuit 104 is configured to electrically couple the first output terminal of each of the detection modules 1022 in the multiple power management chips 102 to each synchronization signal terminal of the multiple power management chips 102. The judgment circuit 104 is configured to electrically connect the synchronization signal terminals of the multiple power management chips 102 together. In addition, the judgment circuit 104 is configured to electrically couple the synchronization signal terminals of the multiple power management chips 102 to the control input terminals of each of the control modules 1024 in the multiple power management chips 102. In this way, the level states of all power management chips are coupled to each other.
[0031] In a specific application scenario, the determination circuit 104 is a SYNC synchronization circuit.
[0032] In a specific application scenario, the target voltage VCC_DIV of each power management chip 102 after voltage division is input into its corresponding voltage comparator for comparison with the reference voltage REF. If the target voltage VCC_DIV is greater than the reference voltage REF, the voltage comparator outputs a low level. If the target voltage VCC_DIV is not greater than the reference voltage REF, the voltage comparator outputs a high level. At this time, the level signal output by the voltage comparator is input into the NMOS tube corresponding to the power management chip 102 via the output end of the voltage comparator to control the on and off of the NMOS tube; if the level state of the voltage comparator is low, the NMOS tube is cut off, and the source S of the NMOS tube is pulled high under the action of the resistor, so that the source S of the NMOS tube outputs a high level signal. If the level state of the voltage comparator is high, the NMOS tube is turned on, and the source S of the NMOS tube is pulled low under the action of the drain D being grounded, so that the source S of the NMOS tube outputs a low level signal.
[0033] The source S of the NMOS tube of each power management chip 102 is connected to the judgment circuit 104. Therefore, when any NMOS tube in the judgment circuit 104 is turned on, the source S of all NMOS tubes is pulled down under the action of the drain D of the turned-on NMOS tube being grounded, and the SYNC signal of the judgment circuit 104 is in a low level state. When any NMOS tube in the circuit is turned off, the source S of all NMOS tubes is pulled up under the action of their corresponding resistors, and the SYNC signal of the judgment circuit 104 is in a high level state. It can be seen that if the target voltage VCC_DIV of any power management chip 102 is not greater than the reference voltage REF, the SYNC signal of the judgment circuit 104 is in a low level state. If the target voltage VCC_DIV of all power management chips 102 is greater than the reference voltage REF, the SYNC signal of the judgment circuit 104 is in a high level state.
[0034] Each power management chip 102 detects the synchronization signal of the judgment circuit 104 in real time. If the detected synchronization signal is in a high-level state, the power management chip 102 starts the power-on procedure; if the detected synchronization signal is in a low-level state, the power management chip 102 will not start the power-on procedure. At the moment when the SYNC signal of the judgment circuit jumps from a low-level state to a high-level state, each power management chip 102 synchronously detects the rising edge jump, so all power management chips 102 are powered on at the same time. It can be seen that if the target voltage VCC_DIV of any power management chip 102 is not greater than the reference voltage REF, all power management chips 102 will not be powered on. If the target voltage VCC_DIV of all power management chips 102 is greater than the reference voltage REF, all power management chips 102 are powered on synchronously.
[0035] In a specific application scenario, the power supply device includes three power management chips 102, each power management chip 102 includes 20 power modules 1026, and each power module 1026 includes a converter 2602 and a power supply channel 2604. When the three power management chips 102 are used at the same time, the power supply device can simultaneously control 60 power modules in parallel. At this time, if it is necessary to start the 60 power modules in sequence according to the timing of starting one power module every 1ms, the clock signal CLK synchronizes the time of the three power management chips 102 to ensure that the three power management chips 102 can output the power supply voltage through the power supply channel 1 to the power supply channel 60 respectively according to the timing of 1ms to 60ms.
[0036] Figure 3 2 is a flow chart showing a method 200 for controlling a power supply device according to an embodiment of the present invention. The method 200 is applied to the above-mentioned power supply device. Figure 3 , including the following steps 202 to 208.
[0037] In step 202, the target voltage based on the input power supply voltage is compared with the reference voltage in each power management chip to generate a level signal at the first output terminal. In this way, in order to ensure the safety of the power management chip, it is generally necessary to detect whether the power supply voltage of the power management chip is greater than the set voltage during the boot process. If it is greater, the power supply devices of each circuit are started. Due to certain differences in process fluctuations of different chips, it is difficult to ensure that the power supply voltage of each power management chip meets the power-on conditions at the same time. Therefore, the target voltage of each power management chip is detected to accurately obtain the status of each power management chip.
[0038] In step 204 , a synchronization signal is received at a control input terminal in each power management chip, and a switch control signal is generated based on the synchronization signal.
[0039] In step 206 , in each power management chip, a supply voltage is output at at least one second output terminal based on the switch control signal.
[0040] In step 208, it is determined whether the level signals generated at each of the first output terminals have a first value, and the synchronization signal corresponding to the determination result is sent to each of the control input terminals. In this way, since it is difficult for all power management chips to meet the power-on condition at the same time, there are differences in the startup timings of different chips. In order to reduce the startup timing differences of different chips, the level signals of all power management chips are received by the judgment circuit. When there is a power management chip that does not meet the power-on condition, all power management chips will not start.
[0041] In summary, the present invention provides a power supply device and a method for controlling a power supply device, which respectively controls multiple power modules by providing multiple power management chips, so that multiple power supplies are respectively integrated on different power management chips, avoiding the problem of too many integrated channels of a single power management chip. At the same time, each power management chip is provided with a comparator, based on which the target voltage of each power management chip is respectively detected to be greater than the reference voltage, and a corresponding level signal is respectively generated according to the supply voltage, so as to ensure the power-on safety of each power management chip. Since there are certain differences in the process fluctuations of different chips, it is impossible to ensure that the voltage conditions of each power management chip can meet the power-on conditions at the same time, so there are differences in the power-on timing between different power management chips. For this reason, the present invention sets a judgment circuit, and the judgment circuit determines the corresponding synchronization signal according to the level signal of each power management chip, so as to control all power management chips to realize synchronous startup or synchronous shutdown based on the synchronization signal, thereby reducing the startup timing difference between different power management chips, ensuring that all power management chips can be turned on and off synchronously, and avoiding the problem of poor power timing control accuracy caused by the difference in startup timing between different power management chips.
[0042] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A power supply device, characterized in that: include: Multiple power management chips, each including: a detection module configured to compare a target voltage based on an input power supply voltage with a reference voltage to generate a level signal at a first output terminal; a control module configured to receive a synchronization signal at a control input and generate a switch control signal based on the synchronization signal; at least one power supply module, configured to output a supply voltage at at least one second output terminal based on the switch control signal; and The judgment circuit is configured to judge whether the level signals generated at each of the first output terminals all have a first value, and send the synchronization signal corresponding to the judgment result to each of the control input terminals.
2. The power supply device according to claim 1, characterized in that: The judgment circuit is configured as follows: When the level signals generated at the first output terminals all have the first value, sending the synchronization signal having a valid level to the control input terminals; as well as When the level signal generated at any one of the first output terminals has a second value opposite to the first value, the synchronization signal having an inactive level is transmitted to each of the control input terminals.
3. The power supply device according to claim 1, characterized in that: The judgment circuit is configured as follows: Electrically coupling the first output end of each of the detection modules in the multiple power management chips to each synchronization signal end of the multiple power management chips; Electrically connecting the synchronization signal terminals of the plurality of power management chips together; as well as The synchronization signal terminals of the plurality of power management chips are electrically coupled to the control input terminals of the control modules in the plurality of power management chips.
4. The power supply device according to claim 2, characterized in that: The control module is configured to: When the synchronization signal has the valid level, generating the switch control signal so that the at least one power supply module outputs the supply voltage; as well as When the synchronization signal has the invalid level, the switch control signal is generated to cause the at least one power supply module to stop outputting the supply voltage.
5. The power supply device according to claim 1, characterized in that: The control module is further configured to: A clock signal is received, and the switch control signal is further generated according to a set timing based on the clock signal.
6. The power supply device according to claim 1, characterized in that: The detection module is configured as follows: receiving the input power supply voltage, and dividing the input power supply voltage to obtain the target voltage; When the target voltage is greater than or equal to the reference voltage, generating the level signal having the first value at the first output terminal; as well as When the target voltage is less than the reference voltage, the level signal having a second value opposite to the first value is generated at the first output terminal.
7. The power supply device according to claim 1, characterized in that: The detection module comprises: A comparator, comprising a first input terminal for receiving the target voltage, a second input terminal for receiving the reference voltage, and a comparison output terminal for outputting a comparison result signal; a transistor including a control terminal receiving the comparison result signal, a first terminal electrically coupled to the first output terminal, and a second terminal grounded; and A resistor includes a first terminal electrically coupled to the input supply voltage and a second terminal electrically coupled to the first output terminal.
8. The power supply device according to claim 7, characterized in that: The detection module is configured as follows: When the target voltage is greater than or equal to the reference voltage, turning off the transistor so that the level signal at the first output terminal has a high level; and When the target voltage is less than the reference voltage, the transistor is turned on so that the level signal at the first output terminal has a low level.
9. The power supply device according to claim 1, characterized in that: The power module comprises: a converter configured to receive the input power voltage and convert the input power voltage into the supply voltage according to the switch control signal; and The power supply channel is configured to output the power supply voltage via the second output terminal.
10. A method for controlling a power supply device, characterized in that: include: comparing a target voltage based on an input power voltage with a reference voltage in each power management chip to generate a level signal at a first output terminal; receiving a synchronization signal at a control input terminal in each power management chip, and generating a switch control signal based on the synchronization signal; In each power management chip, based on the switch control signal, the power supply voltage is output at at least one second output terminal; as well as It is determined whether the level signals generated at the first output terminals all have a first value, and the synchronization signal corresponding to the determination result is sent to the control input terminals.