Low-noise amplifier circuit for short-distance wireless communication

By designing a low-noise amplifier circuit including input matching network, transistor amplification network, output matching network and bias circuit, the problem of difficulty in achieving low noise figure and high gain at the same time in the prior art is solved, and the simultaneous matching of low noise and high gain is achieved, which improves the sensitivity of the circuit and reduces the loss of the matching network.

CN119652265AInactive Publication Date: 2025-03-18CHENGDU AEROSPACE BOMU ELECTRONIC TECH CO LTD

Patent Information

Application Number
CN202411726236.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-28
Publication Date
2025-03-18
Estimated Expiration
Not applicable · inactive patent

AI Technical Summary

Technical Problem

The existing millimeter wave low-noise amplifier circuits are difficult to achieve low noise figure and high gain at the same time, which limits the research and development and application of millimeter wave circuits.

Method used

A low-noise amplifier circuit including an input matching network, a transistor amplification network, an output matching network and a bias circuit is designed to achieve simultaneous matching of low noise and high gain through the combination of common source and co-gate levels.

Benefits of technology

The simultaneous matching of low noise figure and high gain is achieved, which reduces the noise figure, improves the sensitivity of the circuit, and reduces the loss of the matching network.

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Abstract

The invention belongs to the technical field of millimeter wave communication, and discloses a low-noise amplifier circuit for short-distance wireless communication, which comprises an input matching network, a transistor amplification network, an output matching network and a biasing circuit, the input end of the low-noise amplifier circuit is connected with the input end of the input matching network and is used for inputting a radio frequency signal; the input matching network is used for realizing 50-ohm impedance matching between an input radio-frequency signal and the transistor amplification network, the output end of the input matching network is connected with the input end of the transistor amplification network, the transistor amplification network is used for realizing amplification of the radio-frequency signal, and the output end of the transistor amplification network is connected with the input end of the output matching network; the output matching network is used for achieving output impedance matching, the output end of the output matching network is the output end of the low-noise amplifier circuit, and the bias circuit is used for providing first bias voltage and second bias voltage for the transistor amplification network. According to the invention, the low-noise and high-gain signal amplification function can be realized, the signal loss can be effectively reduced, and the available bandwidth can be expanded.
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Description

Technical Field

[0001] The present invention belongs to the technical field of millimeter wave communications, and in particular relates to a low noise amplifier circuit for short-range wireless communications. Background Art

[0002] In recent years, wireless communication technology has developed rapidly, and various demands have been continuously put forward, requiring higher-speed wireless communication technology, which requires higher bandwidth. The millimeter wave frequency band has high frequency, large available bandwidth, and fast transmission rate, and is widely used in communication, radar, Internet of Things and other fields. The millimeter wave frequency band has become a hot research topic in short-range wireless communication due to its abundant spectrum resources, good directivity, and large loss in free space.

[0003] In millimeter wave circuits, low noise amplifiers are key modules used to receive radio frequency signals, but their design is difficult, and gain and noise figure are key indicators. General millimeter wave low noise amplifier circuits are difficult to achieve low noise figure, high gain and other indicators at the same time, which limits the research and development and application of millimeter wave circuits. Summary of the invention

[0004] The object of the present invention is to provide a low noise amplifier circuit for short-range wireless communication, which can achieve low noise figure and high gain at the same time.

[0005] In order to achieve the above-mentioned object, one aspect of the present invention provides a low noise amplifier circuit for short-range wireless communication, comprising an input matching network, a transistor amplification network, an output matching network, and a bias circuit;

[0006] The input end of the low-noise amplifier circuit is connected to the input end of the input matching network for inputting a radio frequency signal; the input matching network is used to achieve 50 ohm impedance matching between the input radio frequency signal and the transistor amplification network, and its output end is connected to the input end of the transistor amplification network; the transistor amplification network is used to achieve amplification of the radio frequency signal, and its output end is connected to the input end of the output matching network; the output matching network is used to achieve output impedance matching, and its output end is the output end of the low-noise amplifier circuit; the bias circuit is used to provide a first bias voltage and a second bias voltage for the transistor amplification network;

[0007] The transistor amplification network includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a third inductor, a fourth inductor, a fifth inductor, a second capacitor, and a third capacitor;

[0008] The gate of the first MOS tube is the input end of the transistor amplification network, and its gate bias voltage is the first bias voltage, the source is connected to the fourth inductor to the ground, and the drain is connected to the third inductor to the power supply; the gate bias voltage of the second MOS tube is the first bias voltage, the gate bias voltage of the third MOS tube is the second bias voltage, and the drain of the third MOS tube is connected to the power supply through the fifth inductor; the gate bias voltage of the fourth MOS tube is the first bias voltage, the gate bias voltage of the fifth MOS tube is the second bias voltage, and the drain of the fifth MOS tube is the output end of the transistor amplification network; one end of the second capacitor is connected to the drain of the first MOS tube, and the other end is connected to the gate of the second MOS tube, the source of the second MOS tube is grounded, and the drain is connected to the source of the third MOS tube; one end of the third capacitor is connected to the drain of the third MOS tube, and the other end is connected to the gate of the fourth MOS tube, the source of the fourth MOS tube is grounded, and the drain is connected to the source of the fifth MOS tube.

[0009] Preferably, the input matching network includes a first inductor, a first capacitor, and a second inductor;

[0010] Among them, one end of the first inductor is connected to the input RF signal and one end of the first capacitor, and the other end is grounded. The other end of the first capacitor is connected to one end of the second inductor. One end of the second inductor is connected to the first capacitor, and the other end serves as the output end of the input matching network and is connected to the input end of the transistor amplification network.

[0011] Preferably, the output matching network includes a sixth inductor, a seventh inductor, an eighth inductor, a fourth capacitor, and a fifth capacitor;

[0012] Among them, one end of the sixth inductor is connected to the output end of the transistor amplifier network, and the other end is connected to one end of the seventh inductor and the eighth inductor. The other end of the seventh inductor is connected to the power supply. The other end of the eighth inductor is connected to one end of the fourth capacitor and the fifth capacitor. The other end of the fourth capacitor is grounded, and the other end of the fifth capacitor serves as the output end of the output matching network.

[0013] Preferably, the bias circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, and a decoupling capacitor;

[0014] Among them, one end of the first resistor is connected to one end of the second resistor, and the other end is connected to the power supply, and the other end of the second resistor is grounded; one end of the third resistor is connected to one end of the first resistor and one end of the second resistor, and the other end is connected to the first bias voltage; one end of the fourth resistor is connected to the power supply, and the other end is connected to the second bias voltage and grounded through a decoupling capacitor.

[0015] According to the low noise amplifier circuit for short-distance wireless communication according to the above aspect of the present invention, a low noise figure and a high gain can be achieved simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings used in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work:

[0017] Figure 1 is a schematic structural diagram of a low noise amplifier circuit for short-range wireless communication according to an embodiment of the present invention;

[0018] Figure 2 It is a schematic diagram of the structure of an input matching network of a low noise amplifier circuit for short-range wireless communication according to an embodiment of the present invention;

[0019] Figure 3 It is a schematic structural diagram of a transistor amplification network of a low noise amplifier circuit for short-range wireless communication according to an embodiment of the present invention;

[0020] Figure 4 It is a schematic diagram of the structure of an output matching network of a low noise amplifier circuit for short-range wireless communication according to an embodiment of the present invention;

[0021] Figure 5 The figure is a schematic diagram of a bias circuit of a low noise amplifier circuit for short-range wireless communication according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] One embodiment of the present invention provides a low noise amplifier circuit for short-range wireless communication, such as Figure 1 As shown, the low noise amplifier circuit for short-range wireless communication according to the embodiment of the present invention includes an input matching network, a transistor amplification network, an output matching network, and a bias circuit.

[0024] Among them, the input end of the low-noise amplifier circuit is connected to the input end of the input matching network for inputting radio frequency signals; the input matching network is used to achieve 50 ohm broadband impedance matching between the input radio frequency signal and the transistor amplification network, so as to transmit the radio frequency signal to the maximum extent, and its output end is connected to the input end of the transistor amplification network; the transistor amplification network is a single-ended output, so as to achieve amplification of the radio frequency signal and suppress the noise of the subsequent circuit in the system, and its output end is connected to the input end of the output matching network; the output matching network is used to achieve output impedance matching, reduce the loss of the matching network, and transmit the radio frequency signal to the subsequent circuit, and its output end is the output end of the low-noise amplifier circuit; the bias circuit provides bias voltages for the transistor amplification network, namely, the first bias voltage VB1 and the second bias voltage VB2, and VDD is the power supply, which provides the working voltage of the circuit.

[0025] The working process of the low-noise amplifier circuit of the embodiment of the present invention is as follows: the input signal is the radio frequency signal RFin, which passes through the input matching network to achieve low-noise matching and broadband impedance matching, and the output end is the signal RFin1; then the signal RFin1 is sent to the transistor amplification network, passes through the three-stage amplification structure, and achieves low-noise, high-gain amplification, and the output end is RFout1; and then passes through the output matching network to achieve broadband output impedance matching and output power optimization, maximize the transmission of radio frequency signals, and achieve low-noise reception and high-gain amplification of millimeter wave signals, and the output end is RFout.

[0026] like Figure 2 As shown, the input matching network includes a first inductor L1, a first capacitor C1, and a second inductor L2. The first inductor L1 is a parallel inductor connected to the ground, the first capacitor C1 is a series capacitor, and the second inductor L2 is a series inductor.

[0027] One end of the first inductor L1 is connected to the input signal RFin and one end of the first capacitor C1, and the other end is grounded. The other end of the first capacitor C1 is connected to one end of the second inductor L2. One end of the second inductor L2 is connected to the first capacitor C1, and the other end serves as the output end of the input matching network and is connected to the input end RFin1 of the transistor amplifier network.

[0028] The input matching network of the embodiment of the present invention expands the bandwidth through a broadband matching network composed of capacitors and inductors; within the operating frequency range, the input reflection coefficient is about -15dB; the inductors are designed with top metal and sub-top metal of the CMOS process, which reduces substrate loss and reduces the loss of the matching network.

[0029] like Figure 3As shown, the transistor amplification network is a three-stage structure, including a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a second capacitor C2, and a third capacitor C3.

[0030] The gate of the first MOS tube M1 is the input terminal RFin1 of the transistor amplifier network, and its gate bias voltage is the first bias voltage VB1. The source is connected to the fourth inductor L4 to the ground, and the drain is connected to the third inductor L3 to VDD, forming a first-stage common-source amplifier network. The gate bias voltage of the second MOS tube M2 is the first bias voltage VB1, the gate bias voltage of the third MOS tube M3 is the second bias voltage VB2, and the drain of the third MOS tube M3 is connected to the voltage VDD through the fifth inductor L5, forming a second-stage common-source and common-gate amplifier network. The gate bias voltage of the fourth MOS tube M4 is the first bias voltage VB1, the gate bias voltage of the fifth MOS tube M5 is the second bias voltage VB2, and the drain of the fifth MOS tube M5 is the output terminal RFout1 of the transistor amplifier network, forming a third-stage common-source and common-gate amplifier network. The first-stage amplifier network and the second-stage amplifier network are connected by the second capacitor C2, and the second-stage amplifier network and the third-stage amplifier network are connected by the third capacitor C3. Specifically, one end of the second capacitor C2 is connected to the drain of the first MOS tube M1, and the other end is connected to the gate of the second MOS tube M2. The source of the second MOS tube M2 is grounded, and the drain is connected to the source of the third MOS tube M3. One end of the third capacitor C3 is connected to the drain of the third MOS tube M3, and the other end is connected to the gate of the fourth MOS tube M4. The source of the fourth MOS tube M4 is grounded, and the drain is connected to the source of the fifth MOS tube M5.

[0031] Among them, the gate of the first MOS tube M1 is the input end of the transistor amplification network, and the bias voltage is the first bias voltage VB1, which is provided by the bias circuit; the fourth inductor L4 is the source inductor, and by adjusting the parameters, low noise coefficient matching and broadband impedance matching are achieved at the same time; the second-stage common source and common gate structure and the third-stage common source and common gate structure are to improve the gain of the low noise amplifier and suppress the noise of the subsequent circuit in the system; the third inductor L3, the second capacitor C2, the fifth inductor L5, and the third capacitor C3 constitute an inter-stage matching network, which is mainly used to adjust the positive slope of the amplifier gain and optimize the in-band gain flatness.

[0032] The beneficial effects of the above transistor amplification network solution are: reducing the noise coefficient, increasing the gain, and maximizing the sensitivity of the low-noise amplifier.

[0033] like Figure 4As shown, the output matching network includes a sixth inductor L6, a seventh inductor L7, an eighth inductor L8, a fourth capacitor C4, and a fifth capacitor C5. The sixth inductor L6 is a series inductor, the seventh inductor L7 is a parallel inductor, the eighth inductor L8 is a series inductor, the fourth capacitor C4 is a parallel ground capacitor, and the fifth capacitor C5 is a series capacitor.

[0034] Among them, one end of the sixth inductor L6 is connected to the output end RFout1 of the transistor amplifier network, and the other end is connected to one end of the seventh inductor L7 and the eighth inductor L8. The other end of the seventh inductor L7 is connected to the power supply VDD. The other end of the eighth inductor L8 is connected to one end of the fourth capacitor C4 and the fifth capacitor C5. The other end of the fourth capacitor C4 is grounded. The other end of the fifth capacitor C5 serves as the output end of the output matching network, which is also the output end RFout of the entire circuit.

[0035] The output matching network forms a multi-component matching network through the joint design of inductors and capacitors, which has greater design freedom, thereby achieving a compromise between bandwidth and output power and optimizing them together.

[0036] like Figure 5 As shown, the bias circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a decoupling capacitor Cdecap.

[0037] The first resistor R1 and the second resistor R2 form a voltage divider network, one end of the first resistor R1 is connected to one end of the second resistor R2, and the other end is connected to the power supply VDD, and the other end of the second resistor R2 is grounded; one end of the third resistor R3 is connected to the connection between the first resistor R1 and the second resistor R2, that is, connected to one end of the first resistor R1 and one end of the second resistor R2, and the other end is connected to the first bias voltage VB1, that is, the gates of the first MOS tube M1, the second MOS tube M2, and the fourth MOS tube M4; one end of the fourth resistor R4 is connected to the power supply VDD, and the other end is connected to the second bias voltage VB2, and is grounded through the decoupling capacitor Cdecap to reduce the impact of external power supply fluctuations.

[0038] Compared with the prior art, the low noise amplifier circuit for short-range wireless communication according to the embodiment of the present invention has the following advantages:

[0039] The low-noise amplifier circuit of the present invention adopts a common source stage as the first stage, which reduces the noise coefficient compared with the common source and common gate stage, and uses a source inductor L4 to achieve low noise and broadband impedance matching at the same time; adopts a two-stage common source and common gate stage to improve the circuit gain and suppress the influence of the subsequent circuit in the system; a simple LC network is used for inter-stage matching to reduce signal transmission loss, adjust the gain positive slope, and improve the in-band gain flatness; the purpose of low noise coefficient and high gain is achieved.

[0040] The input / output matching networks of the present invention are designed with multiple passive components, which improves the design freedom, reduces the matching network loss while meeting the extended 3dB bandwidth index, and achieves the purpose of low noise and high gain.

[0041] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A low noise amplifier circuit for short-range wireless communication, characterized in that: Including input matching network, transistor amplification network, output matching network, bias circuit; The input end of the low-noise amplifier circuit is connected to the input end of the input matching network for inputting a radio frequency signal; the input matching network is used to achieve 50 ohm impedance matching between the input radio frequency signal and the transistor amplification network, and its output end is connected to the input end of the transistor amplification network; the transistor amplification network is used to achieve amplification of the radio frequency signal, and its output end is connected to the input end of the output matching network; the output matching network is used to achieve output impedance matching, and its output end is the output end of the low-noise amplifier circuit; the bias circuit is used to provide a first bias voltage and a second bias voltage for the transistor amplification network; The transistor amplification network includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a third inductor, a fourth inductor, a fifth inductor, a second capacitor, and a third capacitor; The gate of the first MOS tube is the input end of the transistor amplification network, the gate bias voltage thereof is the first bias voltage, the source is connected to the fourth inductor to the ground, and the drain is connected to the third inductor to the power supply; the gate bias voltage of the second MOS tube is the first bias voltage, the gate bias voltage of the third MOS tube is the second bias voltage, and the drain of the third MOS tube is connected to the power supply through the fifth inductor; The gate bias voltage of the fourth MOS tube is the first bias voltage, the gate bias voltage of the fifth MOS tube is the second bias voltage, and the drain of the fifth MOS tube is the output end of the transistor amplification network; one end of the second capacitor is connected to the drain of the first MOS tube, and the other end is connected to the gate of the second MOS tube, the source of the second MOS tube is grounded, and the drain is connected to the source of the third MOS tube; one end of the third capacitor is connected to the drain of the third MOS tube, and the other end is connected to the gate of the fourth MOS tube, the source of the fourth MOS tube is grounded, and the drain is connected to the source of the fifth MOS tube.

2. The low noise amplifier circuit according to claim 1, characterized in that The input matching network includes a first inductor, a first capacitor, and a second inductor; Among them, one end of the first inductor is connected to the input RF signal and one end of the first capacitor, and the other end is grounded. The other end of the first capacitor is connected to one end of the second inductor. One end of the second inductor is connected to the first capacitor, and the other end serves as the output end of the input matching network and is connected to the input end of the transistor amplification network.

3. The low noise amplifier circuit according to claim 1 or 2, characterized in that: The output matching network includes a sixth inductor, a seventh inductor, an eighth inductor, a fourth capacitor, and a fifth capacitor; Among them, one end of the sixth inductor is connected to the output end of the transistor amplifier network, and the other end is connected to one end of the seventh inductor and the eighth inductor. The other end of the seventh inductor is connected to the power supply. The other end of the eighth inductor is connected to one end of the fourth capacitor and the fifth capacitor. The other end of the fourth capacitor is grounded, and the other end of the fifth capacitor serves as the output end of the output matching network.

4. The low noise amplifier circuit according to claim 1 or 2, characterized in that: The bias circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a decoupling capacitor; Among them, one end of the first resistor is connected to one end of the second resistor, and the other end is connected to the power supply, and the other end of the second resistor is grounded; one end of the third resistor is connected to one end of the first resistor and one end of the second resistor, and the other end is connected to the first bias voltage; one end of the fourth resistor is connected to the power supply, and the other end is connected to the second bias voltage and grounded through a decoupling capacitor.

Citation Information

Patent Citations

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