Method, device, medium and system for evaluating high-speed signal quality of domestic switching chips

Abstract

This invention discloses a method, device, medium, and system for evaluating the high-speed signal quality of a domestically produced switching chip. This method, which belongs to the field of embedded systems, includes the steps of: In response to a PortWrite event reported by a domestically produced switching chip, utilizing the pseudo-random binary sequence (PRBS) generator of an 1800 chip to perform a random sequence bit error rate test on the switching chip's lanes. This invention offers the advantages of low cost, simple operation, and accurate results.

Description

Technical Field

[0001] The present invention relates to the field of embedded systems, and more specifically, to a method, device, medium and system for evaluating the quality of high-speed signals of a domestic switching chip. Background Art

[0002] In embedded system applications, all hardware components are connected via buses. Due to limitations in transmission rates and system topology, traditional interconnect buses are no longer able to meet the demands of ever-increasing processor frequencies and performance. Therefore, in embedded environments, the RapidIO high-speed serial bus is widely used for inter-chip and inter-board interconnection and transmission, achieving communication rates ranging from 1Gbps to 60Gbps.

[0003] Currently, integrated electronic information systems primarily consist of network switching modules (RCMs), general data processing modules (DPMs), and general signal processing modules (SPMs). Domestic RapidIO switching chips are used to achieve high-reliability data transmission between chips and boards. The network switching modules, general signal processing modules, and data processing modules are all equipped with one or more domestic SRIO switching chips, forming a RapidIO-based network transmission framework.

[0004] During system integration, domestic switching chips often report PortWrite events. According to the chip manual, the cause of the report could be poor hardware signal quality or a software error, causing nodes to erroneously exit or fail to join the network, resulting in system malfunction. In these cases, it's crucial to quickly isolate the hardware or software issue. The traditional method involves using an oscilloscope to create an eye diagram. However, such oscilloscopes have high bandwidth and sampling rate requirements and are expensive.

[0005] The disadvantages of this existing method are:

[0006] (1) Oscilloscopes have high requirements for bandwidth and sampling rate, and are expensive, so sometimes the conditions may not be met.

[0007] (2) When using an oscilloscope for testing, it is necessary to manually confirm the start and end points of the eye pattern, which is cumbersome.

[0008] (3) The eye diagram obtained by using an oscilloscope signal may not be accurate. The position and time of signal capture as well as the experience of using the oscilloscope have a great impact on the eye diagram result. Summary of the Invention

[0009] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method, device, medium and system for evaluating the quality of high-speed signals of a domestic switching chip, which has the advantages of low cost, simple operation and accurate results.

[0010] The object of the present invention is achieved through the following solutions:

[0011] A method for evaluating the quality of high-speed signals in a domestic switching chip uses the pseudo-random binary sequence (PRBS) generator of the 1800 chip to perform a random sequence bit error rate test on the lanes of the switching chip. The method specifically includes the following steps:

[0012] S1, traverses and detects all domestic switching chips in the network;

[0013] S2, traverse and detect all ports 0 to 17 of the switch chip;

[0014] S3: If the PORT_OK bit field of the RIO Port Error and Status CSR is 2, the port is valid; otherwise, the port is invalid and the program jumps to S2 to check the next port.

[0015] S4, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip local port Lane {0..47} Control Register register value to 0x28E000A;

[0016] S5, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip's opposite port Lane{0..47}Control Register register value to 0x28E000A;

[0017] S6, read the Lane{0..47}PRBS Error CounterRegister register values ​​of the local and peer switching chips through I2C read operations;

[0018] S7, store and analyze the data to determine the port quality. If the PRBS_ERR bit field is 0, the signal quality is good. If the PRBS_ERR bit field is 1, the signal quality is poor. The larger the PRBS_ERR_CNT bit field value, the more errors there are and the worse the signal quality.

[0019] S8, record the data and jump to S2 to detect the next port;

[0020] S9: After detecting the current switch chip, jump to S1 to detect the next switch chip;

[0021] S10: Report the signal quality results of all switch chip ports.

[0022] Furthermore, in step S1, the detection network is an SRIO network.

[0023] Furthermore, the SRIO network includes: 1 SRIO switch board, 1 data processing board and 2 signal processing boards. The data processing board and the signal processing board are interconnected through the SRIO domestic switch chip to jointly build an SRIO network environment.

[0024] Furthermore, a testing device is included, and the testing device resides in the master control node of the SRIO switch board.

[0025] A domestic switching chip high-speed signal quality evaluation device comprises a processor and a memory, wherein the memory stores a computer program and executes any of the above methods when the computer program is loaded by the processor.

[0026] A computer-readable storage medium stores a computer program, wherein the computer program executes any of the above methods when loaded by a processor.

[0027] A domestic switching chip high-speed signal quality evaluation system includes the domestic switching chip high-speed signal quality evaluation device as described above.

[0028] The beneficial effects of the present invention include:

[0029] (1) The solution of the present invention targets the problem of domestic switching chips reporting PortWrite events in the prior art. By using the pseudo-random binary sequence (PRBS) generator of the 1800 chip, a random sequence bit error rate test is performed on the lanes of the switching chip, providing a solution for node quality assessment of domestic switching chips.

[0030] (2) The solution of the present invention has the advantage of low cost. The method of using an oscilloscope to drill an eye diagram to detect signal quality requires an expensive oscilloscope. The present invention uses the pseudo-random binary sequence (PRBS) generator of the 1800 chip to perform a random sequence bit error rate test on the lanes of the switching chip, and then completes the monitoring, recording and analysis of the port. It is simple and effective and does not require an expensive, high-bandwidth and high-sampling-rate oscilloscope.

[0031] (3) The solution of the present invention has the advantages of simple operation and accurate results. The eye diagram results obtained by using an oscilloscope may be inaccurate. The signal capture position and time, as well as the experience of using the oscilloscope, have a significant impact on the eye diagram results. The method and device of the present invention can automatically traverse and detect the signal quality of all paths passing through the port in the SRIO network. The operation is simple, no manual eye diagram is required, and the results are accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 Schematic diagram of a domestic switch chip node quality assessment device according to an embodiment of the present invention;

[0034] Figure 2 FIG. 4 is a schematic diagram of an SRIO network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0036] Explanation of terms

[0037] RIO Port Error and Status CSR PORT_OK, PORT_OK bit field of the RIO port error status register;

[0038] Lane{0..47}Control Register(0xFF8000), channel control register base address;

[0039] Lane{0..47}PRBS Error Counter Register(0xFF8008;), channel PRBS error counter register base address;

[0040] 0xFF8008+0x100*lanenum, the PRBS error count register address of the channel with channel number lanenum;

[0041] BIT23 refers to the BIT32 bit of the RIO Port Error and Status CSR register, namely the PORT_OK bit segment;

[0042] lane, channel.

[0043] like Figure 2 As shown in the figure, it is a schematic diagram of SRIO network. The chassis contains one SRIO domestic switch board, one data processing board and two signal processing boards. The modules are interconnected through SRIO domestic switch chips to jointly build an SRIO network environment. The test device resides in the master node of the switch module. As a further embodiment of the present invention, Figure 1 As shown, a method for evaluating the quality of a domestic switching chip node is provided, comprising the following steps:

[0044] S1, traverses and detects all domestic switching chips in the network;

[0045] S2, traverse and detect all ports 0 to 17 of the switch chip;

[0046] In step S3, if the PORT_OK field in the RIO Port Error and Status CSR (address 0x158+0x20*portnum) is 2, the port is valid. Otherwise, the port is invalid and the program jumps to step S2 to check the next port.

[0047] S4, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip local port Lane {0..47} Control Register register (address 0xFF8000+0x100*lanenum) value to 0x28E000A;

[0048] S5, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip's opposite port Lane{0..47}Control Register register (address 0xFF8000+0x100*lanenum) to 0x28E000A;

[0049] S6, read the values ​​of the Lane{0..47}PRBS Error CounterRegister register (address 0xFF8008+0x100*lanenum) of the local and peer switching chips through I2C read operations;

[0050] S7, store and analyze the data to determine the port quality. If the PRBS_ERR bit field is 0, the signal quality is good. If the PRBS_ERR bit field is 1, the signal quality is poor. The larger the PRBS_ERR_CNT bit field value, the more errors there are and the worse the signal quality.

[0051] S8, record the data and jump to S2 to detect the next port;

[0052] S9: After detecting the current switch chip, jump to S1 to detect the next switch chip;

[0053] S10: Report the signal quality results of all switch chip ports.

[0054] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0055] Example 1

[0056] A method for evaluating the quality of high-speed signals in a domestic switching chip uses the pseudo-random binary sequence (PRBS) generator of the 1800 chip to perform a random sequence bit error rate test on the lanes of the switching chip. The method specifically includes the following steps:

[0057] S1, traverses and detects all domestic switching chips in the network;

[0058] S2, traverse and detect all ports 0 to 17 of the switch chip;

[0059] S3: If the PORT_OK bit field of the RIO Port Error and Status CSR is 2, the port is valid; otherwise, the port is invalid and the program jumps to S2 to check the next port.

[0060] S4, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip local port Lane {0..47} Control Register register value to 0x28E000A;

[0061] S5, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip's opposite port Lane{0..47}Control Register register value to 0x28E000A;

[0062] S6, read the Lane{0..47}PRBS Error CounterRegister register values ​​of the local and peer switching chips through I2C read operations;

[0063] S7, store and analyze the data to determine the port quality. If the PRBS_ERR bit field is 0, the signal quality is good. If the PRBS_ERR bit field is 1, the signal quality is poor. The larger the PRBS_ERR_CNT bit field value, the more errors there are and the worse the signal quality.

[0064] S8, record the data and jump to S2 to detect the next port;

[0065] S9: After detecting the current switch chip, jump to S1 to detect the next switch chip;

[0066] S10: Report the signal quality results of all switch chip ports.

[0067] Example 2

[0068] Based on Example 1, in step S1, the detection network is an SRIO network.

[0069] Example 3

[0070] Based on Example 2, the SRIO network includes: 1 SRIO switch board, 1 data processing board and 2 signal processing boards. The data processing board and the signal processing board are interconnected through the SRIO domestic switch chip to jointly build an SRIO network environment.

[0071] Example 4

[0072] On the basis of embodiment 3, a testing device is further included, and the testing device resides in the master control node of the SRIO switch board.

[0073] Example 5

[0074] A domestic switching chip high-speed signal quality assessment device includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is loaded by the processor, the method described in any one of Examples 1 to 5 is executed.

[0075] Example 6

[0076] A computer-readable storage medium stores a computer program, wherein the computer program executes the method described in any one of Embodiments 1 to 4 when loaded by a processor.

[0077] Example 7

[0078] A domestic switching chip high-speed signal quality assessment system includes the domestic switching chip high-speed signal quality assessment device as described in Example 5.

[0079] The units involved in the embodiments of the present invention may be implemented in software or hardware, and the units described may also be provided in a processor. In some cases, the names of these units do not limit the units themselves.

[0080] According to one aspect of an embodiment of the present invention, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations described above.

[0081] As another aspect, embodiments of the present invention further provide a computer-readable medium, which may be included in the electronic device described in the above embodiments, or may exist independently and not incorporated into the electronic device. The computer-readable medium carries one or more programs, and when executed by the electronic device, the electronic device implements the methods described in the above embodiments.

Claims

1. A method for evaluating the quality of high-speed signals of a domestic switching chip, characterized in that: Use the pseudo-random binary sequence PRBS generator of the 1800 chip to perform a random sequence bit error rate test on the lanes of the switch chip. The specific steps include the following: S1, traverses and detects all domestic switching chips in the network; S2, traverse and detect all ports 0 to 17 of the switch chip; S3: If the PORT_OK bit field of the RIO Port Error and Status CSR is 2, the port is valid; otherwise, the port is invalid and the program jumps to S2 to check the next port. S4, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip local port Lane {0..47} Control Register register value to 0x28E000A; S5, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip's opposite port Lane {0..47} Control Register register value to 0x28E000A; S6, read the Lane {0..47} PRBS Error CounterRegister register values ​​of the local and peer switching chips through I2C read operations; S7, store and analyze the data to determine the port quality. If the PRBS_ERR bit field is 0, the signal quality is good. If the PRBS_ERR bit field is 1, the signal quality is poor. The larger the PRBS_ERR_CNT bit field value, the more errors there are and the worse the signal quality. S8, record the data and jump to S2 to detect the next port; S9: After detecting the current switch chip, jump to S1 to detect the next switch chip; S10: Report the signal quality results of all switch chip ports.

2. The method for evaluating the quality of high-speed signals of a domestic switching chip according to claim 1, characterized in that: In step S1, the detection network is an SRIO network.

3. The method for evaluating the quality of high-speed signals of a domestic switching chip according to claim 2, characterized in that: The SRIO network includes: 1 SRIO switching board, 1 data processing board and 2 signal processing boards. The data processing board and the signal processing board are interconnected through the SRIO domestic switching chip to jointly build an SRIO network environment.

4. The method for evaluating the quality of high-speed signals of a domestic switching chip according to claim 3, characterized in that: The system also includes a testing device, which resides in a master control node of the SRIO switch board.

5. A domestic switching chip high-speed signal quality assessment device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 1 to 4 is executed.

6. A computer-readable storage medium, characterized in that A computer program is stored in a readable storage medium, and when the computer program is loaded by a processor, the method according to any one of claims 1 to 4 is executed.

7. A domestic switching chip high-speed signal quality evaluation system, characterized in that: It includes the domestic switching chip high-speed signal quality evaluation device as described in claim 5.

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