Pixel circuit, image sensor, camera module and electronic equipment

Abstract

The invention discloses a pixel circuit, an image sensor, a camera module and electronic equipment, and belongs to the technical field of electronics. The pixel circuit comprises a double-capacitor circuit, the double-capacitor circuit comprises a photodiode, a first capacitor and a second capacitor, the capacitance value of the first capacitor is larger than that of the second capacitor, and the first capacitor and the second capacitor are used for receiving and storing electrons overflowing from the photodiode; the electronic emptying circuit is connected with the first capacitor, and the electronic emptying circuit is used for emptying electrons in the first capacitor under the condition that the voltage value of the first capacitor is smaller than a first threshold value; and the phase inverting circuit is connected with the double-capacitor circuit and the electronic emptying circuit, and is used for inverting an output signal of the electronic emptying circuit and controlling the on-off of an electronic transmission path between the photodiode and the first capacitor.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and specifically relates to a pixel circuit, an image sensor, a camera module and an electronic device. Background Art

[0002] For many imaging applications, such as automotive imaging, surveillance, and mobile phone photography, there will be shooting scenes with huge differences between the brightest and darkest parts. For such shooting scenes, the DR (Dynamic Range, defined as the ratio of the full well capacity of the image sensor to the readout noise) of the image sensor needs to exceed 105dB or even 106dB to accurately capture the image of the shooting scene. At present, manufacturers have developed a large number of CMOS (Complementary Metal Oxide Semiconductor) image sensors with HDR (High Dynamic Range).

[0003] For example, increasing the dynamic range of an image sensor can be achieved by reducing its readout noise. Based on this, manufacturers have developed pixel imaging devices with extremely low or even sub-electron noise. However, the cost of reducing the readout noise of an image sensor is to significantly increase its conversion gain to more than 100μV / e-, while its maximum output signal still cannot exceed about 1.5V. In this way, the FWC (Full Well Capacity, the maximum amount of charge that each pixel in a CMOS image sensor can accommodate) of the image sensor will be limited by the output signal, and the dynamic range of the image sensor has not increased significantly.

[0004] Furthermore, increasing the dynamic range of an image sensor can also be achieved by increasing its FWC and the output signal span of the ADC (Analog-to-Digital Converter). However, due to the low operating voltage of the image sensor, the pixel will become smaller, thereby reducing the pixel area and FWC, and the growth of the dynamic range of the image sensor is limited. In addition, if the image sensor is to have a high dynamic range, the resolution of the ADC must exceed 16 bits.

[0005] Furthermore, the image sensor can also have a high dynamic range through a DCG (Dual Conversion Gain) pixel structure with a dual-gain column amplifier and a dual ADC. In this pixel structure, a pixel array is operated by two column amplifiers, one column amplifier has a gain of 1, and the other column amplifier has a gain of 30, and the outputs of the two column amplifiers are digitized by independent 11-bit ADCs. The dynamic ranges of the signal processing channels of the two column amplifiers are 64dB (high gain) and 74dB (low gain), respectively, but the dynamic range of their combined result is 92dB, and there is only 1.2e-RMS (Root Mean Square) noise. Among them, 1.2e-RMS noise refers to the noise level measured on the image sensor, e represents electrons, RMS represents root mean square, and 1.2e-RMS means that on average, the noise on each pixel is the root mean square value of the readout noise of 1.2 electrons.

[0006] The principle of the above pixel structures is to make the capacitor larger so that it can hold more electrons, thus making the image sensor have a high dynamic range. However, due to the limitation of small pixels, the capacitor cannot be infinitely large. The larger the capacitor, the larger the area it occupies, which makes it difficult to implement on mobile electronic devices. Therefore, the dynamic range that can be achieved by the above pixel structures is limited, and the maximum can reach about 120dB.

[0007] Based on this, without the need to design new pixels, multiple exposures of the image sensor have become one of the effective methods to make the image sensor have a high dynamic range. However, the method of making the image sensor have a high dynamic range by multiple exposures of the image sensor requires exposing the image sensor at different times, which is prone to motion artifacts, especially in fast-moving scenes such as car imaging, resulting in poor imaging quality.

[0008] It can be seen from this that by using the currently common method of increasing the capacitance in the image sensor or exposing the image sensor multiple times, while ensuring the imaging quality, the growth of the dynamic range of the image sensor is limited, and it is difficult for the image sensor to have an ultra-high dynamic range. Summary of the invention

[0009] The purpose of the embodiments of the present application is to provide a pixel circuit, an image sensor, a camera module and an electronic device, which can achieve an ultra-large full well capacity and low noise of the image sensor without expanding the capacitance and without affecting the imaging quality, thereby greatly increasing the dynamic range of the image sensor, so that the image sensor has an ultra-high dynamic range.

[0010] In the first aspect, an embodiment of the present application provides a pixel circuit, including: a dual capacitor circuit, including a photodiode, a first capacitor and a second capacitor, the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor, and the first capacitor and the second capacitor are used to receive and store electrons overflowing from the photodiode; an electron clearing circuit, connected to the first capacitor, and the electron clearing circuit is used to clear the electrons in the first capacitor when the voltage value of the first capacitor is less than a first threshold value; an inverting circuit, connected to both the dual capacitor circuit and the electron clearing circuit, and the inverting circuit is used to invert the output signal of the electron clearing circuit and control the on and off of the electron transmission path between the photodiode and the first capacitor.

[0011] In a second aspect, an embodiment of the present application provides an image sensor, comprising: a pixel array, comprising at least one pixel circuit of the first aspect; a first driving circuit, connected to the pixel array, the first driving circuit being used to output a high-level signal or a low-level signal to the pixel circuit in the pixel array; a readout circuit, connected to the pixel array, the readout circuit being used to read and process the output signal of the pixel circuit in the pixel array.

[0012] In a third aspect, an embodiment of the present application provides a camera module, comprising: the image sensor of the second aspect.

[0013] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: the camera module of the third aspect.

[0014] The pixel circuit provided in the embodiment of the present application includes a dual capacitor circuit, an electron clearing circuit and an inverting circuit. Among them, the dual capacitor circuit includes a photodiode, a first capacitor and a second capacitor, the electron clearing circuit is connected to the first capacitor, and the inverting circuit is connected to both the dual capacitor circuit and the electron clearing circuit. Further, the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor, the first capacitor and the second capacitor are used to receive and store the electrons overflowing from the photodiode, the electron clearing circuit is used to clear the electrons in the first capacitor when the voltage value of the first capacitor is less than the first threshold value, and the inverting circuit is used to invert the output signal of the electron clearing circuit and control the on-off of the electron transmission path between the photodiode and the first capacitor. Through the above-mentioned pixel circuit, a first capacitor with a large capacity but poor noise performance and a second capacitor with a small capacity but good noise performance are used to receive and store the electrons overflowed by the exposure of the photodiode, and based on the voltage value of the first capacitor and the set first threshold value, the electrons in the large capacitor, i.e., the first capacitor, are quantitatively cleared. In this way, there is no need to expand the capacitance of the capacitor, and the full well capacity of the pixel itself is no longer a limiting factor. By combining the large and small capacitors to output, the image sensor can have an ultra-large full well capacity and low noise, thereby enabling the image sensor to have a high dynamic range. Moreover, by quantitatively clearing the electrons in the large capacitor, the dynamic range of the image sensor can be further increased on the basis of the high dynamic range, thereby enabling the image sensor to have an ultra-high dynamic range without affecting the imaging quality of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of a pixel circuit provided in some embodiments of the present application;

[0016] Figure 2 A schematic diagram of the structure of a pixel circuit provided in some embodiments of the present application;

[0017] Figure 3 A schematic diagram of the structure of a pixel circuit provided in some embodiments of the present application;

[0018] Figure 4 A schematic diagram of the structure of a pixel circuit provided in some embodiments of the present application;

[0019] Figure 5 A working principle diagram of an electronic clearing circuit provided for some embodiments of the present application;

[0020] Figure 6 An operation timing diagram of a pixel circuit provided for some embodiments of the present application;

[0021] Figure 7 A schematic diagram of the structure of an image sensor provided in some embodiments of the present application;

[0022] Figure 8A structural block diagram of a camera module provided for some embodiments of the present application;

[0023] Fig. 9 A structural block diagram of an electronic device provided for some embodiments of the present application.

[0024] Description of reference numerals:

[0025] 100-pixel circuit, 102-dual capacitor circuit, 104-photodiode, 106-first capacitor, 108-second capacitor, 110-electronic clearing circuit, 112-inverting circuit, 114-first transistor, 116-second transistor, 118-first power supply, 120-third transistor, 122-fourth transistor, 124-second power supply, 126-fifth transistor, 128-sixth transistor, 130-third power supply, 132-first resistor, 134-amplifier, 136-fourth power supply, 1 38-second resistor, 140-third capacitor, 142-counter, 144-seventh transistor, 146-eighth transistor, 148-fifth power supply, 200-image sensor, 202-pixel array, 204-first drive circuit, 206-readout circuit, 208-timing waveform generator, 210-phase-locked loop, 212-second drive circuit, 214-serial interface, 216-gain amplifier, 218-analog-to-digital converter, 220-peripheral circuit, 300-camera module, 400-electronic device. DETAILED DESCRIPTION

[0026] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0027] The features of the terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0028] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0029] Combine the following Figure 1-Figure 9 The pixel circuit, image sensor, camera module and electronic device according to the embodiments of the present application are described in detail.

[0030] like Figure 1 As shown, an embodiment of the present application provides a pixel circuit 100 , wherein the pixel circuit 100 includes a dual-capacitor circuit 102 , an electron clearing circuit 110 , and an inverting circuit 112 .

[0031] Furthermore, the dual-capacitor circuit 102 includes a photodiode 104 , a first capacitor 106 , and a second capacitor 108 .

[0032] Further, the electronic clearing circuit 110 is connected to the first capacitor 106 .

[0033] Furthermore, the inverting circuit 112 is connected to both the dual-capacitance circuit 102 and the electron clearing circuit 110 .

[0034] Further, the capacitance value of the first capacitor 106 is greater than the capacitance value of the second capacitor 108. Specifically, the capacitance value of the first capacitor 106 is large, but the noise performance is poor, and the capacitance value of the second capacitor 108 is small, but the noise performance is good.

[0035] Furthermore, the photodiode 104 is used to sense light signals and convert the light signals into electrical signals. The photodiode 104 generates electrons during the exposure process, and the first capacitor 106 and the second capacitor 108 are used to receive and store the electrons overflowing from the photodiode 104 .

[0036] Specifically, in the dual capacitor circuit 102, when the electrons generated by the exposure of the photodiode 104 overflow, the electrons overflowing from the photodiode 104 will be transferred to the first capacitor 106 and the second capacitor 108 for storage. Based on this, compared with the existing pixel structure, the pixel circuit 100 of the present application retains the small capacitor with high conversion gain, namely the second capacitor 108, and adds a large-capacity first capacitor 106. Through the joint output of the first capacitor 106 and the second capacitor 108, the full well capacity of the pixel itself is no longer a limiting factor, and an ultra-large full well capacity and low noise can be achieved at the same time. The dynamic range of the image sensor in which the pixel circuit 100 is located will be greatly increased, so that the image sensor has a high dynamic range.

[0037] It is understandable that as the electrons are transferred to the first capacitor 106 and the second capacitor 108, the voltage values ​​of the first capacitor 106 and the second capacitor 108 will decrease, and when the voltage value of the first capacitor 106 is less than the first threshold value, the electron clearing circuit 110 will clear the electrons in the first capacitor 106. In this way, the full well capacity of the image sensor can be further expanded without increasing the capacitance, thereby further increasing the dynamic range of the image sensor on the basis of the high dynamic range, so that the image sensor has an ultra-high dynamic range.

[0038] For example, the first capacitor 106 and the second capacitor 108 can achieve 400k electron storage by themselves, and the readout noise of the image sensor is about 1e-. Based on this, the image sensor has a high dynamic range of 110dB. On this basis, the electron clearing circuit 110 is added to quantitatively clear the electrons in the first capacitor 106. If the number of bits of the counter for counting the number of electron clearing times of the first capacitor 106 is 8 bits, the first capacitor 106 and the second capacitor 108 can achieve 76800k electrons on the receiving photodiode 104. At this time, the image sensor can have an ultra-high dynamic range of 157dB, which is far beyond the dynamic range of the human eye.

[0039] Furthermore, the inverting circuit 112 is used to invert the output signal of the electron clearing circuit 110 and control the on / off of the electron transmission path from the photodiode 104 to the first capacitor 106 , that is, to control whether the electrons overflowing from the photodiode 104 are transmitted to the first capacitor 106 .

[0040] In actual application, the first capacitor 106 and the second capacitor 108 may use a thin gate oxide material to increase the density of the first capacitor 106 and the second capacitor 108 , thereby further increasing the dynamic range of the image sensor.

[0041] According to the pixel circuit 100 of the embodiment of the present application, it includes a dual capacitor circuit 102, an electron clearing circuit 110 and an inverting circuit 112. Among them, the dual capacitor circuit 102 includes a photodiode 104, a first capacitor 106 and a second capacitor 108, the electron clearing circuit 110 is connected to the first capacitor 106, and the inverting circuit 112 is connected to both the dual capacitor circuit 102 and the electron clearing circuit 110. Further, the capacitance value of the first capacitor 106 is greater than the capacitance value of the second capacitor 108, the first capacitor 106 and the second capacitor 108 are used to receive and store the electrons overflowing from the photodiode 104, the electron clearing circuit 110 is used to clear the electrons in the first capacitor 106 when the voltage value of the first capacitor 106 is less than the first threshold value, and the inverting circuit 112 is used to invert the output signal of the electron clearing circuit 110, and control the on-off of the electron transmission path from the photodiode 104 to the first capacitor 106. Through the above pixel circuit 100, the first capacitor 106 with large capacity but poor noise performance and the second capacitor 108 with small capacity but good noise performance are used to receive and store the electrons overflowed by the exposure of the photodiode 104, and the electrons in the large capacitor, i.e., the first capacitor 106, are quantitatively cleared based on the voltage value of the first capacitor 106 and the set first threshold. In this way, there is no need to expand the capacitance, and the full well capacity of the pixel itself is no longer a limiting factor. By combining the large and small capacitors for output, the ultra-large full well capacity and low noise of the image sensor can be achieved, so that the image sensor has a high dynamic range. Moreover, by quantitatively clearing the electrons in the large capacitor, the dynamic range of the image sensor can be further increased on the basis of the high dynamic range, so that the image sensor has an ultra-high dynamic range without affecting the imaging quality of the image sensor.

[0042] According to some embodiments of the present application, optionally, Figure 1 As shown, the dual-capacitor circuit 102 further includes a first transistor 114 , a second transistor 116 , a third transistor 120 , a fourth transistor 122 , and a fifth transistor 126 .

[0043] Among them, the first end of the first transistor 114 is connected to the cathode of the photodiode 104, the anode of the photodiode 104 is grounded, the second end of the first transistor 114 is connected to the first end of the third transistor 120, and the control end of the first transistor 114 is used to receive the first control signal TX1, and the first control signal TX1 is used to control the on and off of the first transistor 114.

[0044] Further, the first transistor 114 is used to control whether the electrons overflowing from the photodiode 104 are transmitted to the second capacitor 108. Specifically, when the first control signal TX1 is a high-level signal, the first control signal TX1 is used to control the first transistor 114 to turn on, so as to conduct the photodiode 104 and the second capacitor 108, so that the electrons overflowing from the photodiode 104 can be transmitted to the second capacitor 108 for storage; when the first control signal TX1 is a low-level signal, the first control signal TX1 is used to control the first transistor 114 to turn off, so as to prohibit the electrons in the photodiode 104 from being transmitted to the second capacitor 108.

[0045] Furthermore, the first end of the second transistor 116 is connected to the first end of the first capacitor 106, the second end of the first capacitor 106 is grounded, the second end of the second transistor 116 is connected to the first power supply 118, and the control end of the second transistor 116 is used to receive a second control signal RST, and the second control signal RST is used to control the on and off of the second transistor 116.

[0046] Further, the first power supply 118 is used to clear the residual electrons in the first capacitor 106, and the second transistor 116 is used to control whether the first power supply 118 clears the residual electrons in the first capacitor 106. Specifically, when the second control signal RST is a high-level signal, the second control signal RST is used to control the second transistor 116 to turn on, and at this time, the first power supply 118 can clear the residual electrons in the first capacitor 106; when the second control signal RST is a low-level signal, the second control signal RST is used to control the second transistor 116 to turn off, and at this time, the first power supply 118 does not clear the residual electrons in the first capacitor 106.

[0047] Furthermore, the second end of the third transistor 120 is connected to the first end of the second transistor 116 and the first end of the first capacitor 106 , and the control end of the third transistor 120 is used to receive a third control signal TX2 , and the third control signal TX2 is used to control the on and off of the third transistor 120 .

[0048] Further, the third transistor 120 is used to control the on / off of the path between the first capacitor 106 and the second capacitor 108. Specifically, when the third control signal TX2 is a high-level signal, the third control signal TX2 is used to control the third transistor 120 to turn on, so as to conduct the first capacitor 106 and the second capacitor 108 through the third transistor 120; when the third control signal TX2 is a low-level signal, the third control signal TX2 is used to control the third transistor 120 to turn off, so as to disconnect the first capacitor 106 and the second capacitor 108.

[0049] Furthermore, when the second transistor 116 is turned on, if the third transistor 120 is turned on, the first power supply 118 is also used to clear the residual electrons in the second capacitor 108 , and if the first transistor 114 is also turned on, the first power supply 118 is also used to clear the residual electrons in the photodiode 104 .

[0050] Furthermore, the first end of the fourth transistor 122 is connected to the second end of the fifth transistor 126, the second end of the fourth transistor 122 is connected to the second power supply 124, the control end of the fourth transistor 122 is connected to the first end of the second capacitor 108, and the second end of the second capacitor 108 is grounded.

[0051] Furthermore, the second power supply 124 is used to provide a high level for the fourth transistor 122 so that the fourth transistor 122 is always in an on state, and the fourth transistor 122 is used to transmit the capacitor signal to the fifth transistor 126 for output.

[0052] Furthermore, the first end of the fifth transistor 126 is used to output a signal, and the dual-capacitor circuit 102 can output a high-gain or low-gain signal to the outside through the fifth transistor 126 .

[0053] Furthermore, the control terminal of the fifth transistor 126 is used to receive a fourth control signal SEL, and the fourth control signal SEL is used to control the on-off of the fifth transistor 126 .

[0054] Specifically, when the fourth control signal SEL is a high-level signal, the fourth control signal SEL is used to control the fifth transistor 126 to turn on, so as to output the signal of the dual-capacitor circuit 102 to the outside through the fifth transistor 126. When the fourth control signal SEL is a low-level signal, the fourth control signal SEL is used to control the fifth transistor 126 to turn off.

[0055] According to the pixel circuit 100 of the embodiment of the present application, the dual-capacitor circuit 102 further includes a first transistor 114, a second transistor 116, a third transistor 120, a fourth transistor 122, and a fifth transistor 126. Among them, the first end of the first transistor 114 is connected to the cathode of the photodiode 104, the control end of the first transistor 114 is used to receive a first control signal, the first control signal is used to control the on and off of the first transistor 114, and the anode of the photodiode 104 is grounded; the first end of the second transistor 116 is connected to the first end of the first capacitor 106, the second end of the second transistor 116 is connected to the first power supply 118, the control end of the second transistor 116 is used to receive a second control signal, the second control signal is used to control the on and off of the second transistor 116, and the second end of the first capacitor 106 is grounded; the first end of the third transistor 120 is connected to the second end of the first transistor 114, the control end of the third transistor 120 is used to receive a second control signal, the second control signal is used to control the on and off of the second transistor 116, and the second end of the first capacitor 106 is grounded; The second end of the transistor 120 is connected to the first end of the second transistor 116, and the control end of the third transistor 120 is used to receive a third control signal, and the third control signal is used to control the on and off of the third transistor 120; the second end of the fourth transistor 122 is connected to the second power supply 124, and the control end of the fourth transistor 122 is connected to the first end of the second capacitor 108, and the second end of the second capacitor 108 is grounded; the first end of the fifth transistor 126 is connected to the readout circuit, the second end of the fifth transistor 126 is connected to the first end of the fourth transistor 122, and the control end of the fifth transistor 126 is used to receive a fourth control signal, and the fourth control signal is used to control the on and off of the fifth transistor 126. In this way, by controlling each transistor in the dual-capacitor circuit 102 to turn on or off, the electrons of the dual-capacitor storage photodiode 104 can be controlled, and the amount of electrons contained in the capacitor is increased, thereby increasing the full well capacity of the image sensor and improving the dynamic range of the image sensor.

[0056] According to some embodiments of the present application, optionally, Figure 1 As shown, the pixel circuit 100 further includes a sixth transistor 128 .

[0057] Among them, the first end of the sixth transistor 128 is connected to the first end of the first capacitor 106 and the input end of the electronic clearing circuit 110, the second end of the sixth transistor 128 is connected to the third power supply 130, and the control end of the sixth transistor 128 is connected to the output end of the electronic clearing circuit 110.

[0058] Furthermore, the third power supply 130 is used to clear the electrons in the first capacitor 106 , and the sixth transistor 128 is used to control whether the third power supply 130 clears the electrons in the first capacitor 106 .

[0059] It is understandable that after the first capacitor 106 receives the electrons transmitted by the photodiode 104, the voltage value of the first capacitor 106 will decrease. The electron clearing circuit 110 is specifically used to: when the voltage value of the first capacitor 106 is less than the first threshold value, control the sixth transistor 128 to turn on, so as to clear the electrons in the first capacitor 106 through the third power supply 130. On this basis, in the process of clearing the electrons in the first capacitor 106, after the first capacitor 106 releases the electrons, the voltage value of the first capacitor 106 will increase. The electron clearing circuit 110 is also specifically used to: when the voltage value of the first capacitor 106 is greater than the second threshold value, control the sixth transistor 128 to turn off, so as to stop clearing the electrons in the first capacitor 106.

[0060] Among them, the specific value of the second threshold can be set by those skilled in the art according to actual conditions. For example, the second threshold can be 2.8V, which is not specifically limited here.

[0061] Furthermore, the first threshold is smaller than the second threshold. A person skilled in the art may set the specific value of the first threshold according to actual conditions. For example, the first threshold may be 1.4V, 1V, or 0.8V, etc., and no specific limitation is given here.

[0062] The pixel circuit 100 according to the embodiment of the present application further includes a sixth transistor 128. The first end of the sixth transistor 128 is connected to the first end of the first capacitor 106 and the electron clearing circuit 110, the second end of the sixth transistor 128 is connected to the third power supply 130, and the control end of the sixth transistor 128 is connected to the electron clearing circuit 110; wherein the electron clearing circuit 110 is specifically used to: when the voltage value of the first capacitor 106 is less than the first threshold value, control the sixth transistor 128 to turn on, so as to clear the electrons in the first capacitor 106 through the third power supply 130; when the voltage value of the first capacitor 106 is greater than the second threshold value, control the sixth transistor 128 to turn off. In this way, based on the set first threshold value and the second threshold value, the electrons in the first capacitor 106 are quantitatively cleared, and the amount of electrons contained in the first capacitor 106 can be increased without expanding the capacitance of the first capacitor 106, further increasing the full well capacity of the pixel, so that the dynamic range of the image sensor can be further increased on the basis of the high dynamic range of the image sensor, so that the image sensor has an ultra-high dynamic range.

[0063] According to some embodiments of the present application, optionally, Figure 1 and Figure 2 As shown, the electronic clearing circuit 110 includes a first resistor 132 , an amplifier 134 , and a second resistor 138 .

[0064] Among them, the first end of the amplifier 134 is connected to the fourth power supply 136, the second end of the amplifier 134 is grounded, the third end of the amplifier 134, i.e. the positive input end, is connected to the first resistor 132, the fourth end of the amplifier 134, i.e. the negative input end, is connected to the first end of the first capacitor 106, and the output end of the amplifier 134 is connected to the control end of the sixth transistor 128 and the input end of the inverting circuit 112.

[0065] Furthermore, a first end of the second resistor 138 is connected between the first resistor 132 and the amplifier 134 , and a second end of the second resistor 138 is connected to an output end of the amplifier 134 .

[0066] Furthermore, the first resistor 132 is used to calibrate the bias current of the amplifier 134 to reduce the influence of noise on the amplifier 134 .

[0067] Furthermore, the second resistor 138 is a feedback resistor for setting a closed-loop dynamic range of the amplifier 134 . The selection of the feedback resistor will affect the gain and stability of the amplifier 134 .

[0068] Furthermore, the fourth power supply 136 is used to provide a stable operating voltage for the amplifier 134 .

[0069] Furthermore, the amplifier 134 is used to output a high-level signal to control the sixth transistor 128 to turn on when the voltage value of the first capacitor 106 is less than the first threshold, and to output a low-level signal to control the sixth transistor 128 to turn off when the voltage value of the first capacitor 106 is greater than the second threshold.

[0070] It can be understood that after the first capacitor 106 receives the electrons transmitted by the photodiode 104, the voltage value of the first capacitor 106 will decrease, and the input voltage of the fourth terminal of the amplifier 134 will also decrease. In the case where the voltage value of the first capacitor 106 is less than the first threshold value, that is, when the input voltage of the fourth terminal of the amplifier 134 is less than the first threshold value, the amplifier 134 will output a high-level signal to control the sixth transistor 128 to turn on, so as to clear the electrons in the first capacitor 106 through the third power supply 130. On this basis, in the process of clearing the electrons in the first capacitor 106, after the first capacitor 106 releases the electrons, the voltage value of the first capacitor 106 will increase, and the input voltage of the fourth terminal of the amplifier 134 will also increase. In the case where the voltage value of the first capacitor 106 is greater than the second threshold value, that is, when the input voltage of the fourth terminal of the amplifier 134 is greater than the second threshold value, the amplifier 134 will output a low-level signal to control the sixth transistor 128 to turn off, so as to stop clearing the electrons in the first capacitor 106.

[0071] That is, the working principle of the electronic clearing circuit 110 provided in the embodiment of the present application can be specifically as follows: Figure 5Specifically, in the process that the first capacitor 106 receives the electrons of the photodiode 104, the input voltage Vin of the fourth terminal of the amplifier 134 is Figure 5 From right to left, that is, the input voltage Vin of the fourth terminal of the amplifier 134 changes from large to small, the input voltage Vin of the fourth terminal of the amplifier 134 decreases, and when the input voltage Vin of the fourth terminal of the amplifier 134 is less than the first threshold value Vth1, it is triggered instantly, and the output voltage Vout of the amplifier 134 jumps from the low level Vol to the high level Voh, the sixth transistor 128 is turned on, and the third power supply 130 starts to empty the electrons in the first capacitor 106. On this basis, in the process of emptying the electrons in the first capacitor 106, the input voltage Vin of the fourth terminal of the amplifier 134 changes according to Figure 5 It changes from left to right, that is, the input voltage Vin of the fourth terminal of the amplifier 134 changes from small to large, and the input voltage Vin of the fourth terminal of the amplifier 134 increases. When the input voltage Vin of the fourth terminal of the amplifier 134 is greater than the second threshold value Vth2, it is triggered instantly, and the output voltage Vout of the amplifier 134 jumps from the high level Voh to the low level Vol, and the sixth transistor 128 is turned off.

[0072] The high level Voh is the power voltage of the fourth power supply 136 , and the low level Vol is the ground voltage GND.

[0073] Furthermore, the relationship between Vth1, Vth2 and the reference voltage Vref at the third terminal, ie, the non-inverting input terminal, of the amplifier 134 is:

[0074]

[0075] R1 represents the resistance of the first resistor 132 , and Rfb represents the resistance of the second resistor 138 .

[0076] By combining the above equations (1) and (2), the reference voltage Vref at the third terminal, ie, the non-inverting input terminal, of the amplifier 134 and the resistance R1 of the first resistor 132 can be calculated.

[0077] According to the pixel circuit 100 of the embodiment of the present application, the electronic clearing circuit 110 includes a first resistor 132, an amplifier 134 and a second resistor 138. Among them, the first end of the amplifier 134 is connected to the fourth power supply 136, the second end of the amplifier 134 is grounded, the third end of the amplifier 134 is connected to the first resistor 132, the fourth end of the amplifier 134 is connected to the first end of the first capacitor 106, and the output end of the amplifier 134 is connected to the control end of the sixth transistor 128; the second resistor 138 is connected to the third end and the output end of the amplifier 134. Further, the amplifier 134 is used to output a high level signal when the voltage value of the first capacitor 106 is less than the first threshold value to control the sixth transistor 128 to turn on, and output a low level signal when the voltage value of the first capacitor 106 is greater than the second threshold value to control the sixth transistor 128 to turn off. In this way, the electron clearing circuit 110 outputs a high-level signal or a low-level signal based on the set first threshold and the second threshold, and can quantitatively clear the electrons in the first capacitor 106, thereby increasing the amount of electrons accommodated in the first capacitor 106 without expanding the capacitance of the first capacitor 106, further increasing the full well capacity of the pixel, and being able to further increase the dynamic range of the image sensor on the basis of the high dynamic range of the image sensor, so that the image sensor has an ultra-high dynamic range.

[0078] According to some embodiments of the present application, optionally, Figure 3 As shown, the pixel circuit 100 further includes a third capacitor 140 .

[0079] The first end of the third capacitor 140 is connected to the output end of the electronic clearing circuit 110 , and the second end of the third capacitor 140 is grounded.

[0080] Furthermore, the charge and discharge time of the third capacitor 140 is the same as that of the first capacitor 106. Thus, by converting the charge of the third capacitor 140, the number of electron emptying times of the first capacitor 106 can be calculated according to the charging time of the third capacitor 140.

[0081] The counting principle of the third capacitor 140 is as follows: Assuming that a power source charges the third capacitor 140 through a resistor with a resistance value of R, if the capacitance value of the third capacitor 140 is C, the initial voltage value of the third capacitor 140 is V0, the voltage value of the third capacitor 140 after being fully charged is Vu, and the voltage value of the third capacitor 140 at time t is Vt, the following calculation formula can be obtained: Vt = V0 + (Vu-V0) × (1-e -t / RCBased on this, the charging time t of the third capacitor 140 can be calculated according to the voltage value of the third capacitor 140, and the charging time of the first capacitor 106 is the same as the charging time of the third capacitor 140. Then, the charging times of the first capacitor 106 can be calculated according to the charging time of the third capacitor 140, thereby obtaining the number of electron emptying times of the first capacitor 106.

[0082] The pixel circuit 100 according to the embodiment of the present application further includes a third capacitor 140. The first end of the third capacitor 140 is connected to the output end of the electron clearing circuit 110, and the second end of the third capacitor 140 is grounded. Further, the charging and discharging time of the third capacitor 140 is the same as the charging and discharging time of the first capacitor 106. In this way, it is convenient to calculate the number of electron clearing times of the first capacitor 106 by the charging time of the third capacitor 140, so as to quickly calculate the total amount of electrons generated by the photodiode 104 based on the number of electron clearing times, thereby improving the operating speed of the image sensor and improving the frame rate of the image sensor imaging.

[0083] According to some embodiments of the present application, optionally, Figure 4 As shown, the pixel circuit 100 further includes a counter 142 .

[0084] The counter 142 is connected to the output end of the electronic clearing circuit 110 .

[0085] Furthermore, the counter 142 is used to count the number of times the electrons of the first capacitor 106 are emptied.

[0086] According to the pixel circuit 100 of the embodiment of the present application, the pixel circuit 100 further includes a counter 142. The counter 142 is connected to the output end of the electron clearing circuit 110, and the counter 142 is used to count the number of electron clearing times of the first capacitor 106. In this way, the number of electron clearing times of the first capacitor 106 is counted by the counter 142, so as to quickly calculate the total amount of electrons generated by the photodiode 104 based on the number of electron clearing times, thereby improving the operating speed of the image sensor and improving the frame rate of the image sensor imaging.

[0087] According to some embodiments of the present application, optionally, Figure 1 As shown, the inverter circuit 112 includes a seventh transistor 144 and an eighth transistor 146 .

[0088] The first end of the seventh transistor 144 is grounded, the second end of the seventh transistor 144 is connected to the control end of the third transistor 120 , and the control end of the seventh transistor 144 is connected to the output end of the electron clearing circuit 110 .

[0089] Further, a first end of the eighth transistor 146 is connected to the fifth power supply 148 , a second end of the eighth transistor 146 is connected to the control end of the third transistor 120 , and the control end of the eighth transistor 146 is connected to the output end of the electronic clearing circuit 110 .

[0090] Furthermore, the seventh transistor 144 and the eighth transistor 146 are used to control the flow of current and voltage in the inverter circuit 112, and utilize their own amplification characteristics and inversion characteristics to amplify the input signal and output it in reverse, thereby making the phase difference between the input signal and the output signal 180°.

[0091] Furthermore, the inverting circuit 112 is specifically used to: output a low level signal to control the third transistor 120 to be turned off when the electronic clearing circuit 110 outputs a high level signal; and output a high level signal to control the third transistor 120 to be turned on when the electronic clearing circuit 110 outputs a low level signal.

[0092] According to the pixel circuit 100 of the embodiment of the present application, the inverter circuit 112 includes a seventh transistor 144 and an eighth transistor 146. The first end of the seventh transistor 144 is grounded, the second end of the seventh transistor 144 is connected to the control end of the third transistor 120, and the control end of the seventh transistor 144 is connected to the output end of the electronic clearing circuit 110; the first end of the eighth transistor 146 is connected to the fifth power supply 148, the second end of the eighth transistor 146 is connected to the control end of the third transistor 120, and the control end of the eighth transistor 146 is connected to the output end of the electronic clearing circuit 110. Further, the inverter circuit 112 is used to output a low level signal to control the third transistor 120 to turn off when the electronic clearing circuit 110 outputs a high level signal, and output a high level signal to control the third transistor 120 to turn on when the electronic clearing circuit 110 outputs a low level signal. In this way, the third transistor 120 is controlled to be turned on or off through the inverting circuit 112, thereby controlling the on and off of the electron transmission path from the photodiode 104 to the first capacitor 106, and the electrons of the dual-capacitor storage photodiode 104 can be controlled, thereby increasing the amount of electrons that the capacitor can accommodate, increasing the full well capacity of the image sensor, and improving the dynamic range of the image sensor.

[0093] In summary, compared with the high dynamic range method of multiple exposures, the pixel circuit 100 provided in the embodiment of the present application can make the image sensor have a high dynamic range through a single exposure, can minimize motion artifacts, and has a better linear response.

[0094] Further, compared with the pixel structure of double gain, the pixel circuit 100 provided in the embodiment of the present application does not need to be large in capacitance. Through the dual-capacitor pixel structure of the first capacitor 106 and the second capacitor 108, the image sensor can have a high dynamic range of more than 100dB, and a two-layer design can be adopted to make the image sensor have a high dynamic range of 120dB. On this basis, with the electronic clearing circuit 110 and the counter 142, the electrons of the first capacitor 106 are quantitatively cleared, so that the first capacitor 106 can receive more electrons from the photodiode 104. The counter 142 with a bit number of 8 bits can realize the reception of 76800k electrons on the photodiode 104. In this way, the magnitude of the number of electrons received by the first capacitor 106 is improved, which is conducive to the reception of electrons in high light and high brightness scenes, and the image sensor can have an ultra-high dynamic range such as 156dB, while the second capacitor 108 has a large conversion gain, good noise performance, and good signal-to-noise ratio performance in low light scenes.

[0095] According to some embodiments of the present application, optionally, Figure 7 As shown, the embodiment of the present application further provides an image sensor 200 , wherein the image sensor 200 includes a pixel array 202 , a first driving circuit 204 , and a readout circuit 206 .

[0096] The pixel array 202 includes at least one pixel circuit 100 in any of the above embodiments.

[0097] Furthermore, the first driving circuit 204 is connected to the pixel array 202 , and is used to output a high level signal or a low level signal to the pixel circuit 100 in the pixel array 202 , so as to control each transistor in the pixel circuit 100 to turn on or off.

[0098] Furthermore, the readout circuit 206 is connected to the pixel array 202 , and the readout circuit 206 is used to read and process the output signals of the pixel circuits 100 in the pixel array 202 .

[0099] The image sensor 200 provided in the embodiment of the present application includes the pixel circuit 100 in any of the above embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0100] In actual application, those skilled in the art may set the number of pixel circuits 100 in the pixel array 202 according to actual conditions. For example, the pixel array 202 may include 4096×3072 pixel circuits 100, and no specific limitation is made here.

[0101] Furthermore, the number of the readout circuits 206 may be two, and the two readout circuits 206 may be located at the top and the bottom of the pixel array 202 respectively.

[0102] According to some embodiments of the present application, optionally, Figure 7 As shown, the image sensor 200 further includes a timing waveform generator 208 , a phase-locked loop 210 , a second driving circuit 212 , a serial interface 214 and some peripheral circuits 220 .

[0103] The timing waveform generator 208 is connected to the first driving circuit 204 , and the timing waveform generator 208 is used to generate a timing control signal, and the first driving circuit 204 is used to convert the timing control signal into a high level signal or a low level signal.

[0104] Furthermore, the phase-locked loop 210 is connected to the timing waveform generator 208 , and the phase-locked loop 210 can automatically track the frequency of the input signal and generate an oscillation signal with the same frequency as the input signal. The phase-locked loop 210 is synchronized with the frequency and phase of the external signal and the internal signal of the image sensor 200 .

[0105] Furthermore, the second driving circuit 212 is connected to the pixel array 202. The second driving circuit 212 has the same circuit structure as the first driving circuit 204, and the second driving circuit 212 and the first driving circuit 204 are respectively disposed on both sides of the pixel array 202.

[0106] Furthermore, the serial interface 214 is connected to the second driving circuit 212 , and the image sensor 200 can be configured to different sensor working modes through the serial interface 214 .

[0107] According to some embodiments of the present application, optionally, Figure 7 As shown, readout circuit 206 includes a gain amplifier 216 and an analog-to-digital converter 218 .

[0108] The gain amplifier 216 is connected to the pixel array 202 , and the analog-to-digital converter 218 is connected to the gain amplifier 216 .

[0109] Furthermore, the gain amplifier 216 is used to amplify the output signal of the pixel circuit 100 in the pixel array 202, and the analog-to-digital converter 218 is used to perform analog-to-digital conversion on the amplified output signal to convert the output signal into a digital signal.

[0110] According to some embodiments of the present application, optionally, during the operation of the image sensor 200, at a first moment, the first driving circuit 204 is used to output a high-level first control signal TX1, a second control signal RST and a third control signal TX2 to the pixel circuit 100 to control the first transistor 114, the second transistor 116 and the third transistor 120 in the pixel circuit 100 to turn on.

[0111] At the second moment, the first driving circuit 204 is used to output the low-level first TX1, the second control signal RST and the high-level fourth control signal SEL to the pixel circuit 100, so as to control the first transistor 114 and the second transistor 116 in the pixel circuit 100 to be turned off, and control the fifth transistor 126 in the pixel circuit 100 to be turned on. At the second moment, the readout circuit 206 is used to read the first signal output by the pixel circuit 100, which includes the first noise signal of the first capacitor 106 and the second noise signal of the second capacitor 108 in the pixel circuit 100.

[0112] At the third moment, the first driving circuit 204 is used to output a low-level third control signal TX2 to the pixel circuit 100 to control the third transistor 120 in the pixel circuit 100 to turn off. At the third moment, the readout circuit 206 is used to read the second signal output by the pixel circuit 100, and the second signal only includes the second noise signal.

[0113] At the fourth moment, the first driving circuit 204 is used to output a high level first control signal TX1 to the pixel circuit 100 to control the first transistor 114 in the pixel circuit 100 to turn on. At the fourth moment, the readout circuit 206 is used to read the third signal output by the pixel circuit 100, the third signal including the second capacitance signal of the second capacitor 108.

[0114] At the fifth moment, the first driving circuit 204 is used to output a high-level third control signal TX2 to the pixel circuit 100 to control the third transistor 120 in the pixel circuit 100 to turn on. At the fifth moment, the readout circuit 206 is used to read a fourth signal output by the pixel circuit 100, the fourth signal including the first capacitance signal of the first capacitor 106 and the second capacitance signal of the second capacitor 108.

[0115] On this basis, the readout circuit 206 is also used to: determine a first electron quantity based on the first signal and the fourth signal, the first electron quantity being the total amount of electrons remaining in the first capacitor 106 and the second capacitor 108; determine a second electron quantity based on the second signal and the third signal, the second electron quantity being the total amount of electrons remaining in the second capacitor 108; read the number of electron clearing times of the pixel circuit 100, and determine a third electron quantity based on the number of electron clearing times, the first threshold, the second threshold and the first electron quantity, the third electron quantity being the total amount of electrons generated by the photodiode 104 in the pixel circuit 100.

[0116] In summary, if Figure 6 As shown, the working timing of the pixel circuit 100 in the image sensor 200 may specifically include time T1 to time T11.

[0117] Among them, at the first moment T1, before the photodiode 104 in the pixel circuit 100 starts to be exposed, the first driving circuit controls the first transistor 114 to turn on through the first control signal TX1, controls the second transistor 116 to turn on through the second control signal RST, and controls the third transistor 120 to turn on through the third control signal TX2. At this time, the first capacitor 106 (the area on the right side of the dotted line) and the second capacitor 108 (the area on the left side of the dotted line) are turned on, and the first power supply 118 connected by the second transistor 116 clears the residual electrons in the photodiode 104, the first capacitor 106, and the second capacitor 108. Among them, the voltage value of the first capacitor 106 is the power supply voltage of the first power supply 118.

[0118] At the second moment T2, after the residual electrons in the photodiode 104, the first capacitor 106 (the area on the right side of the dotted line) and the second capacitor 108 (the area on the left side of the dotted line) are emptied, the first drive circuit controls the first transistor 114 to turn off through the first control signal TX1, and controls the second transistor 116 to turn off through the second control signal RST, and the third transistor 120 remains on to connect the first capacitor 106 and the second capacitor 108. Further, the fourth transistor 122 is always in the on state, and the first drive circuit controls the fifth transistor 126 to turn on through the fourth control signal SEL to perform the first signal sampling. At this time, the sampling signal is the first signal, and the first signal includes the first noise signal of the first capacitor 106 and the second noise signal of the second capacitor 108. The first signal passes through the fourth transistor 122 and the fifth transistor 126 and is output to the readout circuit 206.

[0119] At time T3, the photodiode 104 begins to expose and accumulate electrons. At this time, the first transistor 114 remains off, the third transistor 120 remains on, and the first capacitor 106 (the area on the right side of the dotted line) and the second capacitor 108 (the area on the left side of the dotted line) are turned on.

[0120] At time T4, when the electrons in the photodiode 104 are fully accumulated, the first transistor 114 and the third transistor 120 are both turned on, and the electrons in the photodiode 104 overflow to the first capacitor 106 (the area on the right side of the dotted line) and the second capacitor 108 (the area on the left side of the dotted line) for storage. At this time, the voltage value of the first capacitor 106 begins to decrease.

[0121] At time T5, when the voltage value of the first capacitor 106 drops to the set first threshold, the electron clearing circuit 110 is triggered. At this time, the electron clearing circuit 110 outputs a high-level signal, triggering the sixth transistor 128 to turn on. At the same time, the high-level signal output by the electron clearing circuit 110 is converted into a low-level signal through the inverting circuit 112, triggering the third transistor 120 to turn off, so as to disconnect the first capacitor 106 and the second capacitor 108. After the sixth transistor 128 is turned on and the third transistor 120 is turned off, the electrons in the first capacitor 106 are cleared through the third power supply 130, and the electrons in the photodiode 104 no longer overflow to the first capacitor 106.

[0122] At time T6, the electrons in the first capacitor 106 are emptied, and the voltage value of the first capacitor 106 rises. When the voltage value of the first capacitor 106 rises to the set second threshold value, the electron clearing circuit 110 is triggered. At this time, the electron clearing circuit 110 outputs a low-level signal, triggering the sixth transistor 128 to turn off. At the same time, the low-level signal output by the electron clearing circuit 110 is converted into a high-level signal through the inverting circuit 112, triggering the third transistor 120 to turn on, so as to turn on the first capacitor 106 and the second capacitor 108.

[0123] At time T7, the photodiode 104 continues to be exposed, the first transistor 114 and the third transistor 120 are both turned on, and the electrons overflowing from the photodiode 104 continue to flow into the first capacitor 106 (the area on the right side of the dotted line) and the second capacitor 108 (the area on the left side of the dotted line) for storage.

[0124] At time T8, the steps of time T4, time T5, time T6 and time T7 are repeated until the exposure is finished or there is no more electron overflow in the photodiode 104, and the number of times the electrons of the first capacitor 106 are cleared is recorded.

[0125] At time T9, i.e., the third time, the first driving circuit controls the third transistor 120 to be turned off through the third control signal TX2 to disconnect the first capacitor 106 and the second capacitor 108. The fourth transistor 122 and the fifth transistor 126 are in the on state, and the second signal sampling is performed. At this time, the sampling signal is the second signal, and the second signal is the second noise signal of the second capacitor 108. The second signal passes through the fourth transistor 122 and the fifth transistor 126 and is output to the readout circuit 206.

[0126] At time T10, i.e., the fourth time, the first driving circuit controls the first transistor 114 to turn on through the first control signal TX1, the third transistor 120 remains turned off, the first capacitor 106 and the second capacitor 108 are disconnected, and the electrons in the photodiode 104 (the area on the left side of the dotted line) flow into the second capacitor 108, and the third signal sampling begins. At this time, the sampling signal is a high-gain third signal. The third signal includes the second capacitor signal of the second capacitor 108 and the second noise signal. The third signal passes through the fourth transistor 122 and the fifth transistor 126 and is output to the readout circuit 206.

[0127] At time T11, i.e., the fifth time, the first driving circuit controls the third transistor 120 to turn on through the third control signal TX2, and the electrons in the photodiode 104 (the area on the left side of the dotted line) flow into the first capacitor 106, and the fourth signal sampling starts. At this time, the sampling signal is a low-gain fourth signal. The fourth signal includes the first capacitance signal of the first capacitor 106, the first noise signal, and the second capacitance signal and the second noise signal of the second capacitor 108. The fourth signal passes through the fourth transistor 122 and the fifth transistor 126 and is output to the readout circuit 206, so as to sense the charges on the first capacitor 106 and the second capacitor 108 through the fourth signal.

[0128] It should be noted that, for shooting scenes with low brightness, since the electrons in the photodiode 104 will not overflow, the pixel circuit 100 will not pass through the above-mentioned T4, T5, T6, T7 and T8. At this time, the pixel circuit 100 is read out similarly to a common pixel structure, and CDS (Correlated Double Sampling) is completed by reading the reset level of the second capacitor 108 at T2.

[0129] On this basis, the readout circuit 206 can calculate the combined voltage value of the first capacitor 106 and the second capacitor 108 according to the difference between the fourth signal and the first signal, thereby calculating the total amount of electrons remaining in the first capacitor 106 and the second capacitor 108. Further, the readout circuit 206 can also calculate the voltage value of the second capacitor 108 according to the difference between the third signal and the second signal, thereby calculating the amount of electrons remaining in the second capacitor 108.

[0130] Exemplarily, the first noise signal of the first capacitor 106 is N1, the second noise signal of the second capacitor 108 is N2, the first capacitance signal of the first capacitor 106 is V1, and the second capacitance signal of the second capacitor 108 is V2. At this time, the first signal obtained by the first sampling is (N1+N2), the second signal obtained by the second sampling is N2, the third signal obtained by the third sampling is (V2+N2), and the fourth signal obtained by the fourth sampling is (V1+V2+N1+N2). On this basis, according to the difference between the fourth signal and the first signal, the combined voltage value (V1+V2) of the first capacitor 106 and the second capacitor 108 can be calculated, and according to the difference between the third signal and the second signal, the voltage value V2 of the second capacitor 108 can be calculated.

[0131] On this basis, the readout circuit 206 can calculate the target voltage value according to the counted number of electron clearing times of the first capacitor 106 , the difference between the second threshold and the first threshold, and the combined voltage value of the first capacitor 106 and the second capacitor 108 .

[0132] In actual application, the above target voltage value can be calculated by the following formula (3):

[0133] S=S2+K×Vth (3)

[0134] Wherein, S represents the target voltage value, S2 represents the combined voltage value of the first capacitor 106 and the second capacitor 108, K represents the number of electron clearing times, and Vth represents the difference between the second threshold value and the first threshold value.

[0135] Exemplarily, the combined voltage value S2 of the first capacitor 106 and the second capacitor 108 is 10V, the number of electron clearing times is 5 times, the first threshold is 1.8V, the second threshold is 2.8V, and the target voltage value S=10+5×(2.8-1.8)=15V is calculated.

[0136] Exemplarily, the combined voltage value S2 of the first capacitor 106 and the second capacitor 108 is 8V, the number of electron clearing times is 3 times, the first threshold is 0.8V, the second threshold is 2.8V, and the target voltage value S is calculated to be 8+3×(2.8-0.8)=14V.

[0137] Furthermore, the difference between the second threshold and the first threshold is used to indicate the amount of electrons emptied from the first capacitor 106 each time, the combined voltage value of the first capacitor 106 and the second capacitor 108 is used to indicate the total amount of electrons remaining in the first capacitor 106 and the second capacitor 108, and the target voltage value is used to indicate the total amount of electrons generated by the photodiode 104. By converting the target voltage value into electrical quantity, the total amount of electrons generated by the photodiode 104 can be quickly calculated, thereby improving the operating speed of the image sensor 200 and improving the frame rate of imaging of the image sensor 200.

[0138] It is understandable that in the related art, for pixel structures with high dynamic range, single-exposure pixel structures are more popular because they can minimize motion artifacts and have better linear response, which can achieve a dynamic range of more than 120dB. Currently, single-exposure pixel structures can be divided into two categories: dual photodiode and multiple pixel gain.

[0139] For the single-exposure pixel structure of the dual-photodiode type, the pixel structure uses two fixed photodiodes with a sensitivity ratio of 6.5:1. The two sensing nodes are connected by a transistor switch. When the sensing node is activated, the conversion gain decreases due to the joint capacitance of the sensing node. At this time, one photodiode uses a low conversion gain for readout, and the other photodiode can use two conversion gains for readout at the same time. Based on the above three-way readout, combined with ADC and digital peripherals, the dynamic range can exceed 120dB and the readout noise is 0.94e-RMS.

[0140] For the single-exposure pixel structure of the multiple pixel gain type, in this pixel structure, the capacitance of other nodes is added to the capacitance of the sensing node using transistors to reduce the conversion gain. In this pixel structure, two signal measurements are performed using low conversion gain and high conversion gain, which can achieve a dynamic range of 87dB and 2.0e-RMS noise. Based on the triple gain scheme of the above pixel structure, the dynamic range can be increased to 91dB, while the combination of double gain and double exposure can increase the dynamic range to 120dB.

[0141] It can be seen that the above-mentioned single-exposure pixel structure has a high dynamic range. However, the above-mentioned single-exposure pixel structure has a slow response time, poor power consumption, and is prone to temporal noise and spatial noise.

[0142] Therefore, the pixel circuit 100 in the image sensor 200 provided in the embodiment of the present application uses a dual capacitor to store the electrons generated by the exposure of the photodiode 104 based on the process of electron overflow of the photodiode 104, quantitatively clears the electrons in the large capacitor, i.e., the first capacitor 106, and records the number of electron clearing times of the first capacitor 106, and then according to the number of electron clearing times and the total amount of electrons remaining in the dual capacitor, the total amount of electrons generated by the photodiode 104 can be quickly calculated. In this way, the structure and operation principle of the pixel circuit 100 provided in the embodiment of the present application are relatively simple, the dynamic range of the image sensor 200 is increased from the circuit aspect, and the total amount of electrons generated by the photodiode 104 is quickly calculated according to the number of electron clearing times and the total amount of electrons remaining in the dual capacitor, the circuit operates quickly, and a high frame rate image can be output.

[0143] For example, assuming that the photodiode 104 generates a total of 1000k electrons, the electrons overflow from the photodiode 104 to the first capacitor 106 and the second capacitor 108, and the electrons overflowing to the first capacitor 106 are emptied multiple times, assuming that 300k electrons are emptied each time, and the number of empties is recorded as 3 times, the number of electrons remaining in the first capacitor 106 and the second capacitor 108 is 100k. At this time, by reading the number of electrons remaining in the first capacitor 106 and the second capacitor 108, which is 100k, and the number of empties is 3, the total amount of electrons generated by the photodiode 104 can be quickly calculated as: (100k+3×300k)=1000k.

[0144] For example, assuming that the photodiode 104 generates a total of 500k electrons, the electrons overflow from the photodiode 104 to the first capacitor 106 and the second capacitor 108, and the electrons overflowing to the first capacitor 106 are emptied multiple times, assuming that 300k electrons are emptied each time, and the number of empties is recorded as 1, and finally the number of electrons remaining in the first capacitor 106 and the second capacitor 108 is 200k. At this time, by reading the number of electrons remaining in the first capacitor 106 and the second capacitor 108, 200k, and the number of empties is 1, the total amount of electrons generated by the photodiode 104 can be quickly calculated as: (200k+1×300k)=500k.

[0145] According to some embodiments of the present application, optionally, Figure 8 As shown, the embodiment of the present application further provides a camera module 300. The camera module 300 includes an image sensor 200. The camera module 300 provided in the embodiment of the present application includes an image sensor 200 and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0146] According to some embodiments of the present application, optionally, Fig. 9 As shown, the embodiment of the present application further provides an electronic device 400. The electronic device 400 includes a camera module 300. The electronic device 400 provided in the embodiment of the present application includes a camera module 300 and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0147] It should be noted that the electronic device 400 in the embodiment of the present application includes a mobile electronic device and a non-mobile electronic device.

[0148] In the actual application process, the electronic device 400 can be a terminal or other devices other than a terminal. For example, the electronic device 400 can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiments of the present application.

[0149] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0150] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A pixel circuit, characterized in that: include: A dual-capacitor circuit, comprising a photodiode, a first capacitor and a second capacitor, wherein the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor, and the first capacitor and the second capacitor are used to receive and store electrons overflowed from the photodiode; an electron clearing circuit connected to the first capacitor, the electron clearing circuit being used to clear electrons in the first capacitor when a voltage value of the first capacitor is less than a first threshold value; An inverting circuit is connected to both the dual-capacitor circuit and the electron clearing circuit, and is used to invert the output signal of the electron clearing circuit and control the on-off of the electron transmission path between the photodiode and the first capacitor.

2. The pixel circuit according to claim 1, characterized in that: The dual capacitor circuit also includes: a first transistor, wherein a first end of the first transistor is connected to a cathode of the photodiode, a control end of the first transistor is used to receive a first control signal, the first control signal is used to control the on and off of the first transistor, and an anode of the photodiode is grounded; a second transistor, wherein a first end of the second transistor is connected to a first end of the first capacitor, a second end of the second transistor is connected to a first power supply, a control end of the second transistor is used to receive a second control signal, the second control signal is used to control the on and off of the second transistor, and a second end of the first capacitor is grounded; a third transistor, wherein a first end of the third transistor is connected to a second end of the first transistor, a second end of the third transistor is connected to a first end of the second transistor, and a control end of the third transistor is used to receive a third control signal, and the third control signal is used to control the on and off of the third transistor; a fourth transistor, wherein a second end of the fourth transistor is connected to a second power supply, a control end of the fourth transistor is connected to a first end of the second capacitor, and a second end of the second capacitor is grounded; A fifth transistor, wherein the first end of the fifth transistor is used to output a signal, the second end of the fifth transistor is connected to the first end of the fourth transistor, and the control end of the fifth transistor is used to receive a fourth control signal, and the fourth control signal is used to control the on and off of the fifth transistor.

3. The pixel circuit according to claim 2, characterized in that: Also includes: a sixth transistor, wherein a first end of the sixth transistor is connected to the first end of the first capacitor and the electronic clearing circuit, a second end of the sixth transistor is connected to a third power supply, and a control end of the sixth transistor is connected to the electronic clearing circuit; The electron clearing circuit is specifically used to: when the voltage value of the first capacitor is less than the first threshold, control the sixth transistor to turn on so as to clear the electrons in the first capacitor through the third power supply; when the voltage value of the first capacitor is greater than the second threshold, control the sixth transistor to turn off.

4. The pixel circuit according to claim 3, characterized in that: The electronic clearing circuit comprises: a first resistor; an amplifier, wherein a first terminal of the amplifier is connected to a fourth power supply, a second terminal of the amplifier is grounded, a third terminal of the amplifier is connected to the first resistor, a fourth terminal of the amplifier is connected to a first terminal of the first capacitor, and an output terminal of the amplifier is connected to a control terminal of the sixth transistor; a second resistor connected to the third terminal and the output terminal of the amplifier; In which, the amplifier is used to output a high-level signal to control the sixth transistor to turn on when the voltage value of the first capacitor is less than the first threshold, and to output a low-level signal to control the sixth transistor to turn off when the voltage value of the first capacitor is greater than the second threshold.

5. The pixel circuit according to claim 2, characterized in that: Also includes: a third capacitor, wherein a first end of the third capacitor is connected to the output end of the electronic clearing circuit, and a second end of the third capacitor is grounded; The charging and discharging time of the third capacitor is the same as the charging and discharging time of the first capacitor.

6. The pixel circuit according to claim 2, characterized in that: Also includes: A counter is connected to the output end of the electronic clearing circuit, and the counter is used to count the number of times the electronic clearing of the first capacitor occurs.

7. The pixel circuit according to any one of claims 2 to 6, characterized in that: The inverting circuit comprises: a seventh transistor, wherein a first terminal of the seventh transistor is grounded, a second terminal of the seventh transistor is connected to the control terminal of the third transistor, and the control terminal of the seventh transistor is connected to the output terminal of the electronic clearing circuit; an eighth transistor, wherein a first end of the eighth transistor is connected to a fifth power source, a second end of the eighth transistor is connected to a control end of the third transistor, and a control end of the eighth transistor is connected to an output end of the electronic clearing circuit; Wherein, the inverting circuit is used to output a low level signal to control the third transistor to turn off when the electronic clearing circuit outputs a high level signal, and to output a high level signal to control the third transistor to turn on when the electronic clearing circuit outputs a low level signal.

8. An image sensor, characterized in that: include: A pixel array comprising at least one pixel circuit according to any one of claims 1 to 7; A first driving circuit connected to the pixel array, the first driving circuit being used to output a high level signal or a low level signal to the pixel circuit in the pixel array; A readout circuit is connected to the pixel array, and is used to read and process output signals of the pixel circuits in the pixel array.

9. The image sensor according to claim 8, characterized in that: Also includes: A timing waveform generator connected to the first driving circuit, the timing waveform generator is used to generate a timing control signal, and the first driving circuit is used to convert the timing control signal into a high level signal or a low level signal; A phase-locked loop, connected to the timing waveform generator; A second driving circuit connected to the pixel array; A serial interface is connected to the second driving circuit.

10. The image sensor according to claim 8, characterized in that The readout circuit comprises: A gain amplifier connected to the pixel array; The analog-to-digital converter is connected to the gain amplifier.

11. The image sensor according to any one of claims 8 to 10, characterized in that: At a first moment, the first driving circuit is used to output a first control signal, a second control signal and a third control signal of high level to the pixel circuit; At the second moment, the first driving circuit is used to output a low-level first control signal, a second control signal and a high-level fourth control signal to the pixel circuit; the readout circuit is used to read a first signal output by the pixel circuit, wherein the first signal includes a first noise signal and a second noise signal; At a third moment, the first driving circuit is used to output a third control signal of a low level to the pixel circuit; the readout circuit is used to read a second signal output by the pixel circuit, wherein the second signal includes the second noise signal; At a fourth moment, the first driving circuit is used to output a high-level first control signal to the pixel circuit; the readout circuit is used to read a third signal output by the pixel circuit, wherein the third signal includes a second capacitance signal; At a fifth moment, the first driving circuit is used to output a third control signal of a high level to the pixel circuit; the readout circuit is used to read a fourth signal output by the pixel circuit, the fourth signal including the first capacitance signal and the second capacitance signal; The readout circuit is also used to: determine a first electron quantity based on the first signal and the fourth signal; determine a second electron quantity based on the second signal and the third signal; read the number of electron clearing times of the pixel circuit, and determine a third electron quantity based on the number of electron clearing times, a first threshold, a second threshold and the first electron quantity.

12. A camera module, characterized in that: include: An image sensor as claimed in any one of claims 8 to 11.

13. An electronic device, characterized in that: include: The camera module as claimed in claim 12.

Images