Semiconductor memory device, method for manufacturing the same, and electronic system including the same

Abstract

A semiconductor memory device includes: a peripheral circuit structure; and a cell structure including a cell substrate and a gate electrode, and on the peripheral circuit structure. The peripheral circuit structure includes: a peripheral circuit board including a first surface facing the cell structure and a second surface opposite to the first surface; a first circuit element on a first surface of the peripheral circuit board; a first wiring electrically connected to the first circuit element in the first interlayer insulating layer; a capacitor dielectric layer covering the second surface of the peripheral circuit board; a first capacitor electrode in the capacitor dielectric layer; a second capacitor electrode spaced apart from the first capacitor electrode in the capacitor dielectric layer; and a first connection via electrically connecting the first capacitor electrode with the first wiring by passing through the peripheral circuit board.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0123336 filed in the Korean Intellectual Property Office on September 15, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various example embodiments relate to a semiconductor memory device, a method for manufacturing the semiconductor memory device, and / or an electronic system including the semiconductor memory device. Background Art

[0004] Since electronic systems require or expect semiconductor memory devices capable of storing high-capacity data, methods capable of increasing the data storage capacity of semiconductor memory devices have been studied. As one of the methods capable of increasing the data storage capacity of semiconductor memory devices, a semiconductor memory device including three-dimensionally arranged memory cells rather than two-dimensionally arranged memory cells is proposed. Summary of the invention

[0005] Various example embodiments may provide a semiconductor memory device having a reduced size.

[0006] Alternatively or additionally, various example embodiments may provide an electronic system including a semiconductor memory device having a reduced size.

[0007] Alternatively or additionally, various example embodiments may provide a method for manufacturing a semiconductor memory device having a reduced size.

[0008] Example embodiments are not limited to those described above, and additional purposes of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0009] According to some example embodiments, a semiconductor memory device includes: a peripheral circuit structure; and a unit structure, on the peripheral circuit structure, and including a unit substrate and a gate electrode. The peripheral circuit structure includes: a peripheral circuit board, including a first surface facing the unit structure and a second surface opposite to the first surface; a first circuit element, on the first surface of the peripheral circuit board; a first interlayer insulating layer, covering the first surface of the peripheral circuit board; a first wiring, electrically connected to the first circuit element in the first interlayer insulating layer; a capacitor dielectric layer, covering the second surface of the peripheral circuit board; a first capacitor electrode, in the capacitor dielectric layer; a second capacitor electrode, spaced apart from the first capacitor electrode in the capacitor dielectric layer; and a first connecting via, electrically connecting the first capacitor electrode to the first wiring by passing through the peripheral circuit board.

[0010] Alternatively or additionally, according to some example embodiments, a semiconductor memory device includes: a first peripheral circuit structure; and a unit structure stacked on the first peripheral circuit structure and including a memory cell. The first peripheral circuit structure includes: a first peripheral circuit board including a first surface facing the unit structure and a second surface opposite to the first surface; a first circuit element on the first surface of the first peripheral circuit board; and a first capacitor on the second surface of the first peripheral circuit board.

[0011] Alternatively or additionally, according to some example embodiments, an electronic system includes: a mainboard; a semiconductor memory device on the mainboard and including a peripheral circuit structure and a unit structure, the unit structure being stacked on the peripheral circuit structure; and a controller electrically connected to the semiconductor memory device on the mainboard. The peripheral circuit structure includes: a peripheral circuit board including a first surface facing the unit structure and a second surface opposite to the first surface; a first circuit element on the first surface of the peripheral circuit board; and a capacitor configured to provide an operating voltage to the first circuit element on the second surface of the peripheral circuit board.

[0012] Alternatively or additionally, according to some example embodiments, a method for manufacturing a semiconductor memory device includes: forming a pre-peripheral circuit structure including a peripheral circuit board having a first surface and a second surface opposite to each other, a circuit element on the first surface of the peripheral circuit board, a connecting through-hole passing through a portion of the peripheral circuit board, and a first wiring electrically connected to the circuit element or the connecting through-hole; bonding the pre-peripheral circuit structure to a semiconductor chip; exposing a portion of the connecting through-hole by etching a portion of the second surface of the peripheral circuit board; and forming a capacitor electrically connected to the connecting through-hole on the second surface of the peripheral circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features will become more apparent by describing in detail various example embodiments with reference to the accompanying drawings, in which:

[0014] Figure 1 is an example block diagram illustrating a semiconductor memory device according to some example embodiments;

[0015] Figure 2 is an example circuit diagram illustrating a semiconductor memory device according to some example embodiments;

[0016] Figure 3 is a schematic perspective view illustrating a semiconductor memory device according to some example embodiments;

[0017] Figure 4 is a cross-sectional view illustrating a semiconductor memory device according to some example embodiments;

[0018] Figure 5 It shows Figure 4 A magnified view of region Q;

[0019] Figure 6 It shows Figure 4 An enlarged view of region S1;

[0020] Figure 7 It shows Figure 4 An enlarged view of region A;

[0021] Figures 8 to 10 is a diagram illustrating a capacitor electrode of a semiconductor memory device according to some example embodiments;

[0022] Fig.11 is a diagram illustrating a semiconductor memory device according to some example embodiments;

[0023] Fig.12 is a diagram illustrating a semiconductor memory device according to some example embodiments;

[0024] Fig.13 is a cross-sectional view illustrating a semiconductor memory device according to some example embodiments;

[0025] Fig.14 It shows Fig.13 An enlarged view of region S1;

[0026] Fig.15 is a cross-sectional view illustrating a semiconductor memory device according to some example embodiments;

[0027] Fig.16 It shows Fig.15 An enlarged view of region B;

[0028] Fig.17 It shows Fig.15 An enlarged view of region C;

[0029] Fig.18 It shows Fig.15 An enlarged view of region D;

[0030] Fig.19 is a schematic perspective view illustrating a semiconductor memory device according to some example embodiments;

[0031] Figure 20 to Figure 22 are diagrams showing intermediate steps describing a method for manufacturing a semiconductor memory device according to some example embodiments;

[0032] Fig.23 is an exemplary block diagram illustrating an electronic system according to some example embodiments;

[0033] Fig.24is an exemplary perspective view showing an electronic system according to some example embodiments;

[0034] Fig.25 is along Fig.24 A schematic cross-sectional view taken along line II of ; and

[0035] Figure 26 to Figure 28 is a diagram illustrating a semiconductor memory device according to some example embodiments. DETAILED DESCRIPTION

[0036] Figure 1 is an exemplary block diagram illustrating a semiconductor memory device according to some example embodiments.

[0037] Reference Figure 1 , a semiconductor memory device 10 according to some example embodiments includes a memory cell array 20 and a peripheral circuit 30 .

[0038] The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells, such as but not limited to one or more of a main cell, a dummy cell, and a redundant cell. The memory cell array 20 may be connected to the peripheral circuit 30 through a bit line BL, a word line WL, at least one string selection line SSL, and at least one ground selection line GSL. Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through the word line WL, the string selection line SSL, and the ground selection line GSL. In addition, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit line BL.

[0039] The peripheral circuit 30 may receive one or more of an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor memory device 10, and may transmit data DATA to and / or receive data DATA from an external device of the semiconductor memory device 10. The peripheral circuit 30 may include a control logic 37, a row decoder 33, and a page buffer 35. Although not shown, the peripheral circuit 30 may also include various sub-circuits such as one or more of an input / output circuit, a voltage generating circuit for generating various voltages required or used for the operation of the semiconductor memory device 10, and an error correction circuit for correcting errors of the data DATA read from the memory cell array 20.

[0040] The control logic 37 may be connected to the row decoder 33, the input / output circuit, and the voltage generating circuit. The control logic 37 may control the overall operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals used in the semiconductor memory device 10 in response to the control signal CTRL. For example, when performing a storage operation (such as a program operation and / or an erase operation), the control logic 37 may adjust the voltage level supplied to the word line WL and / or the bit line BL.

[0041] The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and may select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected memory cell block BLK1 to BLKn. In addition, the row decoder 33 may transmit a voltage for performing a storage operation to the word line WL of the selected memory cell block BLK1 to BLKn.

[0042] The page buffer 35 may be connected to the memory cell array 20 through the bit line BL. The page buffer 35 may operate as a write driver and / or as a sense amplifier. Specifically, when a program operation is performed, the page buffer 35 may operate as a write driver to apply a voltage to the bit line BL according to the data DATA to be stored in the memory cell array 20. At the same time, when a read operation is performed, the page buffer 35 may operate as a sense amplifier to read out the data DATA stored in the memory cell array 20.

[0043] Figure 2 is an example circuit diagram illustrating a semiconductor memory device according to some example embodiments.

[0044] Reference Figure 2 , a memory cell array (e.g., Figure 1 20) includes a common source line CSL, a plurality of bit lines BL and a plurality of cell strings CSTR.

[0045] A plurality of bit lines BL may be two-dimensionally arranged on a plane including a first direction X and a second direction Y. For example, the bit lines BL may extend along the second direction Y and may be arranged spaced apart from each other along the first direction X. A plurality of cell strings CSTR may be respectively connected to the corresponding bit lines BL in parallel. The cell strings CSTR may be commonly connected to a common source line CSL. For example, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

[0046] Each of the cell strings CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Each of the memory cell transistors MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

[0047] The common source line CSL may be commonly connected to the source of the ground selection transistor GST. In addition, the ground selection line GSL, the plurality of word lines WL11 to WL1n and WL21 to WL2n, and the string selection line SSL may be disposed between the common source line CSL and the bit line BL. Here, "n" describing the number of word lines may be the same as that of the reference Figure 1 The "n" describing the number of blocks may be the same or different. The ground selection line GSL may be used as a gate electrode of the ground selection transistor GST, the word lines WL11 to WL1n and WL21 to WL2n may be used as gate electrodes of the memory cell transistors MCT, and the string selection line SSL may be used as a gate electrode of the string selection transistor SST.

[0048] Figure 3 is a schematic perspective view illustrating a semiconductor memory device according to some example embodiments. Figure 4 is a cross-sectional view illustrating a semiconductor memory device according to some example embodiments. Figure 5 It shows Figure 4 A magnified view of region Q. Figure 6 It shows Figure 4 An enlarged view of area S1. Figure 7 It shows Figure 4 Magnified view of area A.

[0049] Reference Figure 3 and Figure 4 , a semiconductor memory device according to some example embodiments may include a peripheral circuit structure PERI and a first unit structure CELL1. The peripheral circuit structure PERI and the first unit structure CELL1 are stacked in a third direction Z. The first unit structure CELL1 is disposed above the peripheral circuit structure PERI. Hereinafter, an upper portion, an upper surface, a lower portion, and a lower surface of the first unit structure CELL1 are defined based on the opposite direction of the third direction Z, and an upper portion, an upper surface, a lower portion, and a lower surface of the peripheral circuit structure PERI are defined based on the third direction Z.

[0050] The semiconductor memory device according to some example embodiments may have a chip-to-chip (C2C) structure. The C2C structure may mean that an upper chip including a first unit structure CELL1 is manufactured on a first wafer (e.g., a first unit substrate 310), a lower chip including a peripheral circuit structure PERI is manufactured on a second wafer different from the first wafer (e.g., a peripheral circuit board 210 or a peripheral circuit structure), and then the upper chip and the lower chip are connected to each other by a bonding method. In some example embodiments, either or both of the first wafer and the second wafer may be cut and singulated before bonding, for example, by wafer-to-wafer (W2W), chip-to-wafer (D2W), or chip-to-chip (D2D) bonding, or may not be cut and singulated; example embodiments are not limited thereto.

[0051] For example, the bonding method may refer to a method of electrically connecting the first bonding metal 270a, 270b and 270c formed on the uppermost metal layer of the lower chip to the first bonding metal 370a, 370b and 370c formed on the uppermost metal layer of the upper chip. For example, when the first bonding metal 270a, 270b and 270c and the first bonding metal 370a, 370b and 370c are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is only an example, and the first bonding metal 270a, 270b and 270c and the first bonding metal 370a, 370b and 370c may be formed of various other metals, such as aluminum (Al) and / or tungsten (W).

[0052] Each of the peripheral circuit structure PERI and the first unit structure CELL may include a bit line bonding area BLBA, a word line bonding area WLBA and an external pad bonding area PA. The word line bonding area WLBA may be defined around the bit line bonding area BLBA. For example, the word line bonding area WLBA may surround the bit line bonding area BLBA. The external pad bonding area PA may be defined outside the word line bonding area WLBA. For example, in a plan view, the external pad bonding area PA may surround the word line bonding area WLBA.

[0053] The peripheral circuit structure PERI includes a peripheral circuit board 210, a plurality of first capacitor electrodes 201a, 202a, 203a, 204a and 205a, a plurality of second capacitor electrodes 201b, 202b, 203b, 204b and 205b, a capacitor dielectric layer 206, a first insulating film 207, a first input / output pad 208, a first input / output contact plug 212, a connecting via 214, a first interlayer insulating layer 215, a plurality of circuit elements 220a, 220b and 220c, a first wiring 230a, 230b and 230c, a second wiring 240a, 240b and 240c, and a first bonding metal 270a, 270b and 270c.

[0054] The peripheral circuit board 210 may include a first surface 210a and a second surface 210b opposite to each other. The first surface 210a may be referred to as a front side, and the second surface 210b may be referred to as a rear side; example embodiments are not limited thereto. The first surface 210a may face the first unit structure CELL1.

[0055] The circuit elements 220a, 220b, and 220c are disposed on the first surface 210a of the peripheral circuit board 210. The circuit elements 220a, 220b, and 220c may constitute or be included in a peripheral circuit (eg, Figure 1 For example, circuit elements 220a, 220b, and 220c may include control logic (e.g., Figure 1 37), a row decoder (e.g., Figure 1 33) and page buffers (e.g., Figure 1 of 35).

[0056] The circuit elements 220a, 220b, and 220c may include, for example, transistors, but are not limited thereto. For example, the circuit elements 220a, 220b, and 220c may also include various passive elements (such as resistors and / or inductors) and various active elements (such as transistors and / or diodes). In addition, although Figure 1 It is illustrated that the circuit elements 220 a , 220 b , and 220 c extend along the second direction Y; however, example embodiments are not limited thereto.

[0057] The first interlayer insulating layer 215 may be disposed on the first surface 210a of the peripheral circuit board 210 to cover the circuit elements 220a, 220b, and 220c. The first wiring 230a, 230b, and 230c and the second wiring 240a, 240b, and 240c may be disposed in the first interlayer insulating layer 215. The first wiring 230a, 230b, and 230c and the second wiring 240a, 240b, and 240c may be sequentially disposed on the circuit elements 220a, 220b, and 220c. The circuit elements 220a, 220b, and 220c may be electrically connected to the first wiring 230a, 230b, and 230c and the second wiring 240a, 240b, and 240c. The first interlayer insulating layer 215 may be composed of a plurality of insulating layers. The number and / or arrangement of the first wirings 230 a , 230 b , and 230 c and the second wirings 240 a , 240 b , and 240 c shown are merely examples and are not limited thereto.

[0058] The first interlayer insulating layer 215 may include, for example, an insulating material such as silicon oxide and / or silicon nitride. The first wirings 230a, 230b, and 230c and the second wirings 240a, 240b, and 240c may include the same or different conductive materials, for example, one or more of tungsten, aluminum, copper, and the like.

[0059] Reference Figure 4 and Figure 5 , the capacitors C1, C2, C3, C4, and C5 are disposed on the second surface 210b of the peripheral circuit board 210. The capacitors C1, C2, C3, C4, and C5 may be disposed on the entire second surface 210b of the peripheral circuit board 210. The capacitors C1, C2, C3, C4, and C5 may overlap or at least partially overlap with at least a portion of the circuit elements 220a, 220b, and 220c in the third direction Z.

[0060] The first capacitor electrodes 201a, 202a, 203a, 204a and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b and 205b may be spaced apart from each other in a direction (e.g., a first direction X and / or a second direction Y) horizontal to the second surface 210b of the peripheral circuit board 210. The first capacitor electrodes 201a, 202a, 203a, 204a and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b and 205b adjacent to each other and the capacitor dielectric layer 206 therebetween may constitute or be included in or correspond to the capacitors C1, C2, C3, C4 and C5, for example, corresponding to the plates of the capacitors C1, C2, C3, C4 and C5.

[0061] Specifically, the capacitor dielectric layer 206 is disposed on the second surface 210b of the peripheral circuit board 210. The first capacitor electrodes 201a, 202a, 203a, 204a and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b and 205b are disposed in the capacitor dielectric layer 206. The capacitor dielectric layer 206 covers the first capacitor electrodes 201a, 202a, 203a, 204a and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b and 205b. The first capacitor electrodes 201a, 202a, 203a, 204a and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b and 205b are not exposed by the capacitor dielectric layer 206.

[0062] Different voltages may be applied to the first capacitor electrodes 201a, 202a, 203a, 204a, and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b, and 205b. For example, the first capacitor electrodes 201a, 202a, 203a, 204a, and 205a may be electrically connected to the connection through-holes 214 passing through the peripheral circuit board 210. The connection through-holes 214 may receive a voltage from, for example, the third input / output pad 309 through the first wirings 230a, 230b, and 230c, the second wirings 240a, 240b, and 240c, and the third input / output contact plugs 314. In some example embodiments, the second capacitor electrodes 201b, 202b, 203b, 204b, and 205b may not be directly electrically connected to any connection through-holes passing through the peripheral circuit board 210.

[0063] For example, the first capacitor electrodes 201a, 202a, 203a, 204a and 205a may include the (1-1)th electrodes to the (1-5)th electrodes 201a, 202a, 203a, 204a and 205a sequentially stacked in the opposite direction of the third direction Z, and the second capacitor electrodes 201b, 202b, 203b, 204b and 205b may include the (2-1)th electrodes to the (2-5)th electrodes 201b, 202b, 203b, 204b and 205b sequentially stacked in the opposite direction of the third direction Z. Each of the (1-1)th to (1-5)th electrodes 201a, 202a, 203a, 204a, and 205a and each of the (2-1)th to (2-5)th electrodes 201b, 202b, 203b, 204b, and 205b and the capacitor dielectric layer 206 therebetween may constitute the first to fifth capacitors C1, C2, C3, C4, and C5. At least some of the capacitances of the first to fifth capacitors C1, C2, C3, C4, and C5 may be different from each other. For example, the capacitances of the first to fifth capacitors C1, C2, C3, C4, and C5 may be arranged in an arithmetic progression or a geometric progression; example embodiments are not limited thereto.

[0064] The capacitor dielectric layer 260 may include a plurality of layers. The number and / or arrangement of the first capacitor electrodes 201a, 202a, 203a, 204a, and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b, and 205b shown are examples only and are not limited thereto.

[0065] The capacitor dielectric layer 260 may include an insulating material, and may include, for example, silicon oxide and / or silicon nitride. Alternatively or additionally, the capacitor dielectric layer 260 may include a high-k material (e.g., aluminum oxide (Al2O3)) with a dielectric constant higher than that of silicon oxide. 2 O 3 ), hafnium oxide (HfO 2 )).

[0066] The first capacitor electrodes 201a, 202a, 203a, 204a and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b and 205b may include a conductive material. Each of the first capacitor electrodes 201a, 202a, 203a, 204a and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b and 205b may independently or simultaneously include at least one of tungsten, aluminum or copper.

[0067] The capacitors C1, C2, C3, C4, and C5 may be electrically connected to at least one of the circuit elements 220a, 220b, and 220c through the connecting vias 214, the first wirings 230a, 230b, and 230c, and the second wirings 240a, 240b, and 240c. The capacitors C1, C2, C3, C4, and C5 may provide an operating voltage to at least one of the circuit elements 220a, 220b, and 220c through the connecting vias 214, the first wirings 230a, 230b, and 230c, and the second wirings 240a, 240b, and 240c.

[0068] Return to reference Figure 4 , a first insulating film 207 may be disposed on the capacitor dielectric layer 206. The first insulating film 207 may cover the capacitor dielectric layer 206. A first input / output pad 208 may be disposed on the first insulating film 207. The first input / output pad 208 may be electrically connected to at least one circuit element 220a through a first input / output contact plug 212.

[0069] The first unit structure CELL1 may include a first unit substrate 310, a plurality of gate electrodes 331 to 338; 330, a second interlayer insulating layer 315, a channel structure CH, a plurality of gate contact plugs 340 including gate contact plugs 341 to 347, a source layer 320, a first wiring 350a, 350b and 350c, a second wiring 360a, 360b and 360c, a first bonding metal 370a, 370b and 370c, a second insulating film 307, second and third input / output pads 308 and 309, and second and third input / output contact plugs 312 and 314.

[0070] The peripheral circuit board 210 and the first unit substrate 310 may be or include, for example, one or more of a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, or be included therein.

[0071] A memory cell array including a plurality of memory cells ( Figure 1 20) may be disposed on the bit line bonding area BLBA of the first cell structure CELL1. In some example embodiments, the memory cells included in the first cell structure CELL1 may be nonvolatile memory cells.

[0072] For example, the channel structure CH, the gate electrode 330, and the bit line 360c may be disposed on the first unit substrate 310 of the bit line bonding area BLBA. In the following description, the surface of the first unit substrate 310 on which the memory cell array is disposed may be referred to as the front side. In contrast, the surface of the first unit substrate 310 opposite to the front side of the first unit substrate 310 may be referred to as the back side of the first unit substrate 310. The gate electrode 330 may be disposed on the front side of the first unit substrate 310. The gate electrode 330 may have a layered structure extending parallel to the front side of the first unit substrate 310. The gate electrodes 330 may be sequentially stacked on the first unit substrate 310 by being separated from each other by the second interlayer insulating layer 315. The gate electrodes 330 may be stacked in a stepped manner in the word line bonding area WLBA of the first unit structure CELL1.

[0073] For example, the gate electrode 331 may be provided as a ground selection line ( Figure 2 The gate electrode 338 may be set as a string selection line ( Figure 2 SSL), and the gate electrodes 332 to 337 may be set as word lines ( Figure 2 WL11 to WL1n and WL21 to WL2n).

[0074] Each of the gate electrodes 330 may include a conductive material, for example, one or more of a metal such as tungsten (W), cobalt (Co), and nickel (Ni) or a semiconductor material such as silicon, but is not limited thereto.

[0075] The second interlayer insulating layer 315 may be disposed on the front side of the first unit substrate 310 to cover the gate electrode 330. The second interlayer insulating layer 315 may be composed of a plurality of insulating layers. The second interlayer insulating layer 315 may include, for example, at least one of silicon oxide, silicon oxynitride, or a low-k material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0076] The channel structure CH may be disposed on the first unit substrate 310 of the bit line bonding area BLBA. The channel structure CH may extend along the third direction Z to pass through the gate electrode 330. For example, the channel structure CH may have a columnar shape (eg, cylindrical) extending along the third direction Z. Thus, the channel structure CH may intersect the gate electrode 330.

[0077] In some example embodiments, the channel structures CH may be arranged in a zigzag shape. For example, the channel structures CH may be arranged to alternate with each other in the first direction X and the second direction Y. In some example embodiments, the channel structures CH may be arranged in a honeycomb shape.

[0078] Reference Figure 6 , the channel structure CH may include a semiconductor pattern 130 and an information storage layer 132 .

[0079] The semiconductor pattern 130 may extend along the third direction Z to pass through the gate electrode 330. Although the semiconductor pattern 130 is shown as having only a cup shape, this is only an example, and the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a quadrangular barrel shape, and a filled column shape. The semiconductor pattern 130 may include, for example, a semiconductor material such as single crystal silicon (such as doped or undoped single crystal silicon), polycrystalline silicon (such as doped or undoped polycrystalline silicon), an organic semiconductor material, and a carbon nanostructure, but is not limited thereto.

[0080] The information storage layer 132 may be interposed between the semiconductor pattern 130 and each gate electrode 330. For example, the information storage layer 132 may extend along the outer side of the semiconductor pattern 130. In some example embodiments, the information storage layer 132 may be formed of multiple layers. For example, the information storage layer 132 may include a tunnel insulating layer 132a, a charge storage layer 132b, and a blocking insulating layer 132c, which are sequentially stacked on the outer side of the semiconductor pattern 130.

[0081] Each of the tunnel insulating layer 132a and the blocking insulating layer 132c may include, for example, silicon oxide and / or a high-k material having a dielectric constant higher than that of silicon oxide (eg, aluminum oxide (Al 2 O 3 ) and / or hafnium oxide (HfO 2 )). The charge storage layer 132b may include, for example, silicon nitride.

[0082] In some example embodiments, the channel structure CH may further include a filling pattern 134. For example, the channel structure CH may be provided with a channel hole extending in the third direction Z to pass through the gate electrode 330. The information storage layer 132, the semiconductor pattern 130, and the filling pattern 134 may be sequentially stacked in the channel hole. Each of the information storage layer 132 and the semiconductor pattern 130 may extend to conform along the contour of the channel hole. The filling pattern 134 may fill the area of ​​the channel hole remaining after being filled with the information storage layer 132 and the semiconductor pattern 130.

[0083] In some example embodiments, the channel structure CH may further include a channel pad. The channel pad may be electrically connected to an upper portion of the semiconductor pattern 130.

[0084] In some example embodiments, the source layer 320 may be interposed between the first unit substrate 310 and the gate electrode 330. For example, the source layer 320 may extend to conform along the front side of the first unit substrate 310. In some example embodiments, the source layer 320 may be formed on the bit line bonding area BLBA and the word line bonding area WLBA, and may not be formed on the external pad bonding area PA.

[0085] The source layer 320 may be connected to the semiconductor pattern 130 of each channel structure CH. For example, the source layer 320 may contact the side of the semiconductor pattern 130 by passing through the information storage layer 132. The source layer 320 may be provided as a common source line (eg, Figure 2 The source layer 320 may include, for example, metal and / or polysilicon doped with impurities, but is not limited thereto.

[0086] In some example embodiments, a support layer 322 may be disposed on the source layer 320. The support layer 322 may be interposed between the first unit substrate 310 and the source layer 320.

[0087] Reference Figure 7 , in some example embodiments, as shown in A1, the channel structure CH may not include a bent portion. In some example embodiments, as shown in A2, the channel structure CH may include a bent portion. For example, the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. At the boundary between the lower channel LCH and the upper channel UCH, the width of the lower channel LCH may be greater than the width of the upper channel UCH. The channel structure CH may have a bent portion at the boundary between the lower channel LCH and the upper channel UCH. For example, the gate electrodes 332 and 333 forming the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. Data may not be stored in a memory cell connected to the dummy word line. The voltage level applied to the dummy word line may be different from (e.g., greater than or less than) the voltage level applied to the general word line. The number of gate electrodes 331 and 332 through which the lower channel LCH passes and / or the number of word lines 333 to 338 through which the upper channel UCH passes are shown as examples only and are not limited thereto.

[0088] Return to reference Figure 4 , the first wiring 350c and the second wiring 360c may be sequentially disposed on the channel structure CH and thereby electrically connected to the channel structure CH. For example, the first wiring 350c may be electrically connected to the semiconductor pattern ( Figure 6 130). The second wiring 360c may be electrically connected to the channel structure CH through the first wiring 350c. The second wiring 360c may be provided as a bit line ( Figure 2 The second wirings 360c may extend in the second direction Y and may be arranged to be spaced apart from each other in the first direction X.

[0089] In the bit line bonding area BLBA, the first bonding metal 370c of the first cell structure CELL1 may be electrically connected to the first bonding metal 270c of the peripheral circuit structure PERI by a bonding method. The second wiring 360c may be electrically connected to the peripheral circuit structure PERI by the first bonding metal 370c and the first bonding metal 270c. For example, a portion of the circuit element 220c may provide a page buffer, and the second wiring 360c may be electrically connected to the circuit element 220c providing the page buffer by the first bonding metal 370c and the first bonding metal 360c.

[0090] In the word line bonding area WLBA, the gate contact 340 may be electrically connected to the gate electrode 330. For example, each of the gate contacts 340 may extend in the third direction Z on the gate electrode 330 and thereby be electrically connected to the corresponding gate electrode 330. The first wiring 350b and the second wiring 360b may be sequentially disposed on the gate contact 340 and thereby be electrically connected to the gate contact 340.

[0091] In the word line bonding area WLBA, the first bonding metal 370b of the first cell structure CELL1 may be electrically connected to the first bonding metal 270b of the peripheral circuit structure PERI by a bonding method. The gate contact 340 may be electrically connected to the peripheral circuit structure PERI by the first bonding metal 370b and the first bonding metal 270b. For example, a portion of the circuit element 220b may provide a row decoder, and the gate contact 340 may be electrically connected to the circuit element 220b providing the row decoder by the first bonding metal 370b and the first bonding metal 270b.

[0092] In the external pad landing area PA, the source contact plug 380 may be electrically connected to the source layer 320. For example, the source contact plug 380 may extend in the third direction Z on the source layer 320 and thereby be electrically connected to the corresponding source layer 320. The first wiring 350a and the second wiring 360a may be sequentially disposed on the source contact plug 380 and thereby be electrically connected to the source contact plug 380.

[0093] In the external pad bonding area PA, the first bonding metal 370a of the first cell structure CELL1 may be electrically connected to the first bonding metal 270a of the peripheral circuit structure PERI by a bonding method. The source contact plug 380 may be electrically connected to the peripheral circuit structure PERI through the first bonding metal 370a and the first bonding metal 270a.

[0094] The second insulating film 307 may be disposed on the rear side of the first unit substrate 310. The second insulating film 307 may cover the rear side of the first unit substrate 310. The second input / output pad 308 and the third input / output pad 309 may be disposed on the second insulating film 307. The second input / output contact plug 312 and the third input / output contact plug 314 may be electrically connected to the peripheral circuit structure PERI through the first bonding metal 370a and the first bonding metal 270a. The second input / output pad 308 may be electrically connected to at least one circuit element 220a through the second input / output contact plug 312. The third input / output pad 309 may be electrically connected to the first capacitor electrodes 201a, 202a, 203a, 204a, and 205a through the third input / output contact plug 314 and the connection through hole 214.

[0095] In the semiconductor memory device according to some example embodiments, the capacitors C1, C2, C3, C4, and C5 are disposed on the second surface 210b of the peripheral circuit board 210, rather than on the first surface 210a of the peripheral circuit board 210 where the circuit elements 220a, 220b, and 220c are disposed. The capacitors C1, C2, C3, C4, and C5 may be disposed not only in a specific area of ​​the peripheral circuit board 210, but also in the entire bit line bonding area BLBA, the word line bonding area WLBA, and the external pad bonding area PA. Therefore, compared with the case where the capacitors C1, C2, C3, C4, and C5 are formed on the first surface 210a of the peripheral circuit board 210, a semiconductor memory device with a reduced size and / or increased integration may be provided using the second surface 210b of the peripheral circuit board 210.

[0096] Figures 8 to 10 is a diagram illustrating a capacitor electrode of a semiconductor memory device according to some example embodiments.

[0097] Reference Figure 4 and Figure 8 In a semiconductor memory device according to some example embodiments, at least a portion of the first capacitor electrodes 201a, 202a, 203a, 204a, and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b, and 205b may include an extension portion 20a extending in a random direction. The extension portion 20a may have a linear shape extending in a random direction. For example, the extension portion 20a may extend in a direction parallel to the second surface 210b of the peripheral circuit board 210.

[0098] Reference Figure 4 and Fig. 9In a semiconductor memory device according to some example embodiments, at least a portion of the first capacitor electrodes 201a, 202a, 203a, 204a, and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b, and 205b may include first extension portions 20a and 20c extending in a first random direction and a second extension portion 20b extending in a second random direction. For example, the first random direction and the second random direction may be parallel to the second surface 210b of the peripheral circuit board 210 and may be perpendicular to each other. The second extension portion 20b may be arranged in the second random direction. The first extension portion 20a may be connected to one end of the second extension portion 20b, and the first extension portion 20c may be connected to the other end of the second extension portion 20b. The first extension portion 20a, the second extension portion 20b, and the first extension portion 20c may be arranged in sequence and connected to each other. In some example embodiments, an area (e.g., surface area) of the first extension portions 20a and 20c and an area (e.g., surface area) of the second extension portion 20b may increase, which may affect the capacitance of at least one of the first capacitor electrodes 201a, 202a, 203a, 204a, and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b, and 205b.

[0099] Reference Figure 4 and Fig.10 In a semiconductor memory device according to some example embodiments, at least some of the first capacitor electrodes 201a, 202a, 203a, 204a, and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b, and 205b may be adjacent to each other in a direction parallel to the second surface 210b of the peripheral circuit board 210 and may have a comb shape. In some example embodiments, capacitance may be affected by or at least partially determined by the comb shape.

[0100] For example, the (1-1)th electrode 201a may include a first extension portion 20a extending in a first random direction and a second extension portion 20b extending in a second random direction, and the (2-1)th electrode 201b may include a first extension portion 20d extending in the first random direction and a second extension portion 20e extending in the second random direction. The second extension portion 20b of the (1-1)th electrode 201a and the second extension portion 20e of the (1-2)th electrode 201b may be alternately arranged in the first random direction.

[0101] The electrodes disposed on the same metal layer among the first capacitor electrodes 201a, 202a, 203a, 204a, and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b, and 205b may have Figures 8 to 10The electrodes disposed on different metal layers among the first capacitor electrodes 201a, 202a, 203a, 204a, and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b, and 205b may have the same shape, or may have different shapes.

[0102] Fig.11 is a diagram showing a semiconductor memory device according to some example embodiments. Figures 1 to 10 Redundant parts of the description.

[0103] Reference Fig.11 , the peripheral circuit structure PERI according to some example embodiments may include a high voltage region HV and a low voltage region LV. The operating voltage of the high voltage circuit element 220hv disposed in the high voltage region HV may be different from the operating voltage of the low voltage circuit element 220lv disposed in the low voltage region LV. The operating voltage of the high voltage circuit element 220hv disposed in the high voltage region HV may be relatively higher (e.g., higher in absolute value) than the operating voltage of the low voltage circuit element 220lv disposed in the low voltage region LV.

[0104] In the semiconductor memory device according to some example embodiments, high voltage capacitors C1hv, C2hv, C3hv, C4hv, and C5hv and low voltage capacitors C1lv, C2lv, C3lv, C4lv, and C5lv may be formed on the second surface 210 b of the peripheral circuit board 210 .

[0105] The first capacitor electrodes 201ahv, 202ahv, 203ahv, 204ahv, and 205ahv and the second capacitor electrodes 201bhv, 202bhv, 203bhv, 204bhv, and 205bhv may be disposed in the capacitor dielectric layer 206. Different voltages may be applied to the first capacitor electrodes 201ahv, 202ahv, 203ahv, 204ahv, and 205ahv and the second capacitor electrodes 201bhv, 202bhv, 203bhv, 204bhv, and 205bhv. For example, the first capacitor electrodes 201ahv, 202ahv, 203ahv, 204ahv, and 205ahv may receive voltages through the connection through-holes 214hv that pass through the peripheral circuit board 210.

[0106] Each of the (1-1)th to (1-5)th electrodes 201ahv, 202ahv, 203ahv, 204ahv, and 205ahv, each of the (2-1)th to (2-5)th electrodes 201bhv, 202bhv, 203bhv, 204bhv, and 205bhv, and the capacitor dielectric layer 206 therebetween may constitute each of the first to fifth high-voltage capacitors C1hv, C2hv, C3hv, C4hv, and C5hv. The capacitances of the high-voltage capacitors C1hv, C2hv, C3hv, C4hv, and C5hv may be different from one another. For example, the capacitances of the high-voltage capacitors C1hv, C2hv, C3hv, C4hv, and C5hv may be arranged in an arithmetic progression or a geometric progression with respect to one another.

[0107] The high voltage capacitors C1hv, C2hv, C3hv, C4hv, C5hv may provide an operating voltage to the high voltage circuit element 220hv through the connection via 214hv, the first wiring 230hv, and the second wiring 240hv. The first bonding metal 270hv may be provided on the second wiring 240hv.

[0108] The first capacitor electrodes 201alv, 202alv, 203alv, 204alv, and 205alv and the second capacitor electrodes 201blv, 202blv, 203blv, 204blv, and 205blv may be disposed in the capacitor dielectric layer 206. Different voltages may be applied to the first capacitor electrodes 201alv, 202alv, 203alv, 204alv, and 205alv and the second capacitor electrodes 201blv, 202blv, 203blv, 204blv, and 205blv. For example, the first capacitor electrodes 201alv, 202alv, 203alv, 204alv, and 205alv may receive voltages through the connection through-holes 214lv passing through the peripheral circuit board 210.

[0109] Each of the (1-1)th electrode to the (1-5)th electrode 201alv, 202alv, 203alv, 204alv and 205alv, each of the (2-1)th electrode to the (2-5)th electrode 201blv, 202blv, 203blv, 204blv and 205blv and the capacitor dielectric layer 206 therebetween can constitute each of the first low-voltage capacitor to the fifth low-voltage capacitor C1lv, C2lv, C3lv, C4lv and C5lv. The capacitances of the low-voltage capacitors C1lv, C2lv, C3lv, C4lv and C5lv can be different from each other. For example, the capacitances of the low-voltage capacitors C1lv, C2lv, C3lv, C4lv and C5lv can be arranged in an arithmetic progression or a geometric progression.

[0110] The low voltage capacitors C11v, C21v, C31v, C41v, and C51v may provide an operating voltage to the low voltage circuit element 2201v through the connection via 2141v, the first wiring 2301v, and the second wiring 2401v. The first bonding metal 2701v may be disposed on the second wiring 2401v.

[0111] The first capacitor electrodes 201ahv, 202ahv, 203ahv, 204ahv and 205ahv, the second capacitor electrodes 201bhv, 202bhv, 203bhv, 204bhv and 205bhv, the first capacitor electrodes 201alv, 202alv, 203alv, 204alv and 205alv, and the second capacitor electrodes 201blv, 202blv, 203blv, 204blv and 205blv may have the above-mentioned reference numerals, respectively. Figures 8 to 10 Describe the shape.

[0112] Fig.12 is a diagram showing a semiconductor memory device according to some example embodiments. Fig.11 Redundant parts of the description.

[0113] Reference Fig.12 , in the semiconductor memory device according to some example embodiments, the high voltage capacitors C1hv, C2hv, C3hv, C4hv and C5hv are formed on the second surface 210b of the peripheral circuit board 210, but the low voltage capacitors C1lv, C2lv and C3lv may be formed on the first surface 210a of the peripheral circuit board 210.

[0114] The first capacitor electrodes 201alv, 202alv, and 203alv and the second capacitor electrodes 201blv, 202blv, and 203blv may be disposed in the first interlayer insulating layer 215. Different voltages may be applied to the first capacitor electrodes 201alv, 202alv, and 203alv and the second capacitor electrodes 201blv, 202blv, and 203blv. For example, the first capacitor electrodes 201alv, 202alv, and 203alv may receive a voltage through the first bonding metal 2701v.

[0115] Each of the (1-1)th to (1-3)th electrodes 201alv, 202alv, and 203alv, each of the (2-1)th to (2-3)th electrodes 201blv, 202blv, and 203blv, and the capacitor dielectric layer 206 therebetween may constitute each of the first to third low-voltage capacitors C1lv, C2lv, and C3lv. The capacitances of the low-voltage capacitors C1lv, C2lv, and C3lv may be different from each other. For example, each of the (1-1)th to (1-3)th electrodes 201alv, 202alv, and 203alv may be formed on the same metal layer as the first wiring in the first interlayer insulating layer 215, the through hole of the second wiring in the first interlayer insulating layer 215, and the wiring of the second wiring in the first interlayer insulating layer 215.

[0116] The low voltage capacitors C11v, C21v, and C31v may provide an operating voltage to the low voltage circuit element 2201v through the first wiring and the second wiring in the first interlayer insulating layer 215. The first bonding metal 2701v may be disposed on the (1-3)th electrode 203alv. The first bonding metal 2701v may be disposed on the (2-3)th electrode 203blv.

[0117] Fig.13 is a cross-sectional view illustrating a semiconductor memory device according to some example embodiments. Fig.14 It shows Fig.13 For the sake of convenience, the above referenced Figures 1 to 12 Redundant parts of the description.

[0118] Reference Fig.13 and Fig.14 , a semiconductor memory device according to some example embodiments may include a source pattern 324 .

[0119] The source pattern 324 may be formed on the first unit substrate 310. The source pattern 324 may be connected to the semiconductor pattern 130 of the channel structure CH. For example, the semiconductor pattern 130 may contact the upper surface of the source pattern 324 by passing through the information storage layer 132. The source pattern 324 and the first unit substrate 310 may be provided as a common source line ( Figure 2 The lower portion of the source pattern 324 is shown as being embedded only in the first unit substrate 310, but this is only an example. As another example, the lower surface of the source pattern 324 may be disposed on the front side and coplanar surface of the first unit substrate 310.

[0120] The source pattern 324 may include a conductive material, such as metal or polysilicon doped with impurities, but is not limited thereto. The source pattern 324 may be formed, for example, by a selective epitaxial growth process from the first unit substrate 310, but is not limited thereto.

[0121] In some example embodiments, an upper surface of the source pattern 324 may intersect a portion of the gate electrode 330. For example, an upper surface of the source pattern 324 may be higher than an upper surface of the gate electrode 331. In this case, a gate insulating film 315S may be interposed between the source pattern 324 and the gate electrode (e.g., the gate electrode 331) intersecting the source pattern 324.

[0122] Fig.15 is a cross-sectional view illustrating a semiconductor memory device according to some example embodiments. Fig.16 It shows Fig.15 Magnified view of area B. Fig.17 It shows Fig.15 Magnified view of area C. Fig.18 It shows Fig.15 For ease of description, the above referenced Figures 1 to 14 Redundant parts of the description.

[0123] Reference Fig.15 , a semiconductor memory device according to some example embodiments may include a plurality of cell structures CELL1 and CELL2, in which a memory cell array including memory cells is provided ( Figure 1 20). For example, the second unit structure CELL2 may be stacked on the first unit structure CELL1. The structure of the second unit structure CELL2 in the area other than the peripheral area PA may be the same as or different from the structure of the first unit structure CELL1. In the following, the upper part, the upper surface, the lower part, and the lower surface of the second unit structure CELL2 are defined based on the opposite direction of the third direction Z, but this is only an example. Only one of the first upper chip and the second upper chip may be reversed and connected in a bonding manner.

[0124] The second unit structure CELL2 includes a second unit substrate 410, multiple gate electrodes 430 (including gate electrodes 431 to 438, the number of gate electrodes 431 to 438 may be the same as or different from the number of multiple gate electrodes 330), a third interlayer insulating layer 415, a channel structure CH, multiple gate contacts 441 to 447; 440, a source layer 420, a first wiring 450a, 450b and 450c, a second wiring 460a, 460b and 460c, a first bonding metal 470a, 470b and 470c, a second insulating film 401, a second input / output pad 405 and a third input / output pad 406, and a second input / output contact plug 403 and a third input / output contact plug 404.

[0125] A memory cell array including a plurality of memory cells ( Figure 1 20) may be disposed on the bit line bonding area BLBA of the second unit structure CELL2. For example, the channel structure CH, the gate electrode 430, and the bit line 460c may be disposed on the second unit substrate 410 in the bit line bonding area BLBA. In the following description, the surface of the second unit substrate 410 on which the memory cell array is disposed may be referred to as the front side. Conversely, the surface of the second unit substrate 410 opposite to the front side of the second unit substrate 410 may be referred to as the back side of the second unit substrate 410.

[0126] The gate electrode 430 may be disposed on the front side of the second unit substrate 410. The third interlayer insulating layer 415 may be disposed on the front side of the second unit substrate 410 to cover the gate electrode 430. The channel structure CH may be disposed on the second unit substrate 410 in the bit line bonding area BLBA. The source layer 420 may be disposed between the second unit substrate 410 and the gate electrode 430. The first wiring 450c and the second wiring 460c may be sequentially disposed on the channel structure CH and thereby electrically connected to the channel structure CH. The second wiring 460c may be provided as a bit line ( Figure 2 of BL).

[0127] The shapes and structures of the gate electrode 430, the third interlayer insulating layer 415, the channel structure CH of the second unit structure CELL2, the source layer 420, the first wiring 450c and the second wiring 460c may be the same as or similar to the shapes and structures of the gate electrode 330, the second interlayer insulating layer 315, the channel structure CH of the first unit structure CELL1, the source layer 320, the first wiring 350c and the second wiring 360c.

[0128] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell structure CELL1, and the second through electrode THV2 may be disposed in the second cell structure CELL2. The first through electrode THV1 may pass through the source layer 320 and the gate electrode 330, but this is only an example. The first through electrode THV1 may also pass through the first cell substrate 310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as those of the first through electrode THV1.

[0129] In some example embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other through the first through metal pattern 372d and the second through metal pattern 472d. The first through hole 371d may be provided between the first through electrode THV1 and the first through metal pattern 372d, and the second through hole 471d may be provided between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d may be connected to each other by a bonding method.

[0130] In the word line bonding area WLBA, the gate contact 440 may be electrically connected to the gate electrode 430. The gate contact 440 may be electrically connected to the peripheral circuit structure PERI through the cell contact plug 348.

[0131] In the external pad landing area PA, the source contact plug 480 may be electrically connected to the source layer 420. The first wiring 450a and the second wiring 460a may be sequentially disposed on the source contact plug 480 and thereby electrically connected to the source contact plug 480.

[0132] The second insulating film 401 may be disposed on the rear side of the second unit substrate 410. The second insulating film 401 may cover the rear side of the second unit substrate 410. The second input / output pad 405 and the third input / output pad 406 may be disposed on the second insulating film 401. The second input / output pad 405 may be electrically connected to at least one circuit element 220a of the peripheral circuit structure PERI through the second input / output contact plugs 403 and 303, and the third input / output pad 406 may be electrically connected to at least one circuit element 220a of the peripheral circuit structure PERI through the third input / output contact plugs 404 and 304. The connection through-hole 214 may receive a voltage through, for example, the second input / output contact plugs 403 and 303 or the third input / output contact plugs 404 and 304.

[0133] In some example embodiments, the third input / output contact plug 404 may be separated from the second unit substrate 410 in a direction parallel to the front side of the second unit substrate 410 and may be electrically connected to the third input / output pad 406 by passing through the third interlayer insulating layer 145 of the second unit structure CELL2.

[0134] Reference Fig.16 As shown in B1, the third input / output contact plug 404 may extend along the third direction Z, and the diameter of the third input / output contact plug 404 may increase toward the second insulating film 401. For example, as shown in B2, the third input / output contact plug 404 may extend along the third direction Z, and the diameter of the third input / output contact plug 404 may decrease toward the second insulating film 401.

[0135] Reference Fig.17 In some example embodiments, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the second unit substrate 410 .

[0136] For example, as shown in C1, an opening 408 is formed through the second unit substrate 410, and the second input / output contact plug 403 can be directly connected to the second input / output pad 405 through the opening 408 formed in the second unit substrate 410. Exemplarily, as shown in C2, a contact 407 can be formed in the opening 408. One end of the contact 407 can be connected to the second input / output pad 405, and the other end of the contact 407 can be connected to the second input / output contact plug 403. For example, as shown in C3, unlike C2, a blocking portion 409 can also be formed on the upper surface of the opening 408 of the second unit substrate 410. The blocking portion 409 can be a metal line formed on the same layer as the source layer 420, but this is only an example. The blocking portion 409 can be a metal line formed on the same layer as the at least one gate electrode 430.

[0137] According to an embodiment, a slit 411 may be formed in the second unit substrate 410. For example, the slit 411 may be formed at any position of the external pad bonding area PA. Fig.18 For example, as shown in D1, a slit 411 may be formed to pass through the second unit substrate 410. For example, as shown in D2, a conductive material 412 may be formed in the slit 411. For example, as shown in D3, an insulating material 413 may be formed in the slit 411.

[0138] According to various example embodiments, the first to third input / output pads 205, 405, and 406 may be selectively formed. For example, the semiconductor memory device may include at least one of the first to third input / output pads 205, 405, or 406.

[0139] Fig.19 is a schematic perspective view showing a semiconductor memory device according to some example embodiments. Figures 1 to 14 Redundant parts of the description.

[0140] Reference Fig.19 In a semiconductor memory device according to some example embodiments, the peripheral circuit structure PERI may include a first peripheral circuit structure PERI1 and a second peripheral circuit structure PERI2. The first peripheral circuit structure PERI1, the second peripheral circuit structure PERI2, and the first cell structure CELL1 are stacked in a third direction Z.

[0141] Peripheral circuit structure ( Figures 1 to 14 A portion of the peripheral circuit structure PERI) may be disposed in a first peripheral circuit structure PERI1, and another portion of the peripheral circuit structure may be disposed in a second peripheral circuit structure PERI2.

[0142] In some example embodiments, the peripheral circuit board 210, the capacitors C1, C2, C3, C4 and C5, and Figures 1 to 14 The circuit elements 220a, 220b and 220c electrically connected to the capacitors C1, C2, C3, C4 and C5 may be disposed in the first peripheral circuit structure PERI1. The second peripheral circuit structure PERI2 may include a peripheral circuit board, and circuit elements 220a, 220b and 220c on the peripheral circuit board that are not electrically connected to the capacitors C1, C2, C3, C4 and C5.

[0143] In some example embodiments, the peripheral circuit board 210, the capacitors C1, C2, C3, C4 and C5, and Figures 1 to 14 The circuit elements 220a, 220b and 220c electrically connected to the capacitors C1, C2, C3, C4 and C5 may be disposed in the second peripheral circuit structure PERI2. The first peripheral circuit structure PERI1 may include a peripheral circuit board, and circuit elements 220a, 220b and 220c on the peripheral circuit board that are not electrically connected to the capacitors C1, C2, C3, C4 and C5.

[0144] Figure 20 to Figure 22 is a diagram showing intermediate steps of a method for manufacturing a semiconductor memory device according to some example embodiments. Figures 1 to 14 Redundant parts of the description.

[0145] Reference Fig. 20 , forming a pre-peripheral circuit structure P_PERI.

[0146] The pre-peripheral circuit structure P_PERI includes a peripheral circuit board 210, circuit elements 220a, 220b and 220c, connecting vias 214, first wirings 230a, 230b and 230c, second wirings 240a, 240b and 240c, first bonding metals 270a, 270b and 270c, and a first interlayer insulating layer 215.

[0147] The peripheral circuit board 210 may include a first surface 210a and a second surface 210b opposite to each other. Circuit elements 220a, 220b and 220c and a connecting through hole 214 are formed on the first surface 210a of the peripheral circuit board 210. A portion of the connecting through hole 214 is formed in the peripheral circuit board 210. For example, the connecting through hole 214 may pass through a portion of the peripheral circuit board 210. First wirings 230a, 230b and 230c, second wirings 240a, 240b and 240c, and first bonding metals 270a, 270b and 270c are formed on the connecting through hole 214 and the peripheral circuit board 210. A first interlayer insulating layer 215 is formed on the first surface 210a of the peripheral circuit board 210. Circuit elements 220a, 220b, and 220c, connection vias 214, first wirings 230a, 230b, and 230c, second wirings 240a, 240b, and 240c, and first bonding metals 270a, 270b, and 270c are formed in the first interlayer insulating layer 215. Upper surfaces of the first bonding metals 270a, 270b, and 270c may be exposed through the first interlayer insulating layer 215.

[0148] Reference Fig.21 , Fig. 20 The pre-peripheral circuit structure P_PERI is bonded to the semiconductor chip L. The first surface 210 a of the peripheral circuit board 210 may be bonded to the semiconductor chip L such that the first surface 210 a of the peripheral circuit board 210 faces the semiconductor chip L.

[0149] For example, the semiconductor chip L may include a bonding metal, and the semiconductor chip L and the pre-peripheral circuit structure P_PERI may be bonded to each other through bonding between the bonding metal and the first bonding metals 270 a , 270 b , and 270 c .

[0150] In some example embodiments, the semiconductor chip L may be Figure 3 The first cell structure CELL1 is shown in FIG.

[0151] In some example embodiments, the semiconductor chip L may be a dummy wafer or a dummy chip or a dummy die, for example, a wafer or a chip or a die without any electrically active element and / or a blank wafer or a chip or a die. In this case, after forming the peripheral circuit structure PERI, the semiconductor chip L may be removed, and the peripheral circuit structure PERI and the first unit structure CELL1 may be bonded to each other.

[0152] Subsequently, a portion of the peripheral circuit board 210 is removed so that a portion of the connection through hole 214 is exposed. A portion of the connection through hole 214 may protrude toward the outside. For example, grinding, chemical mechanical polishing, or etching back may be performed on the second surface 210b of the peripheral circuit board 210 so that the connection through hole 214 is exposed.

[0153] Reference Fig. 22 , a capacitor electrically connected to the connection through hole 214 is formed on the second surface 210 b of the peripheral circuit board 210 .

[0154] First capacitor electrodes 201a, 202a, 203a, 204a and 205a, second capacitor electrodes 201b, 202b, 203b, 204b and 205b, and a capacitor dielectric layer 206 are formed on the second surface 210b of the peripheral circuit board 210. The first capacitor electrodes 201a, 202a, 203a, 204a and 205a and the second capacitor electrodes 201b, 202b, 203b, 204b and 205b are formed in or inside the capacitor dielectric layer 206 and are therefore not exposed to the outside. The first capacitor electrodes 201a, 202a, 203a, 204a and 205a are formed on the connection through holes 214. A first insulating film 207, a first input / output pad 208 and a first input / output contact plug 212 are formed, thereby forming a peripheral circuit structure PERI.

[0155] Fig.23 is an example block diagram illustrating an electronic system according to some example embodiments. Fig.24 is an example perspective view illustrating an electronic system according to some example embodiments. Fig.25 is along Fig.24 For ease of description, the above reference will be briefly described or omitted. Figures 1 to 14 Redundant parts of the description.

[0156] Reference Fig.23, the electronic system 1000 according to some example embodiments may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be or may include or be included in one or more of a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device having one or more semiconductor memory devices 1100.

[0157] The semiconductor memory device 1100 may be a nonvolatile memory device (eg, a NAND flash memory device), and may be, for example, a memory device such as a memory device 1100 shown in FIG. Figures 1 to 14 The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0158] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 (eg, Figure 1 , a row decoder 33), a page buffer 1120 (eg, Figure 1 110 and logic circuit 1130 (eg, Figure 1 For example, the first structure 1100F may correspond to the reference Figures 1 to 13 Describe the peripheral circuit structure PERI.

[0159] The second structure 1100S may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR, which are referred to above. Figure 2 The cell string CSTR may be connected to the decoder circuit 1110 through the word line WL, at least one string selection line SSL, and at least one ground selection line GSL. In addition, the cell string CSTR may be connected to the page buffer 1120 through the bit line BL. For example, the second structure 1100S may correspond to the reference Figures 1 to 13 A first cell structure CELL1 is described.

[0160] In some example embodiments, the common source line CSL and the cell string CSTR may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from the first structure 1100F to the second structure 1100S. For example, the first connection line 1115 may correspond to the reference Figures 1 to 13 For example, the gate contact 340 can connect the gate electrode 330 to the decoder circuit 1110 (eg, Figure 1 The row decoder 33) is electrically connected.

[0161] In some example embodiments, the bit line BL may be electrically connected to the page buffer 1120 through the second connection line 1125. For example, the second connection line 1125 may correspond to the reference Figures 1 to 13 For example, the first wiring 350c can connect the bit line BL to the page buffer 1120 (eg, Figure 1 The page buffer 35 is electrically connected.

[0162] The semiconductor memory device 1100 may be electrically connected to a logic circuit 1130 (eg, Figure 1 The input / output pad 1101 of the control logic 37 of the first structure 1100F performs communication with the controller 1200. The input / output pad 1101 can be electrically connected to the logic circuit 1130 through the input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S. For example, the connection line 1135 may correspond to the reference Figures 1 to 13 The second input / output contact plug 312 and the third input / output contact plug 314 are depicted.

[0163] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some example embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor memory devices 1100.

[0164] The processor 1210 may control some or all of the electronic system 1000 including the controller 1200, such as the overall operation. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor memory device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100. A control command for controlling the semiconductor memory device 1100, data to be written into the memory cell transistor MCT of the semiconductor memory device 1100, data to be read from the memory cell transistor MCT of the semiconductor memory device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

[0165] Reference Fig.24 and Fig.25, an electronic system 2000 according to some example embodiments may include a main board 2001, a main controller 2002 packaged on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through a wiring pattern 2005 formed in the main board 2001.

[0166] The mainboard 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may perform communication with the external host according to any one or more of interfaces such as a universal serial bus (USB), a peripheral component interconnect high-speed bus (PCI-Express), a serial advanced technology attachment (SATA), and M-Phy (UFS) for universal flash storage. In some example embodiments, the electronic system 2000 may be operated by a power supply provided from an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes the power provided from the external host to the main controller 2002 and the semiconductor package 2003.

[0167] The main controller 2002 may write data to or read data from the semiconductor package 2003 , and may increase the operating speed of the electronic system 2000 .

[0168] The DRAM 2004 may be a buffer memory for alleviating a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a cache memory and may provide a space for temporarily storing data in a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the main controller 2002 may include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0169] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of the corresponding semiconductor chip 2200, a connection structure 2400 for electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 on the package substrate 2100 and the connection structure 2400.

[0170] The package substrate 2100 may be a printed circuit board including the package upper pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.23 Input / output pad 1101.

[0171] In some example embodiments, the connection structure 2400 may be a bonding wire for electrically connecting the input / output pad 2210 with the package on-pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package on-pad 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through silicon via (TSV), instead of or in addition to the connection structure 2400 in the bonding wire manner.

[0172] In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in one package. In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be packaged on a separate interposer substrate different from the main board 2001, and the main controller 2002 may be connected to the semiconductor chip 2200 through wiring formed in the interposer substrate.

[0173] In some example embodiments, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include: a package substrate body portion 2120; a package upper pad 2130 disposed on an upper surface of the package substrate body portion 2120; a lower pad 2125 disposed on a lower surface of the package substrate body portion 2120 or exposed through the lower surface; and an internal wiring 2135 electrically connecting the upper pad 2130 with the lower pad 2125 inside the package substrate body portion 2120. The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to a wiring pattern 2005 of a main board 2001 of the electronic system 2000 through a conductive connector 2800, such as Fig.24 shown.

[0174] In an electronic system according to some example embodiments, each of the semiconductor chips 2200 may include a reference Figures 1 to 13 The semiconductor memory device described herein. For example, each of the semiconductor chips 2200 may include a peripheral circuit structure PERI and a first unit structure CELL stacked on the peripheral circuit structure PERI. Exemplarily, the peripheral circuit structure PERI may include first capacitor electrodes 201a, 202a, 203a, 204a, and 205a, second capacitor electrodes 201b, 202b, 203b, 204b, and 205b, and a capacitor dielectric layer 206, which are disposed on the back side 210b of the peripheral circuit board 210, and the peripheral circuit structure PERI and the first unit structure CELL1 may be bonded to each other by a first bonding metal 270 including bonding metals 270a, 270b, and 270c and a second bonding metal 370 including bonding metals 370a, 370b, and 370c.

[0175] Figure 26 to Figure 28 is a diagram illustrating a semiconductor memory device according to some example embodiments. Fig. 27 is along Fig.26 A cross-sectional view taken along line AA of Fig.28 is along Fig.26 A schematic cross-sectional view taken along line BB of FIG.

[0176] Reference Figure 26 to Figure 28 , in a semiconductor memory device according to some example embodiments, Figure 3 The memory cells included in the first cell structure CELL1 may be volatile memory cells.

[0177] Reference Fig.26 , substrate ( Fig. 27 and Fig.28 The substrate 100 may include a plurality of active regions ACT. The active region ACT may be formed by an element isolation layer ( Fig. 27 and Fig.28 For example, the active area ACT may extend along the third direction DR3.

[0178] A plurality of gate electrodes extending in the first direction DR1 may be disposed across the active area ACT. The plurality of gate electrodes may extend parallel to each other. The plurality of gate electrodes may be, for example, a plurality of word lines WL.

[0179] Each active area ACT may be divided into three parts by two word lines WL extending along the first direction DR1. The active area ACT may include a storage connection area 103b and a bit line connection area 103a. The bit line connection area 103a may be located at the central part of the active area ACT, and the storage connection area 103b may be located at the end of the active area ACT. For example, the bit line connection area 103a may be an area connected to the bit line BL, and the storage connection area 103b may be an area connected to the capacitor structure 190. For example, the bit line connection area 103a may correspond to a common drain area, and the storage connection area 103b may correspond to a source area. Each word line WL and the bit line connection area 103a and the storage connection area 103b adjacent to each word line WL may constitute a transistor.

[0180] A plurality of bit lines BL extending in a second direction DR2 perpendicular to the word lines WL may be disposed on the word lines WL. The plurality of bit lines BL may extend parallel to each other.

[0181] Reference Fig. 27 and Fig.28 , a semiconductor memory device according to some example embodiments may include a plurality of gate structures 110 , a plurality of bit line structures 140ST, a plurality of bit line contacts 146 , and a memory structure such as a memristor and / or capacitor structure 190 .

[0182] The gate structure 110 may be formed in the substrate 100 and the element isolation layer 105. The gate structure 110 may be formed on the element isolation layer 105 and the active region ACT defined by the element isolation layer 105. The gate structure 110 may include a gate trench 115, a gate insulating film 111, a gate electrode 112, a gate capping pattern 113, and a gate capping conductive film 114. The gate electrode 112 may correspond to a word line ( Fig.26 of WL).

[0183] The gate insulating film 111 may extend along the sidewall and bottom surface of the gate trench 115. The gate electrode 112 may be disposed on the gate insulating film 111. The gate electrode 112 may fill a portion of the gate trench 115. The gate capping conductive layer 114 may extend along the upper surface of the gate electrode 112. The gate capping pattern 113 may fill the gate trench 115 remaining after the gate electrode 112 and the gate capping conductive layer 114 are formed.

[0184] The bit line structure 140ST may include a conductive line 140 and a line capping layer 144. The conductive line 140 may be disposed on the element isolation layer 105 and the substrate 100 in which the gate structure 110 is formed. The conductive line 140 may cross the element isolation layer 105 and the active region ACT. The conductive line 140 may be formed to cross the gate structure 110. The conductive line 140 may correspond to the bit line ( Fig.26 A line capping layer 144 may be disposed on the conductive line 140. A bit line spacer 150 may be disposed on sidewalls of the conductive line 140 and the line capping layer 144.

[0185] The bit line contact 146 may be formed between the bit line connection region 103a of the active region ACT and the conductive line 140. The bit line contact 146 may be connected to the bit line connection region 103a. The bit line contact 146 may correspond to a direct contact portion ( Fig.26 DC).

[0186] A plurality of storage contacts 120 may be disposed between the conductive lines 140 adjacent to each other in the first direction DR1. The storage contacts 120 may be connected to the storage connection region 103b of the active region ACT. The storage contacts 120 may correspond to buried contacts BC.

[0187] The storage pad 160 may be disposed on the storage contact 120. The storage pad 160 may be electrically connected to the storage contact 120. The storage pad 160 may correspond to the landing pad LP. The pad isolation insulating layer 180 includes an insulating material and may electrically isolate the plurality of storage pads 160 from each other. The etching stop film 195 may be disposed on the storage pad 160 and the pad isolation insulating layer 180.

[0188] The capacitor structure 190 may be disposed on the storage pad 160. The capacitor structure 190 may be electrically connected to the storage pad 160. The capacitor structure 190 may include a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193.

[0189] Any of the elements and / or functional blocks disclosed above may be included or implemented in a processing circuit, such as hardware including a logic circuit; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include electronic components such as at least one of a transistor, a resistor, a capacitor, etc. The processing circuit may include electronic components such as a logic gate including at least one of an AND gate, an OR gate, a NAND gate, a NOT gate, etc.

[0190] Although various example embodiments have been described with reference to the accompanying drawings, it is obvious to those skilled in the art that the present disclosure can be manufactured in various forms without being limited to the above-described example embodiments, and can be embodied in other specific forms without departing from the technical spirit and basic features of the inventive concept. Therefore, the above-described embodiments should be regarded as illustrative rather than restrictive in all aspects. In addition, the example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more drawings, and may also include one or more other features described with reference to one or more other drawings.

Claims

1. A semiconductor memory device, comprising: Peripheral circuit structure; as well as a cell structure, on the peripheral circuit structure, and comprising a cell substrate and a gate electrode, Wherein, the peripheral circuit structure includes: a peripheral circuit board including a first surface facing the unit structure and a second surface opposite to the first surface, a first circuit element, on the first surface of the peripheral circuit board, a first interlayer insulating layer covering the first surface of the peripheral circuit board, a first wiring electrically connected to the first circuit element in the first interlayer insulating layer, a capacitor dielectric layer covering the second surface of the peripheral circuit board, a first capacitor electrode in said capacitor dielectric layer, a second capacitor electrode spaced apart from the first capacitor electrode in the capacitor dielectric layer, and The first connecting through hole electrically connects the first capacitor electrode with the first wiring by passing through the corresponding peripheral circuit board.

2. The semiconductor memory device according to claim 1, wherein: The first capacitor electrode and the second capacitor electrode are not exposed by the capacitor dielectric layer.

3. The semiconductor memory device according to claim 1, wherein: The first capacitor electrode and the second capacitor electrode are spaced apart from each other in a direction parallel to the second surface of the peripheral circuit board.

4. The semiconductor memory device according to claim 1, wherein The first capacitor electrode includes 1-1th electrode to 1-nth electrode sequentially stacked on the second surface of the peripheral circuit board, wherein, n is a natural number greater than or equal to 2, and The second capacitor electrode includes 2-1th to 2-nth electrodes sequentially stacked on the second surface of the peripheral circuit board.

5. The semiconductor memory device according to claim 4, wherein: At least a portion of the 1-1th to 1-nth electrodes and at least a portion of the 2-1th to 2-nth electrodes have a linear shape extending in a direction parallel to the second surface of the peripheral circuit board.

6. The semiconductor memory device according to claim 4, wherein: At least a portion of the 1-1 electrode to the 1-n electrode and at least a portion of the 2-1 electrode to the 2-n electrode have a comb shape.

7. The semiconductor memory device according to claim 4, wherein: At least a portion of the 1-1 electrode to the 1-n electrode and at least a portion of the 2-1 electrode to the 2-n electrode include: a first extending portion extending in a first direction parallel to the second surface of the peripheral circuit board, The second extending portion extends along a second direction parallel to the second surface of the peripheral circuit board and intersecting the first direction.

8. The semiconductor memory device according to claim 1, wherein: The peripheral circuit structure also includes: a second circuit element, on the first surface of the peripheral circuit board, a second wiring electrically connected to the second circuit element in the first interlayer insulating layer, a third capacitor electrode, in the capacitor dielectric layer, a fourth capacitor electrode spaced apart from the third capacitor electrode in the capacitor dielectric layer, and a second connecting through hole electrically connecting the third capacitor electrode to the second wiring by passing through the peripheral circuit board, wherein The second circuit element is configured to operate at an operating voltage different from an operating voltage of the first circuit element.

9. The semiconductor memory device according to claim 1, wherein: The peripheral circuit structure also includes: a second circuit element, on the first surface of the peripheral circuit board, a second wiring electrically connected to the second circuit element in the first interlayer insulating layer, a third capacitor electrode in the first interlayer insulating layer, and A fourth capacitor electrode is spaced apart from the third capacitor electrode in the first interlayer insulating layer.

10. The semiconductor memory device according to claim 9, wherein: The second circuit element is configured to operate at an operating voltage of the second circuit element that is lower than an operating voltage of the first circuit element.

11. A semiconductor memory device comprising: a first peripheral circuit structure; as well as a unit structure stacked on the first peripheral circuit structure and comprising a memory cell, Wherein, the first peripheral circuit structure includes: a first peripheral circuit board including a first surface facing the unit structure and a second surface opposite to the first surface, a first circuit element on the first surface of the first peripheral circuit board, and A first capacitor is on the second surface of the first peripheral circuit board.

12. The semiconductor memory device according to claim 11, wherein The unit structure includes a first bonding metal, and The first peripheral circuit structure further includes: a second bonding metal bonded to the first bonding metal, a first wiring between the first circuit element and the second bonding metal, and A connecting through-hole electrically connects the first capacitor to the first wiring by penetrating the first peripheral circuit board.

13. The semiconductor memory device according to claim 11, wherein: The first peripheral circuit structure further includes: a second circuit element on the first surface of the first peripheral circuit board, and A second capacitor is on the first surface of the first peripheral circuit board.

14. The semiconductor memory device according to claim 11, wherein: The first capacitor comprises: a capacitor dielectric layer on the second surface of the first peripheral circuit board, a first capacitor electrode in the capacitor dielectric layer, and A second capacitor electrode is in the capacitor dielectric layer and is spaced apart from the first capacitor electrode in a direction parallel to the second surface of the first peripheral circuit board.

15. The semiconductor memory device according to claim 11, further comprising: a second peripheral circuit structure, comprising a second peripheral circuit board and a second circuit element on the second peripheral circuit board, Wherein, the second peripheral circuit structure is between the first peripheral circuit structure and the unit structure.

16. The semiconductor memory device according to claim 11, further comprising: a second peripheral circuit structure, comprising a second peripheral circuit board and a second circuit element on the second peripheral circuit board, Wherein, the first peripheral circuit structure is between the second peripheral circuit structure and the unit structure.

17. The semiconductor memory device according to claim 11, wherein: At least some of the memory cells are volatile memory cells.

18. The semiconductor memory device according to claim 11, wherein At least some of the memory cells are non-volatile memory cells.

19. An electronic system comprising: Motherboard; a semiconductor memory device on the main board and comprising a peripheral circuit structure and a unit structure, the unit structure being stacked on the peripheral circuit structure; as well as a controller electrically connected to the semiconductor memory device on the main board; Wherein, the peripheral circuit structure includes: a peripheral circuit board including a first surface facing the unit structure and a second surface opposite to the first surface, a first circuit element on the first surface of the peripheral circuit board, and A capacitor is configured to provide an operating voltage to the first circuit element on the second surface of the peripheral circuit board.

20. The electronic system according to claim 19, wherein: The capacitor comprises: a capacitor dielectric layer covering the second surface of the peripheral circuit board, a first capacitor electrode stacked in the capacitor dielectric layer, and A second capacitor electrode is stacked in the capacitor dielectric layer.

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