Semiconductor memory device

Abstract

A semiconductor memory device may include an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array in which a plurality of channel pillars passing through the electrode structure are arranged in the second direction. The plurality of channel pillars includes a first pillar having an uppermost plane having a first shape and a second pillar having an uppermost plane having a second shape. The N first columns and the N second columns may be alternately arranged in a first direction different from the second direction, N being a natural number greater than or equal to 1.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202010818368.4 (application date: August 14, 2020, invention name: semiconductor memory device). Technical Field

[0002] Various embodiments relate generally to an electronic device, and more particularly, to a semiconductor memory device. Background Art

[0003] In order to meet the needs of consumers for high performance and low cost, the integration of semiconductor devices has been improved. In particular, for semiconductor memory devices, since the integration is an important factor in determining product costs, it is advantageous to increase the integration. Therefore, three-dimensional semiconductor memory devices each including memory cells arranged in a three-dimensional manner have been proposed. Summary of the invention

[0004] A semiconductor memory device having a stable structure and improved integration is described herein.

[0005] In one embodiment, a semiconductor memory device may include: an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel pillars passing through the electrode structure are arranged in a second direction. The plurality of channel pillars may include a first pillar having a first shape on the uppermost plane and a second pillar having a second shape different from the first shape on the uppermost plane. N (N is a natural number greater than or equal to 1) first pillars and N second pillars may be alternately arranged in a first direction different from the second direction.

[0006] In one embodiment, a semiconductor memory device may include: an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel pillars passing through the electrode structure are arranged in a zigzag manner in a second direction. The plurality of channel pillars may include a first pillar having a first shape on the uppermost plane and a second pillar having a second shape different from the first shape on the uppermost plane. In any row of the channel array, N (N is a natural number greater than or equal to 1) first pillars and M (M is a natural number greater than or equal to 2) second pillars are alternately arranged in a first direction different from the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1B is a block diagram schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 2 is a diagram schematically showing a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 3 is an equivalent circuit diagram schematically showing a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 4 is a plan view showing a semiconductor memory device according to a first embodiment of the present disclosure.

[0011] Figure 5 It is along Figure 4 The cross-sectional view of the semiconductor memory device according to the first embodiment of the present disclosure is taken along line AA′.

[0012] Fig. 6A and Figure 6B is a plan view showing a modified example of the semiconductor memory device according to the first embodiment of the present disclosure.

[0013] Figure 7 is a plan view showing a semiconductor memory device according to a second embodiment of the present disclosure.

[0014] Figure 8 is a plan view showing a semiconductor memory device according to a third embodiment of the present disclosure.

[0015] Fig. 9 is a plan view showing a semiconductor memory device according to a fourth embodiment of the present disclosure.

[0016] Fig.10 is a plan view showing a semiconductor memory device according to a fifth embodiment of the present disclosure.

[0017] Fig.11 is a block diagram of a configuration of a memory system according to one embodiment of the present disclosure.

[0018] Fig.12 is a block diagram of a configuration of a memory system according to one embodiment of the present disclosure.

[0019] Fig.13 is a block diagram of a configuration of a computing system according to one embodiment of the present disclosure.

[0020] Fig.14 is a block diagram of a computing system according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] With reference to the following detailed description and in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving them will become apparent. However, the scope of the present disclosure is not limited to this embodiment, and the present disclosure can be implemented in various forms. The embodiments to be described below are provided to help those skilled in the art understand the scope of the present disclosure in the technical field to which the present disclosure belongs. The present disclosure is limited only by the scope of the attached claims. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for the sake of clarity. Throughout the entire specification, the same reference numerals are used to represent the same elements.

[0022] The embodiment of the present disclosure to be described below is to provide a semiconductor memory device with a stable structure and improved integration. More specifically, the embodiment of the present disclosure to be described below provides a semiconductor memory device that can improve the integration and at the same time substantially prevent the structural instability and degradation of operating characteristics caused by the increase in integration. The semiconductor memory device may be a three-dimensional semiconductor memory device based on an electrode structure in which an interlayer dielectric film and a gate conductive film are alternately stacked multiple times. In order to improve the integration of the semiconductor memory device, the embodiment of the present disclosure relates to a plurality of channel columns passing through the electrode structure and the planar shape of their arrangement, wherein the plurality of channel columns may include a first column having a first shape on the uppermost plane and a second column having a second shape on the uppermost plane, and the first column and the second column may be alternately arranged in one direction.

[0023] Hereinafter, a semiconductor memory device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In the embodiment of the present disclosure described below, the first direction D1 may be an x-axis direction or a row direction, and the second direction D2 may be a y-axis direction or a column direction orthogonal to the first direction D1. The third direction D3 may be a z-axis direction or a vertical direction orthogonal to the first direction D1 and the second direction D2. In addition, the fourth direction D4 and the fifth direction D5 may be diagonal directions having an inclination based on or relative to the first direction D1 or the second direction D2, and may not be parallel to each other.

[0024] Meanwhile, in the embodiment of the present disclosure to be described below, it is shown that the first direction D1 and the second direction D2 are the x-axis direction and the y-axis direction, respectively; however, in a modified example, the first direction D1 may be the y-axis direction, and the second direction D2 may be the x-axis direction.

[0025] Figure 1A and Figure 1B is a block diagram schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0026] like Figure 1Aand Figure 1B As shown, a semiconductor memory device may include a peripheral circuit (PC) and a cell array (CA) disposed on a substrate (SUB).

[0027] The substrate (SUB) may be a single crystal semiconductor film. For example, the substrate SUB may be any one of a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, and an epitaxial thin film formed by a selective epitaxial growth method.

[0028] A cell array (CA) may include a plurality of memory blocks. Each memory block may include a plurality of cell strings. Each cell string may be electrically connected to a bit line, a source line, a word line, and a select line. Each cell string may include a memory cell and a select transistor connected in series. Each select line may be used as a gate of a select transistor corresponding thereto, and each word line may be used as a gate of a memory cell corresponding thereto.

[0029] The peripheral circuit (PC) may include circuit elements such as transistors (e.g., NMOS transistors and PMOS transistors), resistors, inductors, and / or capacitors. The circuit elements may be electrically connected to the cell array (CA). As an example, NMOS and PMOS transistors, resistors, and capacitors may be used as elements constituting a row decoder, a column decoder, a page buffer, and a control circuit.

[0030] like Figure 1A As shown, a semiconductor memory device according to an embodiment of the present disclosure may have a structure in which a cell array (CA) and a peripheral circuit (PC) are arranged adjacent to each other on a substrate (SUB).

[0031] In addition, if Figure 1B As shown, according to one embodiment of the present disclosure, a semiconductor memory device may have a structure in which a peripheral circuit (PC) and a cell array (CA) are sequentially stacked on a substrate (SUB). In this case, because the peripheral circuit (PC) overlaps with the cell array (CA), the area of ​​the substrate SUB occupied by the cell array (CA) and the peripheral circuit (PC) may be reduced. In one embodiment, the peripheral circuit (PC) may be located between the substrate (SUB) and the cell array (CA). The peripheral circuit (PC) may be connected to the channel pillar of the electrode structure.

[0032] Figure 2 is a diagram schematically showing a memory block of a semiconductor memory device according to one embodiment of the present disclosure.

[0033] like Figure 2As shown in , a cell array (CA) of a semiconductor memory device according to an embodiment of the present disclosure may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be arranged to be spaced apart from each other in a second direction D2 along which the bit lines BL1 to BLm extend. For example, the first memory block BLK1 to the zth memory block BLKz may be arranged to be spaced apart from each other along the second direction D2, and may include a plurality of memory cells stacked along a third direction D3.

[0034] Figure 3 is an equivalent circuit diagram schematically showing a memory block of a semiconductor memory device according to one embodiment of the present disclosure.

[0035] like Figure 3 As shown, the cell array (CA) of the semiconductor memory device may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of cell strings (SR). Each cell string (SR) may include one or more source select transistors (SST) connected in series, a plurality of memory cell transistors MC1 to MCn, and one or more drain select transistors (DST). Although Figure 3 A case where one cell string (SR) includes one source selection transistor (SST) and one drain selection transistor (DST) is shown, but each of the source selection transistor (SST) and the drain selection transistor (DST) may also be composed of a plurality of selection transistors connected in series. In this case, the number of the plurality of source selection transistors connected in series may be substantially the same as the number of the plurality of drain selection transistors connected in series, or the number of the plurality of source selection transistors connected in series may be greater than the number of the plurality of drain selection transistors connected in series.

[0036] The cell strings (SR) may be arranged in a matrix along the first direction D1 and the second direction D2 to form an array. The cell strings (SR) located on substantially the same line in the second direction D2 may be connected to substantially the same bit line. The cell strings (SR) located on substantially the same line in the first direction D1 may be commonly connected to the gate lines SSL, WL1 to WLn, and DSL.

[0037] The source selection transistor (SST), a plurality of memory cell transistors MC1 to MCn, and a drain selection transistor (DST) constituting one cell string (SR) may share one channel film. The cell string (SR) may be arranged between the bit lines BL1 to BLm and the source line SL. The gate lines SSL, WL1 to WLn, and DSL may be stacked between the bit lines BL1 to BLm and the source line SL, and the gate lines SSL, WL1 to WLn, and DSL may be electrically insulated from each other.

[0038] The source selection line SSL may be used as a gate of a source selection transistor (SST), and the word lines WL1 to WLn may be used as gates of memory cell transistors MC1 to MCn. The drain selection line DSL may be used as a gate of a drain selection transistor (DST). The word lines WL1 to WLn may be stacked and arranged in parallel. The source selection line SSL may be located below the word lines WL1 to WLn, and the drain selection line DSL may be located above the word lines WL1 to WLn.

[0039] Each of the bit lines BL1 to BLm may be connected to each of the drain selection transistors (DST) of the cell strings (SR) arranged in the second direction D2 corresponding to each of the bit lines BL1 to BLm. For example, the cell strings (SR) commonly connected to one drain selection line DSL may be respectively connected to the bit lines BL1 to BLm different from each other. Therefore, when one drain selection line DSL is selected and any one of the bit lines BL1 to BLm is selected, any one of the plurality of cell strings (SR) may be selected.

[0040] The source line SL is electrically connected to the common source line CSL. The source line SL may transmit an operating voltage applied to the common source line CSL to the cell string (SR). The operating voltage may be selectively transmitted to the cell string (SR) according to a voltage level of the source selection line SSL.

[0041] Figure 4 is a plan view showing a semiconductor memory device according to a first embodiment of the present disclosure, and Figure 5 Yes, along Figure 4 The cross-sectional view of the semiconductor memory device according to the first embodiment of the present disclosure is taken along line AA′.

[0042] like Figure 4 and Figure 5 As shown, the semiconductor memory device according to the first embodiment may include: an electrode structure 100 including a plurality of gate conductive films 34 stacked on a substrate 10; and a channel array 130, wherein a plurality of channel pillars 150 passing through the electrode structure 100 are arranged in a zigzag manner in a second direction D2. The plurality of channel pillars 150 may include a first pillar 110 having a first shape on the uppermost plane 91 and a second pillar 120 having a second shape on the uppermost plane 93. In addition, the channel array 130 may refer to a two-dimensional arrangement of the channel pillars 150 corresponding to one memory block.

[0043] The electrode structure 100 may have a structure in which the interlayer dielectric film 32 and the gate conductive film 34 are alternately stacked multiple times in the third direction D3, and the interlayer dielectric film 32 may be located at the bottom and top layers of the electrode structure 100. Among the multiple gate conductive films 34 stacked on the substrate 10, the gate conductive film 34 located at the bottom layer may be used as the gate of the source selection transistor (SST) or the source selection line SSL, and the gate conductive film 34 located at the top layer may be used as the gate of the drain selection transistor (DST) or the drain selection line DSL. In addition, the gate conductive film 34 located between the gate of the source selection transistor (SST) and the gate of the drain selection transistor (DST) may be used as the gate of the memory cell transistor or the word line WL.

[0044] The source line film 20 may be located between the substrate 10 and the electrode structure 100, and a plurality of channel pillars 150 may pass through the electrode structure 100, and a portion of each channel pillar 150 may extend to the inside of the source line film 20. In addition, a linear slit structure 140 extending in the first direction D1 may be located on each side of the channel array 130 in the second direction D2. The slit structure 140 may be used to separate a plurality of memory blocks. The slit structure 140 may include: a slit groove 62 partially extending to the inside of the source line film 20 by passing through the electrode structure 100; a spacer 64 formed on the sidewall of the slit groove 62; and a conductive film 66 gap-filled in the inside of the slit groove 62. The conductive film 66 gap-filled in the inside of the slit groove 62 may be electrically connected to the source line film 20 and used as a common source line (CSL).

[0045] Each of the plurality of channel pillars 150 may include: an opening portion 42 partially extending to the inside of the source line film 20 by passing through the electrode structure 100; a memory film 44 formed on the surface of the opening portion 42 to contact the plurality of gate conductive films 34; a channel film 46 formed on the memory film 44; a core film 48 formed on the channel film 46 to partially gap-fill the opening portion 42; and a capping film 50 formed on the core film 48 to gap-fill the remaining opening portion 42. As will be described below, in the plurality of channel pillars 150, the uppermost planes 91, 93 of the upper end of the opening portion 42 may have first and second shapes (e.g., circular or elliptical) different from each other, but the plane shapes of the lowermost planes 92, 94 of the opening portion 42 may be substantially the same as each other (e.g., circular). This is to minimize the characteristic differences between the plurality of memory cell transistors in the memory block. The opening portion 42 may have an inclined sidewall because it has a high aspect ratio. The memory film 44 may be a stacked film in which a tunnel insulating film (not shown), a charge trapping film (not shown), and a blocking film (not shown) are stacked in sequence. The tunnel insulating film and the blocking film may include an oxide, and the charge trapping film may include a nitride. The channel film 46 may include a semiconductor material (e.g., polysilicon) and may be electrically connected to the source line film 20. The core film 48 may include an insulating material. In addition, the capping film 50 may include a semiconductor material (e.g., polysilicon) and may be electrically connected to the channel film 46.

[0046] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the first direction D1, and N (N is a natural number equal to or greater than 1) first pillars 110 and N second pillars 120 may be alternately arranged in the first direction D1. The intervals between the first pillars 110 and the second pillars 120 in the first direction D1 may be substantially the same. The first embodiment shows a case where one first pillar 110 and one second pillar 120 are alternately arranged in the first direction D1 (i.e., the N value is 1).

[0047] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be arranged in a zigzag shape in the second direction D2. In this case, among the plurality of channel pillars 150, the plane centers of the channel pillars 150 located in odd rows (row 1, row 3, and row 5) may be aligned with each other along substantially the same line in the second direction D2, and the plane centers of the channel pillars 150 located in even rows (row 2, row 4, and row 6) may be aligned with each other along substantially the same line in the second direction D2.

[0048] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the fourth direction D4, and the 2N first pillars 110 and the 2N second pillars 120 may be alternately arranged in the fourth direction D4. The first embodiment shows a case where a pair of first pillars 110 and a pair of second pillars 120 are alternately arranged in the fourth direction D4 (i.e., the N value is 1). In this embodiment, the plane centers of the channel pillars 150 of the odd rows deviate from the plane centers of the channel pillars 150 of the even rows, thereby forming a zigzag shape.

[0049] The first shape and the second shape are the shapes of the uppermost plane 91 of the first column 110 and the uppermost plane 93 of the second column 120, respectively, and the first shape may be a circular shape and the second shape may be an elliptical shape having a strong (long) axis and a weak (short) axis. The long axis of the second shape may extend in the second direction D2 and may be substantially equal to or greater than the diameter of the first shape. The short axis of the second shape may extend in the first direction D1 and may be smaller than the diameter of the first shape. When the long axis of the second shape is greater than the diameter of the first shape and the short axis of the second shape is smaller than the diameter of the first shape, the length of the long axis and the length of the short axis of the second shape may be adjusted so that the outermost circumference of the second shape is substantially the same as the outermost circumference of the first shape. That is, the outermost circumference of the first shape and the outermost circumference of the second shape may be equal to each other. Here, the outermost circumference of the first shape and the outermost circumference of the second shape are formed to be equal to each other in order to substantially prevent the occurrence of characteristic differences between a plurality of memory cell transistors sharing the first column 110 and a plurality of memory cell transistors sharing the second column 120.

[0050] Meanwhile, the shapes of the uppermost plane 91 of the first pillar 110 and the uppermost plane 93 of the second pillar 120 are different from each other, but the lowermost plane 92 of the first pillar 110 and the lowermost plane 94 of the second pillar 120 may have a third shape substantially the same as the first shape (see Figure 4). Specifically, the shape of the lowermost plane 92 of the first column 110 and the lowermost plane 94 of the second column 120 may be a circular shape, and the diameter of the shape of the lowermost plane may be substantially the same as or smaller than the length of the short axis of the second shape. Therefore, the first column 110 may have a structure in which the uppermost plane 91 has a first shape (i.e., a circular shape), the lowermost plane 92 of the first column has a third shape (i.e., a circular shape), the third shape is substantially the same as the first shape, but the diameter gradually decreases from the uppermost plane 91 to the lowermost plane 92. On the other hand, the second column 120 may have a structure in which the uppermost plane 93 has a second shape (i.e., an elliptical shape), the lowermost plane 94 of the second column has a third shape (i.e., a circular shape), the third shape is different from the second shape, and the length of the major axis and the length of the minor axis of the second shape gradually decrease from the uppermost plane 93 to the lowermost plane 94, but the length of the major axis decreases more than the length of the minor axis.

[0051] As described above, in the semiconductor memory device according to the first embodiment, the plurality of channel pillars 150 include the first pillars 110 and the second pillars 120 having different uppermost plane shapes, and in the channel array 130, the N first pillars 110 and the N second pillars 120 are alternately arranged in the first direction D1, so that the size of the memory block can be reduced. In particular, the width of the memory block in the first direction D1 can be reduced, so that the chip size can be reduced and the package fit-in issue can be solved by changing the form factor of the package.

[0052] In a semiconductor memory device of a three-dimensional structure introduced to improve the integration of the semiconductor memory device, the occupied area of ​​a row decoder (X-DEC) for driving a memory cell array continuously increases in proportion to the increase in the number of stacked word lines WL in the memory cell array or the electrode structure 100. Therefore, even in a unit-under-periphery (PUC) structure in which a peripheral circuit including a row decoder is arranged below the memory cell array, the area of ​​the row decoder is larger than the occupied area of ​​a stepped contact region for connecting the memory cell array and the peripheral circuit, which becomes a factor inhibiting chip size reduction. In particular, due to the contact connection relationship with the memory cell array, the row decoder has a strip shape with a long axis extending in the first direction D1, resulting in a package assembly problem.

[0053] Fig. 6A and Figure 6B is a plan view showing a modified example of the semiconductor memory device according to the first embodiment of the present disclosure.

[0054] like Fig. 6A and Figure 6BAs shown, in the semiconductor memory device according to the modified example of the first embodiment, the first shape and the second shape are the uppermost planar shapes of the first pillar 110 and the second pillar 120, respectively, and the first shape may be a circular shape and the second shape may be an elliptical shape having a major axis and a minor axis.

[0055] Reference Fig. 6A , the major axis of the second shape may extend in the fourth direction D4 and may be substantially equal to or greater than the diameter of the first shape. That is, in the channel array 130, all second pillars 120 each having the second shape may each have a shape in which the major axis extends in the fourth direction D4.

[0056] On the other hand, refer to Figure 6B , the uppermost planes of the second pillars 120 located in the odd rows (row 1, row 3, and row 5) in the second direction D2 may each have a second shape in which the major axis extends in the fourth direction D4, and the uppermost planes of the second pillars 120 located in the even rows (row 2, row 4, and row 6) in the second direction D2 may each have a second shape in which the major axis extends in a fifth direction D5 intersecting the fourth direction D4. For some embodiments, the intersecting directions refer to different directions.

[0057] Here, the major axis of the second shape extends in the fourth direction D4 or the fifth direction D5, so it is easier to increase the length of the major axis of the second shape than in the first embodiment. Therefore, it is easier to make the outermost perimeter of the first shape substantially the same as the outermost perimeter of the second shape than in the first embodiment.

[0058] As described above, in the semiconductor memory device according to the modified example of the first embodiment, the plurality of channel pillars 150 include the first pillars 110 and the second pillars 120 having different uppermost plane shapes, and in the channel array 130, the N first pillars 110 and the N second pillars 120 are alternately arranged in the first direction D1, so that the size of the memory block can be reduced. In particular, the width of the memory block in the first direction D1 can be reduced, so that the chip size can be reduced and the packaging assembly problem can be solved.

[0059] In addition, the second shape is an elliptical shape having a major axis and a minor axis, and the major axis of the second shape extends in the fourth direction D4 or the fifth direction D5, and therefore, the occurrence of characteristic differences between multiple memory cell transistors sharing the first column 110 and multiple memory cell transistors sharing the second column 120 can be basically and effectively prevented.

[0060] Figure 7is a plan view showing a semiconductor memory device according to a second embodiment of the present disclosure. Hereinafter, for convenience of description, the same elements as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0061] like Figure 7 As shown, the semiconductor memory device according to the second embodiment may include: an electrode structure 100 including a plurality of gate conductive films 34 stacked on a substrate 10; and a channel array 130, wherein a plurality of channel pillars 150 passing through the electrode structure 100 are arranged in a zigzag shape in a second direction D2. The plurality of channel pillars 150 may include a first pillar 110 whose uppermost plane has a first shape and a second pillar 120 whose uppermost plane has a second shape.

[0062] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the first direction D1, and N (N is a natural number greater than or equal to 1) first pillars 110 and N second pillars 120 may be alternately arranged in the first direction D1. The second embodiment shows a case where one first pillar 110 and one second pillar 120 are alternately arranged in the first direction D1 (i.e., the N value is 1).

[0063] In the channel array 130 , plane centers of the plurality of channel pillars 150 may be arranged in a zigzag manner in the second direction D2 .

[0064] In the channel array 130 , planar centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the fourth direction D4 , and the channel pillars 150 each having substantially the same uppermost planar shape may be arranged in the fourth direction D4 .

[0065] The first shape and the second shape are the uppermost planar shapes of the first column 110 and the second column 120, respectively, and the first shape may be a circular shape, and the second shape may be an elliptical shape having a major axis and a minor axis. The major axis of the second shape may extend in the second direction D2 and may be substantially equal to or greater than the diameter of the first shape. The minor axis of the second shape may extend in the first direction D1 and may be smaller than the diameter of the first shape. When the major axis of the second shape is greater than the diameter of the first shape and the minor axis of the second shape is smaller than the diameter of the first shape, the length of the major axis and the length of the minor axis of the second shape may be adjusted so that the outermost perimeter of the second shape is substantially the same as the outermost perimeter of the first shape. That is, the outermost perimeter of the first shape and the outermost perimeter of the second shape may be equal to each other. Here, the outermost perimeter of the first shape and the outermost perimeter of the second shape are formed to be equal to each other in order to substantially prevent the occurrence of characteristic differences between a plurality of memory cell transistors sharing the first column 110 and a plurality of memory cell transistors sharing the second column 120.

[0066] Meanwhile, the uppermost plane shapes of the first pillar 110 and the second pillar 120 are different from each other, but the lowermost planes of the first pillar 110 and the second pillar 120 may have a third shape substantially the same as the first shape (see Figure 7 dotted line). Specifically, each of the lowermost planar shapes of the first column 110 and the second column 120 may be a circular shape, and the diameter of the lowermost planar shape may be substantially equal to or less than the length of the minor axis of the second shape. Therefore, the first column 110 may have a structure in which the uppermost planar shape (i.e., circular shape) and the lowermost planar shape (i.e., circular shape) are substantially the same as each other, but the diameter gradually decreases from the top to the bottom. On the other hand, the second column 120 may have a structure in which the uppermost planar shape (i.e., elliptical shape) and the lowermost planar shape (i.e., circular shape) are different from each other, and the length of the major axis and the length of the minor axis gradually decrease from the top to the bottom, but the length of the major axis decreases more than the length of the minor axis.

[0067] As described above, in the semiconductor memory device according to the second embodiment, the plurality of channel pillars 150 include the first pillars 110 and the second pillars 120 having different uppermost plane shapes, and in the channel array 130, the N first pillars 110 and the N second pillars 120 are alternately arranged in the first direction D1, so that the size of the memory block can be reduced. In particular, the width of the memory block in the first direction D1 can be reduced, so that the chip size can be reduced and the packaging assembly problem can be solved.

[0068] At the same time, as mentioned above Fig. 6A and Figure 6B As described above, in a modification of the semiconductor memory device according to the second embodiment, the uppermost planar shape of the second pillar 120 (i.e., the second shape) is an elliptical shape having a major axis and a minor axis, and the major axis of the second shape can extend in the fourth direction D4 or the fifth direction D5 and can be substantially equal to or greater than the diameter of the first shape.

[0069] Figure 8 is a plan view showing a semiconductor memory device according to a third embodiment of the present disclosure. Hereinafter, for convenience of description, the same elements as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0070] like Figure 8As shown, the semiconductor memory device according to the third embodiment may include: an electrode structure 100 including a plurality of gate conductive films 34 stacked on a substrate 10; and a channel array 130, wherein a plurality of channel pillars 150 passing through the electrode structure 100 are arranged in a zigzag manner in a second direction D2. The plurality of channel pillars 150 may include a first pillar 110 whose uppermost plane has a first shape and a second pillar 120 whose uppermost plane has a second shape.

[0071] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the first direction D1, and N (N is a natural number greater than or equal to 1) first pillars 110 and M (M is a natural number greater than or equal to 2) second pillars 120 may be alternately arranged in the first direction D1. The third embodiment shows a case where one first pillar 110 and two second pillars 120 are alternately arranged in the first direction D1 (i.e., the N value is 1 and the M value is 2).

[0072] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be arranged in a zigzag manner in the second direction D2. In this case, among the plurality of channel pillars 150, the plane centers of the channel pillars 150 located in odd rows (row 1, row 3, and row 5) may be aligned with each other along substantially the same line in the second direction D2, and the plane centers of the channel pillars 150 located in even rows (row 2, row 4, and row 6) may be aligned with each other along substantially the same line in the second direction D2. In this embodiment, the plane centers of the channel pillars 150 of the odd rows deviate from the plane centers of the channel pillars 150 of the even rows, thereby forming a zigzag shape.

[0073] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the fourth direction D4, and 2N first pillars 110 and 2M second pillars 120 may be alternately arranged in the fourth direction D4. The third embodiment shows a case where two first pillars 110 and four second pillars 120 are alternately arranged in the fourth direction D4 (i.e., the N value is 1 and the M value is 2).

[0074] The first shape and the second shape are the uppermost planar shapes of the first column 110 and the second column 120, respectively, and the first shape may be a circular shape and the second shape may be an elliptical shape having a major axis and a minor axis. The major axis of the second shape may extend in the second direction D2 and may be substantially equal to or greater than the diameter of the first shape. The minor axis of the second shape may extend in the first direction D1 and may be smaller than the diameter of the first shape. When the major axis of the second shape is greater than the diameter of the first shape and the minor axis of the second shape is smaller than the diameter of the first shape, the length of the major axis and the length of the minor axis of the second shape may be adjusted so that the outermost perimeter of the second shape is substantially the same as the outermost perimeter of the first shape. That is, the outermost perimeter of the first shape and the outermost perimeter of the second shape may be equal to each other. Here, the outermost perimeter of the first shape and the outermost perimeter of the second shape are formed to be equal to each other in order to substantially prevent the occurrence of characteristic differences between a plurality of memory cell transistors sharing the first column 110 and a plurality of memory cell transistors sharing the second column 120.

[0075] Meanwhile, the uppermost plane shapes of the first pillar 110 and the second pillar 120 are different from each other, but the lowermost planes of the first pillar 110 and the second pillar 120 may have a third shape substantially the same as the first shape (see Figure 8 dotted line). Specifically, each of the lowermost planar shapes of the first column 110 and the second column 120 may be a circular shape, and the diameter of the lowermost planar shape may be substantially equal to or less than the length of the minor axis of the second shape. Therefore, the first column 110 may have a structure in which the uppermost planar shape (i.e., circular shape) and the lowermost planar shape (i.e., circular shape) are substantially the same as each other, but the diameter gradually decreases from the top to the bottom. On the other hand, the second column 120 may have a structure in which the uppermost planar shape (i.e., elliptical shape) and the lowermost planar shape (i.e., circular shape) are different from each other, and the length of the major axis and the length of the minor axis gradually decrease from the top to the bottom, but the length of the major axis decreases more than the length of the minor axis.

[0076] As described above, in the semiconductor memory device according to the third embodiment, the plurality of channel pillars 150 include the first pillars 110 and the second pillars 120 having different uppermost plane shapes, and in the channel array 130, the N first pillars 110 and the M second pillars 120 are alternately arranged in the first direction D1, so that the size of the memory block can be reduced. In particular, the width of the memory block in the first direction D1 can be reduced, so that the chip size can be reduced and the packaging assembly problem can be solved.

[0077] At the same time, as mentioned above Fig. 6A and Figure 6BAs described above, in a modified example of the semiconductor memory device according to the third embodiment, the uppermost planar shape of the second pillar 120 (i.e., the second shape) is an elliptical shape having a major axis and a minor axis, and the major axis of the second shape can extend in the fourth direction D4 or the fifth direction D5 and can be substantially equal to or greater than the diameter of the first shape.

[0078] Fig. 9 is a plan view showing a semiconductor memory device according to a fourth embodiment of the present disclosure. Hereinafter, for convenience of description, the same elements as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0079] like Fig. 9 As shown, the semiconductor memory device according to the fourth embodiment may include: an electrode structure 100 including a plurality of gate conductive films 34 stacked on a substrate 10; and a channel array 130, wherein a plurality of channel pillars 150 passing through the electrode structure 100 are arranged in a zigzag manner in a second direction D2. The plurality of channel pillars 150 may include a first pillar 110 whose uppermost plane has a first shape and a second pillar 120 whose uppermost plane has a second shape.

[0080] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the first direction D1. In this case, in odd rows (row 1, row 3, and row 5), N (N is a natural number greater than or equal to 1) first pillars 110 and M (M is a natural number greater than or equal to 2) second pillars 120 may be alternately arranged in the first direction D1. On the other hand, in even rows (row 2, row 4, and row 6), M first pillars 110 and N second pillars 120 may be alternately arranged in the first direction D1. The fourth embodiment shows a case where one first pillar 110 and two second pillars 120 are alternately arranged in odd rows (row 1, row 3, and row 5) and two first pillars 110 and one second pillar 120 are alternately arranged in even rows (row 2, row 4, and row 6). The fourth embodiment shows a case where the N value is 1 and the M value is 2.

[0081] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be arranged in a zigzag shape in the second direction D2. In this case, among the plurality of channel pillars 150, the plane centers of the channel pillars 150 located in odd rows (row 1, row 3, and row 5) may be aligned with each other along substantially the same line in the second direction D2, and the plane centers of the channel pillars 150 located in even rows (row 2, row 4, and row 6) may be aligned with each other along substantially the same line in the second direction D2. In this embodiment, the plane centers of the channel pillars 150 of the odd rows deviate from the plane centers of the channel pillars 150 of the even rows, thereby forming a zigzag shape.

[0082] In the channel array 130 , plane centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the fourth direction D4 .

[0083] The first shape and the second shape are the uppermost planar shapes of the first column 110 and the second column 120, respectively, and the first shape may be a circular shape and the second shape may be an elliptical shape having a major axis and a minor axis. The major axis of the second shape may extend in the second direction D2 and may be substantially equal to or greater than the diameter of the first shape. The minor axis of the second shape may extend in the first direction D1 and may be smaller than the diameter of the first shape. When the major axis of the second shape is greater than the diameter of the first shape and the minor axis of the second shape is smaller than the diameter of the first shape, the length of the major axis and the length of the minor axis of the second shape may be adjusted so that the outermost perimeter of the second shape is substantially the same as the outermost perimeter of the first shape. That is, the outermost perimeter of the first shape and the outermost perimeter of the second shape may be equal to each other. Here, the outermost perimeter of the first shape and the outermost perimeter of the second shape are formed to be equal to each other in order to substantially prevent the occurrence of characteristic differences between a plurality of memory cell transistors sharing the first column 110 and a plurality of memory cell transistors sharing the second column 120.

[0084] Meanwhile, the uppermost plane shapes of the first pillar 110 and the second pillar 120 are different from each other, but the lowermost planes of the first pillar 110 and the second pillar 120 may have a third shape substantially the same as the first shape (see Fig. 9 dotted line). Specifically, each of the lowermost planar shapes of the first column 110 and the second column 120 may be a circular shape, and the diameter of the lowermost planar shape may be substantially equal to or less than the length of the minor axis of the second shape. Therefore, the first column 110 may have a structure in which the uppermost planar shape (i.e., circular shape) and the lowermost planar shape (i.e., circular shape) are substantially the same, but the diameter gradually decreases from the top to the bottom. On the other hand, the second column 120 may have a structure in which the uppermost planar shape (i.e., elliptical shape) and the lowermost planar shape (i.e., circular shape) are different from each other, and the length of the major axis and the length of the minor axis gradually decrease from the top to the bottom, but the length of the major axis decreases more than the length of the minor axis.

[0085] As described above, in the semiconductor memory device according to the fourth embodiment, the plurality of channel pillars 150 include the first pillars 110 and the second pillars 120 having different uppermost plane shapes, and the N first pillars 110 and the M second pillars 120 are alternately arranged in the odd rows (row 1, row 3, and row 5) in the first direction D1, and the M first pillars 110 and the N second pillars 120 are alternately arranged in the even rows (row 2, row 4, and row 6) in the first direction D1, so the size of the memory block can be reduced. In particular, the width of the memory block in the first direction D1 can be reduced, so that the chip size can be reduced and the packaging assembly problem can be solved.

[0086] At the same time, as mentioned above Fig. 6A and Figure 6B As described above, in a modification of the semiconductor memory device according to the fourth embodiment, the uppermost planar shape of the second pillar 120 (i.e., the second shape) is an elliptical shape having a major axis and a minor axis, and the major axis of the second shape can extend in the fourth direction D4 or the fifth direction D5 and can be substantially equal to or greater than the diameter of the first shape.

[0087] Fig.10 is a plan view showing a semiconductor memory device according to a fifth embodiment of the present disclosure. Hereinafter, for convenience of description, the same elements as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0088] like Fig.10 As shown, the semiconductor memory device according to the fifth embodiment may include: an electrode structure 100 including a plurality of gate conductive films 34 stacked on a substrate 10; and a channel array 130, wherein a plurality of channel pillars 150 passing through the electrode structure 100 are arranged in a checkerboard manner. The plurality of channel pillars 150 may include a first pillar 110 whose uppermost plane has a first shape and a second pillar 120 whose uppermost plane has a second shape.

[0089] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the first direction D1, and N (N is a natural number greater than or equal to 1) first pillars 110 and N second pillars 120 may be alternately arranged in the first direction D1. The fifth embodiment shows a case where one first pillar 110 and one second pillar 120 are alternately arranged in the first direction D1 (i.e., the N value is 1).

[0090] In the channel array 130, the plane centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the second direction D2, and the N first pillars 110 and the N second pillars 120 may be alternately arranged in the second direction D2. The fifth embodiment shows a case where one first pillar 110 and one second pillar 120 are alternately arranged in the second direction D2 (i.e., the N value is 1).

[0091] In the channel array 130 , planar centers of the plurality of channel pillars 150 may be aligned along substantially the same line in the fourth direction D4 , and the channel pillars 150 each having substantially the same uppermost planar shape may be arranged in the fourth direction D4 .

[0092] The first shape and the second shape are the uppermost planar shapes of the first column 110 and the second column 120, respectively, and the first shape may be a circular shape and the second shape may be an elliptical shape having a major axis and a minor axis. The major axis of the second shape may extend in the second direction D2 and may be substantially equal to or greater than the diameter of the first shape. The minor axis of the second shape may extend in the first direction D1 and may be smaller than the diameter of the first shape. When the major axis of the second shape is greater than the diameter of the first shape and the minor axis of the second shape is smaller than the diameter of the first shape, the length of the major axis and the length of the minor axis of the second shape may be adjusted so that the outermost perimeter of the second shape is substantially the same as the outermost perimeter of the first shape. That is, the outermost perimeter of the first shape and the outermost perimeter of the second shape may be equal to each other. Here, the outermost perimeter of the first shape and the outermost perimeter of the second shape are formed to be equal to each other in order to substantially prevent the occurrence of characteristic differences between a plurality of memory cell transistors sharing the first column 110 and a plurality of memory cell transistors sharing the second column 120.

[0093] Meanwhile, the uppermost plane shapes of the first pillar 110 and the second pillar 120 are different from each other, but the lowermost planes of the first pillar 110 and the second pillar 120 may have a third shape substantially the same as the first shape (see Fig.10 In particular, each of the lowermost planar shapes of the first column 110 and the second column 120 may be a circular shape, and the diameter of the lowermost planar shape may be substantially equal to or less than the length of the minor axis of the second shape. Therefore, the first column 110 may have a structure in which the uppermost planar shape (i.e., circular shape) and the lowermost planar shape (i.e., circular shape) are substantially the same as each other, but the diameter gradually decreases from the top to the bottom. On the other hand, the second column 120 may have a structure in which the uppermost planar shape (i.e., elliptical shape) and the lowermost planar shape (i.e., circular shape) are different from each other, and the length of the major axis and the length of the minor axis gradually decrease from the top to the bottom, but the length of the major axis decreases more than the length of the minor axis.

[0094] As described above, in the semiconductor memory device according to the fifth embodiment, the plurality of channel pillars 150 include the first pillar 110 and the second pillar 120 having different uppermost plane shapes, and in the channel array 130, the N first pillars 110 and the N second pillars 120 are alternately arranged in each of the first direction D1 and the second direction D2, so that the size of the memory block can be reduced. In particular, a greater number of channel pillars 150 can be arranged in substantially the same area, and the width of the memory block in the first direction D1 can be reduced, so that the chip size can be reduced and the packaging assembly problem can be solved.

[0095] At the same time, as mentioned above Fig. 6A and Figure 6B As described above, in a modification of the semiconductor memory device according to the fifth embodiment, the uppermost planar shape of the second pillar 120 (i.e., the second shape) is an elliptical shape having a major axis and a minor axis, and the major axis of the second shape can extend in the fourth direction D4 or the fifth direction D5 and can be substantially equal to or greater than the diameter of the first shape.

[0096] Fig.11 is a block diagram of a configuration of a memory system 1000 according to one embodiment of the present disclosure.

[0097] like Fig.11 As shown, the memory system 1000 may include a memory device 1200 and a controller 1100 .

[0098] The memory device 1200 may be used to store various data types such as text, graphics, and software code. The memory device 1200 may be a non-volatile memory. The memory device 1200 may be a memory device as described above with reference to FIG. Figures 4 to 10Semiconductor device described. In addition, the memory device 1200 may include: an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel pillars passing through the electrode structure are arranged in a second direction, wherein the plurality of channel pillars include a first pillar having a first shape on the uppermost plane and a second pillar having a second shape on the uppermost plane, and N (N is a natural number greater than or equal to 1) first pillars and N second pillars are alternately arranged in a first direction intersecting the second direction. In addition, the memory device 1200 may include: an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel pillars passing through the electrode structure are arranged in a zigzag shape in the second direction, wherein the plurality of channel pillars include a first pillar having a first shape on the uppermost plane and a second pillar having a second shape different from the first shape on the uppermost plane, and in any one row of the channel array, N (N is a natural number greater than or equal to 1) first pillars and M (M is a natural number greater than or equal to 2) second pillars are alternately arranged in a first direction intersecting the second direction. Since the memory device 1200 is formed and manufactured in the above-described manner, a detailed description thereof will be omitted.

[0099] The controller 1100 may be coupled to the host and the memory device 1200, and may access the memory device 1200 in response to a request from the host. For example, the controller 1100 may control read, write, erase, and background operations of the memory device 1200.

[0100] The controller 1100 may include a random access memory (RAM) 1110 , a central processing unit (CPU) 1120 , a host interface 1130 , an error correction code (ECC) circuit 1140 , and a memory interface 1150 .

[0101] The RAM 1110 may be used as an operation memory of the CPU 1120, a cache memory between the memory device 1200 and the host, and a buffer memory between the memory device 1200 and the host. The RAM 1110 may be replaced by a static random access memory (SRAM) or a read only memory (ROM).

[0102] The host interface 1130 can interface with the host. For example, the controller 1100 can communicate with the host through one of various interface protocols including a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a dedicated protocol.

[0103] The ECC circuit 1140 may detect and correct an error included in data read from the memory device 1200 by using an error correction code (ECC).

[0104] The memory interface 1150 may interface with the memory device 1200. For example, the memory interface 1150 may include a NAND interface or a NOR interface.

[0105] For example, the controller 1100 may further include a buffer memory (not shown) configured to temporarily store data. The buffer memory may temporarily store data transmitted from the outside through the host interface 1130, or temporarily store data transmitted from the memory device 1200 through the memory interface 1150. In addition, the controller 1100 may further include a ROM storing code data for interfacing with the host.

[0106] As described above, since the memory system 1000 according to the embodiment of the present disclosure may be reliably manufactured and includes the memory device 1200 having a stable structure and improved characteristics, the characteristics of the memory system 1000 may also be improved.

[0107] Fig.12 1 is a block diagram of a configuration of a memory system 1000 ′ according to one embodiment of the present disclosure. Hereinafter, description of common contents with the previously described embodiments is omitted.

[0108] like Fig.12 As shown, the memory system 1000' may include a memory device 1200' and a controller 1100. In addition, the controller 1100 may include a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, and a memory interface 1150.

[0109] The memory device 1200' may be a non-volatile memory device. The memory device 1200' may be the above reference Figures 4 to 10Semiconductor device described. In addition, the memory device 1200' may include an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel columns passing through the electrode structure are arranged in a second direction. The plurality of channel columns include a first column having a first shape on the uppermost plane and a second column having a second shape on the uppermost plane, and N (N is a natural number greater than or equal to 1) first columns and N second columns are alternately arranged in a first direction intersecting the second direction. In addition, the memory device 1200' may include: an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel columns passing through the electrode structure are arranged in a zigzag shape in the second direction. The plurality of channel columns include a first column having a first shape on the uppermost plane and a second column having a second shape different from the first shape on the uppermost plane, and in any row of the channel array, N (N is a natural number greater than or equal to 1) first columns and M (M is a natural number greater than or equal to 2) second columns are alternately arranged in a first direction intersecting the second direction. Since the memory device 1200 ′ is formed and manufactured in the above-described manner, a detailed description thereof will be omitted.

[0110] In addition, the memory device 1200' may be a multi-chip package consisting of a plurality of memory chips. The plurality of memory chips may be divided into a plurality of groups. The plurality of groups may communicate with the controller 1100 through the first channel CH1 to the kth channel CHk. In addition, the memory chips included in a single group may be suitable for communicating with the controller 1100 through a common channel. The memory system 1000' may be modified so that a single memory chip may be connected to a single channel.

[0111] As described above, since the memory system 1000' according to the embodiment of the present disclosure can be reliably manufactured and includes the memory device 1200' having a stable structure and improved characteristics, the characteristics of the memory system 1000' can also be improved. In addition, by forming the memory device 1200' using a multi-chip package, the data storage capacity of the memory system 1000' can be further increased.

[0112] Fig.13 2 is a block diagram of a configuration of a computing system 2000 according to one embodiment of the present disclosure. Hereinafter, descriptions of common contents with the previously described embodiments are omitted.

[0113] like Fig.13 As shown, the computing system 2000 may include a memory device 2100 , a CPU 2200 , a random access memory (RAM) 2300 , a user interface 2400 , a power supply 2500 , and a system bus 2600 .

[0114] The memory device 2100 may store data input through the user interface 2400 and data processed by the CPU 2200. In addition, the memory device 2100 may be electrically coupled to the CPU 2200, the RAM 2300, the user interface 2400, and the power supply 2500. For example, the memory device 2100 may be coupled to the system bus 2600 through a controller (not shown), or directly coupled to the system bus 2600. When the memory device 2100 is directly coupled to the system bus 2600, the function of the controller may be performed by the CPU 2200 and the RAM 2300.

[0115] The memory device 2100 may be a non-volatile memory. Figures 4 to 10 The semiconductor memory device described. The memory device 2100 may include an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel pillars passing through the electrode structure are arranged in a second direction, wherein the plurality of channel pillars include a first pillar having a first shape on the uppermost plane and a second pillar having a second shape on the uppermost plane, and N (N is a natural number greater than or equal to 1) first pillars and N second pillars are alternately arranged in a first direction intersecting the second direction. In addition, the memory device 2100 may include: an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel pillars passing through the electrode structure are arranged in a zigzag shape in the second direction, wherein the plurality of channel pillars include a first pillar having a first shape on the uppermost plane and a second pillar having a second shape different from the first shape on the uppermost plane, and in any row of the channel array, N (N is a natural number greater than or equal to 1) first pillars and M (M is a natural number greater than or equal to 2) second pillars are alternately arranged in a first direction intersecting the second direction. Since the memory device 2100 is formed and manufactured in the manner described above, a detailed description thereof will be omitted.

[0116] In addition, as mentioned above Fig.12 As described above, the memory device 2100 may be a multi-chip package consisting of a plurality of memory chips.

[0117] The computing system 2000 having the above configuration may be one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a three-dimensional (3D) television, a digital recorder, a digital audio player, a digital photo recorder, a digital image player, a digital video recorder, a digital video player, a device for sending / receiving information in a wireless environment, one of various electronic devices for a home network, one of various electronic devices for a computer network, one of various electronic devices for a telematics network, an RFID device, and / or one of various devices for a computing system, and the like.

[0118] As described above, since the computing system 2000 according to one embodiment of the present disclosure may be reliably manufactured and include the memory device 2100 having a stable structure and improved characteristics, the characteristics of the computing system 2000 may also be improved.

[0119] Fig.14 is a block diagram of a computing system 3000 according to one embodiment of the present disclosure.

[0120] like Fig.14 As shown, the computing system 3000 may include a software layer including an operating system 3100, an application 3200, a file system 3300, and a translation layer 3400. In addition, the computing system 3000 may include a hardware layer such as a memory device 3500.

[0121] The operating system 3100 manages software and hardware resources of the computing system 3000. The operating system 3100 may control program execution of the central processing unit. The application 3200 may include various application programs executed by the computing system 3000. The application 3200 may be an entity executed by the operating system 3100.

[0122] The file system 3300 may refer to a logical structure configured to manage data and files present in the computing system 3000. The file system 3300 may organize files or data to be stored in the memory device 3500 according to rules. The file system 3300 may be determined according to the operating system 3100 used in the computing system 3000. For example, when the operating system 3100 is a system based on Microsoft Windows, the file system 3300 may be a file allocation table (FAT) or an NT file system (NTFS). In addition, when the operating system 3100 is a system based on Unix / Linux, the file system 3300 may be an extended file system (EXT), a Unix file system (UFS), or a journaled file system (JFS).

[0123] Fig.14 The operating system 3100, the application 3200, and the file system 3300 are shown in separate blocks. However, the application 3200 and the file system 3300 may be included in the operating system 3100.

[0124] The translation layer 3400 may translate an address suitable for the memory device 3500 in response to a request from the file system 3300. For example, the translation layer 3400 may translate a logical address generated by the file system 3300 into a physical address of the memory device 3500. Mapping information of the logical address and the physical address may be stored in an address translation table. For example, the translation layer 3400 may be a flash translation layer (FTL) or a universal flash link layer (ULL), etc.

[0125] The memory device 3500 may be a non-volatile memory. The memory device 3500 may be the memory device described above with reference to Figures 4 to 10Semiconductor memory device described. In addition, the memory device 3500 may include an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel pillars passing through the electrode structure are arranged in a second direction, wherein the plurality of channel pillars include a first pillar having a first shape on the uppermost plane and a second pillar having a second shape on the uppermost plane, and N (N is a natural number greater than or equal to 1) first pillars and N second pillars are alternately arranged in a first direction intersecting the second direction. In addition, the memory device 3500 may include an electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel pillars passing through the electrode structure are arranged in a zigzag shape in the second direction, wherein the plurality of channel pillars include a first pillar having a first shape on the uppermost plane and a second pillar having a second shape different from the first shape on the uppermost plane, and in any one row of the channel array, N (N is a natural number greater than or equal to 1) first pillars and M (M is a natural number greater than or equal to 2) second pillars are alternately arranged in a first direction intersecting the second direction. Since the memory device 3500 is formed and manufactured in the above-described manner, a detailed description thereof will be omitted.

[0126] The computing system 3000 having the above configuration can be divided into an operating system layer operating in the upper layer area and a controller layer operating in the lower layer area. The operating system 3100, the application 3200, and the file system 3300 can be included in the operating system layer and driven by the operating memory. In addition, the conversion layer 3400 can be included in the operating system layer or the controller layer.

[0127] As described above, since the computing system 3000 according to one embodiment of the present disclosure may be reliably manufactured and include the memory device 3500 having a stable structure and improved characteristics, the characteristics of the computing system 3000 may also be improved.

[0128] Although the present disclosure has been described in detail with reference to the preferred embodiments, the present disclosure is not limited to these embodiments, and various modifications can be made by those skilled in the art within the technical scope of the present disclosure.

[0129] CROSS-REFERENCE TO RELATED APPLICATIONS

[0130] This application claims the benefit of Korean Application No. 10-2020-0046485 filed on April 17, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: An electrode structure, the electrode structure comprising a plurality of gate conductive films stacked on a substrate; as well as a channel array, in which a plurality of channel pillars pass through the electrode structure, wherein the plurality of channel pillars include at least one first pillar and at least one second pillar, the upper surface of the first pillar includes a first shape, the upper surface of the second pillar includes a second shape, the second shape is different from the first shape regardless of orientation, and the upper surface of the first pillar and the upper surface of the second pillar are coplanar, and The first columns and the second columns are alternately arranged in the same row in the first direction.

2. The semiconductor memory device according to claim 1, wherein In the channel array, the plane centers of the plurality of channel pillars are aligned with each other in the first direction, and the first pillars and the second pillars are arranged in a zigzag manner in a second direction different from the first direction, and Among the plurality of channel pillars, the plane centers of the channel pillars located in odd rows are aligned with each other in the second direction, and the plane centers of the channel pillars located in even rows are aligned with each other in the second direction.

3. The semiconductor memory device according to claim 1, wherein: In the channel array, plane centers of the plurality of channel pillars are aligned with each other in each of the first direction and a second direction different from the first direction, and Wherein, N first columns and N second columns are alternately arranged in the second direction, and N is a natural number greater than or equal to 1.

4. The semiconductor memory device according to claim 1, wherein: In the channel array, the plane centers of the plurality of channel pillars are aligned with each other in an oblique direction having an inclination relative to the first direction, and 2N first pillars and 2N second pillars are alternately arranged in the oblique direction, and Wherein, N is a natural number greater than or equal to 1.

5. The semiconductor memory device according to claim 1, wherein: In the channel array, plane centers of the plurality of channel pillars are aligned with each other in an oblique direction having an inclination with respect to the first direction, and a plurality of channel pillars each having the same upper surface shape are arranged in the oblique direction.

6. The semiconductor memory device according to claim 1, wherein: The first shape comprises a circular shape, and the second shape comprises an elliptical shape having a major axis and a minor axis, and The length of the minor axis of the second shape is smaller than the diameter of the first shape, and the length of the major axis of the second shape is equal to or greater than the diameter of the first shape.

7. The semiconductor memory device according to claim 6, wherein: The major axis of the second shape extends in a second direction different from the first direction or in an oblique direction having an inclination with respect to the first direction.

8. The semiconductor memory device according to claim 6, wherein: In the channel array, the long axis of the second shape of each of the second columns located in odd rows in the second direction extends in a first oblique direction having an inclination relative to the first direction, and wherein the long axis of the second shape of each of the second columns located in even rows in the second direction extends in a second oblique direction different from the first oblique direction.

9. The semiconductor memory device according to claim 1, wherein: The first shape comprises a circular shape; The second shape comprises an elliptical shape having a major axis and a minor axis; A lowermost plane of each of the plurality of channel pillars has a third shape that is the same as the first shape; and The diameter of the third shape is equal to or less than the length of the minor axis of the second shape.

10. The semiconductor memory device according to claim 1, wherein Each of the plurality of channel pillars comprises: an opening portion, the opening portion passing through the electrode structure; a memory film formed on a side wall of the opening portion to contact the plurality of gate conductive films and including a tunnel insulating film, a charge trap film, and a blocking film sequentially stacked in the opening portion; a channel film formed on the memory film; a core film formed on the channel film and partially gap-filling the opening portion; and A cover film is formed on the core film and gap-fills the remaining opening portion and is electrically connected to the channel film.

11. A semiconductor memory device, the semiconductor memory device comprising: An electrode structure, the electrode structure comprising a plurality of gate conductive films stacked on a substrate; as well as a channel array, in which a plurality of channel pillars passing through the electrode structure are arranged in a zigzag manner in a second direction, The plurality of channel pillars include a first pillar and a second pillar, the upper surface of the first pillar has a first shape, the upper surface of the second pillar has a second shape, the second shape is different from the first shape and has nothing to do with the orientation, and In any one row of the channel array, N first pillars and M second pillars are alternately arranged in a first direction different from the second direction, wherein N is a natural number greater than or equal to 1, and M is a natural number greater than or equal to 1.

12. The semiconductor memory device according to claim 11, wherein In odd-numbered rows of the channel array, the N first pillars and the M second pillars are alternately arranged in the first direction, and In even-numbered rows of the channel array, M first pillars and N second pillars are alternately arranged in the first direction.

13. The semiconductor memory device according to claim 11, wherein: In the channel array, the plane centers of the plurality of channel pillars are aligned with each other in the first direction, and Among the plurality of channel pillars, plane centers of the channel pillars located in odd-numbered rows are aligned with each other in the second direction, and plane centers of the channel pillars located in even-numbered rows are aligned with each other in the second direction.

14. The semiconductor memory device according to claim 11, wherein: In the channel array, plane centers of the plurality of channel pillars are aligned with each other in an oblique direction having an inclination relative to the first direction, and 2N first pillars and 2M second pillars are alternately arranged in the oblique direction.

15. The semiconductor memory device according to claim 11, wherein In the channel array, the plane centers of the plurality of channel pillars are aligned with each other in an oblique direction having an inclination relative to the first direction, and the plurality of channel pillars each having the same upper surface shape are arranged in the oblique direction.

16. The semiconductor memory device according to claim 11, wherein The first shape comprises a circular shape, and the second shape comprises an elliptical shape having a major axis and a minor axis, and The length of the minor axis of the second shape is smaller than the diameter of the first shape, and the length of the major axis of the second shape is equal to or greater than the diameter of the first shape.

17. The semiconductor memory device according to claim 16, wherein: The major axis of the second shape extends in the second direction or in an oblique direction having an inclination with respect to the first direction.

18. The semiconductor memory device according to claim 16, wherein: In the channel array, the long axis of the second shape of each of the second columns located in odd rows in the second direction extends in a first oblique direction having an inclination based on the first direction, and the long axis of the second shape of each of the second columns located in even rows in the second direction extends in a second oblique direction different from the first oblique direction.

19. The semiconductor memory device according to claim 11, wherein: The first shape comprises a circular shape; The second shape comprises an elliptical shape having a major axis and a minor axis; A lowermost plane of each of the plurality of channel pillars has a third shape that is the same as the first shape; and The diameter of the third shape is equal to or less than the length of the minor axis of the second shape.

20. The semiconductor memory device according to claim 11, wherein Each of the plurality of channel pillars comprises: an opening portion, the opening portion passing through the electrode structure; a memory film formed on a side wall of the opening portion to contact the plurality of gate conductive films and including a tunnel insulating film, a charge trap film, and a blocking film sequentially stacked in the opening portion; a channel film formed on the memory film; a core film formed on the channel film and partially gap-filling the opening portion; and A cover film is formed on the core film and gap-fills the remaining opening portion and is electrically connected to the channel film.

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