Semiconductor device

Abstract

Embodiments relate to a semiconductor device. An embodiment includes a first electrode, a second electrode, a semiconductor portion, a gate electrode, and a first portion having an insulating property. The first electrode and the second electrode are disposed across the first region, the second region, and the third region. The semiconductor part is arranged between the first electrode and the second electrode. In the first region, a gate electrode is provided in the semiconductor portion. The first portion is disposed on the first electrode in the third region. The first region is an IGBT region. The second region is a diode region. The third region isolates the first region from the second region between the first region and the second region. In the third region, a bottom surface of the first portion is in contact with the first electrode, an upper surface of the first portion is in contact with the fourth semiconductor layer, and a side surface of the first portion is in contact with the third semiconductor layer.

Description

[0001] Related Application

[0002] This application claims the priority of Japanese Patent Application No. 2023-149525 (filing date: September 14, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device. Background Art

[0004] IGBT (Insulated Gate Bipolar Transistor) is widely used as a semiconductor element for power control. Among them, there is a reverse conducting IGBT (RC-IGBT) in which a diode connected in anti-parallel is integrated.

[0005] In such RC-IGBT, there is a strong demand for improving the reverse recovery characteristics of the integrated diode. Summary of the invention

[0006] A semiconductor device of an embodiment comprises: a first electrode, which is arranged across a first region, a second region, and a third region between the first region and the second region; a second electrode, which is arranged across the first region, the second region, and the third region; a semiconductor portion, which is arranged between the first electrode and the second electrode; a gate electrode, which extends within the semiconductor portion between the second electrode and the semiconductor portion in the first region and is electrically isolated from the semiconductor portion; and a first portion with insulating properties, which is arranged on the first electrode in the third region. The semiconductor portion includes: a first semiconductor layer of a first conductivity type, provided on the first electrode in the first region and electrically connected to the first electrode; a second semiconductor layer of a second conductivity type, provided on the first electrode in the second region and electrically connected to the first electrode; a third semiconductor layer of the second conductivity type, provided on the first semiconductor layer and the second semiconductor layer in the first region and the second region; a fourth semiconductor layer of the second conductivity type, provided on the third semiconductor layer and the first portion in the first region, the second region and the third region; a fifth semiconductor layer of the first conductivity type, provided on the fourth semiconductor layer in the first region and electrically connected to the second electrode; a sixth semiconductor layer of the second conductivity type, selectively provided on the fifth semiconductor layer and electrically connected to the second electrode; a seventh semiconductor layer of the first conductivity type, provided on the fourth semiconductor layer in the second region and the third region and electrically connected to the second electrode; and an eighth semiconductor layer of the first conductivity type, selectively provided on the fifth semiconductor layer, provided on the seventh semiconductor layer and electrically connected to the second electrode. The gate electrode faces the fifth semiconductor layer via a gate insulating film. The bottom surface of the first portion is in contact with the first electrode, the top surface of the first portion is in contact with the fourth semiconductor layer, and the side surface of the first portion is in contact with the third semiconductor layer.

[0007] According to the embodiment, it is possible to provide a semiconductor device having improved reverse recovery characteristics during diode operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0009] Figure 2 It is a schematic cross-sectional view for explaining the operation of the semiconductor device according to the embodiment.

[0010] Figure 3 It is a schematic cross-sectional view for explaining the operation of the semiconductor device of the comparative example.

[0011] Figure 4This is a schematic cross-sectional view illustrating a semiconductor device according to a modified example.

[0012] Description of Reference Numerals

[0013] 1…Collector

[0014] 2…Emitter electrode

[0015] 10…Semiconductor Division

[0016] 11…n - Drift Layer

[0017] 12a…p - Base layer

[0018] 12b…p-type anode layer

[0019] 13…n + Type Source Layer

[0020] 14…p + Type collector layer

[0021] 15…n + Cathode layer

[0022] 16…n + Buffer layer

[0023] 17…p + Type emitter layer

[0024] 18…p + Contact layer

[0025] 19…n-type barrier layer

[0026] 21…Gate electrode

[0027] 31…Gate insulating film

[0028] 32…Interlayer insulation film

[0029] 41…Conductor

[0030] 51…Insulation film

[0031] 61…Insulator

[0032] 61B…Bottom

[0033] 61S…side view

[0034] 61T…Upper surface

[0035] 71…High resistance part

[0036] 100, 200…Semiconductor devices DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0038] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc. are not necessarily the same as in reality. Even when the same part is shown, there are cases where the sizes and ratios are shown differently depending on the drawings.

[0039] In the specification and drawings of the present application, the same elements as those already described are denoted by the same reference numerals, and detailed description thereof will be appropriately omitted.

[0040] In the following description and drawings, n + 、n - and p + , p These marks indicate the relative high and low of each impurity concentration. That is, a mark with "+" indicates that the impurity concentration is relatively higher than a mark without "+" or "-", and a mark with "-" indicates that the impurity concentration is relatively lower than a mark without either. In the case where each region contains both p-type impurities and n-type impurities, these marks indicate the relative high and low of the net impurity concentration after these impurities compensate for each other.

[0041] In each embodiment described below, each embodiment may be implemented by reversing the p-type and n-type of each semiconductor region.

[0042] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0043] like Figure 1 As shown, the semiconductor device 100 of the embodiment includes a collector electrode 1, an emitter electrode 2, a semiconductor portion 10, a gate electrode 21, and an insulator 61. The semiconductor portion 10 is provided between the collector electrode 1 and the emitter electrode 2. The insulator 61 is provided on the collector electrode 1 and extends from the collector electrode 1 into the semiconductor portion 10.

[0044] The collector electrode (first electrode) 1 is provided on the back side of the semiconductor part 10 and functions as one of the main electrodes of the RC-IGBT. The emitter electrode (second electrode) 2 is provided on the front side of the semiconductor part 10 and functions as the main electrode of the RC-IGBT. The gate electrode 21 faces the semiconductor part 10 via the gate insulating film 31.

[0045] The semiconductor device 100 includes a first region I, a second region II, and a third region III. The third region III is disposed between the first region I and the second region II.

[0046] In the first region I, the semiconductor device 100 mainly operates as an IGBT. The operation as an IGBT, in an n-type IGBT, means that the IGBT is turned on when a voltage sufficiently higher than the gate threshold voltage is applied to the gate electrode 21, and is turned off when a voltage sufficiently lower than the gate threshold voltage is applied to the gate electrode 21.

[0047] In the second region II, the semiconductor device 100 mainly operates as a diode. The operation as a diode, in the case of an n-type IGBT, means an operation in which a current flows into the emitter electrode 2 and flows out from the collector electrode 1 when the IGBT is turned off. Hereinafter, the operation of the semiconductor device as an IGBT is sometimes referred to as IGBT operation, and the operation of the semiconductor device as a diode is sometimes referred to as diode operation.

[0048] The third region III electrically isolates the first region I from the second region II. The distance W3 is the width of the third region III, which is the distance between the first region I and the second region II.

[0049] The collector electrode 1 , the semiconductor portion 10 , and the emitter electrode 2 are provided across the first region I, the second region II, and the third region III.

[0050] Hereinafter, the structure of the semiconductor device 100 may be described using an XYZ coordinate system. The direction from the collector electrode 1 toward the emitter electrode 2 is described as the direction of the Z axis. The first region I, the third region III, and the second region II are arranged in this order in the direction of the X axis orthogonal to the Z axis. For example, the first region I and the second region II are arranged alternately with the third region III interposed therebetween. That is, in Figure 1 In a specific example, the first region I may be arranged on the positive side of the second region II in the X-axis direction via the third region III. In addition, the second region II may be arranged on the negative side of the first region I in the X-axis direction via the third region III. The repetition of the arrangement of the first region I to the third region III may also be applied to the Y-axis direction.

[0051] The longer the distance W3 is, the less interference there is between the operation in the first region I and the operation in the second region II. On the other hand, as the distance W3 is extended, the area of ​​the semiconductor device 100 increases in a plan view, and the cost performance decreases.

[0052] In the semiconductor device 100 of the embodiment, the insulator (first portion) 61 is provided in the third region III. The width W0 of the insulator 61 is equal to or shorter than the distance W3. In the semiconductor device 100, by including the insulator 61, interference between the operation in the first region I and the operation in the second region II can be suppressed even with a short distance W3.

[0053] The interference between the operation in the first region I and the operation in the second region II refers to the movement of minority carriers injected into the first region I to the second region II when the semiconductor device 100 performs diode operation. If the minority carriers injected into the first region I move to the second region II, the charge amount of the minority carriers in the second region II becomes excessive, and the reverse recovery time becomes longer. The insulator 61 is provided in the third region III to restrict the movement of minority carriers from the first region I to the second region II.

[0054] The structure of the semiconductor device 100 will be described in more detail. Hereinafter, the semiconductor device 100 will be described as an n-type RC-IGBT. When the semiconductor device 100 performs a diode operation, the collector electrode 1 functions as a cathode electrode of the diode, and the emitter electrode 2 functions as an anode electrode of the diode.

[0055] The semiconductor portion 10 includes n - Type drift layer 11, p - type base layer 12a, p-type anode layer 12b, n + Type source layer 13, p + Type collector layer 14, n + Type cathode layer 15, n + Type buffer layer 16 and p + The semiconductor portion 10 further includes a p-type emitter layer 17. + The semiconductor portion 10 includes an n-type contact layer 18 and an n-type barrier layer 19. The semiconductor portion 10 includes, for example, Si.

[0056] p + The p-type collector layer (first semiconductor layer) 14 is provided on the collector 1 in the first region I and is electrically connected to the collector 1. + The type collector layer 14 is not provided in the second region II and the third region III.

[0057] n + The cathode layer (second semiconductor layer) 15 is provided on the collector electrode 1 in the second region II and is electrically connected to the collector electrode 1. + The cathode layer 15 is not provided in the first region I and the third region III.

[0058] n + The buffer layer (third semiconductor layer) 16 is provided in the first region I at the p + Type collector layer 14. + The type buffer layer 16 is provided in the second region II. + Type cathode layer 15. + The type buffer layer 16 is provided on the collector 1 in the third region III. Figure 1 In the specific example of n +The type buffer layer 16 surrounds the insulator 61 in the third region III.

[0059] n - The type drift layer (fourth semiconductor layer) 11 is provided in the first region I and the second region II. + Type buffer layer 16. - The type drift layer 11 is provided on the insulator 61 in the third region III. Figure 1 In the specific example of n - The type drift layer 11 is provided at n + Type buffer layer 16.

[0060] The n-type barrier layer 19 is provided in the first region I. - The n-type drift layer 11 is formed on the n-type barrier layer 19. The n-type barrier layer 19 is not formed in the second region II and the third region III.

[0061] p - The n-type base layer (fifth semiconductor layer) 12a is provided on the n-type barrier layer 19 in the first region I. - The type base layer 12a is not provided in the second region II and the third region III.

[0062] The p-type anode layer (seventh semiconductor layer) 12b is provided in the second region II and the third region III. - The p-type anode layer 12b is not provided in the first region I.

[0063] n + The type source layer (sixth semiconductor layer) 13 is selectively provided in the first region I. - On the type base layer 12a. + The type source layer 13 is not provided in the second region II and the third region III.

[0064] p + The type emitter layer (eighth semiconductor layer) 17 is selectively provided in the first region I. - On the base layer 12a. + The p-type emitter layer 17 is provided on the p-type anode layer 12 b in the second region II and the third region III.

[0065] p + The type contact layer 18 is selectively provided in the first region I at the p - In the first region I, p + The p-type contact layer 18 is provided on the surface where no p + The position of the emitter layer 17. + The type contact layer 18 is not provided in the second region II and the third region III.

[0066] n- The impurity concentration of the drift layer 11 is n + Type cathode layer 15, n + Type buffer layer 16 and n + The impurity concentration of each type source layer is low. - The impurity concentration of the n-type drift layer 11 is lower than that of the n-type barrier layer 19. - type drift layer 11 and p - When a reverse bias is applied between the base layer 12a and the n - The desired withstand voltage is achieved by expanding into the n-type drift layer 11. - When a reverse bias is applied between the p-type drift layer 11 and the p-type anode layer 12b, the depletion layer also - The type drift layer 11 is expanded to achieve the desired withstand voltage.

[0067] p + The impurity concentration of the emitter layer 17 is higher than p - The impurity concentration of the p-type base layer 12a is high. + The impurity concentration of the p-type emitter layer 17 is higher than the impurity concentration of the p-type anode layer 12 b.

[0068] The insulator 61 is provided in the third region III, and preferably is provided throughout the entire third region III. The insulator 61 is provided on the collector 1 and is in contact with the collector 1 at the lower surface 61B. The insulator 61 is in contact with the n at the side surface 61S. + The insulator 61 is connected to the n-type buffer layer 16. + The buffer layer 16 is disconnected. Figure 1 As in the specific example, the insulator 61 extends to n - The insulator 61 is connected to the n type drift layer 11 at the upper surface 61T. - The type drift layer 11 is in contact with the n type drift layer 11, and the side surface 61S of the upper part of the insulator 61 is connected to the n type drift layer 11. - type drift layer 11.

[0069] The insulator 61 includes an insulating material such as Si oxide or Si nitride, for example, SiO 2 The insulator 61 may be any other insulating material as long as it can block the movement of the holes, and may include, for example, insulating materials such as rubber and other resins. In addition, the interior of the insulator 61 may not be completely filled with insulating materials, and may include gaps.

[0070] The insulator 61 can be formed, for example, as follows. That is, in the third region III, a dielectric layer is formed that penetrates the back surface of the semiconductor portion 10. + type buffer layer 16 and reaches n -The concave portion of the drift layer 11 is formed, and SiO is formed in the formed concave portion. 2 The concave portion is composed of a bottom surface facing the upper surface 61T of the insulator 61 and a side surface continuous with the bottom surface and facing the side surface 61S of the insulator 61. In forming the concave portion, for example, an anisotropic etching method such as reactive ion etching (RIE) can be used. 2 For forming the film, for example, chemical vapor deposition (CVD) can be used.

[0071] The gate electrode 21 extends from the surface of the semiconductor portion 10 toward the inside in the first region I and is electrically isolated from the semiconductor portion 10. The gate electrode 21 is connected to the p-type semiconductor portion 10 via the gate insulating film 31. - The gate electrode 21 faces the n-type base layer 12a. The gate electrode 21 faces the n-type barrier layer 19 via the gate insulating film 31. - Part of the type drift layer 11 faces each other.

[0072] The conductor 41 is selectively disposed in the first region I. Figure 1 In the specific example, the conductor 41 is provided between two gate electrodes 21 arranged in the direction of the X axis. The conductor 41 extends from the surface of the semiconductor portion 10 toward the inside and is electrically isolated from the semiconductor portion 10.

[0073] The conductor 41 is connected to the p-type conductor via the insulating film 51 in the first region I. - The conductor 41 is connected to the selectively provided p-type base layer 12a via the insulating film 51 in the first region I. + The conductor 41 is opposite to the selectively provided p-type emitter layer 17 via the insulating film 51 in the first region I. + The conductor 41 faces the n-type contact layer 18 in the first region I. The conductor 41 faces the n-type barrier layer 19 in the first region I. - Part of the type drift layer 11 faces each other.

[0074] The conductor 41 extends from the surface of the semiconductor portion 10 toward the inside in each of the second region II and the third region III, and is electrically isolated from the semiconductor portion 10 .

[0075] The conductor 41 faces the p-type anode layer 12b via the insulating film 51 in each of the second region II and the third region III. + The conductor 41 is connected to the n type emitter layer 17 via the insulating film 51 in each of the second region II and the third region III.- Part of the type drift layer 11 faces each other.

[0076] Although not shown, the gate electrode 21 and the conductor 41 extend in the Y-axis direction and are formed in a stripe shape in a plan view. The gate electrode 21 and the conductor 41 are made of, for example, polycrystalline Si.

[0077] The emitter electrode 2 is provided in the first region I at n + On the source layer 13, p + On the emitter layer 17, p + The emitter electrode 2 is connected to the n type contact layer 18 and the conductor 41 in the first region I. + Type source layer 13, p + Type emitter layer 17, p + The contact layer 18 and the conductor 41 are electrically connected.

[0078] The emitter electrode 2 is provided on the gate electrode 21 in the first region I. The emitter electrode 2 is electrically isolated from the gate electrode 21 by an interlayer insulating film 32 provided between the emitter electrode 2 and the gate electrode 21 .

[0079] The emitter electrode 2 is provided at p in each of the second region II and the third region III. + The emitter electrode 2 is connected to the p-type emitter layer 17 and the conductor 41 in each of the second region II and the third region III. + The emitter layer 17 and the conductor 41 are electrically connected.

[0080] The operation of the semiconductor device 100 according to the embodiment will be described.

[0081] Figure 2 It is a schematic cross-sectional view for explaining the operation of the semiconductor device according to the embodiment.

[0082] exist Figure 2 In FIG. 1 , arrows A11 to A21 indicate the paths and directions of movement of holes when the semiconductor device 100 performs a diode operation.

[0083] First, a case where the semiconductor device 100 performs an IGBT operation will be described.

[0084] In the IGBT operation, when the semiconductor device 100 is turned on, a sufficiently high voltage exceeding the gate threshold is applied to the gate electrode 21 relative to the emitter electrode 2. This voltage - An inversion layer is formed on the surface of the n-type base layer 12a. + The electrons supplied from the n-type source layer 13 flow into the inversion layer, - Type drift layer 11 and n + Type buffer layer 16.

[0085] Since a higher voltage is applied to the collector electrode 1 than to the emitter electrode 2, p + The type collector layer 14 injects holes into the n + Type buffer layer 16 and n - type drift layer 11. Thus, the IGBT is turned on.

[0086] In the IGBT operation, when the semiconductor device 100 is turned off, a sufficiently low voltage lower than the gate threshold is applied to the gate electrode 21 relative to the emitter electrode 2. For example, by applying a negative voltage relative to the voltage of the emitter electrode 2, the gate electrode 21 is turned off. - An accumulation layer is formed in the type base layer 12a.

[0087] n - The holes in the type drift layer 11 pass through the accumulation layer and the p-type drift layer without forming the accumulation layer. - The p-type base layer 12a is recovered to the emitter electrode 2 side. When a sufficiently low voltage is applied to the emitter electrode 2, - When the accumulation layer is formed in the type base layer 12 a , the excess holes are recovered and the turn-off speed of the semiconductor device 100 is improved.

[0088] Next, a case where the semiconductor device 100 performs a diode operation will be described.

[0089] like Figure 2 As shown in the figure, in the diode operation, since a higher voltage than the collector electrode 1 is applied to the emitter electrode 2, the p + The emitter layer 17 is n- - The type drift layer 11 injects holes. According to the amount of charge of the injected holes, the + The cathode layer 15 supplies electrons, and current flows from the emitter electrode 2 to the collector electrode 1 .

[0090] In the first region I, holes also flow from p + type emitter layer 17 and p + The n-type contact layer 18 is implanted with n-type - Type drift layer 11.

[0091] The n implanted into the first region I - The holes in the type drift layer 11 reach the n - The paths of the type drift layer 11 include a first path indicated by arrows A11 , A12 , and A13 , and a second path indicated by arrow A21 .

[0092] Arrows A11, A12, and A13 each constitute a part of the first path. That is, arrow A11 indicates the direction from n to n in the first region I.- Type drift layer 11 reaches n + The arrow A12 indicates the path from the first region I to the n-type buffer layer 16. + The type buffer layer 16 reaches the n-type buffer layer of the third region III. + The arrow A13 indicates the path from the n-type buffer layer 16 to the third region III. + The type buffer layer 16 reaches the n-type buffer layer of the second region II. + The type buffer layer 16 is a portion of the path.

[0093] In the second path, arrow A21 indicates the n from the first area I - The type drift layer 11 passes through the n-type drift layer of the third region III. - The n type drift layer 11 reaches the second region II - The path of the drift layer 11.

[0094] In the semiconductor device 100 of the embodiment, an insulator 61 is provided on the collector electrode 1 in the third region III. The insulator 61 penetrates through the collector electrode 1 in the third region III. + The type buffer layer 16 is provided, and n is formed between the first region I and the second region II. + Therefore, as shown by the dashed arrow A13, in the first path, the n-type buffer layer 16 is electrically isolated. - The movement of holes in the type drift layer 11 to the second region II is blocked by the insulator 61 in the third region III.

[0095] In the first path, there is a ratio n - The sheet resistance of the drift layer 11 is low, and the sheet resistance is n + The type buffer layer 16 is included in a part of the path. Figure 2 The resistance value of the first path formed by arrows A11, A12, and A13 is lower than the resistance value of the second path formed by arrow A21. - The holes in the type drift layer 11 are basically supposed to reach the second region II via the first path, but since their movement is blocked by the insulator 61, they cannot reach the second region II, thereby suppressing the reverse recovery characteristic in the second region II from being deteriorated.

[0096] Figure 3 It is a schematic cross-sectional view for explaining the operation of the semiconductor device 100 a according to the comparative example.

[0097] like Figure 3 As shown, in the semiconductor device 100 a of the comparative example, the insulator 61 provided in the third region III is replaced, and the distance W3 a in the third region III is made sufficiently long.

[0098] Arrows A11a and A12a each constitute a part of the first path. Arrow A21a constitutes the second path. In any path, the resistance value of the path can be substantially increased by making the length of the path sufficiently long. In this way, the n injected into the first region I can be suppressed. - The holes in the type drift layer 11 move to the second region II.

[0099] On the other hand, the distance W3a of the third region III becomes longer, and the area of ​​the region that does not contribute to the IGBT operation and the diode operation increases. Therefore, the cost performance of the semiconductor device 100a decreases.

[0100] (Variation Example)

[0101] Figure 4 This is a schematic cross-sectional view illustrating a semiconductor device according to a modified example.

[0102] like Figure 4 As shown in FIG. 1 , the semiconductor device 200 of this modification example includes a high resistance portion (second portion) 71 in the third region III. The high resistance portion 71 is provided at n in the third region III. - The n-type drift layer 11 is provided in the high resistance portion 71 on the upper surface 61T of the insulator 61. The n-type impurity concentration of the high resistance portion 71 is higher than n - The n-type drift layer 11 has a low n-type impurity concentration.

[0103] The high resistance portion 71 has a higher resistance than n in the third region III. - The sheet resistance of the drift layer 11 is low. Therefore, it is possible to more reliably cut off Figure 2 The movement of holes along the first path shown can be suppressed, and the movement of holes along the second path can be suppressed, thereby more reliably preventing the reverse recovery characteristics in the second region II from being deteriorated.

[0104] The high resistance portion 71 can be formed, for example, in the following manner. That is, after forming a recess for forming the insulator 61, the bottom surface of the recess is - The high resistance portion 71 can be formed by introducing p-type impurities into the p-type drift layer 11. For example, an ion implantation method can be used to introduce the p-type impurities.

[0105] Effects of the semiconductor device 100 according to the embodiment and the semiconductor device 200 according to the modification example will be described.

[0106] In the semiconductor devices 100 and 200, in order to prevent the n-type transistor from being formed when a reverse bias is applied between the collector electrode 1 and the emitter electrode 2, - The depletion layer of the drift layer 11 extends to the collector 1, and n + type buffer layer 16. On the other hand, n+ The type buffer layer 16 may become a path for holes injected into the first region I to move to the second region II when the semiconductor device 100 or 200 performs a diode operation. In the semiconductor device 100 or 200 of the embodiment, in the third region III between the first region I and the second region II, n + The insulator 61 is provided in a manner that the n-type buffer layer 16 is disconnected. + The migration of the type buffer layer 16 to the second region II is blocked, the charge amount of the excess holes in the second region II is reduced, and the reverse recovery characteristic is improved.

[0107] By making the width W0 of the insulator 61 sufficient, it is possible to more reliably block the movement of holes from the first region I to the second region II. + The buffer layer 16 fully extends to n - The interior of the type drift layer 11 can further reliably cut off the movement of holes from the first region I to the second region II.

[0108] In the semiconductor device 200 of the modification, since the high resistance portion 71 is provided on the insulator 61 , it is possible to more reliably block the movement of holes from the first region I to the second region II.

[0109] The relative height of the impurity concentration between each semiconductor region in each embodiment described above can be confirmed using, for example, SCM (scanning electrostatic capacitance microscope). In addition, the carrier concentration in each semiconductor region can be regarded as equal to the activated impurity concentration in each semiconductor region. Therefore, the relative height of the carrier concentration between each semiconductor region can also be confirmed using SCM. In addition, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (secondary ion mass spectrometry).

[0110] Several embodiments of the present invention are illustrated above, but these embodiments are proposed as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the scope of the main purpose of the invention. These embodiments and their modifications are included in the scope and main purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents. In addition, the aforementioned embodiments can be implemented in combination with each other.

[0111] The embodiments include the following aspects.

[0112] (Note 1)

[0113] A semiconductor device comprising:

[0114] A first electrode is arranged across a first region, a second region, and a third region between the first region and the second region;

[0115] A second electrode is arranged across the first region, the second region and the third region;

[0116] a semiconductor portion disposed between the first electrode and the second electrode;

[0117] a gate electrode extending within the semiconductor portion between the second electrode and the semiconductor portion in the first region and electrically isolated from the semiconductor portion; and

[0118] An insulating first portion is provided on the first electrode in the third region;

[0119] The semiconductor unit includes:

[0120] A first semiconductor layer of a first conductivity type is disposed on the first electrode in the first region and is electrically connected to the first electrode;

[0121] A second semiconductor layer of a second conductivity type is disposed on the first electrode in the second region and is electrically connected to the first electrode;

[0122] The third semiconductor layer of the second conductivity type is provided on the first semiconductor layer and the second semiconductor layer in the first region and the second region;

[0123] The fourth semiconductor layer of the second conductivity type is provided on the third semiconductor layer and the first portion in the first region, the second region and the third region;

[0124] The fifth semiconductor layer of the first conductivity type is provided on the fourth semiconductor layer in the first region and is electrically connected to the second electrode;

[0125] The sixth semiconductor layer of the second conductivity type is selectively disposed on the fifth semiconductor layer and is electrically connected to the second electrode;

[0126] The seventh semiconductor layer of the first conductivity type is provided on the fourth semiconductor layer in the second region and the third region and is electrically connected to the second electrode; and

[0127] The eighth semiconductor layer of the first conductivity type is selectively disposed on the fifth semiconductor layer and on the seventh semiconductor layer, and is electrically connected to the second electrode;

[0128] The gate electrode faces the fifth semiconductor layer via a gate insulating film.

[0129] A bottom surface of the first portion is in contact with the first electrode, an upper surface of the first portion is in contact with the fourth semiconductor layer, and a side surface of the first portion is in contact with the third semiconductor layer.

[0130] (Note 2)

[0131] The semiconductor device according to Supplementary Note 1, wherein:

[0132] The side surface of the first portion is in contact with the fourth semiconductor layer at an upper portion of the first portion.

[0133] (Note 3)

[0134] The semiconductor device according to Supplement 1 or 2, wherein:

[0135] The third region further includes a second portion having a carrier concentration lower than the carrier concentration of the fourth semiconductor layer on the first portion.

[0136] (Note 4)

[0137] The semiconductor device according to Supplementary Note 3, wherein:

[0138] The second portion is connected to an upper surface of the first portion.

[0139] (Note 5)

[0140] The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein:

[0141] The third semiconductor layer is disposed on the first electrode.

[0142] A side surface of the first portion is in contact with the third semiconductor layer.

[0143] (Note 6)

[0144] The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein:

[0145] The first portion is provided in such a manner as to disconnect the third semiconductor layer in the first region from the third semiconductor layer in the second region.

[0146] (Note 7)

[0147] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein:

[0148] The first portion includes Si oxide or Si nitride.

Claims

1. A semiconductor device, characterized in that: have: A first electrode is arranged across a first region, a second region, and a third region between the first region and the second region; A second electrode is arranged across the first region, the second region and the third region; a semiconductor portion disposed between the first electrode and the second electrode; a gate electrode extending within the semiconductor portion between the second electrode and the semiconductor portion in the first region and electrically isolated from the semiconductor portion; as well as An insulating first portion is provided on the first electrode in the third region; The semiconductor unit includes: A first semiconductor layer of a first conductivity type is disposed on the first electrode in the first region and is electrically connected to the first electrode; A second semiconductor layer of a second conductivity type is disposed on the first electrode in the second region and is electrically connected to the first electrode; The third semiconductor layer of the second conductivity type is provided on the first semiconductor layer and the second semiconductor layer in the first region and the second region; The fourth semiconductor layer of the second conductivity type is provided on the third semiconductor layer and the first portion in the first region, the second region and the third region; The fifth semiconductor layer of the first conductivity type is provided on the fourth semiconductor layer in the first region and is electrically connected to the second electrode; The sixth semiconductor layer of the second conductivity type is selectively disposed on the fifth semiconductor layer and is electrically connected to the second electrode; The seventh semiconductor layer of the first conductivity type is provided on the fourth semiconductor layer in the second region and the third region and is electrically connected to the second electrode; as well as The eighth semiconductor layer of the first conductivity type is selectively disposed on the fifth semiconductor layer and on the seventh semiconductor layer, and is electrically connected to the second electrode; The gate electrode faces the fifth semiconductor layer via a gate insulating film. A bottom surface of the first portion is in contact with the first electrode, an upper surface of the first portion is in contact with the fourth semiconductor layer, and a side surface of the first portion is in contact with the third semiconductor layer.

2. The semiconductor device according to claim 1, wherein: The side surface of the first portion is in contact with the fourth semiconductor layer at an upper portion of the first portion.

3. The semiconductor device according to claim 1, wherein: The third region further includes a second portion having a carrier concentration lower than the carrier concentration of the fourth semiconductor layer on the first portion.

4. The semiconductor device according to claim 3, wherein: The second portion is connected to an upper surface of the first portion.

5. The semiconductor device according to claim 1, wherein: The third semiconductor layer is disposed on the first electrode. A side surface of the first portion is in contact with the third semiconductor layer.

6. The semiconductor device according to claim 1, wherein: The first portion is provided in such a manner as to disconnect the third semiconductor layer in the first region from the third semiconductor layer in the second region.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that The first portion includes Si oxide or Si nitride.

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