Semiconductor device

Abstract

The purpose of the present invention is to provide a semiconductor device in which an increase in an electric field is suppressed and an avalanche withstand voltage is improved by reducing the hole density at a trench end portion in the semiconductor device. An extension portion (10a) of a lower electrode (10), which extends to the outside than an upper electrode (9), further extends to the upper surface of the semiconductor substrate so as to cover an end portion of the upper electrode (9) at an outer peripheral portion in an extension direction of a trench (7) located in an outer peripheral region (40) of the semiconductor device, and the width of the trench (7) is made to be narrowest at a trench end portion (7a).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Patent document 1 discloses a semiconductor device having a MOSFET having a split gate structure in which an electrode inside a trench is divided into two parts. The invention described in patent document 1 increases the withstand voltage of the trench ends located at the periphery by increasing the width of the trench at the periphery of the semiconductor device. In addition, the invention describes that the invention can be applied even when the semiconductor switching element is an IGBT other than a MOSFET.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2021-128948

[0004] The semiconductor device described in Patent Document 1 does not fully consider the movement of carriers. As an example, consider the increase in hole density at the end of the trench when the switch is turned off. Specifically, when the switch is turned off, holes flow into the end of the trench at a high density, so that the hole density at the end of the trench increases. As a result, the space charge increases with the increase in hole density, so the electric field increases and avalanche occurs. This phenomenon occurs significantly in IGBT (Insulated Gate Bipolar Transistor) among bipolar devices in particular. When the invention described in Patent Document 1 is applied to IGBT, the width of the trench becomes wider at the end of the trench located in the periphery, so the area between the trenches becomes narrower, and the hole density is easily increased. Therefore, the electric field increases with the increase in hole density, and the avalanche withstand voltage decreases. Summary of the invention

[0005] The present disclosure is made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device that suppresses an increase in electric field and improves avalanche withstand voltage by reducing the hole density at the end of a trench.

[0006] The semiconductor device disclosed in the present invention comprises an active region constituting a semiconductor switch element and a peripheral region outside the active region provided with a gate electrode, wherein the semiconductor switch element comprises: a first conductive type drift layer; a second conductive type base layer, which is arranged on the upper surface side of the first conductive type drift layer; a first conductive type source layer, which is arranged on the upper surface side of the second conductive type base layer; a second conductive type collector layer, which is arranged on the lower surface side of the first conductive type drift layer; an emitter electrode, which is electrically connected to the first conductive type source layer; and a collector electrode, which is electrically connected to the second conductive type collector layer, and the range from the upper surface of the first conductive type source layer to the lower surface of the second conductive type collector layer is set as a semiconductor substrate, and the semiconductor device further comprises: a plurality of grooves, which They penetrate from the upper surface of the semiconductor substrate in the depth direction to reach the first conductive type drift layer, and extend from the active area toward the peripheral area; and an interlayer insulating film, which covers each of the multiple grooves, each of the multiple grooves is stacked with a lower electrode, a boundary insulating film and an upper electrode in sequence via an insulating film inside the groove to form a two-level structure, the lower electrode is electrically connected to the emitter electrode, and the upper electrode is electrically connected to the gate electrode, at the peripheral part of the extension direction of the groove located in the peripheral area, the extension part of the lower electrode in the lower electrode that extends to the outside than the upper electrode further extends to the upper surface of the semiconductor substrate in a manner covering the end of the upper electrode, and the width of the groove is narrowest at the end of the groove.

[0007] According to the semiconductor device of the present disclosure, the hole density at the end of the trench is reduced to suppress the increase of the electric field, thereby improving the avalanche withstand voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is an overall plan view of the semiconductor device according to the first embodiment.

[0009] Figure 2 The semiconductor device of the first embodiment Figure 1 AA section view in.

[0010] Figure 3 The semiconductor device of the first embodiment Figure 1 BB section view in.

[0011] Figure 4 The semiconductor device of the first embodiment Figure 1 Enlarged top view of point C in the figure.

[0012] Figure 5 This is an enlarged plan view of the outer periphery of the trench of the semiconductor device according to the first embodiment.

[0013] Figure 6 This is an enlarged plan view of the outer periphery of the trench of the semiconductor device according to the second embodiment.

[0014] Figure 7 This is an enlarged plan view of the outer periphery of the trench of the semiconductor device according to the second embodiment.

[0015] Figure 8 This is an enlarged plan view of the outer periphery of the trench of the semiconductor device according to the third embodiment.

[0016] Fig. 9 This is an enlarged plan view of the outer periphery of the trench of the semiconductor device according to the third embodiment.

[0017] Fig.10 This is an enlarged plan view of the outer periphery of the trench of the semiconductor device according to the third embodiment.

[0018] Fig.11 This is an enlarged plan view of the outer periphery of the trench of the semiconductor device according to the fourth embodiment.

[0019] Description of reference numerals: 1...n － type drift layer; 3...p-type base layer; 4...n + type source layer; 6...p-type collector layer; 7...groove; 7a...end of the groove; 8...insulating film; 8a...upper insulating film; 8b...lower insulating film; 9...upper electrode; 10...lower electrode; 10a...extension portion; 10b...pull-up region portion; 11...boundary insulating film; 12...interlayer insulating film; 13...emitter electrode; 14...collector; 15...gate electrode; 20...tapered portion; 21...cross trench; 22...cross insulating film; 23...cross electrode; 30...active region; 40...peripheral region; 50...pull-up region; 100...semiconductor device. DETAILED DESCRIPTION

[0020] <First>

[0021] In the following description, n-type and p-type refer to the conductivity type of the semiconductor. In the present disclosure, the first conductivity type is set to n-type and the second conductivity type is set to p-type for description. However, the first conductivity type may be set to p-type and the second conductivity type may be set to n-type. － Type means that the impurity concentration is lower than that of n-type. + The n-type indicates that the impurity concentration is higher than that of the n-type. － Type means that the impurity concentration is lower than that of p-type. + Type means that the impurity concentration is higher than that of p-type.

[0022] In addition, for the sake of convenience, the following Figures 1 to 11 As shown, the width direction of the semiconductor device 100 is set as the x direction, the depth direction of the semiconductor device 100 intersecting the x direction is set as the y direction, and the thickness direction or depth direction of the semiconductor device 100, that is, the normal direction relative to the xy plane is set as the z direction.

[0023] In addition, the drawings are schematically shown, and the size and position relationship of the images shown in different drawings are not necessarily accurately recorded, but can be appropriately changed. In addition, in the following description, the same components are marked with the same reference numerals for illustration, and their names and functions are also the same, so their detailed description is sometimes omitted.

[0024] Implementation method 1.

[0025] Hereinafter, Embodiment 1 will be described using the drawings. Figure 1 FIG. 1 is a top view schematically showing the overall upper surface structure of the semiconductor device 100 according to the first embodiment. Figure 1 As shown, in the semiconductor device 100, there are: an active region 30 constituting a semiconductor switch element, and a peripheral region 40 around the active region 30. In addition, the groove 7 is set to extend from the active region 30 toward the peripheral region 40 along the Y direction. The Y direction is set as the extension direction of the groove 7. In addition, the plurality of grooves 7 are set to be adjacent in the direction orthogonal to the extension direction of the groove 7, that is, the X direction. Figure 1 In the figure, the number of the trenches 7 is shown as 5, but the number of the trenches 7 is not limited to this. In addition, in this embodiment, a semiconductor device having a split gate trench structure and using an insulated gate bipolar transistor (IGBT) as a semiconductor switch element is described as an example. Figure 2 to Figure 5 , the detailed structure of the semiconductor device 100 of this embodiment is described.

[0026] Figure 2 2 is a cross-sectional view of the active region 30 of the semiconductor device 100 according to the first embodiment, taken in a direction perpendicular to the extending direction of the trench 7 . Figure 2 Show Figure 1 The cross section at the dotted line AA is shown. Figure 3 This is a cross-sectional view in a direction parallel to the extending direction of the groove 7 of the first embodiment. Figure 3 Show Figure 1 The cross section is shown at the dotted line BB. Figure 4 1 is a top view of the outer periphery of the trench 7 of the semiconductor device 100 according to the first embodiment. Figure 4 Show Figure 1The enlarged view of area C is shown and Figure 2 A top view taken along the dashed line C is shown. Figure 5 Yes means Figure 4 A top view of a modified example of the groove 7 is shown.

[0027] First, use Figure 2 , Figure 3 , the cross-sectional structure of the semiconductor device 100 is described. Figure 2 As shown, the semiconductor device 100 forms a semiconductor switch element in the active region 30. The semiconductor switch element includes: － drift layer 1, n-type carrier storage layer 2, p-type base layer 3, n + n-type source layer 4, n-type buffer layer 5, p-type collector layer 6, trench 7, upper insulating film 8a, lower insulating film 8b, upper electrode 9, lower electrode 10, boundary insulating film 11, interlayer insulating film 12, emitter electrode 13 and collector electrode 14. In addition, as Figure 3 As shown, the gate electrode 15 is provided in the peripheral region 40 .

[0028] The first main surface of the semiconductor substrate in the active region 30 corresponds to n + type source layer 4 and a p + The first main surface is the upper surface of the semiconductor substrate. The second main surface of the semiconductor substrate corresponds to the surface (lower surface) of the p-type collector layer 6. The second main surface is the surface on the opposite side of the first main surface and is the lower surface of the semiconductor substrate. Figure 2 The semiconductor substrate corresponds to n + Type source layer 4 and p + The range is from the upper surface of the p-type contact layer to the lower surface of the p-type collector layer 6.

[0029] n － The drift layer 1 is composed of a semiconductor substrate. － The type drift layer 1 is provided between the first main surface and the second main surface of the semiconductor substrate. － The n-type drift layer 1 is a semiconductor layer containing arsenic, phosphorus, or the like as an n-type impurity, and the concentration of the n-type impurity is preferably 1.0E+12 / cm 3 Above and 1.0E+15 / cm 3 the following.

[0030] The n-type carrier storage layer 2 has a － The n-type drift layer 1 is provided on the first main surface side of the semiconductor substrate. The n-type carrier storage layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity is preferably 1.0E+13 / cm 3 Above and 1.0E+17 / cm 3By providing the n-type carrier storage layer 2, the conduction loss when the current flows can be reduced. In addition, the semiconductor device 100 may be provided with an n-type carrier storage layer 2 instead of an n-type carrier storage layer 2. － The structure of the n-type drift layer 1 can also be formed by forming the n-type carrier accumulation layer 2 and the n-type carrier accumulation layer 2. － type drift layer 1 are collectively defined as a drift layer.

[0031] The p-type base layer 3 is provided on the first main surface side of the semiconductor substrate relative to the n-type carrier storage layer 2. The p-type base layer 3 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is preferably 1.0E+12 / cm 3 Above and 1.0E+19 / cm 3 Next, the p-type base layer 3 is in contact with the upper insulating film 8 a of the trench 7 . When a gate driving voltage is applied to the upper electrode 9 , a channel is formed in the p-type base layer 3 .

[0032] n + The n-type source layer 4 is provided on the first main surface side of the semiconductor substrate relative to the p-type base layer 3. + The p-type source layer 4 is a surface layer of the semiconductor substrate and is selectively provided above the p-type base layer 3. + The source layer 4 is a semiconductor layer containing arsenic, phosphorus or the like as an n-type impurity, and the concentration of the n-type impurity is preferably 1.0E+17 / cm 3 Above and 1.0E+20 / cm 3 Below. + The type source layer 4 is in contact with the upper insulating film 8a of the trench 7. + The type source layer 4 is sometimes referred to as n + type emitter layer.

[0033] Although not shown in the figure, p + The p-type contact layer is provided on the first main surface side of the semiconductor substrate relative to the p-type base layer 3. + The p-type contact layer is selectively disposed above the p-type base layer 3 as a surface layer of the semiconductor substrate. + The p-type contact layer is provided above the p-type base layer 3 along the extending direction of the trench 7 in the region where the n-type contact layer is not provided. + The region of the type source layer 4. + The p-type contact layer is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is preferably 1.0E+15 / cm 3 Above and 1.0E+20 / cm 3 In addition, p + The p-type contact layer is a region where the concentration of p-type impurities is higher than that of the p-type base layer 3. +In the case of the p-type contact layer and the p-type base layer 3, they may be referred to separately or the p + The p-type contact layer and the p-type base layer 3 together define a p-type base layer 3 .

[0034] The n-type buffer layer 5 is n － The n-type drift layer 1 is provided on the second main surface side of the semiconductor substrate. The n-type buffer layer 5 is a semiconductor layer containing at least one of phosphorus and protons as n-type impurities, and the concentration of the n-type impurities is preferably 1.0E+12 / cm 3 Above and 1.0E+18 / cm 3 The concentration of the n-type impurity in the n-type buffer layer 5 is lower than that in the n-type buffer layer 5. － When the semiconductor device 100 is in the off state, the depletion layer of the n-type buffer layer 5 extends from the p-type base layer 3 to the second main surface to reduce the occurrence of punch-through. － type drift layer 1 together is defined as an n － In addition, the n-type carrier storage layer 2, the n-type buffer layer 5, and the n-type drift layer 1 may be formed. － type drift layer 1 together is defined as an n － In addition, the n-type buffer layer 5 is not necessarily required, and an n-type buffer layer 5 may be provided in the region of the n-type buffer layer 5. － Type drift layer 1.

[0035] The p-type collector layer 6 is provided on the second main surface side of the semiconductor substrate relative to the n-type buffer layer 5. The p-type collector layer 6 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is preferably 1.0E+16 / cm 3 Above and 1.0E+20 / cm 3 the following.

[0036] The groove 7 is provided on the first main surface of the semiconductor substrate, that is, the upper surface of the semiconductor substrate. The groove 7 penetrates the semiconductor substrate in the thickness direction from the first main surface of the semiconductor substrate. + type source layer 4 and p-type base layer 3 and reaches n － Type drift layer 1.

[0037] In addition, the inner wall surface of the groove 7 is covered by an insulating film 8. Although the insulating film 8 can be composed of a single film, in the case of the present embodiment, it is composed of an upper insulating film 8a covering the upper part of the groove 7 and a lower insulating film 8b covering the lower part. The upper insulating film 8a covers the side surface of the upper part of the groove 7, and the lower insulating film 8b covers the side surface of the lower part from the bottom of the groove 7. The upper insulating film 8a and the lower insulating film 8b are, for example, oxide films. In addition, the thickness of the lower insulating film 8b can also be made thicker than that of the upper insulating film 8a. By setting such a structure, it is possible to suppress the destruction of the insulating film caused by electric field concentration at the groove end 7a described later.

[0038] In addition, the trench 7 has a two-stage structure having two electrodes, an upper electrode 9 and a lower electrode 10, inside, that is, a split gate structure. The upper electrode 9 is provided in the trench 7 via an upper insulating film 8a, and the lower electrode 10 is provided on the second main surface side of the upper electrode 9 via a lower insulating film 8b. In addition, the upper electrode 9 and the lower electrode 10 are insulated by a boundary insulating film 11. That is, in the trench 7, the lower electrode, the boundary insulating film, and the upper electrode are sequentially stacked via insulating films to form a two-stage structure. Here, the lower electrode 10 is connected to the n via the lower insulating film 8b. － The top electrode 9 is opposite to the p-type drift layer 1. The bottom of the top electrode 9 is located closer to the second main surface than the p-type base layer 3.

[0039] The upper electrode 9 and the lower electrode 10 are formed by depositing polysilicon doped with n-type or p-type impurities, and the impurity concentration of the polysilicon is 1.0E+17 / cm 3 ~1.0E+22 / cm 3 The impurity concentration of the lower electrode 10 is higher than that of the upper electrode 9, for example, 1.0E+19 / cm 3 ~1.0E+22 / cm 3 . Preferably 1.0E+20 / cm 3 ~1.0E+22 / cm 3 .

[0040] In addition, if Figure 3As shown, the upper electrode 9 is electrically connected to the gate electrode 15 at the peripheral region 40, and the lower electrode 10 is electrically connected to the emitter electrode 13 at the active region 30. In addition, at the peripheral portion of the extension direction of the trench 7 located in the peripheral region 40, the lower electrode 10 extends to the outside than the upper electrode 9. The portion of the lower electrode 10 that extends to the outside than the upper electrode 9 is set as the extension portion 10a of the lower electrode 10. Moreover, the extension portion 10a is further extended to the first main surface of the semiconductor substrate in a manner covering the end of the upper electrode 9. In addition, the extension portion 10a is also insulated from the upper electrode 9 by the boundary insulating film 11. In addition, the portion of the lower electrode 10 for electrically connecting the lower electrode 10 to the emitter electrode 13 is set as the pull-up region portion 10b. The pull-up region portion 10b is further extended to the first main surface of the semiconductor substrate in a manner penetrating the upper electrode 9. In addition, the pull-up region portion 10b is also insulated from the upper electrode 9 by the boundary insulating film 11.

[0041] In addition, if Figure 3 As shown, the interlayer insulating film 12 is provided on the upper electrode 9 and the lower electrode 10 of the trench 7 .

[0042] Although not shown in the figure, the barrier metal is formed on the first main surface of the semiconductor substrate, in the region where the interlayer insulating film 12 is not provided, and on the interlayer insulating film 12. The barrier metal is formed of, for example, a conductor containing titanium. The conductor containing titanium is, for example, titanium nitride or TiSi. TiSi is an alloy of titanium and silicon (Si). + Type source layer 4, p + The barrier metal and the n + Type source layer 4, p + The type contact layer is electrically connected to the lower electrode 10.

[0043] The emitter electrode 13 is provided on the barrier metal provided in the active region 30. The emitter electrode 13 is formed of, for example, an aluminum silicon alloy (Al-Si alloy). The emitter electrode 13 is connected to the n + Type source layer 4, p + The emitter electrode 13 is electrically connected to the contact layer and the lower electrode 10. The emitter electrode 13 can also be composed of a plurality of metal films, which are composed of an aluminum alloy film and other metal films. For example, the emitter electrode 13 can also be composed of an aluminum alloy film and a plated film. The plated film is formed, for example, by chemical plating or electrolytic plating. The plated film is, for example, a nickel (Ni) film. A tungsten film can also be formed in a tiny area between mutually adjacent interlayer insulating films 12. The emitter electrode 13 is formed on the tungsten film. The embedding property of the tungsten film is better than that of the plated film, so a good emitter electrode 13 is formed.

[0044] In addition, the barrier metal and the emitter electrode 13 may be defined together as one emitter electrode 13. In addition, the barrier metal is not necessarily required. In the case where the barrier metal is not provided, the emitter electrode 13 is provided at n + Type source layer 4, p + The barrier metal may be disposed only on the n-type contact layer and the lower electrode 10, and in ohmic contact with them. + The emitter electrode 13 is formed on an n-type semiconductor layer such as the n-type source layer 4. The interlayer insulating film 12 may be provided on a portion of the lower electrode 10. In this case, the emitter electrode 13 is electrically connected to the lower electrode 10 in any region on the lower electrode 10.

[0045] In addition, if Figure 3 As shown, the gate electrode 15 is provided at n in the peripheral region 40. － The gate electrode 15 is formed on the drift layer 1 and the upper electrode 9 and is in ohmic contact with them. In addition, the interlayer insulating film 12 may be provided on a part of the upper electrode 9. In this case, the gate electrode 15 is electrically connected to the upper electrode 9 in any region on the upper electrode 9.

[0046] The collector electrode 14 is provided on the second main surface side of the semiconductor substrate relative to the p-type collector layer 6. The collector electrode 14 is formed of an aluminum alloy, for example, similarly to the emitter electrode 13. The collector electrode 14 is in ohmic contact with the p-type collector layer 6 and is electrically connected to the p-type collector layer 6. The collector electrode 14 may also be composed of an aluminum alloy and a plated film. In addition, the collector electrode 14 may also have a structure different from that of the emitter electrode 13.

[0047] As described above, the semiconductor device 100 including the IGBT is constructed. Figure 4 , the details of the structure of the outer peripheral portion of the groove 7 in the extending direction of the groove 7 in the structure of the above-mentioned groove 7 will be described.

[0048] like Figure 4 As shown, the region of the groove 7 corresponding to the extension portion 10a of the lower electrode 10 is set as the groove end 7a. The groove width is narrowest at the groove end 7a. Here, the width of the groove end 7a is set as the first width W1, and the groove width becomes the smallest W1 at the groove end 7a.

[0049] By adopting the above-mentioned structure, it is possible to improve the avalanche withstand voltage of the semiconductor device 100. The reason for this will be described below.

[0050] First, in the on state in the IGBT, the － A large number of electrons and holes flow into the n-type drift layer 1. Next, when the switch is turned off, the electrons and holes stop flowing to the n-type drift layer 1. － Here, the flow into the n －The holes in the type drift layer 1 flow from the peripheral region 40 where there is no discharge path toward the emitter electrode 13 for discharging holes. That is, the holes also flow into the trench end 7a at a high density, so that the hole density at the trench end 7a increases. Since the inflow of electrons stops, the space charge density at the trench end 7a increases, the electric field strength increases, and thus an avalanche occurs.

[0051] As described above, by configuring the groove width to be the narrowest at the groove end 7a, the mesa width W1 in the region between the grooves can be increased at the groove end 7a. M , thus expanding the hole discharge path and reducing the hole density. As a result, the space charge density can be reduced, the increase in electric field strength can be suppressed, and the avalanche withstand voltage can be improved.

[0052] In addition, since the lower electrode 10 is electrically connected to the emitter electrode 13, the potential is lower than that of the upper electrode 9. Therefore, when the switch is turned off, holes are attracted not only to the side walls of the region corresponding to the upper electrode 9 in the groove 7, but also to the side walls of the region corresponding to the lower electrode 10. As described above, by configuring the extension portion 10a of the lower electrode 10 at the front end portion in the groove 7, holes are also attracted to the side walls of the groove end 7a, which can be － A low-resistance p-type inversion layer is formed in the p-type drift layer 1. That is, at the trench end 7a, holes can pass through the low-resistance p-type inversion layer, thereby promoting the discharge of holes.

[0053] Next, use Figure 5 A modification of the first embodiment is described. Figure 5 As shown in FIG. 1 , the region with the narrowest groove width may be set to a region corresponding to a portion of the upper electrode 9 in addition to the region corresponding to the extension portion 10a in the groove 7. Here, the region corresponding to a portion of the upper electrode 9 is a region corresponding to the upper electrode 9 existing in the peripheral region 40. By setting such a structure, the region where the groove width is set to W1, which is the narrowest in the groove 7, is expanded. Therefore, the mesa width W M The wide area is enlarged, so the hole density can be further reduced and the avalanche withstand voltage can be improved.

[0054] As described above, in the semiconductor device 100 of the present embodiment, the mesa width is changed by changing the trench width, so that the mesa width at the trench end 7a becomes the largest. This can reduce the hole density at the trench end 7a, and in the semiconductor device 100 having an IGBT with a split gate structure, it is possible to improve the avalanche withstand voltage.

[0055] In addition, in the semiconductor device 100 of the present embodiment, the hole discharge path can be expanded, so holes can be easily discharged and turn-off loss can be reduced. Therefore, by reducing turn-off loss, switching loss can be reduced in the semiconductor device 100 having an IGBT with a split gate structure.

[0056] The method for manufacturing the semiconductor device 100 of the present embodiment is basically the same as the method for manufacturing the semiconductor device 100 of the conventional IGBT having a split gate trench structure. However, in the etching step for forming the trench 7, an etching mask is used which sets the trench width at least at the trench end 7a of the trench 7 to the narrowest W1.

[0057] The method for manufacturing the semiconductor device 100 will be described in detail. The method for manufacturing the semiconductor device 100 includes a step of preparing a semiconductor substrate, a step of forming a first main surface side of the semiconductor substrate, and a step of forming a second main surface side of the semiconductor substrate.

[0058] First, the process of preparing a semiconductor substrate is described. In this embodiment, an n-type wafer containing n-type impurities is prepared as a semiconductor substrate. The semiconductor substrate may be a so-called FZ wafer made by the FZ (Floating Zone) method, or a so-called MCZ wafer made by the MCZ (Magnetic field applied CZochralki) method. Alternatively, the semiconductor substrate may be a wafer made by the sublimation method or CVD (chemical vapor deposition). In this process, the semiconductor substrate as a whole is bonded to the n-type wafer. － The concentration of the n-type impurity is appropriately selected according to the withstand voltage specification of the semiconductor device 100. For example, when the withstand voltage specification of the semiconductor device 100 is 1200V, the concentration of the n-type impurity is adjusted so that the n － The specific resistance of the type drift layer 1 is about 40 to 120 Ω·cm. In this embodiment, although the semiconductor substrate is prepared as a whole, － The process of preparing an n-type wafer of the type drift layer 1 is not limited to this process. For example, the process of ion implanting n-type impurities from the first main surface or the second main surface of the semiconductor substrate and the process of diffusing the n-type impurities by heat treatment can be used to prepare an n-type wafer. － Type drift layer 1 semiconductor substrate.

[0059] Next, the process of forming the first main surface side of the semiconductor substrate is described. First, n-type impurities for forming the n-type carrier storage layer 2 are ion-implanted into the n-type carrier storage layer 2 from the first main surface side of the semiconductor substrate. －The surface layer of the n-type drift layer 1 is formed by ion implantation of p-type impurities from the first main surface side of the semiconductor substrate. The p-type impurities are, for example, boron. After the ion implantation, a heat treatment is performed to diffuse the n-type impurities and the p-type impurities, thereby forming the n-type carrier storage layer 2 and the p-type base layer 3.

[0060] During the above-mentioned ion implantation, a mask having an opening in a prescribed area is formed on the first main surface of the semiconductor substrate. N-type impurities and p-type impurities are injected into the area corresponding to the opening of the mask. The mask is formed by a process of coating a resist on the first main surface of the semiconductor substrate and a process of forming an opening in a prescribed area of ​​the resist using a photolithography (photolithography) technique. Hereinafter, such a process of forming a mask having an opening in a prescribed area is referred to as mask processing. N-type impurities and p-type impurities are injected into the prescribed area by the mask processing. As a result, an n-type carrier storage layer 2 and a p-type base layer 3 are selectively formed within the surface of the first main surface of the semiconductor substrate.

[0061] Next, to form n + The n-type impurities of the p-type source layer 4 are ion-implanted into the surface layer of the p-type base layer 3 from the first main surface side of the semiconductor substrate. At this time, the n-type impurities are implanted through mask processing. + The p-type source layer 4 is selectively formed on the surface layer of the p-type base layer 3. The n-type impurity is, for example, arsenic or phosphorus.

[0062] Next, to form p + The p-type impurity of the p-type contact layer is ion-implanted into the surface layer of the p-type base layer 3 from the first main surface side of the semiconductor substrate. At this time, the p-type impurity is implanted through mask processing, and the p + The p-type contact layers are selectively formed on the surface layer of the p-type base layer 3. The p-type impurity is, for example, boron or aluminum.

[0063] Next, a through hole is formed from the first main surface of the semiconductor substrate. + type source layer 4 and p-type base layer 3 and reaches n － The trench 7 of the type drift layer 1. In the active region 30, the n + The sidewalls of the trench 7 of the type source layer 4 constitute n + Type source layer 4 is a part of the electrode.

[0064] In order to form the trench 7, first, an oxide film is deposited on the first main surface of the semiconductor substrate. The oxide film is, for example, SiO 2Next, an opening is formed in the oxide film of the portion where the groove 7 is formed, and a mask having an opening is formed. In addition, when the mask is formed, a mask having an opening such that the width W1 of the groove 7 is the narrowest in the groove end 7a is formed. Finally, the groove 7 is formed by etching the semiconductor substrate through the mask.

[0065] Next, the semiconductor substrate is heated in an atmosphere containing oxygen to form a lower insulating film 8b on the inner wall of the trench 7 and the first main surface of the semiconductor substrate. The lower insulating film 8b formed on the first main surface of the semiconductor substrate is removed in a later step.

[0066] Next, the lower electrode 10 is formed inside the trench 7 having the lower insulating film 8b formed on the inner wall. Polycrystalline silicon doped with n-type or p-type impurities is deposited inside the trench 7 by CVD (chemical vapor deposition) or the like to form the lower electrode 10. As a result, the lower electrode 10 is formed inside the trench 7 via the lower insulating film 8b.

[0067] Next, a mask is formed by masking to open the trench 7 filled with the upper electrode 9, and the lower electrode 10 in the trench 7 is etched. Thereafter, the portion of the lower insulating film 8b in the trench 7 where the upper insulating film 8a is formed is removed.

[0068] Next, the semiconductor substrate is heated in an atmosphere containing oxygen to form an upper insulating film 8a on the inner wall of the trench 7 and the first main surface of the semiconductor substrate. In addition, a boundary insulating film 11 is formed on the first main surface of the lower electrode 10. In addition, the upper insulating film 8a formed on the first main surface of the semiconductor substrate is removed in a later step.

[0069] Next, the upper electrode 9 is formed inside the trench 7 having the upper insulating film 8a formed on the inner wall. Polycrystalline silicon doped with n-type or p-type impurities is deposited inside the trench 7 by CVD (chemical vapor deposition) or the like to form the upper electrode 9. As a result, the upper electrode 9 is formed inside the trench 7 via the upper insulating film 8a.

[0070] Next, an interlayer insulating film 12 is formed on the trench 7. The interlayer insulating film 12 is deposited by masking, and the oxide film formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 12 includes, for example, SiO 2 as an oxide film.

[0071] Then, a contact hole is formed in the interlayer insulating film 12. The contact hole is formed in the n + Type source layer 4, p + type contact layer.

[0072] Next, a barrier metal is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 12. The barrier metal is formed by PVD (physical vapor deposition) or CVD.

[0073] Next, the emitter electrode 13 is formed on the barrier metal. The emitter electrode 13 is formed by a PVD method such as sputtering or evaporation. The emitter electrode 13, for example, includes an aluminum silicon alloy (Al-Si alloy). In addition, the second emitter electrode 13 may be formed on the emitter electrode 13 by chemical plating or electrolytic plating. The second emitter electrode 13, for example, includes nickel or a nickel alloy. The second emitter electrode 13 may also have a stacked structure, for example, including two or more metal layers. The stacked structure is composed of, for example, a Ni film, a Pd film, and an Au film, and is formed by a plating method.

[0074] Plating can easily form a thick metal film. In the thick emitter electrode 13, the heat capacity increases, so the heat resistance of the emitter electrode 13 is improved. In addition, when a nickel alloy is further formed on the aluminum silicon alloy by plating, the plating process can also be performed after the second main surface side of the semiconductor substrate is processed.

[0075] Next, the process of forming the second main surface side of the semiconductor substrate is described. First, the process of thinning the semiconductor substrate is described. The second main surface of the semiconductor substrate is ground to be thinned to a predetermined thickness corresponding to the design of the semiconductor device 100. The thickness of the ground semiconductor substrate is, for example, not less than 80 μm and not more than 200 μm.

[0076] Next, the steps of forming the n-type buffer layer 5 and the p-type collector layer 6 are described. First, n-type impurities for forming the n-type buffer layer 5 are ion-implanted into the n-type collector layer 6 from the second main surface side of the thinned semiconductor substrate. － The surface layer of the n-type drift layer 1. As the n-type impurity, for example, phosphorus may be implanted, or protons may be implanted. Alternatively, for example, both phosphorus and protons may be implanted.

[0077] Protons are injected from the second main surface of the semiconductor substrate to a deep position at a relatively low acceleration energy. The injection depth of protons can be relatively easily controlled by changing the acceleration energy. Therefore, when protons are injected multiple times while changing the acceleration energy, an n-type buffer layer 5 is formed that is wider than the n-type buffer layer 5 containing phosphorus in the thickness direction of the semiconductor substrate.

[0078] In addition, phosphorus has a higher activation rate as an n-type impurity than protons. Even in a thinned semiconductor substrate, the n-type buffer layer 5 containing phosphorus can more reliably reduce the occurrence of punch-through caused by the expansion of the depletion layer. In order to further thin the semiconductor substrate, it is preferred to form an n-type buffer layer 5 containing both protons and phosphorus. In this case, the protons are injected into a position deeper than the phosphorus from the second main surface of the semiconductor substrate.

[0079] Next, p-type impurities for forming the p-type collector layer 6 are ion-implanted from the second main surface side of the semiconductor substrate. As the p-type impurity, for example, boron is implanted. After the ion implantation, the second main surface of the semiconductor substrate is irradiated with laser. By this laser annealing, the implanted boron is activated to form the p-type collector layer 6.

[0080] During the laser annealing, phosphorus, which is an n-type impurity injected into a relatively shallow position from the second main surface of the semiconductor substrate, is also activated at the same time. On the other hand, protons are activated at a relatively low annealing temperature of about 350°C to 500°C. Therefore, it is preferred that after the protons are injected, the semiconductor substrate is not heated to a temperature higher than 350°C to 500°C except for the step of activating the protons. Laser annealing heats only the vicinity of the second main surface of the semiconductor substrate to a high temperature. Therefore, laser annealing is effective for the activation of n-type impurities or p-type impurities after the injection of protons.

[0081] Next, the process of forming the collector 14 is described. The collector 14 is formed on the second main surface of the semiconductor substrate. The collector 14 may also be formed over the entire second main surface of the semiconductor substrate. The collector 14 includes an aluminum silicon alloy, titanium, etc. The collector 14 is formed by PVD such as sputtering and evaporation. The collector 14 may also be formed by a plurality of metal layers including an aluminum silicon alloy, titanium, nickel, gold, etc. Alternatively, the collector 14 may also have a structure in which another metal film is formed on the metal film formed by PVD by chemical plating or electrolytic plating.

[0082] Through the above-mentioned steps, the semiconductor device 100 is manufactured. Since a plurality of semiconductor devices 100 are manufactured in a matrix on one n-type wafer, the semiconductor device 100 is completed by cutting into individual semiconductor devices 100 by laser dicing or blade dicing.

[0083] Implementation method 2.

[0084] use Figure 6 , 7 The semiconductor device in the second embodiment will be described. Figure 6 , 7 and Figure 4 , 5 Similarly, a top view of the outer periphery of the groove 7 is shown. Figure 6As shown, the width of the groove end 7a in the groove 7 is set to the first width W1. In addition, the groove width of the region with the widest groove width in the groove 7 is set to the second width W2. In the semiconductor device of embodiment 2, similarly to embodiment 1, the groove 7 is formed so that the groove width is narrowest in the groove end 7a. And, it is characterized in that the groove width of the groove end 7a is narrower than the width of the region with the widest groove width in the groove 7. That is, the groove 7 is formed so that the groove width is W1<W2, and the groove width gradually narrows toward the front end of the groove end 7a, so that the groove width changes from W2 to W1. In embodiment 2, the region with the widest groove width is the region in the groove 7 corresponding to a portion of the upper electrode 9 in the peripheral region.

[0085] By setting the above structure, the mesa width is expanded in the area where the groove width is narrow, so the hole discharge path can be expanded. Therefore, the hole discharge is promoted, so the increase of the hole density in the area where the groove width is the widest and holes are difficult to discharge can be suppressed, and the avalanche withstand voltage can be improved.

[0086] In addition, if Figure 7 As shown, the region with the widest groove width exists in the pull-up region 50 that electrically connects the upper electrode 9 and the gate electrode 15, and considering that in the groove 7, the groove width in the pull-up region 50 is wider than the groove width corresponding to the upper electrode 9 existing in the active region 30. This is because the groove width of the pull-up region 50 is widened by an amount equivalent to the area of ​​the contact hole configured to electrically connect the upper electrode 9 and the gate electrode 15. Therefore, the mesa width in the pull-up region 50 becomes narrower, so the hole density increases, and the avalanche withstand voltage is likely to decrease.

[0087] In this case, if Figure 7 As shown, the trench width of the pull-up region 50 as the widest trench width is set to W2, and the trench width of the trench end 7a as the narrowest trench width is set to W1, so that W1 < W2. Furthermore, the trench width is gradually narrowed toward the trench end 7a, so as to change from W2 to W1.

[0088] By adopting the above structure, the mesa width is expanded in the region other than the pull-up region 50, so the hole discharge path can be expanded. Therefore, hole discharge is promoted, so that the increase of hole density in the pull-up region 50 where holes are difficult to discharge can be suppressed, and the avalanche withstand voltage can be improved.

[0089] As described above, in the semiconductor device of the second embodiment, in addition to the same effects as those of the first embodiment, even when there is a region with the widest trench width from which holes are difficult to be discharged, an increase in hole density can be suppressed and the avalanche withstand voltage can be improved.

[0090] Implementation method 3.

[0091] use Figures 8 to 10 The semiconductor device in the third embodiment will be described. Figures 8 to 10 and Figure 4 , 5 Similarly, a top view of the outer periphery of the trench 7 is shown. Here, the semiconductor device of the third embodiment is formed in the same manner as the first embodiment, with the width of the trench end 7a being the first width W1, and the trench width in the trench end 7a being the smallest W1. Furthermore, the feature is that in the trench end 7a, the trench width gradually narrows as it moves toward the front end of the trench end 7a.

[0092] like Figure 8 As shown, in the semiconductor device of Embodiment 3, the trench width is narrowed by two or more steps and becomes the smallest W1 at the trench end 7a. By narrowing the trench width in stages, the variation of the hole density in the trench 7 can be reduced, the electric field concentration can be alleviated, and the avalanche withstand voltage can be further improved.

[0093] In addition, if Fig. 9 As shown in FIG. 1 , a tapered portion 20 may be provided at the groove end 7a. By providing the tapered portion 20, the width of the groove 7 can be gradually narrowed toward the front end of the groove 7. That is, at the groove end 7a, the width of the groove 7 can be made to be the smallest W1. According to the above structure, the deviation of the hole density in the groove 7 can be reduced, the electric field concentration can be alleviated, and the avalanche withstand voltage can be further improved. In addition, although Fig. 9 In the embodiment, the tapered portion is provided only at the trench end 7 a , but the tapered portion may also be provided in the region of the trench 7 corresponding to the upper electrode 9 .

[0094] In addition, if Fig.10 As shown, the front end of the groove end 7a can also be formed into a round shape. In the case where the front end of the groove end 7a is an angular shape, the electric field is easily concentrated on the groove end 7a. By eliminating the angle of the groove end 7a and forming it into a round shape, the width of the groove 7 can be gradually narrowed toward the front end of the groove 7. That is, in the groove end 7a, the width of the groove 7 can be made the smallest W1. According to the above structure, the deviation of the hole density in the groove 7 can be reduced, the electric field concentration can be alleviated, and the avalanche withstand voltage can be further improved.

[0095] As described above, in the semiconductor device of the third embodiment, in addition to the same effects as those of the first embodiment, it is possible to suppress variations in hole density and alleviate electric field concentration, thereby further improving avalanche withstand voltage.

[0096] Implementation method 4.

[0097] use Fig.11 A semiconductor device in accordance with a fourth embodiment will be described. Fig.11 and Figure 4 , 5 Similarly, a top view of the outer periphery of the trench 7 is shown. The semiconductor device of the fourth embodiment is formed in the same manner as the first embodiment, wherein the width of the trench end 7a is set to the first width W1, and the trench width in the trench end 7a is the smallest W1. Furthermore, the respective extension portions 10a are joined by the intersecting trench 21 extending in the direction intersecting the extending direction of the trench 7, that is, the X direction, and the adjacent lower electrodes 10 are connected to each other.

[0098] The inner wall surface of the intersecting groove 21 is covered by an insulating film. As for the insulating film, although it can also be composed of a separate film like the upper insulating film 8a and the lower insulating film 8b, in the fourth embodiment, it is a cross insulating film 22. In addition, a cross electrode 23 is provided in the intersecting groove 21 via the cross insulating film 22. For the cross electrode 23, the extension portion 10a of the lower electrode 10 can also be further formed to extend in a direction intersecting with the extension direction of the groove 7, that is, the X direction. In addition, the cross electrode 23 is electrically connected to the emitter electrode 13. Here, as in the fourth embodiment, when the intersecting groove 21 is formed, the portion of the intersecting groove 21 is not included in the "groove end 7a". By setting it as the above-mentioned structure, the avalanche withstand voltage in the groove end 7a can be further improved. The reason is explained below.

[0099] The trench end 7a is a portion where the electric field is likely to concentrate. In particular, when the switch is turned off, holes are more likely to be attracted to the lower electrode 10 at the emitter potential than to the upper electrode 9 at the gate potential. That is, holes are more likely to be attracted to the trench end 7a where the extension 10a is arranged in the lower electrode 10. Therefore, the electric field at the trench end 7a increases, and a dynamic avalanche is generated, which may sometimes lead to deterioration of the characteristics of the semiconductor device.

[0100] Here, as in Embodiment 4, the adjacent groove ends 7a are connected by the cross groove 21, thereby eliminating the protrusion at the groove ends 7a and relaxing the electric field. Also, as in Embodiment 1, the groove width is made the narrowest W1 at the groove ends 7a, thereby obtaining the same effect as in Embodiment 1.

[0101] As described above, in the semiconductor device of the fourth embodiment, the hole density can be suppressed and the occurrence of avalanche can be suppressed similarly to the first embodiment. In addition, the electric field at the trench end 7a can be further relaxed, and the avalanche withstand voltage can be further improved.

[0102] In addition, the structure shown in the above embodiment is an example of the content of the present disclosure, and can also be combined with other well-known technologies. In addition, part of the structure can be omitted or changed within the scope that does not deviate from the gist of the present disclosure.

[0103] In addition, in the above-mentioned embodiment, an IGBT having a trench structure with a split gate in which the first conductivity type is set to an n-type and the second conductivity type is set to a p-type is described as an example. However, this is only an example, and for example, an IGBT having a trench structure with a split gate of a p-channel type in which the conductivity type of each component is reversed relative to an n-channel type may also be used. In addition, the present invention can also be applied to MOSFETs of the same structure. In the case of MOSFETs, electrons and holes are generated when an avalanche occurs. By applying the present invention to MOSFETs, the discharge of the generated holes is promoted, and the deterioration of the characteristics of the semiconductor device can be suppressed.

Claims

1. A semiconductor device comprising an active region constituting a semiconductor switch element and a peripheral region outside the active region provided with a gate electrode, characterized in that: The semiconductor switch element comprises: a first conductivity type drift layer; A second conductive type base layer, which is disposed on the upper surface side of the first conductive type drift layer; A first conductive type source layer, which is disposed on an upper surface side of the second conductive type base layer; A second conductive type collector layer, which is disposed on the lower surface side of the first conductive type drift layer; an emitter electrode electrically connected to the first conductive type source layer; as well as a collector electrode electrically connected to the second conductive type collector layer, The range from the upper surface of the first conductive type source layer to the lower surface of the second conductive type collector layer is set as a semiconductor substrate, The semiconductor device further comprises: a plurality of trenches, which penetrate from the upper surface of the semiconductor substrate in the depth direction to reach the first conductive type drift layer and extend from the active region toward the peripheral region; and an interlayer insulating film covering each of the plurality of trenches, Each of the plurality of trenches has a two-stage structure in which a lower electrode, a boundary insulating film, and an upper electrode are sequentially stacked via an insulating film inside the trench. The lower electrode is electrically connected to the emitter electrode, The upper electrode is electrically connected to the gate electrode, At the outer peripheral portion of the groove in the outer peripheral region, an extension portion of the lower electrode extending to the outside than the upper electrode further extends to the upper surface of the semiconductor substrate in a manner covering an end portion of the upper electrode. The width of the groove is narrowest at the ends of the groove.

2. The semiconductor device according to claim 1, wherein: The width of the trench is narrowest in a region of the trench corresponding to the extension portion of the lower electrode and a portion of the upper electrode.

3. The semiconductor device according to claim 1, wherein: The width of the groove gradually narrows toward the front end of the groove end.

4. The semiconductor device according to claim 3, wherein: The width of the groove gradually narrows.

5. The semiconductor device according to claim 3, wherein: A tapered portion is provided at the end of the groove.

6. The semiconductor device according to claim 3, wherein: The front end of the groove end is formed in a round shape.

7. The semiconductor device according to claim 1, wherein: The width of the groove gradually narrows from a width of a region where the groove has the widest width toward a front end of the groove end.

8. The semiconductor device according to claim 7, wherein: A region where the trench has the widest width exists in a pull-up region connecting the upper electrode and the gate electrode.

9. The semiconductor device according to any one of claims 1 to 8, wherein: A cross groove is also provided to connect the front end of the groove end with the front end of the adjacent groove end. Inside the intersecting trench, an intersecting electrode is provided via an insulating film. The cross electrode is electrically connected to the emitter electrode.

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