Method of manufacturing super-junction device

Abstract

The application discloses a manufacturing method of a super-junction device, which comprises the following steps: growing a first epitaxial layer; injecting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region, the first selected region at least including a partial region of a terminal region close to a transition region; forming a trench gate, a gate conductive material layer outside a gate trench of the trench gate is removed, and a top surface of the gate conductive material layer in the gate trench is flat; forming a well region and performing annealing; forming a second trench; growing a P-type doped second epitaxial layer in the second trench, removing the second epitaxial layer outside the second trench and flattening a surface of the second epitaxial layer in the second trench; completing subsequent front process and setting a thermal process according to a requirement of controlling mutual diffusion of PN impurities of a super-junction structure; and completing back process. The application can effectively control the mutual diffusion of the PN impurities of the super-junction structure, improve the PN balance of the terminal region, improve BVdss of the device, improve consistency of the BVdss and improve EAS capability.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a superjunction (SJ) device. Background Art

[0002] Compared to conventional VDMOS, existing superjunction MOSFETs (SJMOSFETs) have been widely used in various electronic and power fields due to their superior device characteristics. The SJMOSFET structure's unique N-pillar (N-type pillar) and P-pillar (P-type pillar) compensate for each other, enabling high breakdown voltages at high N-type epitaxial layer (NEPI) concentrations. This results in low on-resistance and high breakdown voltages exceeding the limits of silicon.

[0003] There are two main manufacturing processes for existing superjunction MOSFET devices. One involves multiple epitaxial depositions and photolithography processes to cumulatively form spaced P-type regions, known as P-type pillars, and N-type regions, known as N-type pillars. The other involves forming P-type pillars in a thick N-epitaxial layer through deep trenches and trench filling, thereby forming spaced P-type and N-type regions. In existing deep trench technology, to ensure smooth planarization of the deep trench P-type pillars, the P-type pillar formation process is typically placed before the polysilicon formation process, such as that for the gate structure. Furthermore, the P-type well process is sometimes placed after the P-type pillar formation. This results in the P-type pillars and N-type pillars undergoing gate oxide processing and other high-temperature thermal processes after the P-type pillars are formed in the trenches. This results in the interdiffusion of P-type and N-type pillar impurities, increasing the device's source-drain on-resistance (Rdson) and impacting chip performance.

[0004] With this setup, the vertical Vds is borne by the electric field established within the PN columns (i.e., the P-type and N-type columns) after depletion. In the chip's terminal region, the borne is by the surface electric field formed after PN column depletion. During chip design and manufacturing, it's generally difficult to align the relationship between the source-drain breakdown voltage (BVdss) and the PN dose difference (actually, the P-type impurity concentration is controllable) in the lateral terminal region with the BVdss borne by the vertical electric field within the active region (i.e., the P-N dose difference (actually, the P-type impurity concentration is controllable)). This results in a loss of the device's critical process window and affects the chip's BVdss consistency. Summary of the Invention

[0005] The technical problem solved by the present application is to provide a super-junction device manufacturing method, which can independently set the thermal processes of trench gate, well region and super-junction structure, so that the quality of trench gate and well region is guaranteed, the PN impurity diffusion of super-junction structure is effectively controlled, the smaller step super-junction structure is realized, the on-resistance of super-junction device is reduced, the process complexity and cost are not increased, the PN balance of terminal region is increased, the source-drain breakdown voltage (BVdss) of terminal region is improved, the BVdss of the whole device is further improved, the process window of P-type doping concentration of P-type column is expanded, and the BVdss consistency and single pulse avalanche energy (EAS) capacity of the device are improved.

[0006] To solve the above technical problem, the super-junction device manufacturing method provided by the present application comprises the following steps:

[0007] Growing a first epitaxial layer doped with N-type on the surface of a semiconductor substrate.

[0008] Using photolithography and ion implantation to implant first P-type impurities into the surface region of the first epitaxial layer in a first selected region, the super-junction device comprising an active region, a transition region and a terminal region, the terminal region surrounding the active region, the transition region being between the active region and the terminal region, and the first selected region at least including a part of the terminal region close to the transition region.

[0009] Forming a plurality of trench gates in the first epitaxial layer of the active region, the trench gate comprising a gate oxide layer formed on the inner surface of a gate trench and a gate conductive material layer filled in the gate trench, each trench gate being located in a corresponding N-type column, the gate conductive material layer outside the gate trench being removed, and the top surface of the gate conductive material layer in the gate trench being flat to ensure the formation process of a subsequent second trench, and the quality of the trench gate being adjusted by adjusting the thermal process in the formation process of the trench gate.

[0010] Forming a P-type doped well region in the active region and the transition region by photolithography and ion implantation and annealing the well region, each trench gate passing through the well region, and the well region being set to a desired position and repairing ion implantation damage by adjusting the thermal process of annealing the well region.

[0011] Performing photolithography and etching to form a plurality of second trenches in the first epitaxial layer, the first epitaxial layer between each second trench serving as an N-type column, and the second trenches being located in the active region, the transition region and a part of the terminal region close to the transition region.

[0012] A P-type doped second epitaxial layer is grown in the second trench, the second epitaxial layer outside the second trench is completely removed and the surface of the second epitaxial layer in the second trench is smoothed, a P-type column is formed by the second epitaxial layer filled in the second trench, and a super junction structure is formed by alternating arrangement of the N-type column and the P-type column; outside the well area, the first P-type impurity is used to compensate for the P-type impurity whose surface area of ​​the P-type column is reduced due to thermal segregation.

[0013] After completing the super junction structure, a subsequent front-side process is performed, wherein a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities in the super junction structure so that the on-resistance of the super junction device meets the requirement;

[0014] Complete the backside process of super junction devices.

[0015] A further improvement is that the material of the semiconductor substrate includes silicon, the material of the first epitaxial layer includes silicon, and the material of the second epitaxial layer includes silicon.

[0016] A further improvement is that the steps of forming the trench gate include:

[0017] A first dielectric layer is formed on a top surface of the first epitaxial layer.

[0018] The gate trench formation region is defined by photolithography.

[0019] The first dielectric layer and the first epitaxial layer in the gate trench formation region are sequentially etched to form the gate trench.

[0020] The gate oxide layer is formed by a thermal oxidation process.

[0021] The gate conductive material layer is formed.

[0022] A first chemical mechanical polishing process is performed to planarize the gate conductive material layer to remove the gate conductive material layer above the top surface of the first epitaxial layer outside the gate trench and to planarize the top surface of the gate conductive material layer within the gate trench.

[0023] A further improvement is that the gate conductive material layer is made of polysilicon.

[0024] A further improvement is that, before or after the first chemical mechanical polishing process, the method further comprises:

[0025] Perform a rapid thermal oxidation or a rapid thermal annealing.

[0026] A further improvement is that the maximum annealing temperature of the well region reaches above 1100° C. and the annealing time reaches above 30 minutes.

[0027] A further improvement is that before performing the photolithography process on the second trench, the method further includes: forming a hard mask layer.

[0028] In the etching process of the second trench, the hard mask layer is etched first, and then the first epitaxial layer is etched.

[0029] A further improvement is that the hard mask layer includes a bottom silicon dioxide layer, a middle silicon nitride layer and a top silicon dioxide layer stacked in sequence.

[0030] After the etching of the second trench is completed, the top silicon dioxide layer and the middle silicon nitride layer outside the second trench are removed, and then the second epitaxial layer is grown.

[0031] Afterwards, a second chemical mechanical polishing process is used to planarize the second epitaxial layer, so as to completely remove the second epitaxial layer outside the second trench and make the surface of the second epitaxial layer in the second trench flat.

[0032] A further improvement is that the subsequent front surface process includes:

[0033] Photolithography and ion implantation are performed to form an N-type heavily doped source region, wherein the source region and the corresponding side surface of the gate trench are self-aligned.

[0034] The source region is annealed and activated. The annealing of the source region is performed in a furnace at a temperature below 950° C. or in a rapid thermal annealing process.

[0035] A further improvement is that the subsequent front surface process further includes:

[0036] An interlayer film is formed, wherein the interlayer film is formed by stacking an undoped silicon dioxide layer and a BPSG layer.

[0037] A contact hole opening is formed through the interlayer film.

[0038] A P-type heavily doped contact region is formed at the bottom of the contact hole opening.

[0039] A metal layer is filled in the contact hole opening to form a contact hole.

[0040] A front metal layer is formed and the front metal layer is patterned and etched to form a source and a gate. The source region and the well region are connected to the source through the corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer at the trench gate lead-out end.

[0041] A further improvement is that it also includes performing a front passivation protection process, the front passivation protection process including:

[0042] forming a dielectric protective layer; the dielectric protective layer is one or a combination of SiON layer, SiO2 layer, SiN layer and Si-rich silicon oxide layer.

[0043] performing photolithography and dry etching to pattern the dielectric protective layer to open the lead-out area of the source electrode and the lead-out area of the gate electrode.

[0044] Further improvement is that a front side passivation protection process is also included, which comprises:

[0045] forming a polyimide layer.

[0046] performing photolithography and development to pattern the polyimide layer to open the lead-out area of the source electrode and the lead-out area of the gate electrode.

[0047] baking the polyimide layer.

[0048] Further improvement is that the metal layer forming the contact hole comprises:

[0049] forming a barrier layer on the inner surface of the contact hole opening.

[0050] forming a tungsten layer filled in the contact hole opening.

[0051] the barrier layer and the tungsten layer also extend onto the surface of the interlayer dielectric outside the contact hole opening.

[0052] the front side metal layer is formed on the surface of the tungsten layer, and when the front side metal layer is patterned, the tungsten layer and the barrier layer in the removed area of the front side metal layer are also removed, and the tungsten layer and the barrier layer in the retained area of the front side metal layer are also retained.

[0053] Alternatively, the barrier layer and the tungsten layer outside the contact hole opening are removed before the front side metal layer is formed, and then a second barrier layer and the front side metal layer are formed or the front side metal layer is directly formed.

[0054] Further improvement is that the back side process comprises:

[0055] back side thinning the semiconductor substrate.

[0056] forming an N-type heavily doped drain region; the semiconductor substrate is N-type heavily doped, and the drain region is directly composed of the thinned semiconductor substrate; or the drain region is composed of a back side implantation region formed by back side P-type heavy doping of the semiconductor substrate.

[0057] forming a back side metal layer and composing a drain electrode by the back side metal layer.

[0058] Further improvement is that the setting of the thermal process corresponding to the subsequent front side process includes that when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to no more than 950℃.

[0059] Further improvement is that the second trench has a side vertical structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is constant.

[0060] Alternatively, the second trench has a side inclined structure with a top wide and a bottom narrow, the doping concentration of the second epitaxial layer is constant, and the doping concentration of the first epitaxial layer is set according to the side inclination angle and depth of the second trench, and the doping concentration of the first epitaxial layer at the corresponding depth gradually increases from the bottom to the top of the second trench, so that the charge balance of adjacent N-type columns and corresponding P-type columns at each longitudinal position meets the requirements.

[0061] Alternatively, the second trench has a side inclined structure with a top wide and a bottom narrow, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is set according to the side inclination angle and depth of the second trench, and the doping concentration of the second epitaxial layer at the corresponding depth gradually decreases from the bottom to the top of the second trench.

[0062] Further improvement is that after the first chemical mechanical polishing process, the top surface of the gate conductive material layer in the gate trench is located below the top surface of the first epitaxial layer outside the gate trench. to facilitate the subsequent formation of the second trench.

[0063] Further improvement is that the formation of the source region also includes forming an N-type heavily doped cutoff region in the surface region of the first epitaxial layer outside the lateral edge of the termination region.

[0064] Further improvement is that the inner lateral edge of the first selected region is located between the inner lateral edge and the outer lateral edge of the transition region.

[0065] The outer lateral edge of the first selected region is located inside the outer lateral edge of the outermost P-type column.

[0066] Alternatively, the outer lateral edge of the first selected region is flush with the outer lateral edge of the outermost P-type column.

[0067] Alternatively, the outer lateral edge of the first selected region is located outside the outer lateral edge of the outermost P-type column, and the first distance between the outer lateral edge of the first selected region and the outer lateral edge of the termination region is greater than the maximum distance at which punch-through occurs between the outer lateral edge of the first selected region and the outer lateral edge of the termination region.

[0068] Further improvement is that the first selected area is an opening area of a photoresist pattern formed by photoetching of the first P-type impurity.

[0069] Between the inner edge and the outer edge of the first selected area, the first selected area is fully opened.

[0070] Alternatively, between the inner edge and the outer edge of the first selected area, a subsequent forming area of the P-type column is covered, and an outer area of the P-type column is opened.

[0071] Further improvement is that the implanting impurity of the ion implantation of the first P-type impurity includes boron, and the implanting energy is 50keV-2MeV.

[0072] The implanting dose of the ion implantation of the first P-type impurity ensures that after the backside process is completed, the impurity concentration of the first P-type impurity is not higher than 20% of the N-type impurity concentration of the N-type region outside the P-type column, and the net doping of the N-type region outside the P-type column remains N-type doping.

[0073] Further improvement is that after the ion implantation of the first P-type impurity is completed, it further includes:

[0074] Annealing and activating the first P-type impurity, the maximum temperature of the annealing of the first P-type impurity is above 1100℃, and the minimum time is 60-180 minutes.

[0075] The process flow of the super junction device is specially set, mainly placing the trench gate and well region forming process which requires higher thermal process before the super junction structure forming process, setting the flatness of the gate conductive material layer in the gate trench to include removing the gate conductive material layer outside the gate trench and making the top surface of the gate conductive material layer in the gate trench flat, which can ensure that the etching and filling process of the second trench of the super junction structure is well realized; since the trench gate and well region forming process is placed before the super junction structure forming process, the trench gate and well region forming process which requires higher thermal process can avoid adversely affecting the super junction structure, so that the trench gate and well region can use higher thermal process according to their own needs, so that the quality of the trench gate and well region is well guaranteed; at the same time, the thermal process after the super junction structure is controlled, which can ensure that the PN impurity diffusion of the super junction structure meets the requirements, so that the on-resistance of the super junction device meets the requirements. Since the PN impurity diffusion of the super junction structure can be well controlled, the step of the super junction structure can be further reduced, so that the on-resistance of the super junction device can be further reduced and the performance of the super junction device can be improved.

[0076] The present application controls the flatness of the gate conductive material layer in the gate trench, and can ensure that the super-junction structure can be formed under the conditions of forming the trench gate and the well region, so the present application has the advantages of not increasing the process complexity and cost.

[0077] Therefore, the present application can independently set the heat process of the trench gate, the heat process of the well region and the heat process of the super-junction structure, so that the quality of the trench gate and the well region is guaranteed, and the PN impurity diffusion of the super-junction structure is effectively controlled, which is beneficial to realize smaller step super-junction structure and reduce the on-resistance of the super-junction device, and meanwhile, the process complexity and cost are not increased.

[0078] The present application also adds the first P-type impurity in the termination region, which can compensate the P-type impurity whose surface area of the P-type column is reduced due to thermal segregation, so that the PN balance of the termination region, i.e. the charge matching between the P-type column and the N-type column, is increased, thereby improving the source-drain breakdown voltage (BVdss) of the termination region and further improving the BVdss of the whole device, and also expanding the process window of the P-type doping concentration of the P-type column, improving the BVdss consistency of the device and improving the EAS capability of the device. For example, the BVdss of the termination region is greater than the BVdss of the active region by setting the first P-type impurity, so the BVdss of the whole device is determined by the BVdss of the active region, the P-type doping concentration of the P-type column does not need to be adjusted for the difference between the PN matching of the termination region and the active region, and the P-type doping concentration of the P-type column only needs to meet the needs of the BVdss of the active region, so the process window of the P-type doping concentration of the P-type column is expanded, and the BVdss consistency of the device is increased; after the process window of the P-type doping concentration of the P-type column is expanded, the adjustment range of the P-type doping concentration of the P-type column is increased, which is more beneficial to improve the performance of the super-junction device, for example, by increasing the P-type doping concentration of the P-type column, the EAS performance of the device can be further improved. BRIEF DESCRIPTION OF DRAWINGS

[0079] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0080] Figure 1 is a flow chart of the manufacturing method of the super-junction device of the first embodiment of the present application;

[0081] Figures 2A-2L is a schematic diagram of the device structure in each step of the manufacturing method of the super-junction device of the first embodiment of the present application;

[0082] Figure 3 is a schematic diagram of the device structure of the super-junction device formed by the manufacturing method of the super-junction device of the second embodiment of the present application;

[0083] Figure 4 is a device structure schematic diagram of the super junction device formed by the manufacturing method of the third embodiment of the present application;

[0084] Figure 5 is a device structure schematic diagram of the super junction device formed by the manufacturing method of the fourth embodiment of the present application. DETAILED DESCRIPTION

[0085] As shown in Figure 1 , it is a flow chart of the manufacturing method of the first embodiment of the present application; as shown in Figures 2A to 2L , it is a device structure schematic diagram in each step of the manufacturing method of the first embodiment of the present application; the manufacturing method of the super junction device of the embodiment of the present application includes the following steps:

[0086] Step S101, as shown in Figure 2A , growing a first epitaxial layer 102 doped with N-type on the surface of a semiconductor substrate 101.

[0087] In the first embodiment of the present application, the material of the semiconductor substrate 101 includes silicon, the material of the first epitaxial layer 102 includes silicon, and the material of the subsequently formed second epitaxial layer 108 includes silicon.

[0088] Step S102, as shown in Figure 2A , using photolithography and ion implantation to implant the first P-type impurity 204 into the surface region of the first epitaxial layer 102 in the first selected region 303, the super junction device includes an active region 201, a transition region 202 and a terminal region 203, the terminal region 203 surrounds the active region 201 on the side, the transition region 202 is located between the active region 201 and the terminal region 203, and the first selected region 303 at least includes a part of the terminal region 203 close to the transition region 202.

[0089] Figure 2A In the first embodiment of the present application, the semiconductor substrate 101 has a larger area, and in the cross section of Figure 2A , the curve AA indicates that the active region 201, the transition region 202 and the terminal region 203 are continuously distributed, and the structure in the area omitted by the curve AA can refer to the structure shown in Figure 2A . The ion implantation is indicated by the arrow line marked 302.

[0090] In the first embodiment of the present application, the first selected region 303 is the opening region of the photoresist pattern formed by photolithography of the first P-type impurity 204. Before photolithography, it also includes forming an implantation protection film 301 composed of a dielectric layer. After photolithography, the implantation protection film 301 is etched using the photoresist pattern as a mask, so that the first selected region 303 is transferred to the opening region of the implantation protection film 301.

[0091] Then, the first P-type impurity 204 can be implanted into the surface region of the first epitaxial layer 101 corresponding to the first selected region 303 by ion implantation with the protective film 301 as a mask. Figure 2A In some embodiments, the implanted first P-type impurity 204 is represented by a hollow circle, indicating that the first P-type impurity 204 is implanted into the surface region of the corresponding first epitaxial layer 101, but the net doping concentration of the surface region of the first epitaxial layer 101 implanted with the first P-type impurity 204 is still N-type doping.

[0092] In the first embodiment of the present application, the first selected region 303 is fully open between the inner edge and the outer edge of the first selected region 303. In other embodiments, the formation region of the subsequent P-type pillar can be covered between the inner edge and the outer edge of the first selected region 303, and the outer region of the P-type pillar is open, i.e., the first P-type impurity 204 is only implanted into the surface region of the N-type pillar or the surface region of the first epitaxial layer 101 extending outside the super junction structure in the termination region.

[0093] In the first embodiment of the present application, the outer edge of the first selected region 303 is flush with the outer edge of the outermost P-type pillar.

[0094] The inner edge of the first selected region 303 is located at the inner edge of the transition region 202, i.e., the entire transition region 202 is implanted with the first P-type impurity 204.

[0095] In some embodiments, the implanted impurity of the ion implantation of the first P-type impurity 204 includes boron, and the implantation energy is 50 keV to 2 MeV.

[0096] The implantation dose of the ion implantation of the first P-type impurity 204 ensures that after the subsequent backside process is completed, i.e., after the first P-type impurity 204 has undergone all the thermal processes, the impurity concentration of the first P-type impurity 204 is not higher than 20% of the N-type impurity concentration of the N-type region outside the P-type pillar, and the net doping of the N-type region outside the P-type pillar remains N-type doping.

[0097] In some embodiments, after the ion implantation of the first P-type impurity 204 is completed, further comprising:

[0098] The first P-type impurity 204 is annealed and activated, and the maximum temperature of the annealing of the first P-type impurity 204 is above 1100°C, and the minimum time is 60 minutes to 180 minutes. In some preferred examples, the process parameters of the annealing of the first P-type impurity 204 are: a temperature of 1100°C and a time of 60 minutes to 180 minutes, or a temperature of 1175°C and a time of 60 minutes to 180 minutes.

[0099] Step S103, as Figure 2DAs shown, a plurality of trench gates are formed in the first epitaxial layer 102 of the active region 201, and the trench gates include a gate oxide layer 104 formed on the inner surface of the gate trench 103 and a gate conductive material layer 105 filled in the gate trench 103; each trench gate is located in a subsequent corresponding N-type column; the gate conductive material layer 105 outside the gate trench 103 is removed, and the top surface of the gate conductive material layer 105 inside the gate trench 103 is flat to ensure the implementation of the subsequent second trench 107 formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the trench gate formation process.

[0100] In the first embodiment of the present invention, the steps of forming the trench gate include:

[0101] like Figure 2B As shown, a first dielectric layer 304 is formed on the top surface of the first epitaxial layer 102. The material of the first dielectric layer 304 is generally silicon oxide.

[0102] like Figure 2B As shown, the photolithography defines the formation area of ​​the gate trench 103. The photolithography forms a photoresist pattern 305, and the open area of ​​the photoresist pattern 305 is the formation area of ​​the gate trench 103.

[0103] like Figure 2C As shown, the first dielectric layer 304 and the first epitaxial layer 102 in the gate trench 103 formation region are sequentially etched to form the gate trench 103. The photoresist pattern 305 is removed before or after etching the first epitaxial layer 102 or consumed during the etching process.

[0104] like Figure 2D As shown, a thermal oxidation process is used to form the gate oxide layer 104. The thermal oxidation process has a high temperature thermal process. Since the thermal process corresponding to the thermal oxidation process is not affected by the subsequently formed super junction structure, the parameters of the thermal oxidation process can be set according to the need to form a high-quality gate oxide layer 104, and ultimately the quality of the trench gate is guaranteed.

[0105] like Figure 2D As shown, a gate conductive material layer 105 is formed.

[0106] In the first embodiment of the present invention, the gate conductive material layer 105 is made of polysilicon.

[0107] like Figure 2D As shown, a first chemical mechanical polishing process is performed to planarize the gate conductive material layer 105 to remove the gate conductive material layer 105 above the top surface of the first epitaxial layer 102 outside the gate trench 103 and to flatten the top surface of the gate conductive material layer 105 inside the gate trench 103 .

[0108] In the first embodiment of the present invention, after the first chemical mechanical polishing process, the top surface of the gate conductive material layer 105 in the gate trench 103 is located below the top surface of the first epitaxial layer 102 outside the gate trench 103. so that the second trench 107 can be formed subsequently, that is, so that the subsequent process of the second trench 107 can achieve its goal.

[0109] In some embodiments, before or after the first chemical mechanical polishing process, the method further includes performing a rapid thermal oxidation or a rapid thermal annealing.

[0110] like Figure 2D As shown, after the trench gate is formed, a protective film 205 is formed on the surface of the first epitaxial layer 102. The protective film 205 is formed by thinning the first dielectric layer 304, or by removing the first dielectric layer 304 and then oxidizing it. The protective film 205 can serve as a protective layer for subsequent ion implantation.

[0111] Step S104: Figure 2E As shown, a P-type doped well region 106 is formed in the active region 201 and the transition region 202 by photolithography and ion implantation. The well region 106 is then annealed. Each trench gate passes through the well region 106. The thermal process of the annealing of the well region 106 is adjusted to push the well region 106 to a set position and repair ion implantation damage. The well region located in the transition region 202 is individually indicated by the reference numeral 106a.

[0112] In the first embodiment of the present invention, the maximum annealing temperature of the well region 106 is greater than 1100° C., and the annealing time is greater than 30 minutes.

[0113] Step S105: Figure 2F As shown, photolithography and etching are performed to form multiple second trenches 107 in the first epitaxial layer 102, and the first epitaxial layer 102 between the second trenches 107 serves as an N-type column; the second trenches 107 are located in the active area 201, the transition area 202 and the terminal area 203 in a portion close to the transition area 202.

[0114] In the first embodiment of the present invention, before performing the photolithography process on the second trench 107, the process further includes forming a hard mask layer. The hard mask layer includes a bottom silicon dioxide layer, a middle silicon nitride layer, and a top silicon dioxide layer stacked in sequence.

[0115] In the etching process of the second trench 107 , the hard mask layer is etched first, and then the first epitaxial layer 102 is etched.

[0116] After the etching of the second trench 107 is completed, the top silicon dioxide layer and the middle silicon nitride layer outside the second trench 107 are removed, and then the subsequent growth of the second epitaxial layer 108 is performed.

[0117] Step S106: Figure 2F As shown, a P-type doped second epitaxial layer 108 is grown in the second trench 107, the second epitaxial layer 108 outside the second trench 107 is completely removed and the surface of the second epitaxial layer 108 in the second trench 107 is flattened, the second epitaxial layer 108 filled in the second trench 107 forms a P-type column, and the N-type column and the P-type column are alternately arranged to form a super junction structure; outside the well region 106, the first P-type impurity 204 is used to compensate for the P-type impurity whose surface area of ​​the P-type column is reduced due to thermal segregation.

[0118] The process then includes: planarizing the second epitaxial layer 108 by a second chemical mechanical polishing process, so as to completely remove the second epitaxial layer 108 outside the second trench 107 and make the surface of the second epitaxial layer 108 in the second trench 107 flat.

[0119] The N-type pillars and P-type pillars of the super junction structure achieve charge matching at all longitudinal positions.

[0120] In some embodiments, the second trench 107 has a side vertical structure, the doping concentration of the first epitaxial layer 102 is constant, and the doping concentration of the second epitaxial layer 108 is constant.

[0121] In some embodiments, the second trench 107 may have a side inclined structure with a wide top and a narrow bottom, the doping concentration of the second epitaxial layer 108 may be constant, and the doping concentration of the first epitaxial layer 102 may be set according to the side inclination angle and depth of the second trench 107. From the bottom to the top of the second trench 107, the doping concentration of the first epitaxial layer 102 at the corresponding depth may gradually increase so that the charge balance of adjacent N-type columns and corresponding P-type columns at each longitudinal position may meet the requirements.

[0122] In some embodiments, the second trench 107 may have a side inclined structure with a wide top and a narrow bottom, the doping concentration of the first epitaxial layer 102 may be constant, and the doping concentration of the second epitaxial layer 108 may be set according to the side inclination angle and depth of the second trench 107. From the bottom to the top of the second trench 107, the doping concentration of the second epitaxial layer 108 at the corresponding depth gradually decreases.

[0123] Step S107 : After the super junction structure is completed, a subsequent front side process is performed. In the subsequent front side process, a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities in the super junction structure so that the on-resistance of the super junction device meets the requirement.

[0124] In the first embodiment of the present invention, the setting of the thermal process corresponding to the subsequent front surface process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950°C.

[0125] In the first embodiment of the present invention, the subsequent front surface process includes:

[0126] like Figure 2G As shown, photolithography and ion implantation are performed to form an N-type heavily doped source region 109, which is self-aligned with the side surface of the corresponding gate trench 103. Before forming the source region 109, a protective film 206 needs to be formed.

[0127] In the first embodiment of the present invention, while forming the source region 109 , the method further includes forming an N-type heavily doped cutoff region 109 a in the surface region of the first epitaxial layer 102 at the outer edge of the termination region 203 .

[0128] The source region 109 is annealed and activated. The annealing of the source region 109 is performed in a furnace at a temperature below 950° C. or by rapid thermal annealing.

[0129] like Figure 2H As shown, an interlayer film 110 is formed, and the interlayer film 110 is formed by stacking an undoped silicon dioxide layer and a BPSG layer.

[0130] like Figure 2G As shown, a contact hole opening 111 is formed through the interlayer film 110 . The contact hole opening 111 also penetrates into the first epitaxial layer 102 and passes through the surface source region 109 and contacts the well region 106 .

[0131] A contact hole opening 111 is also formed on the top of the stop region 109 a , and the bottom of the contact hole opening 111 also passes through the stop layer 109 a and contacts the first epitaxial layer 102 at the bottom.

[0132] like Figure 2I As shown, a P-type heavily doped contact region 207 , ie, a contact hole implantation (CT IMP), is formed at the bottom of the contact hole opening 111 .

[0133] A metal layer is filled in the contact hole opening 111 to form a contact hole.

[0134] The metal layers that form the contact holes include:

[0135] like Figure 2I As shown, a barrier layer 112 is formed on the inner surface of the contact hole opening 111 .

[0136] In some embodiments, the material of the barrier layer 112 includes a Ti layer and a TiN layer stacked sequentially.

[0137] like Figure 2J As shown, a tungsten layer 113 is formed and filled in the contact hole opening 111 .

[0138] The barrier layer 112 and the tungsten layer 113 also extend onto the surface of the interlayer film 110 outside the contact hole opening 111 .

[0139] like Figure 2J As shown, a front metal layer 114 is formed. The front metal layer 114 is patterned and etched to form a source and a gate. The source region 109 and the well region 106 are connected to the source through corresponding contact holes at the top. The gate is connected to a contact hole at the top of the gate conductive material layer 105 at the trench gate lead. In some embodiments, the material of the front metal layer 114 includes AlCu.

[0140] In the first embodiment of the present invention, the front metal layer 114 is formed on the surface of the tungsten layer 113. When the front metal layer 114 is patterned, the tungsten layer 113 and the barrier layer 112 in the removal area of ​​the front metal layer 114 are also removed, and the tungsten layer 113 and the barrier layer 112 are also retained in the retention area of ​​the front metal layer 114.

[0141] In other embodiments, the barrier layer 112 and tungsten layer 113 outside the contact hole opening 111 can be removed before forming the front metal layer 114, and then a second barrier layer and the front metal layer 114 can be formed. In some embodiments, the second barrier layer includes a Ti layer and a TiN layer stacked in sequence. Alternatively, the front metal layer 114 can be formed directly without forming the second barrier layer.

[0142] Figure 2J In the figure, the patterned front metal layer 114 includes: a source electrode corresponding to label 114a, a gate bus corresponding to label 114b, a transition region field plate corresponding to label 114c, multiple terminal region field plates corresponding to labels 114d1, 114d2 to 114dx, and a metal connected to the drain electrode corresponding to label 114e. The bottom of metal 114e is connected to the cut-off region 109a. The source electrode 114a and the gate bus 114b need to be separated, and the gate bus 114b and the transition region field plate 114c can be an integrated structure or separated structures. The terminal region field plates 114d1, 114d2 to 114dx are separated structures. The number of terminal region field plates 114d1, 114d2 to 114dx can be adjusted as needed, and the terminal region field plates 114d1, 114d2 to 114dx can also be omitted.

[0143] In the first embodiment of the present invention, a front passivation protection process is further performed, and the front passivation protection process further comprises:

[0144] like Figure 2K As shown, a dielectric protection layer 115 is formed; the dielectric protection layer 115 is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer.

[0145] Photolithography and dry etching are performed to pattern the dielectric protection layer 115 to open the lead-out region of the source and the lead-out region of the gate.

[0146] like Figure 2L As shown, the front passivation protection process also includes:

[0147] A polyimide layer 116 is formed.

[0148] Photolithography and development are performed to pattern the polyimide layer 116 to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

[0149] The polyimide layer 116 is baked.

[0150] In the first embodiment of the present invention, the dielectric protection layer 115 and the polyimide layer 116 are stacked simultaneously.

[0151] In some embodiments, only the dielectric protection layer 115 may be formed, and the polyimide layer 116 may be omitted.

[0152] In some embodiments, the dielectric protection layer 115 can be omitted and only the polyimide layer 116 can be formed.

[0153] Step S108: Figure 2L As shown, the backside process of the super junction device is completed.

[0154] In the first embodiment of the present invention, the back surface process includes:

[0155] The semiconductor substrate 101 is back-thinned.

[0156] Forming a heavily N-type doped drain region. In the first embodiment of the present invention, the semiconductor substrate 101 is heavily N-type doped, and the drain region is directly formed from the thinned semiconductor substrate 101. In this case, the drain region does not require further activation. In other embodiments, the drain region may be formed from a backside implanted region in which the backside of the semiconductor substrate 101 is heavily P-type doped. Subsequently, activation of the drain region is required.

[0157] A back metal layer 117 is formed and the drain electrode is formed by the back metal layer 117. In some embodiments, the back metal layer 117 includes TiNiAg.

[0158] The first embodiment of the present application specially sets the process flow of the super-junction device, mainly places the formation process of the trench gate and the well region 106 which requires higher heat process before the formation process of the super-junction structure, sets the flatness of the gate conductive material layer 105 in the gate trench 103 to include that the gate conductive material layer 105 outside the gate trench 103 is removed and the top surface of the gate conductive material layer 105 in the gate trench 103 is flat, which can ensure that the etching and filling process of the second trench 107 of the subsequent super-junction structure is well realized; since the formation process of the trench gate and the well region 106 is placed before the formation process of the super-junction structure, the formation process of the trench gate and the well region 106 which requires higher heat process can avoid adverse effects on the super-junction structure, so that the trench gate and the well region 106 can use higher heat process according to their own needs, so that the quality of the trench gate and the well region 106 is well guaranteed; at the same time, the first embodiment of the present application also controls the heat process after the super-junction structure, which can ensure that the PN impurity diffusion of the super-junction structure meets the requirements, so that the on-resistance of the super-junction device meets the requirements. Since the PN impurity diffusion of the super-junction structure can be well controlled, the step of the super-junction structure can be further reduced, so that the on-resistance of the super-junction device can be further reduced and the performance of the super-junction device can be improved.

[0159] Although the first embodiment of the present application places the formation process of the trench gate and the well region 106 before the formation process of the super-junction structure, the first embodiment of the present application controls the flatness of the gate conductive material layer 105 in the gate trench 103, which can ensure that the super-junction structure can still be formed under the condition of forming the trench gate and the well region 106, so that the first embodiment of the present application also has the advantages of not increasing the process complexity and cost.

[0160] Therefore, the first embodiment of the present application can independently set the heat process of the trench gate, the heat process of the well region 106 and the heat process of the super-junction structure, so that the quality of the trench gate and the well region 106 is guaranteed, the PN impurity diffusion of the super-junction structure is effectively controlled, which is beneficial to realize the super-junction structure with smaller step and reduce the on-resistance of the super-junction device, and the process complexity and cost are not increased.

[0161] The first embodiment of the present invention further adds a first P-type impurity 204 to the terminal region 203. Outside the well region 106, the first P-type impurity 204 can compensate for the P-type impurity whose surface area of ​​the P-type column is reduced due to thermal segregation. This can increase the PN balance of the terminal region 203, that is, the charge matching between the P-type column and the N-type column, thereby increasing the source-drain breakdown voltage (BVdss) of the terminal region 203 and further increasing the BVdss of the entire device. It can also expand the process window of the P-type doping concentration of the P-type column, improve the BVdss consistency of the device and enhance the EAS capability of the device. For example, by setting the first P-type impurity 204, the BVdss of the terminal region 203 can be made greater than that of the active region 2 01, so the BVdss of the entire device is determined by the BVdss of the active area 201, and the P-type doping concentration of the P-type column does not need to be used to adjust the difference in PN matching between the terminal area 203 and the active area 201. The P-type doping concentration of the P-type column only needs to meet the BVdss requirement of the active area 201, so the process window of the P-type doping concentration of the P-type column is expanded, and the BVdss consistency of the device is increased; after the process window of the P-type doping concentration of the P-type column is expanded, the adjustment range of the P-type doping concentration of the P-type column will be increased, which is more conducive to improving the performance of the super junction device. For example, by increasing the P-type doping concentration of the P-type column, the EAS performance of the device can be further improved.

[0162] like Figure 3 FIG. 1 is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the second embodiment of the present invention. The difference from the method for manufacturing a super junction device according to the first embodiment of the present invention is that in the method for manufacturing a super junction device according to the second embodiment of the present invention:

[0163] The outer edge of the first selected region 303 is located outside the outer edge of the outermost P-type pillar, and a first distance exists between the outer edge of the first selected region 303 and the outer edge of the termination region 203. The first distance is greater than the maximum distance between the outer edge of the first selected region 303 and the outer edge of the termination region 203 at which punch-through occurs. In this application, the outer edge of the termination region 203 refers to the inner edge of the cut-off region 109a; the maximum distance between the outer edge of the first selected region 303 and the outer edge of the termination region 203 at which punch-through occurs refers to the maximum distance less than or equal to which the first P-type impurity 204 will punch-through into the N+-doped cut-off region 109a or the P+-doped contact region 207 corresponding to the bottom of the cut-off region 109a. In some embodiments, the first distance is greater than 10 microns.

[0164] like Figure 4 FIG. 1 is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the third embodiment of the present invention. The difference from the method for manufacturing a super junction device according to the first embodiment of the present invention is that in the method for manufacturing a super junction device according to the third embodiment of the present invention:

[0165] The outer edge of the first selected region 303 is located inside the outer edge of the outermost P-type pillar.

[0166] like Figure 5 , which is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the fourth embodiment of the present invention; the difference from the method for manufacturing a super junction device according to the second embodiment of the present invention is that in the method for manufacturing a super junction device according to the fourth embodiment of the present invention:

[0167] The inner edge of the first selected region 303 is located at the outer edge of the transition region 202 , that is, the first P-type impurity 204 is not implanted into the entire transition region 202 .

[0168] In other embodiments, the inner edge of the first selected region 303 is located in other regions between the inner edge and the outer edge of the transition region 202 , that is, the first P-type impurities 204 are formed only in a portion of the transition region 202 .

[0169] In the first embodiment of the present invention, taking an N-type MOSFET as an example, the thermal process after the formation of the P-type column can be greatly reduced, thereby further reducing the on-resistance of the device. The first embodiment of the present invention also adds a P-type ion implantation region in the terminal area to expand the process window of BVdss and P-type impurity concentration. By setting the terminal injection, that is, the first P-type impurity 204 injection, the absolute value of the terminal BVdss can also be adjusted. For example, when the BVdss of the terminal is higher than the BVdss of the active area, the BVdss of the device can be increased, the consistency of the device can be improved, and the EAS capability can be enhanced.

[0170] The following takes a 600V trench gate super junction N-type MOSFET as an example to further illustrate the first embodiment of the present invention in combination with corresponding parameters:

[0171] In step S101 , the semiconductor substrate 101 is a low-resistivity N-type substrate. For example, the resistivity of the semiconductor substrate 101 is less than 0.003 ohm.cm.

[0172] The thickness of the first epitaxial layer 102 is between 45 and 50 microns. The resistivity design of the first epitaxial layer 102 is related to the stepping of the subsequent P-type and N-type pillars, and can be simulated and designed using computer-aided software. For example, the stepping of the PN pillar is set to 5 microns, and the resistivity is set to 0.5 ohm.cm.

[0173] In step S102, the protective film 301 is injected into the

[0174] The first P-type impurity 204 is implanted with B as the impurity, and the implantation energy is 50keV to 2MeV. The dose is set according to the impurity concentration of the first epitaxial layer 102 of the device. Generally, the highest impurity concentration of B after all subsequent processes is set not to exceed 20% of the N-type impurity concentration. In some examples, the process parameters for the first P-type impurity 204 ion implantation are B600keV8E11 atoms / cm -2 , B60keV8E11 atoms / cm -2 Indicates that the injected impurity is B, the injection capacity is 60keV, and the injection dose is 8E11 atoms / cm -2 After that, it undergoes a high temperature annealing process, such as 1100℃ for 60-180min, or 1175℃ for 60-180min. 1100℃ for 60-180min means the annealing temperature is 1100℃ and the time is 60 minutes to 180 minutes.

[0175] In step S103 , the thickness of the first dielectric layer 201 is 0.5-2 microns.

[0176] The width and depth of the gate trench 103 can be set according to device performance. For example, the width of the gate trench 103 is set to 0.8 to 1.5 microns, and the depth is set to 2.5 to 4 microns. No gate trench 103 is formed in the transition region 202 and the terminal region 203. The first dielectric layer 304, which serves as a hard mask, is then completely removed, typically using a wet etch method.

[0177] The thickness of the gate oxide layer 104 is set to 500 angstroms to 1500 angstroms;

[0178] The resistivity of the polysilicon of the gate conductive material layer 105 is generally set at about 10 ohm.cm to 30 ohm.cm. Before or after the polysilicon planarization of the gate conductive material layer 105 is completed, a high-temperature RTO or high-temperature RTA can be performed to improve the leakage between the gate and drain of the product.

[0179] In step S104, ions are implanted into the well region 106 in the active region 201 and the transition region 202, but not in the terminal region 203. The impurity implanted into the well region 106 is generally B, with an implantation energy of 100 KeV. The implantation dose is designed according to the device threshold voltage requirement, for example, the implantation dose is 1E13 atoms / cm 2The ion implantation of the well region 106 can also be performed by using two different energy B implantations, so that different P-type wells, i.e. the well region 106, can be formed to adjust the performance parameters of the device, including threshold voltage and EAS, etc. After the ion implantation of the well region 106, a high temperature annealing can be performed, for example, 1100C for 30 minutes or higher temperature and longer time, so that the P-type well can be pushed to the set position and some damages caused by the ion implantation can be repaired.

[0180] Before the B implantation of the well region 106, the surface of the silicon, i.e. the semiconductor substrate 101 and the first epitaxial layer 102, is thinned to about 200 angstroms to serve as the protective film 205 during the ion implantation. The oxide film, i.e. the protective film 205, can be the film left after the previous polysilicon CMP, i.e. the first chemical mechanical polishing, and can be obtained by dry or wet etching. It can also be a thermal oxide film or a CVD film generated after the film after the polysilicon CMP is removed, and the latter can increase the consistency of the ion implantation protective film and improve the consistency of the device parameters, especially the threshold voltage.

[0181] In step S105, the thickness of the bottom silicon dioxide layer is The thickness of the middle silicon nitride layer is The thickness of the top silicon dioxide layer is 2-5 microns.

[0182] The width of the deep trench, i.e. the second trench 107, is 2.5 microns, the size of the N region between adjacent trenches, i.e. the distance between the second trenches 107, is 2.5 microns, and the depth of the second trench 107 is 40-42 microns, which can be set according to the requirements of the BVdss of the device.

[0183] After the etching of the second trench 107, the hard mask top SIO2 and SIN, i.e. the top silicon dioxide layer and the middle silicon nitride layer, are removed, and the bottom SIO2, i.e. the bottom silicon dioxide layer, is kept as a protective layer for the Si surface. Then, the second trench 107 is completely filled by P-type epitaxial deposition, and then the surface Si is completely removed by chemical mechanical polishing.

[0184] In this configuration, adjacent P-type and N-type pillars can be configured with the same stepping, P-type pillar width, and N-type pillar width in the active region 201, transition region 202, and terminal region 203. For example, the stepping can be set to 5μm, with a P-type pillar top width of 2.5μm and an N-type pillar top width of 2.5μm. Alternatively, the stepping in the transition region 202 and terminal region 203 can be different from that in the active region. Typically, the stepping in the transition region 202 and terminal region 203 is smaller than that in the active region. For example, the stepping in the transition region 202 and terminal region 203 can be set to 4.8μm, with a P-type pillar top width of 2.5μm and an N-type pillar top width of 2.3μm. The outermost P-type pillars in the terminal region 203 are located a certain distance from the outermost periphery of the chip, for example, 15-30 microns.

[0185] In step S107, Figure 2F As shown, the surface oxide film, that is, the bottom silicon dioxide layer, is partially removed, leaving about A thick film is used as a protective film 206 for the subsequent N+ implantation, i.e., the implantation of the source region 109, or the surface oxide film is completely removed first and then a layer of about 100 nm is deposited by RTO. The oxide film is used as the protective film 206, or a lower temperature process such as a thermal oxidation process at 800℃~950℃ is used to deposit about The thermal oxide film is used as a protective film 206. The reason for not using high temperature or long-term thermal processes is to reduce the mutual diffusion of impurities between the P-type and N-type columns. Then, photolithography and ion implantation are used to form the N+ region, i.e., the cutoff region 109a closest to the chip periphery of the source region 109 and the terminal region 203. No N+ region is provided in the rest of the transition region 202 and the terminal region 203. Here, N+ can be implanted with phosphorus or arsenic (As), for example, using As 60keV1~5E15 atoms / cm 2 , As 60Kev 1~5E15 atoms / cm 2 Indicates that the implanted impurity is As, the implantation energy is 60keV, and the implantation dose is 1 atom / cm 2 ~5E15 atoms / cm 2 After the ion implantation of the source region 109 , an activation process may be performed at a temperature below 950° C., for example, 900° C. for 30 min. RTA activation may also be used.

[0186] In the step of forming the interlayer film 110, a 2000 angstrom undoped silicon dioxide layer is first deposited, and then a 8000-10000 angstrom BPSG layer is deposited.

[0187] In the step of forming the contact hole, the contact hole opening 111 can penetrate into the Si, that is, the middle of the Si of the first epitaxial layer 102. arrive

[0188] The bottom of the contact hole opening 111 can be formed into a P-type region, i.e. a contact region 207, by implanting B or BF2. For example, when the contact region 207 is formed by implanting B, the implantation energy can be 30-60 Kev, and the implantation dose can be 5E14-1E15 / cm 2 This better ensures the ohmic contact between the metal in the contact hole opening 111 and the Si at the bottom of the contact hole opening 111, and reduces the contact resistance.

[0189] In the step of forming the barrier layer 112, the thickness of the Ti layer is The thickness of the TiN layer is

[0190] In the step of forming the tungsten layer 113, the process of filling the contact hole opening 111 with metal tungsten is to grow along the sidewall of the contact hole opening 111 and to contact the upper part in the central region of the contact hole opening 111. The upper part can have some gaps or can have no gaps. The tungsten can completely fill the contact hole opening 111, or can not completely fill the contact hole opening 111, as long as the subsequent metal can well cover the hole.

[0191] In the step of forming the front metal layer 114, the deposition temperature of AlCu can be set to 250-450C, and the thickness can be set to 2-6 microns. Then, the metal Al-Cu, the tungsten layer 113 below the metal Al-Cu, and the barrier layer 112 are removed by metal lithography and dry etching.

[0192] In addition, as an alternative embodiment, the following can be used as an alternative:

[0193] Before forming the front metal layer 114, the W on the surface of the Si is completely removed by dry etching, and then the barrier layer 112 below the W is also completely etched, and then Ti / TiN / AlCu, i.e. the second barrier layer 112a and the front metal layer 114, are deposited. The thickness of the films can be set as follows: 5 microns, or other settings, wherein 5 microns represents the thickness of the Ti layer The thickness of the TiN layer is The thickness of the AlCu is 5 microns. Or, after the W on the surface is completely etched, only AlCu is deposited, for example, 5 microns thick AlCu is deposited. After the AlCu deposition is completed, metal lithography and dry etching are performed.

[0194] It also includes a front passivation protection process, which includes:

[0195] A dielectric protective layer of 1-2 microns can be deposited, which can be SiON, SiO2, SiN, or a silicon-rich silicon oxide film, or a combination thereof. Then, the electrode extraction area of the gate and the electrode extraction area of the source are opened by photolithography and dry etching, while other areas, including the terminal area that bears the lateral voltage, are protected, which can improve the reliability of the product.

[0196] The front side passivation protection process further includes:

[0197] A polyimide film can be deposited on the surface of the silicon wafer, which can be formed on the surface of the dielectric protective layer, or the dielectric protective layer can be omitted. Then, the electrode extraction area of the gate and the electrode extraction area of the source are opened by photolithography and development, while other areas, including the terminal area that bears the lateral voltage, are protected, which can improve the reliability of the product. After photolithography and development, baking at 300-400C (30-90 min) can be performed, and the thickness of the polyimide film is 4-15 microns after baking.

[0198] In step S108, the entire silicon wafer thickness, i.e., the overall thickness of the semiconductor substrate 101 and the first epitaxial layer 102, is thinned to 60-200 microns.

[0199] The thickness of the TiNiAg of the back side metal layer 115 can be The Ti layer The Ni layer The Ag layer

[0200] The above process can realize the manufacture of a super-junction MOSFET, and can form the division of the active region, the transition region, and the terminal region that bears the lateral voltage. The electrode of the source region is extracted through the front side metal layer 114 in Figure 2L The gate is extracted through the trench gate in Figure 2L The drain is the back side metal layer 115.

[0201] In the first embodiment of the present application, the following further optimization can be performed:

[0202] In step S101, the first epitaxial layer 102 can be set according to the angle and depth of the trench, i.e. the second trench 107, in step S104. For example, if the trench is vertical, the resistivity of the first epitaxial layer 102 can be set to be constant, i.e. consistent from top to bottom. If the trench is an inclined trench with a large top and a small bottom, the N epitaxial, i.e. the first epitaxial layer 102, can be set to have a high concentration at the top and a low concentration at the bottom, with a linear change in concentration in the middle, so that at each position perpendicular to the trench, the PN balance can be achieved when the impurity concentration of the P-type column is a single concentration, which can better balance the source-drain breakdown voltage (BVdss) and Rdson of the device.

[0203] The filling of the trench in step S106, i.e. the filling of the second trench 107 with the second epitaxial layer 108, can also be set in combination with the setting of the first epitaxial layer 102 and the angle of the trench. For example, if the trench is vertical, the resistivity of the first epitaxial layer 102 can be set to be constant, i.e. consistent from top to bottom, and the impurity concentration of the P-type column can also be constant. If the resistivity of the first epitaxial layer 102 can be set to be constant, and the trench is an inclined trench with a large top and a small bottom, the P-type epitaxial deposition process can be set to have a high P-type impurity concentration at the beginning and gradually decrease the deposition concentration. Then, by evaluating the BVdss of the device and the window relationship of the P-type impurity setting, the specific process conditions can be determined, and the goal is to expand the process window of the P-type epitaxial process.

[0204] In the first embodiment of the present application, in order to reduce the mutual diffusion of PN impurities after the formation of the P-type column, the temperature during the heat process after the formation of the P-type column is limited to not exceed 950C for more than 10 minutes.

[0205] Compared with the prior art, the first embodiment of the present application adopts a new process flow without increasing the process complexity and cost. The high-temperature process of the gate oxide process, i.e. the formation process of the gate oxide layer 104, and the push well process of the P-type well are placed before the formation of the P-type column trench, i.e. the second trench 107. After the formation of the P-type column, the stability of the heat process is set to be below 950C, or only a RTA or other special short-time activation process is used. The first embodiment of the present application also adds a P-type ion implantation region in the terminal region to expand the process window of BVdss and P-type impurity concentration. By setting the terminal implantation, the absolute value of the terminal BVdss can also be adjusted. For example, when the BVdss of the terminal is higher than that of the active region, the BVdss of the device can be improved, the consistency of the device can be improved, and the EAS capability can be improved.

[0206] The application is described in detail above with specific examples, but these do not constitute a limitation on the application. Those skilled in the art can make many modifications and improvements without departing from the principles of the application, and these should be considered as within the scope of the application.

Claims

1. A method for manufacturing a super junction device, characterized in that: The steps include: growing an N-type doped first epitaxial layer on the surface of the semiconductor substrate; Implanting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region using photolithography and ion implantation, wherein the superjunction device includes an active region, a transition region, and a termination region, wherein the termination region surrounds the active region, the transition region is located between the active region and the termination region, and the first selected region includes at least a portion of the termination region adjacent to the transition region; forming a plurality of trench gates in the first epitaxial layer of the active region, wherein the trench gates include a gate oxide layer formed on an inner surface of a gate trench and a gate conductive material layer filled in the gate trench; Each of the trench gates is located in a subsequent corresponding N-type column; The gate conductive material layer outside the gate trench is removed, and the top surface of the gate conductive material layer inside the gate trench is flat, so as to ensure the implementation of the subsequent second trench formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the trench gate formation process; forming a P-type doped well region in the active region and the transition region by photolithography and ion implantation, and annealing the well region, wherein each trench gate passes through the well region, and adjusting the thermal process of the annealing of the well region so as to push the well region to a set position and repair ion implantation damage; Performing photolithography and etching to form a plurality of second trenches in the first epitaxial layer, wherein the first epitaxial layer between the second trenches serves as an N-type pillar; The second trench is located in a portion of the active region, the transition region, and the terminal region close to the transition region; A P-type doped second epitaxial layer is grown in the second trench, the second epitaxial layer outside the second trench is completely removed, and the surface of the second epitaxial layer in the second trench is flattened, the second epitaxial layer filled in the second trench forms a P-type pillar, and the N-type pillars and the P-type pillars are alternately arranged to form a superjunction structure; outside the well region, the first P-type impurity is used to compensate for the P-type impurity whose surface area of ​​the P-type pillars is reduced due to thermal segregation; After completing the super junction structure, a subsequent front-side process is performed, wherein a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities in the super junction structure so that the on-resistance of the super junction device meets the requirement; Complete the backside process of super junction devices.

2. The method for manufacturing a super junction device according to claim 1, wherein: The steps of forming the trench gate include: forming a first dielectric layer on a top surface of the first epitaxial layer; Photolithography defines a formation area of ​​the gate trench; Sequentially etching the first dielectric layer and the first epitaxial layer in the gate trench formation region to form the gate trench; forming the gate oxide layer by a thermal oxidation process; forming the gate conductive material layer; A first chemical mechanical polishing process is performed to planarize the gate conductive material layer to remove the gate conductive material layer above the top surface of the first epitaxial layer outside the gate trench and to planarize the top surface of the gate conductive material layer within the gate trench.

3. The method for manufacturing a super junction device according to claim 2, wherein: Before or after the first chemical mechanical polishing process, the method further includes: Perform a rapid thermal oxidation or a rapid thermal annealing.

4. The method for manufacturing a super junction device according to claim 1, wherein: The maximum annealing temperature of the well region is above 1100° C., and the annealing time is above 30 minutes.

5. The method for manufacturing a super junction device according to claim 1, wherein: Before performing the photolithography process of the second trench, the method further includes: forming a hard mask layer; In the etching process of the second trench, the hard mask layer is etched first, and then the first epitaxial layer is etched.

6. The method for manufacturing a super junction device according to claim 5, wherein: The hard mask layer includes a bottom silicon dioxide layer, a middle silicon nitride layer and a top silicon dioxide layer stacked in sequence; After the etching of the second trench is completed, removing the top silicon dioxide layer and the middle silicon nitride layer outside the second trench, and then growing the second epitaxial layer; Afterwards, a second chemical mechanical polishing process is used to planarize the second epitaxial layer, so as to completely remove the second epitaxial layer outside the second trench and make the surface of the second epitaxial layer in the second trench flat.

7. The method for manufacturing a super junction device according to claim 1, wherein: The subsequent front surface process includes: Performing photolithography and ion implantation to form an N-type heavily doped source region, wherein the source region and the corresponding side of the gate trench are self-aligned; Annealing and activating the source region, wherein the annealing of the source region is performed in a furnace at a temperature below 950° C. or by rapid thermal annealing; forming an interlayer film, wherein the interlayer film is formed by stacking an undoped silicon dioxide layer and a BPSG layer; forming a contact hole opening through the interlayer film; forming a P-type heavily doped contact region at the bottom of the contact hole opening; Filling the contact hole opening with a metal layer to form a contact hole; A front metal layer is formed and the front metal layer is patterned and etched to form a source and a gate. The source region and the well region are connected to the source through the corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer at the trench gate lead-out end.

8. The method for manufacturing a super junction device according to claim 7, wherein: The process also includes performing a front passivation protection process, wherein the front passivation protection process includes: forming a dielectric protection layer; the dielectric protection layer is a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer, or a combination thereof; The dielectric protection layer is patterned by photolithography and dry etching to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

9. The method for manufacturing a super junction device according to claim 7 or 8, wherein: The process also includes performing a front passivation protection process, wherein the front passivation protection process includes: forming a polyimide layer; Performing photolithography and development to pattern the polyimide layer to open the lead-out region of the source electrode and the lead-out region of the gate electrode; The polyimide layer is baked.

10. The method for manufacturing a super junction device according to claim 7, wherein: The metal layer forming the contact hole includes: forming a barrier layer, wherein the barrier layer is formed on the inner surface of the contact hole opening; forming a tungsten layer, wherein the tungsten layer is filled in the contact hole opening; The barrier layer and the tungsten layer further extend onto the surface of the interlayer film outside the contact hole opening; The front metal layer is formed on the surface of the tungsten layer. When the front metal layer is patterned, the tungsten layer and the barrier layer are also removed in the front metal layer removal area, and the tungsten layer and the barrier layer are also retained in the front metal layer retention area. Alternatively, the barrier layer and the tungsten layer outside the contact hole opening are removed before forming the front metal layer, and then a second barrier layer and the front metal layer are formed, or the front metal layer is directly formed.

11. The method for manufacturing a super junction device according to claim 1, wherein: The setting of the thermal process corresponding to the subsequent front surface process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950°C.

12. The method for manufacturing a super junction device according to claim 1, wherein: The second trench has a side vertical structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is constant; Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the second epitaxial layer is constant, and the doping concentration of the first epitaxial layer is set according to the side inclination angle and the depth of the second trench, and the doping concentration of the first epitaxial layer at the corresponding depth gradually increases from the bottom to the top of the second trench, so that the charge balance between each adjacent N-type pillar and the corresponding P-type pillar at each longitudinal position meets the requirement; Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is set according to the side inclination angle and depth of the second trench. From the bottom to the top of the second trench, the doping concentration of the second epitaxial layer at the corresponding depth gradually decreases.

13. The method for manufacturing a super junction device according to claim 2, wherein: After the first chemical mechanical polishing process, the process further includes making the top surface of the gate conductive material layer in the gate trench below the top surface of the first epitaxial layer outside the gate trench. to facilitate the subsequent formation of the second groove.

14. The method for manufacturing a super junction device according to claim 7, wherein: When the source region is formed, a heavily N-type doped cutoff region is formed in a surface region of the first epitaxial layer at an outer edge of the terminal region.

15. The method for manufacturing a super junction device according to claim 1 or 14, wherein: The inner edge of the first selected area is located between the inner edge and the outer edge of the transition zone; The outer edge of the first selected area is located inside the outer edge of the outermost P-type column; Alternatively, the outer edge of the first selected area is flush with the outer edge of the outermost P-type column; Alternatively, the outer edge of the first selected area is located outside the outer edge of the outermost P-type column, and there is a first distance between the outer edge of the first selected area and the outer edge of the terminal area, and the first distance is greater than the maximum distance at which penetration occurs between the outer edge of the first selected area and the outer edge of the terminal area.

16. The method for manufacturing a super junction device according to claim 15, wherein: The first selected area is an open area of ​​the photoresist pattern formed by photolithography of the first P-type impurity; Between the inner edge and the outer edge of the first selected area, the first selected area is completely open; Alternatively, between the inner edge and the outer edge of the first selected region, the subsequent formation region of the P-type column is covered, and the outer region of the P-type column is open.

17. The method for manufacturing a super junction device according to claim 1, wherein: The implanted impurities of the first P-type impurity ion implantation include boron, and the implantation energy is 50keV to 2MeV; The implantation dose of the first P-type impurity ion implantation ensures that after the back-side process is completed, the impurity concentration of the first P-type impurity is no higher than 20% of the N-type impurity concentration of the N-type region outside the P-type column, and the net doping of the N-type region outside the P-type column remains N-type doping.

18. The method for manufacturing a super junction device according to claim 17, wherein: After the ion implantation of the first P-type impurity is completed, the method further includes: The first P-type impurity is annealed and activated, wherein the maximum annealing temperature of the first P-type impurity is greater than 1100° C., and the minimum annealing time is 60 minutes to 180 minutes.

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