Shield gate trench device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a shield gate trench device and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, wherein the substrate comprises an epitaxial layer, a first groove located in the epitaxial layer, and a first oxide layer covering at least part of the surface of the epitaxial layer and the inner wall of the first groove; a polycrystalline silicon structure filling the first groove is formed, and the doping concentration of the polycrystalline silicon structure is gradually reduced in the direction from the groove bottom to the top end of the first groove; the polycrystalline silicon structure is etched back to form a second groove, the polycrystalline silicon inner wall of the second groove covers the first oxide layer on the inner wall of the first groove, and the second groove is used for forming a shield gate structure; a second oxide layer is formed on the inner wall of the polycrystalline silicon of the second groove based on oxidation treatment, and the thickness of the second oxide layer is gradually decreased in the direction from the groove bottom to the top end of the first groove. According to the invention, free regulation and control of the thickness size and thickness change of the field oxide layer can be realized, and the device is suitable for voltage-withstanding devices with various voltage requirements.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a shielded gate trench device and a method for preparing the same. Background Art

[0002] Shielded gate devices refer to semiconductor devices with shielded gates in the body region of the device, such as SGT MOSFE (Shielded Gate Trench Metal-Oxide-Semiconductor Field-Effect Transistor). The shielded gate can introduce a lateral electric field in the body region to assist in the depletion of the drift region, but the lateral electric field in the trench depth direction has a distribution characteristic of low field strength in the middle and high field strength at the bottom (reference Figure 1 ), the device's withstand voltage performance is not high and unstable. In order to solve the above problems, the related technology uses an EPI (epitaxial layer) with a gradient doping concentration, or a field oxide layer of a composite material layer on the inner wall of the groove to utilize its corrosion rate difference to form a stepped field plate, increase the field strength in the middle, and improve the problem of low field strength in the middle. However, the former method has a poor effect on improving the field strength distribution and affects the etching of the shield gate groove, resulting in problems such as uncontrollable groove size. The latter method is only applicable to devices with high voltage and thick field plates, and cannot be adapted to medium and low voltage devices with thinner field oxygen requirements. Summary of the invention

[0003] In order to solve the above technical problems, the present application discloses, on one hand, a method for preparing a shielded gate trench device, which comprises:

[0004] Providing a substrate, the substrate comprising an epitaxial layer, a first trench in the epitaxial layer, and a first oxide layer covering at least a portion of a surface of the epitaxial layer and an inner wall of the first trench;

[0005] forming a polysilicon structure filling the first trench, wherein the doping concentration of the polysilicon structure decreases gradually from the bottom to the top of the first trench;

[0006] Performing back etching on the polysilicon structure to form a second trench, wherein the polysilicon inner wall of the second trench covers the first oxide layer of the inner wall of the first trench, and the second trench is used to form a shielding gate structure;

[0007] Based on the oxidation treatment, a second oxide layer is formed on the inner wall of the polysilicon of the second trench, and the thickness of the second oxide layer decreases gradually from the bottom to the top of the first trench.

[0008] In an exemplary implementation, along the direction from the bottom to the top of the first trench, the doping concentration of the polysilicon structure decreases in steps, and the thickness of the second oxide layer decreases in steps; or,

[0009] Along the direction from the bottom to the top of the first trench, the doping concentration of the polysilicon structure decreases gradually, and the thickness of the second oxide layer decreases gradually.

[0010] In an exemplary embodiment, the polysilicon structure includes multiple polysilicon layers stacked in sequence along the depth direction of the first trench, and the doping concentration of each polysilicon layer changes gradually; the forming of the polysilicon structure filling the first trench includes:

[0011] In the first trench, multiple doped polysilicon deposition processes and polysilicon etching back processes are repeatedly performed to form the multi-layer polysilicon layer, and the gas flow rate of the doping element gas used in each doped polysilicon deposition step is gradually reduced in timing.

[0012] In an example implementation, the doping concentration and thickness of each of the polysilicon layers are determined based on simulation structure design data corresponding to the shielding gate device, and the simulation structure design data is generated based on a preset electric field distribution of the body region in the shielding gate device, and the preset electric field distribution is used to indicate the expected intensity distribution of the lateral electric field in the body region along the depth direction of the first trench.

[0013] In an exemplary implementation, the oxidation treatment of the polysilicon inner wall of the second trench adopts a wet oxygen thermal oxidation process.

[0014] In an exemplary embodiment, providing a substrate includes:

[0015] Providing an initial substrate, the initial substrate comprising a base layer and an epitaxial layer located on one side of the base layer;

[0016] Performing trench etching on the epitaxial layer to form the first trench;

[0017] The first oxide layer conformally covering at least a portion of the surface of the epitaxial layer and the inner wall of the first trench is formed by oxide film deposition.

[0018] In an exemplary implementation, the etching back the polysilicon structure to form the second trench includes:

[0019] Grinding the polysilicon structure until the first oxide layer on the surface of the epitaxial layer is exposed;

[0020] forming a mask layer on the first oxide layer and the polysilicon structure to shield the first oxide layer and the area where the surface of the polysilicon structure is aligned with the polysilicon sidewall, and exposing the area where the surface of the polysilicon structure is aligned with the second trench;

[0021] The substrate having the mask layer is dry-etched and the mask layer is removed to form the second trench.

[0022] In an example embodiment, the process parameters of the etching treatment are determined based on a preset etching inclination angle corresponding to the simulation structure design data and a preset bottom thickness of the inner wall of the second groove, the preset etching inclination angle is negatively correlated with the change gradient of the side wall of the second oxide layer, and the preset etching inclination angle refers to the angle between the side wall of the second groove and the surface of the substrate, which is the complementary angle of the angle between the side wall of the second groove and the bottom wall of the second groove.

[0023] In an exemplary embodiment, after forming a second oxide layer on the inner wall of the polysilicon of the second trench based on oxidation treatment, the preparation method further includes:

[0024] The shielding gate structure is formed in the second trench in conformity with the second oxide layer, and the width of the shielding gate structure increases gradually from the bottom to the top of the second trench.

[0025] On the other hand, the present application further discloses a shielded gate trench device, which is prepared based on the above-mentioned preparation method.

[0026] In an exemplary embodiment, the shielded gate trench device includes:

[0027] A substrate comprising an epitaxial layer and a first trench in the epitaxial layer;

[0028] a first oxide layer, covering at least a portion of the surface of the epitaxial layer and an inner wall of the first trench;

[0029] A field oxide layer is arranged on the inner wall of the first trench, the field oxide layer surrounds the second trench, and the thickness of the field oxide layer decreases gradually from the bottom to the top of the first trench.

[0030] In an exemplary implementation, the thickness of the field oxide layer decreases in steps from the bottom to the top of the first trench; or, the thickness of the field oxide layer decreases gradually from the bottom to the top of the first trench.

[0031] The present application further discloses an integrated circuit in another aspect, wherein the integrated circuit includes the above-mentioned shielded gate trench device.

[0032] The present application further discloses an electronic device in another aspect, which includes the shielded gate trench device mentioned above.

[0033] Based on the above technical solution, this application has the following beneficial effects:

[0034] The present application forms a filled polysilicon structure in a first trench of an epitaxial layer, and the doping concentration of the polysilicon structure decreases gradually from the bottom to the top of the first trench to form a pre-structure for forming field oxygen, and then the polysilicon structure is back-etched to form a second trench to obtain a trench inner wall with a concentration change, and then the polysilicon inner wall is oxidized based on an oxidation process to form a second oxide layer. Due to the change in doping concentration, the thickness of the second oxide layer also changes accordingly, and then it is combined with the first oxide layer to form a field oxide layer with a thickness that gradually changes from the bottom to the top of the trench, so as to achieve a screen in the second trench. The width of the shielded gate structure can be freely adjusted to significantly optimize the problem of low field strength in the middle of the body region, so that the field strength integrated area of ​​the body region tends to be maximized, effectively improving the voltage resistance performance of the device; and, in the preparation process of the second oxide layer, only one thermal oxidation treatment is required, the thermal budget is small and the back-diffusion problem of doped impurities in the substrate is avoided, thereby avoiding the reduction of the voltage resistance performance of the device; in addition, the thickness size and thickness variation of the field oxide layer can be freely adjusted by modulating the doping concentration of the polysilicon structure in the trench, without limiting the field oxygen thickness. The structure has a high degree of freedom in preparation and can be adapted to voltage-resistant devices with various voltage requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram of the structure of a shielded gate trench device provided by the prior art;

[0037] Figure 2 A schematic diagram of a process for preparing a shielded gate trench device exemplified in the present application;

[0038] Figure 3-11 This is a device structure diagram of an exemplary shielded gate trench device during the preparation process of the present application;

[0039] Fig.12 A device structure diagram of a shielded gate trench device during the preparation process of a reference example provided in the present application;

[0040] Fig.13 A lateral field intensity distribution diagram of a device body region of an exemplary shielded gate trench device of the present application;

[0041] The following is a supplementary description of the attached drawings:

[0042] 101-base layer, 102-epitaxial layer, 103-first oxide layer, 104-second oxide layer, 105-first trench, 106-body region, 107-field oxide layer, 201-polysilicon structure, 202-polysilicon layer, 203-polysilicon sidewall, 204-second trench 204, 205-shielding gate structure, 206-gate structure, 207-isolation oxide layer, 301-mask layer. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may include one or more of the features explicitly or implicitly. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here.

[0045] When a numerical range is disclosed herein, the above range is deemed to be continuous and includes the minimum and maximum values ​​of the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe features or characteristics, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all sub-ranges included therein. For example, a specified range from "1 to 10" should be deemed to include any and all sub-ranges between a minimum of 1 and a maximum of 10. Exemplary sub-ranges of ranges 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0046] The term "layer" as used in this application refers to a portion of a material including an area with a certain thickness. A layer may extend over the entire lower or upper structure, or may extend over a local range of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A layer may include multiple layers. For example, the field oxide layer 107 may include a first oxide layer 103 and a second oxide layer 104, etc., and may have the same or different materials.

[0047] It should be understood that the definitions of “consistent”, “vertical”, etc. used in this application refer to basic consistency or basic verticality that satisfies process errors, and do not refer to absolute consistency or absolute verticality in the physical sense.

[0048] It should be understood that the “plane” used in this application, such as “first plane”, “second plane”, etc., refers to the XY plane of the substrate, etc., corresponding to the XY plane of the semiconductor device, the “in-plane direction” refers to the direction parallel to the XY plane, and the “thickness direction”, “trench depth direction” or “longitudinal direction” refers to the Z direction relative to the XY plane.

[0049] The following combination Figure 2-12 The present invention introduces a method for preparing a shielded gate trench device provided in an embodiment of the present invention. Figure 2 It is a flow chart of the method for preparing a shielded gate trench device. This specification provides method operation steps such as the embodiments or flow charts, but more or fewer operation steps may be included based on conventional or non-creative labor. The order of steps listed in the embodiments is only one way of executing the order of many steps and does not represent the only execution order. When the actual preparation method is executed, it can be executed in the order of the methods shown in the embodiments or the drawings or in parallel. The preparation method may include S11-S14:

[0050] S11: providing a substrate.

[0051] Specifically, refer to Figure 4 The substrate includes an epitaxial layer 102 , a first trench 105 located in the epitaxial layer 102 , and a first oxide layer 103 covering at least a portion of a surface of the epitaxial layer 102 and an inner wall of the first trench 105 .

[0052] Specifically, the substrate also includes a base layer 101, and the epitaxial layer 102 is formed on one side of the base layer 101. The base layer 101 is a semiconductor substrate capable of processing semiconductor devices. Exemplarily, the constituent material of the base layer 101 can be at least one of the following: silicon, a material containing silicon (such as III-V compound semiconductor materials of gallium arsenide (GaAs)), silicon on insulator (Silicon On Insulator, SOI), or other types of semiconductor materials that can form the base layer 101.

[0053] Specifically, the epitaxial layer 102 is formed on the substrate layer 101. Optionally, the epitaxial layer 102 can be formed specifically by an epitaxial growth process, and can be an epitaxial layer 102 of the same nature as the substrate layer 101, such as an epitaxial layer 102 that can continue to grow along the lattice direction of the substrate layer 101, or a heterogeneous epitaxial layer 102. The specific process conditions such as the growth temperature can be the same as the existing process, or can be adaptively adjusted. Optionally, the epitaxial layer 102 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other methods. Exemplarily, the material of the epitaxial layer 102 may include silicon, germanium, gallium arsenide, gallium phosphide (GaP), gallium nitride (GaN), etc., or may be other materials that can be epitaxially grown or deposited on the substrate layer 101 and can be processed in the device area.

[0054] Specifically, the first trench 105 is formed in the epitaxial layer 102 by trench etching, and the epitaxial layer 102 may include a plurality of first trenches 105 and are spaced apart based on the device performance requirements. The substrate also includes a first oxide layer 103 conformally covering at least a portion of the surface of the epitaxial layer 102 and the inner wall of the first trench 105. Optionally, the constituent material of the first oxide layer 103 may be silicon oxide, or other materials that can be used as the field oxide layer 107 of the gate.

[0055] In a possible implementation manner, S11 may include S111-S113:

[0056] S111: providing an initial substrate;

[0057] S112: performing trench etching on the epitaxial layer 102 to form a first trench 105;

[0058] S113 : forming a first oxide layer 103 conformally covering at least a portion of the surface of the epitaxial layer 102 and the inner wall of the first trench 105 by oxide film deposition.

[0059] Specifically, refer to Figure 3 The initial substrate includes a base layer 101 and an epitaxial layer 102 located on one side of the base layer 101. The trench etching can be performed by wet etching or dry etching using a mask. Preferably, a dry etching method is used, and more preferably, an isotropic dry etching method is used to form a first trench 105 with high dimensional accuracy and flat inner wall, thereby improving the flatness of the first oxide layer 103.

[0060] Optionally, the deposition process of the oxide film in S113 as the first thin layer of the field oxide layer 107 can be achieved by thermal oxidation, chemical vapor deposition, physical vapor deposition, atomic layer deposition and the like. Taking the thermal oxidation method to form a silicon dioxide oxide layer as an example, polysilicon material is first deposited in the epitaxial layer 102 and the first trench 105, and then thermally oxidized to obtain the first oxide layer 103. The thermal oxidation treatment can be dry oxygen or wet oxygen heat treatment, preferably wet oxygen heat treatment. Taking the deposition method as an example, an oxide material can be deposited on the surface of the epitaxial layer 102 and the first trench 105 to form the first oxide layer 103, such as Figure 4 shown.

[0061] By forming the conformal first oxide layer 103 , it can serve as a subsequent field oxide structure and as an isolation layer during the preparation of the second oxide layer 104 , thereby avoiding ion back diffusion and structural damage of the epitaxial layer during the preparation of the second oxide layer 104 .

[0062] S12 : forming a polysilicon structure 201 filling the first trench 105 , and along a direction L from the bottom to the top of the first trench 105 , the doping concentration of the polysilicon structure 201 decreases gradually.

[0063] Specifically, refer to Figure 5-6 The polysilicon structure 201 is formed on the first oxide layer 103 in the first trench 105 and fills the first trench 105 . The polysilicon structure 201 may be formed by polysilicon deposition.

[0064] Optionally, the ion doping type of the polysilicon structure 201 can be N-type doping or P-type doping, which can be selected based on the functional requirements of the device. Exemplarily, the doping elements may include, but are not limited to, one or more of boron (B), aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As), antimony (Sb) or bismuth (Bi), or other elements that can achieve P-type doping or N-type doping. In some embodiments, P-type doping is used, and the doping elements may be boron (B), aluminum (Al), gallium (Ga) and indium (In), etc. In other embodiments, the base isolation layer 110 is N-type doped, and the doping elements may be phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi), etc.

[0065] In a possible implementation, along the depth direction of the first trench 105, the doping concentration of the polysilicon structure 201 decreases in a stepwise manner or gradually decreases from the bottom to the top of the trench. Preferably, the gradual decrease may be a linear decrease, and the doping concentration refers to the concentration of the doping element in the polysilicon structure 201. Optionally, the polysilicon structure 201 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other methods.

[0066] In some embodiments, the polysilicon structure 201 may be formed by two or more deposition processes and corresponding back-etching processes; the polysilicon structure 201 includes multiple polysilicon layers 202 stacked in sequence along the depth direction of the first trench 105, each deposition process and back-etching process forms a layer of polysilicon layer 202, and the doping concentration of each polysilicon layer 202 changes gradually. Accordingly, S12 may include: repeatedly performing multiple doped polysilicon deposition processes and polysilicon back-etching processes in the first trench 105 to form multiple polysilicon layers 202. Doped polysilicon deposition process refers to in-situ doping by adding doping element gas during the deposition process of polysilicon.

[0067] Specifically, a first structure filling the first trench 105 is formed by doped polysilicon deposition, and the first structure in the first trench 105 is etched back to a desired thickness, thereby obtaining a first polysilicon layer 202; doped polysilicon deposition is performed again to form a second structure filling the remaining portion of the first trench 105, and the second structure is etched back again to a desired thickness, thereby obtaining a second polysilicon layer 202, and so on and so forth, thereby obtaining a polysilicon structure 201. In this way, polysilicon with longitudinal step changes or gradient doping concentrations in the trench can be formed by multiple doped polysilicon depositions and etch-backs.

[0068] Specifically, the gas flow rate of the doping element gas used in each doped polysilicon deposition step is gradually reduced in the timing sequence; the doping element gas can be determined based on the type of doping element required, and is not specifically limited here. For example, the doping element gas used for P element doping can be PH 3Etc. For example, reference Figure 5 and Figure 6 The polysilicon structure 201 includes five polysilicon layers 202, and the doping concentration increases stepwise from the top to the bottom. The increasing gas flow rate from the back to the front will deposit polysilicon with increasing doping concentration, and the thickness of the oxide layer formed after oxidation changes proportionally, and the step width also changes accordingly. The thickness of the polysilicon layer 202 can be controlled by the back-etching depth, and specifically by the etching time.

[0069] In some cases, the gas flow rate of the doping element gas during the deposition of the single-layer polysilicon layer 202 remains stable, and the gas flow rate of the doping element gas used in the subsequent polysilicon layer 202 in the time sequence is lower than that of the previous polysilicon layer 202, so as to achieve a step-by-step decreasing doping concentration. In other cases, in addition to the gas flow rate of the doping element gas used in the subsequent polysilicon layer 202 in the time sequence being lower than that of the previous layer, the gas flow rate of the doping element gas during the deposition of the single-layer polysilicon layer 202 also decreases in time sequence, so as to achieve a gradually decreasing doping concentration.

[0070] In this way, polysilicon with N-1 levels of step concentration can be formed by repeating N times (N is a positive integer greater than or equal to 2) of polysilicon deposition and etching back with variable concentrations. The step width and depth can be adjusted while achieving in-situ doping by adjusting the doping element gas flow and etching back depth during the polysilicon deposition process, so as to facilitate the subsequent regulation of the step thickness and depth of the second oxide layer 104.

[0071] Optionally, the back etching adopts dry etching, preferably isotropic dry etching, so that the grooves formed after the back etching have precise dimensions and flat inner walls, which is conducive to the precise control of the size and shape of the subsequent polysilicon layer 202. The process conditions such as the etching rate of the back etching can be set based on actual needs and are not limited here. The back etching method adopted has etching inertness to the first oxide layer 103.

[0072] In a possible implementation manner, the degree of variation of the doping concentration of the polysilicon structure 201 is determined based on the simulation structure design data, and the simulation structure design data at least includes parameters such as the size of the epitaxial layer 102, the body region 106, the second trench 204, the field oxide layer 107, and the shielding gate structure 205 in the shielding gate trench device. In the case where the polysilicon includes a plurality of polysilicon layers 202, the doping concentration and thickness of each polysilicon layer 202 are determined based on the simulation structure design data corresponding to the shielding gate device. Among them, the simulation structure design data is generated based on the preset electric field distribution of the body region 106 in the shielded gate device. The body region 106 includes a part of the epitaxial layer 102, a field oxide layer 107 located in the epitaxial layer 102, and a shielded gate structure 205. The body region 106 of the device introduces a lateral electric field by setting the shielded gate structure 205 and the field oxide layer 107, which can assist the depletion of the drift region and improve the voltage resistance performance of the device. The lateral electric field of the body region 106 has a certain field strength distribution along the longitudinal direction. The preset electric field distribution is used to indicate the expected intensity distribution of the lateral electric field of the body region along the depth direction of the first groove 105. The field strength in the middle of the body region 106 in the preset electric field distribution tends to be close to the field strength at both ends. The doping concentration and thickness of different polysilicon layers 202 are designed by reversely designing the expected field strength distribution, so that the lateral field strength distribution of the device body region 106 is uniform and the field strength integrated area (voltage resistance performance) tends to be maximized, which significantly improves the existing structure (such as Figure 1 ) has low field strength in the middle part, resulting in insufficient withstand voltage performance.

[0073] S13 : performing etching back processing on the polysilicon structure 201 to form a second trench 204 .

[0074] Specifically, the deep trench is formed by etching back the entire polysilicon structure 201, and the etching back method is preferably anisotropic dry etching. Figure 8 , the polysilicon inner wall of the second trench 204 covers the first oxide layer 103 of the inner wall of the first trench 105, and the second trench 204 is used to form the shielding gate structure 205. It can be understood that the doping concentration change of the polysilicon inner wall is formed based on the doping concentration change of the polysilicon structure 201. The higher the doping concentration, the thicker the oxide layer formed after the polysilicon is oxidized. Correspondingly, the smaller the width of the second trench 204, the smaller the width of the corresponding area of ​​the shielding gate structure 205.

[0075] In a possible implementation manner, S13 may include S131-S133:

[0076] S131: grinding the polysilicon structure 201 until the first oxide layer 103 on the surface of the epitaxial layer 102 is exposed;

[0077] S132: forming a mask layer 301 on the first oxide layer 103 and the polysilicon structure 201 to shield the first oxide layer 103 and the area where the surface of the polysilicon structure 201 is aligned with the polysilicon sidewall 203, and exposing the area where the surface of the polysilicon structure 201 is aligned with the second trench 204;

[0078] S133 : performing dry etching on the substrate having the mask layer 301 and removing the mask layer 301 to form a second trench 204 .

[0079] Specifically, after the polysilicon structure 201 is deposited, some excess polysilicon material covers the first oxide layer 103 on the epitaxial layer 102, such as Figure 5 As shown, the surface of the polysilicon structure 201 is removed by chemical mechanical polishing or the like until the first oxide layer 103 is exposed. After polishing, the surface of the polysilicon structure 201 is preferably flush with the first oxide layer 103 on the epitaxial layer 102. Figure 6 shown.

[0080] Further, refer to Figure 7 The mask layer 301 can be formed by a photolithography patterning process, and can be formed by chemical vapor deposition, such as plasma enhanced chemical vapor deposition (Plasma Enhanced CVD, PECVD), high density plasma chemical vapor deposition (High Density Plasma CVD, HDPCVD), sub-atmospheric pressure chemical vapor deposition (SubAtmospheric CVD, SACVD), low pressure chemical vapor deposition (Low Pressure CVD, LPCVD), atomic layer deposition (Atomic Layer Deposition, ALD), plasma enhanced atomic layer deposition (Plasma Enhanced Atomic Layer Deposition, PEALD), or other types of chemical vapor deposition processes. The material of the mask layer 301 can be silicon nitride, titanium nitride, silicon dioxide, etc. Reference Figure 7 and Figure 8 The mask layer 301 is used to expose the polysilicon region corresponding to the second trench 204 to facilitate deep trench etching, thereby obtaining the second trench 204 .

[0081] In a possible implementation, the sidewall inclination angle and bottom depth of the second groove 204 can be adjusted based on demand to adjust the sidewall gradient change and bottom thickness of the second oxide layer 104. Accordingly, the process parameters of the etching process are determined based on the preset etching inclination angle and the preset bottom thickness of the inner wall of the second groove corresponding to the simulation structure design data. The bottom thickness of the inner wall of the second groove refers to the distance from the bottom surface of the second groove to the surface of the first oxide layer away from the epitaxial layer. The preset etching inclination angle is negatively correlated with the change gradient of the sidewall of the second oxide layer 104. The preset etching inclination angle α refers to the angle between the sidewall of the second groove 204 and the surface of the substrate 101, which is the complementary angle of the angle between the sidewall of the second groove and the bottom wall of the second groove, that is, the smaller the preset etching inclination angle α, the more inclined the sidewall of the second groove 204, the narrower the bottom wall width, and the greater the thickness change gradient of the sidewall of the second oxide layer 104, and vice versa. In a reference example, reference Fig.12 , a uniform doping concentration is used to fill the polysilicon structure 201, and a tilted second trench sidewall is formed by adjusting a preset etching tilt angle α, and the thickness of the second oxide layer 104 decreases gradually along the direction L from the bottom to the top of the second trench 204, and the width of the shielding gate structure 205 increases gradually. Specifically, the process parameters of the etching process may include but are not limited to the ratio of the mixed etching gas, radio frequency parameters, such as the ratio of carbon fluorine gas to oxygen, etc., and the etching process parameters are set by setting the preset etching tilt angle and the preset bottom thickness to achieve a specific sidewall tilt angle, thereby achieving a thickness change of the polysilicon sidewall 203 and free regulation of the bottom thickness.

[0082] S14: Based on the oxidation treatment, a second oxide layer 104 is formed on the inner wall of the polysilicon of the second trench 204 . The thickness of the second oxide layer 104 decreases gradually along the direction L from the bottom to the top of the first trench 105 .

[0083] In this way, by utilizing the positive correlation between the doping concentration of polysilicon and the thickness of the formed oxide film, polysilicon with a longitudinal multi-level step change or gradient doping concentration is formed in the trench, and then secondary trench etching and wet oxygen oxidation are performed to form multi-level step field oxygen with freely adjustable width and depth or to form gradient thickness field oxygen at one time.

[0084] Optionally, the oxidation treatment of the inner wall of the polysilicon may be a dry oxygen thermal oxidation process or a wet oxygen thermal oxidation process. In a preferred embodiment, the oxidation treatment of the inner wall of the polysilicon of the second trench 204 adopts a wet oxygen thermal oxidation process, so that the thickness difference of the oxide layer formed by the polysilicon with different doping concentrations is more significant, thereby improving the distribution modulation effect of the lateral electric field in the body region. After the oxidation of the inner wall of the polysilicon is completed, a field oxide layer 107 with a gradual or step-changing thickness is formed.

[0085] It can be understood that the thickness of the second oxide layer 104 changes accordingly with the doping concentration of the polysilicon sidewall 203. In some embodiments, the doping concentration of the polysilicon structure 201 decreases in steps from the bottom to the top of the first trench 105, and the thickness of the second oxide layer 104 decreases in steps. In other embodiments, the doping concentration of the polysilicon structure 201 decreases gradually from the bottom to the top of the first trench 105, and the thickness of the second oxide layer 104 decreases gradually.

[0086] In summary, the present application forms a filled polysilicon structure 201 in the first trench 105 of the epitaxial layer 102, and the doping concentration of the polysilicon structure 201 decreases gradually from the bottom to the top of the first trench 105 to form a pre-structure for forming field oxygen, and then the polysilicon structure 201 is back-etched to form a second trench 204 to obtain a trench inner wall with a concentration change, and then the polysilicon inner wall is oxidized based on an oxidation process to form a second oxide layer 104. Due to the change in doping concentration, the thickness of the second oxide layer 104 also changes accordingly, and then it is combined with the first oxide layer 103 to form a field oxide layer 107 with a thickness that gradually changes from the bottom to the top of the trench, The width of the shielding gate structure 205 in the second trench 204 can be freely adjusted to significantly optimize the problem of low field strength in the middle of the body region 106, so that the field strength integrated area of ​​the body region 106 tends to be maximized, and the voltage resistance performance of the device is effectively improved; and in the preparation process of the second oxide layer 104, only one thermal oxidation treatment is required, the thermal budget is small and the back diffusion problem of the doped impurities in the substrate is avoided, thereby avoiding the reduction of the voltage resistance performance of the device; in addition, the thickness size and thickness change of the field oxide layer 107 can be freely adjusted by modulating the doping concentration of the polysilicon structure 201 in the trench, without limiting the field oxide thickness, and the freedom of structural preparation is high, which can be adapted to voltage-resistant devices with various voltage requirements.

[0087] Based on some or all of the above implementations, in possible implementations, reference Fig.10 After S14, the preparation method also includes S15: forming a shielding gate structure 205 in the second trench 204 that is conformal to the second oxide layer 104, and the width of the shielding gate structure 205 increases gradually along the direction L from the bottom to the top of the second trench 204 to achieve uniform distribution of field strength and improve the voltage resistance performance.

[0088] In some embodiments, reference Fig. 9 and Fig.10 Along the direction L from the bottom to the top of the second trench 204 , the thickness of the second oxide layer 104 decreases in steps, and the width of the shielding gate structure 205 increases in steps.

[0089] In a possible implementation, the shielding gate structure 205 is filled in a part of the second trench 204. In the preparation process of the shielding gate trench device, in addition to the above process steps, it also includes the formation of the gate, doping of the body region 106, doping of the source, and formation of the contact hole. For example, the formation process of the gate structure 206 can be specifically performed by Fig.11 An isolation oxide layer 207 is further formed on the top of the shielding gate structure 205 shown, and the isolation oxide layer 207 is used to isolate the gate and the shielding gate, and then a gate structure 206 is further formed on the isolation oxide layer 207. A gate dielectric layer can also be covered on the surface of the epitaxial layer 102 and the surface of the first trench 105, and a contact hole can be formed. The gate material and the shielding gate material can be polysilicon or the like. In other embodiments, the gate material and the shielding gate material can also be a metal gate material such as copper, aluminum, tungsten, chromium, titanium, silver, platinum, nickel or gold. The above gate formation process is only an exemplary scheme, and the present application does not limit the method for preparing the gate.

[0090] In the related art, the preparation process of the field oxide layer 107 can also be to first fill the groove with polysilicon material, and then use the mask layer 301 to perform multiple groove etchings of different widths and perform sidewall thermal oxidation after each etching to prepare a stepped field plate. However, the groove size and accuracy of this method are difficult to guarantee, the thermal budget is high, and the doping concentration of the base layer 101 is higher than that of the epitaxial layer 102. Multiple thermal oxidation treatments cause the ions in the base layer 101 to diffuse back to the epitaxial layer 102, resulting in an increase in the doping concentration of the epitaxial layer 102. The reverse diffusion problem is prominent, which seriously affects the device's withstand voltage performance. Alternatively, a composite field oxide structure can also be used to form a stepped field plate through a difference in etching rate, that is, a composite oxide layer prepared from two or more materials is formed on the inner wall of the groove. Differences in the density and material of different material layers result in different etching rates (such as hydrofluoric acid etching rates) of the oxide layer, and the remaining parts of various materials will form stepped field oxides. However, the field oxide layer 107 prepared in this way is too thick and is only applicable to devices with high voltage and thick field plates. When a thinner field oxide layer 107 is required, it is not easy to produce steps during the etching process and the material selection is greatly restricted.

[0091] The solution of the present application forms a polysilicon structure 201 with a gradually changing doping concentration in the first groove 105, and back-etches to form the corresponding polysilicon inner wall, so as to form a field oxygen layer 107 with a gradually changing longitudinal thickness based on the characteristic that the higher the polysilicon doping concentration, the thicker the oxide layer. Only one thermal oxidation can be performed during the process, with a small thermal budget. In addition, the multi-layer field oxygen steps with arbitrary depth and width can be realized by adjusting the doping concentration and etching depth according to the requirements of the simulation design structure. The structure has a high degree of freedom in preparation and is suitable for the preparation of field oxygen of various thicknesses, thereby being able to meet the process development requirements of low, medium and high voltage SGT. Compared with Figure 1In the device structure shown in FIG. 1 , in the shielded gate trench device formed by the technical solution of the present application, the field intensity distribution of the device body region 106 is significantly improved, referring to FIG. Fig.13 , the blue curve in the figure is Figure 1 The field intensity distribution in the body region of the device structure is shown in Figure 2. The green dashed line is based on Fig.11 The field strength distribution in the body region is simulated based on the device structure in the device. It can be seen that the field strength distribution in the body region is uniform and the integrated area of ​​the field strength tends to be maximized, which significantly improves the device's voltage withstand performance defect caused by the low field strength in the middle.

[0092] The following combination Fig.11 The shielded gate trench device of the present application is introduced. It can be understood that the shielded gate trench device in the drawings is only a technical solution of a specific embodiment of the present application, and the shielded gate trench device of the present application may include fewer or more structural features, and is not limited to the device structure described in the drawings.

[0093] The shielded gate trench device includes a substrate, a first oxide layer 103 and a field oxide layer 107. The substrate includes an epitaxial layer 102 and a first trench 105 in the epitaxial layer 102. The first oxide layer 103 covers at least a portion of the surface of the epitaxial layer 102 and the inner wall of the first trench. The field oxide layer 107 is disposed on the inner wall of the first trench, and the field oxide layer 107 surrounds and forms a second trench 204. The thickness of the field oxide layer 107 decreases gradually from the bottom to the top of the first trench 105.

[0094] In a possible implementation manner, the thickness of the field oxide layer 107 decreases in steps from the bottom to the top of the first trench 105 ; or, the thickness of the field oxide layer 107 decreases gradually from the bottom to the top of the first trench 105 .

[0095] In a possible implementation, the shielding gate trench device further includes a shielding gate structure 205 formed in the second trench 204, the shielding gate structure 205 fills a portion of the second trench 204 in a conformal manner, and the width of the shielding gate structure 205 increases gradually from the bottom to the top of the second trench 204.

[0096] In a possible implementation manner, the width of the shielding gate structure 205 increases in steps from the bottom to the top of the second trench 204 ; or, the width of the shielding gate structure 205 increases gradually from the bottom to the top of the second trench 204 .

[0097] In a possible implementation, the shielded gate trench device further includes an isolation oxide layer 207 and a gate structure 206 located in the second trench 204 and stacked above the shielding gate structure 205 , and the isolation oxide layer 207 is located between the shielding gate structure 205 and the gate structure 206 .

[0098] It should be noted that the above-mentioned shielded gate trench device embodiment and the embodiment of the preparation method are based on the same application concept, and the shielded gate trench device can be prepared by the above-mentioned shielded gate trench device preparation method.

[0099] The embodiment of the present application further provides an electronic device, which includes the above-mentioned shielded gate trench device. Specifically, the electronic device includes the shielded gate trench device and an electronic component connected to the above-mentioned shielded gate trench device.

[0100] The electronic device of the embodiment of the present application can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a tablet computer (pad), a laptop computer, a game console, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a handheld game console (PlayStation Portable, PSP), etc., and can also be any intermediate product of an electronic device made of the above-mentioned shielding gate groove device.

[0101] It should be noted that the above-mentioned sequence of the embodiments of the present application is for description only and does not represent the advantages and disadvantages of the embodiments. The above-mentioned specific embodiments of this specification are described. Other embodiments are within the scope of the attached claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0102] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0103] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0104] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for preparing a shielded gate trench device, characterized in that: include: Providing a substrate, the substrate comprising an epitaxial layer, a first trench in the epitaxial layer, and a first oxide layer covering at least a portion of a surface of the epitaxial layer and an inner wall of the first trench; forming a polysilicon structure filling the first trench, wherein the doping concentration of the polysilicon structure decreases gradually from the bottom to the top of the first trench; Performing back etching on the polysilicon structure to form a second trench, wherein the polysilicon inner wall of the second trench covers the first oxide layer of the inner wall of the first trench, and the second trench is used to form a shielding gate structure; Based on the oxidation treatment, a second oxide layer is formed on the inner wall of the polysilicon of the second trench, and the thickness of the second oxide layer decreases gradually from the bottom to the top of the first trench.

2. The preparation method according to claim 1, characterized in that: Along the direction from the bottom to the top of the first trench, the doping concentration of the polysilicon structure decreases in steps, and the thickness of the second oxide layer decreases in steps; or, Along the direction from the bottom to the top of the first trench, the doping concentration of the polysilicon structure decreases gradually, and the thickness of the second oxide layer decreases gradually.

3. The preparation method according to claim 1, characterized in that: The polysilicon structure includes multiple polysilicon layers stacked in sequence along the depth direction of the first trench, and the doping concentration of each polysilicon layer changes gradually; the polysilicon structure formed to fill the first trench includes: In the first trench, multiple doped polysilicon deposition processes and polysilicon etching back processes are repeatedly performed to form the multi-layer polysilicon layer, and the gas flow rate of the doping element gas used in each doped polysilicon deposition step is gradually reduced in timing.

4. The preparation method according to claim 3, characterized in that: The doping concentration and thickness of each polysilicon layer are determined based on the simulation structure design data corresponding to the shielding gate device, and the simulation structure design data is generated based on the preset electric field distribution of the body region in the shielding gate device, and the preset electric field distribution is used to indicate the expected intensity distribution of the lateral electric field in the body region along the depth direction of the first groove.

5. The preparation method according to claim 1, characterized in that: The oxidation treatment of the polysilicon inner wall of the second trench adopts a wet oxygen thermal oxidation process.

6. The preparation method according to any one of claims 1 to 5, characterized in that: The providing of the substrate comprises: Providing an initial substrate, the initial substrate comprising a base layer and an epitaxial layer located on one side of the base layer; Performing trench etching on the epitaxial layer to form the first trench; The first oxide layer conformally covering at least a portion of the surface of the epitaxial layer and the inner wall of the first trench is formed by oxide film deposition.

7. The preparation method according to any one of claims 1 to 5, characterized in that The etching back the polysilicon structure to form a second trench comprises: Grinding the polysilicon structure until the first oxide layer on the surface of the epitaxial layer is exposed; forming a mask layer on the first oxide layer and the polysilicon structure to shield the first oxide layer and the area where the surface of the polysilicon structure is aligned with the polysilicon sidewall, and exposing the area where the surface of the polysilicon structure is aligned with the second trench; The substrate having the mask layer is dry-etched and the mask layer is removed to form the second trench.

8. The preparation method according to claim 7, characterized in that: The process parameters of the etching treatment are determined based on a preset etching inclination angle corresponding to the simulation structure design data and a preset bottom thickness of the inner wall of the second groove. The preset etching inclination angle is negatively correlated with the change gradient of the side wall of the second oxide layer. The preset etching inclination angle refers to the angle between the side wall of the second groove and the surface of the substrate, which is the complementary angle of the angle between the side wall of the second groove and the bottom wall of the second groove.

9. The preparation method according to any one of claims 1 to 5, characterized in that: After forming a second oxide layer on the inner wall of the polysilicon of the second trench based on oxidation treatment, the preparation method further comprises: The shielding gate structure is formed in the second trench in conformity with the second oxide layer, and the width of the shielding gate structure increases gradually from the bottom to the top of the second trench.

10. A shielded gate trench device, characterized in that: The shielded gate trench device is prepared based on the preparation method described in any one of claims 1 to 9.

11. The shielded gate trench device according to claim 10, characterized in that: The shielded gate trench device comprises: A substrate comprising an epitaxial layer and a first trench in the epitaxial layer; a first oxide layer, covering at least a portion of the surface of the epitaxial layer and an inner wall of the first trench; A field oxide layer is arranged on the inner wall of the first trench, the field oxide layer surrounds the second trench, and the thickness of the field oxide layer decreases gradually from the bottom to the top of the first trench.

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