Semiconductor device and method of manufacturing a semiconductor device

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, at least two super junction structure layers arranged on one side of the substrate, wherein the super junction structure layer comprises P-type strip buried regions and N-type strip buried regions which are arranged alternately and have the same extending direction, and the extending directions of the P-type strip buried regions in adjacent super junction structure layers are different; and an N-type buried layer arranged between the adjacent super junction structure layers. The longitudinal super junction structure layer is added, so that the withstand voltage performance of the whole device is improved, and the super high voltage super junction IGBT is realized. The N-type buried layer is arranged, so that the outflow of holes is prevented. The accumulation of holes appears below the N-type buried layer. When the number of holes is greater than that of electrons, the area cannot maintain charge balance, more electron current is injected into the area by the emitter, the concentration of carriers locally increases, and the reduction of on-state voltage drop is realized.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a method for fabricating a semiconductor device. Background Technology

[0002] Semiconductor devices are commonly used in automotive, electromechanical, power, and information communication equipment industries. Superjunction devices, in particular, employ alternating P-type and N-type stripes to increase lateral breakdown voltage, thereby increasing the doping concentration in the drift region and reducing on-resistance and on-voltage drop. Superjunction devices exhibit excellent performance.

[0003] However, due to the structural limitations of existing semiconductor devices, it is impossible to effectively reduce the on-state voltage drop of semiconductor devices while ensuring their withstand voltage capability.

[0004] Therefore, there is an urgent need for a new semiconductor device and a method for fabricating semiconductor devices. Summary of the Invention

[0005] This application provides a semiconductor device and a method for fabricating a semiconductor device. By adding a vertical superjunction structure layer, the overall voltage withstand performance of the device is improved, realizing an ultra-high voltage superjunction IGBT (Insulated Gate Bipolar Transistor). Furthermore, by setting an N-type buried layer, the outflow of holes can be prevented, and holes accumulate below the N-type buried layer. When the number of holes is greater than the number of electrons, the region cannot maintain charge balance, so more electrons are injected into the region from the emitter, and the concentration of charge carriers locally increases, thereby reducing the on-state voltage drop.

[0006] One embodiment of this application provides a semiconductor device, comprising: a substrate; at least two superjunction structure layers disposed on one side of the substrate, the superjunction structure layers comprising alternating P-type strip buried regions and N-type strip buried regions extending in the same direction, and the P-type strip buried regions in adjacent superjunction structure layers extending in different directions; and an N-type buried layer disposed between adjacent superjunction structure layers.

[0007] According to one aspect of this application, the semiconductor device includes a first superjunction structure layer, a first N-type buried layer, and a second superjunction structure layer, wherein the first superjunction structure layer is disposed close to the substrate relative to the second superjunction structure layer; the P-type strip buried region and the N-type strip buried region in the first superjunction structure layer extend along a first direction, and the P-type strip buried region and the N-type strip buried region in the second superjunction structure layer extend along a second direction, wherein the first direction and the second direction intersect.

[0008] According to one aspect of this application, the semiconductor device includes at least three layers of the superjunction structure and at least two layers of the N-type buried layer.

[0009] According to one aspect of this application, the doping concentration of the N-type buried layers is the same in each layer. According to another aspect of this application, the doping concentration of the P-type strip buried regions in different superjunction structure layers is the same, and the doping concentration of the N-type strip buried regions in different superjunction structure layers is the same.

[0010] According to one aspect of this application, the doping concentrations of the P-type and N-type buried regions within the same superjunction structure layer are the same. According to another aspect of this application, the doping concentration of the N-type buried layer is greater than the doping concentration of the N-type buried regions within the superjunction structure layer.

[0011] According to one aspect of this application, the first direction and the second direction are perpendicular.

[0012] Another aspect of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: providing a substrate; forming at least two superjunction structure layers on one side of the substrate, wherein the superjunction structure layers include alternating P-type strip buried regions and N-type strip buried regions extending in the same direction, the P-type strip buried regions in adjacent superjunction structure layers extending in different directions, and an N-type buried layer is formed between adjacent superjunction structure layers.

[0013] According to another aspect of this application, the step of forming at least two superjunction structure layers on one side of the substrate includes: forming a first superjunction structure layer on one side of the substrate, the first superjunction structure layer including the P-type strip buried region and the N-type strip buried region extending along a first direction; forming a first N-type buried layer on the side of the first superjunction structure layer away from the substrate; and forming a second superjunction structure layer on the side of the first N-type buried layer away from the substrate, the P-type strip buried region and the N-type strip buried region of the second superjunction structure layer extending along a second direction, the first direction and the second direction intersecting.

[0014] Compared with existing technologies, the semiconductor device provided in this invention includes a substrate, at least two superjunction structure layers, and an N-type buried layer. Compared with existing technologies, this invention can provide two, three, or even more superjunction structure layers. The height of the P-type and N-type buried regions in the entire device is increased. By adding vertical superjunction structure layers, the voltage withstand performance of the entire device is improved, realizing an ultra-high voltage superjunction IGBT. Compared with the high aspect ratio process used in existing technologies, this application can use multiple N-type buried layers and form a superjunction structure layer every other N-type buried layer, which can effectively save costs. Since this application uses multiple superjunction structure layers, the resulting semiconductor device is longer vertically, and the carrier reduction is more obvious during device operation. The introduction of the N-type buried layer can prevent the outflow of holes, and hole accumulation occurs below the N-type buried layer. When the number of holes is greater than the number of electrons, the region cannot maintain charge balance, so more electrons are injected into the region from the emitter, the carrier concentration increases locally, and the on-state voltage drop is reduced. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0017] Figure 2 yes Figure 1 Sectional view at point A-A';

[0018] Figure 3 yes Figure 1 Sectional view at point B-B';

[0019] Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0020] Figure 5 The graph shows the relationship between turn-off loss and saturation on-voltage for existing conductor devices and the semiconductor device provided by this invention.

[0021] Figure 6 This is a schematic diagram of the hole current distribution inside the active region of a semiconductor device provided in an embodiment of the present invention;

[0022] Figure 7 This is a flowchart of a semiconductor device fabrication method provided in one embodiment of the present invention;

[0023] Figure 8 This is a cross-sectional schematic diagram of the structure obtained in step S110 of the semiconductor device fabrication method provided in an embodiment of the present invention;

[0024] Figure 9 This is a schematic diagram of the structure obtained in the semiconductor device fabrication method provided in one embodiment of the present invention;

[0025] Figure 10 This is a schematic diagram of the structure obtained in the semiconductor device fabrication method provided in another embodiment of the present invention.

[0026] In the attached image:

[0027] 1-Substrate; 2-Superjunction structure layer; 21-First superjunction structure layer; 22-Second superjunction structure layer; 23-Third superjunction structure layer; 3-N-type buried layer; 31-First N-type buried layer; 32-Second N-type buried layer; NN-type strip buried region; PP-type strip buried region; X-First direction; Y-Second direction. Detailed Implementation

[0028] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0030] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0031] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0032] This application provides a semiconductor device and a method for fabricating a semiconductor device, which will be described below in conjunction with the appendix. Figures 1 to 10 Various embodiments of semiconductor devices and semiconductor device fabrication methods are described.

[0033] Please see Figures 1 to 3 The present application provides a semiconductor device comprising: a substrate 1; at least two superjunction structure layers 2 disposed on one side of the substrate 1, the superjunction structure layers 2 comprising alternating P-type strip buried regions P and N-type strip buried regions N with the same extension direction, and the extension direction of the P-type strip buried regions P in adjacent superjunction structure layers 2 being different; and an N-type buried layer 3 disposed between adjacent superjunction structure layers 2.

[0034] The semiconductor device provided in this embodiment of the invention includes a substrate 1, at least two superjunction structure layers 2, and an N-type buried layer 3. Compared with the prior art, this embodiment of the invention can set two, three, or even more superjunction structure layers 2, increasing the height of the P-type strip buried region P and the N-type strip buried region N in the entire device. By increasing the vertical superjunction structure layers 2, the voltage withstand performance of the entire device is improved, realizing an ultra-high voltage superjunction IGBT. Compared with the high aspect ratio process used in the prior art, this application can use multiple N-type buried layers 3 and form a superjunction structure layer 2 every other N-type buried layer 3, which can effectively save costs. Since this embodiment of the invention uses multiple superjunction structure layers 2, the resulting semiconductor device is longer vertically, and the carrier reduction is more obvious during device operation. The introduction of the N-type buried layer 3 can prevent the outflow of holes, and hole accumulation occurs below the N-type buried layer 3. When the number of holes is greater than the number of electrons, the region cannot maintain charge balance, so more electrons are injected into the region from the emitter, the carrier concentration increases locally, and the on-state voltage drop is reduced.

[0035] Optionally, substrate 1 can be a lightly doped N- substrate or an N+ silicon substrate 1, which can be selected according to the actual situation without any special limitation.

[0036] In this embodiment, since the P-type strip buried region P and the N-type strip buried region N in the same superjunction structure layer 2 extend in the same direction, when the extension directions of the P-type strip buried region P in adjacent superjunction structure layers 2 are different, the extension directions of the N-type strip buried region N in adjacent superjunction structure layers 2 are also different. Considering that when the included angle between the P-type strip buried region P and the included angle between the N-type strip buried region N between the upper and lower superjunction structure layers 2 are both 0°, the P-type strip buried region P and the N-type strip buried region N in the upper and lower superjunction structure layers 2 correspond one-to-one. Hole carriers and electron carriers flow in a single column, which easily causes local non-uniformity of the active region current of the device. By extending the strip buried regions of adjacent superjunction structure layers 2 in different directions, the current can be evenly distributed in each superjunction layer, preventing local current concentration. Figure 6 As shown.

[0037] Optionally, the uppermost superjunction structure layer 2 may also include source region, well region, gate oxide layer, planar gate, and other structures.

[0038] Please see Figure 1 In some optional embodiments, the semiconductor device includes a first superjunction structure layer 21, a first N-type buried layer 31, and a second superjunction structure layer 22. The first superjunction structure layer 21 is disposed close to the substrate 1 relative to the second superjunction structure layer 22. The P-type strip buried region P and the N-type strip buried region N in the first superjunction structure layer 21 extend along a first direction X, and the P-type strip buried region P and the N-type strip buried region N in the second superjunction structure layer 22 extend along a second direction Y. The first direction X and the second direction Y intersect.

[0039] In this embodiment, the semiconductor device includes two superjunction structure layers 2: a first superjunction structure layer 21 and a second superjunction structure layer 22. Compared to the single-layer superjunction structure layer 2 in the prior art, the present invention provides two superjunction structure layers 2, which can effectively increase the height of the P-type strip buried region P and the N-type strip buried region N in the entire device, thereby improving the voltage withstand performance of the entire device. Furthermore, a first N-type buried layer 31 is additionally provided between the first superjunction structure layer 21 and the second superjunction structure layer 22. By providing the first N-type buried layer 31, the local concentration of charge carriers can be increased, thereby reducing the on-state voltage drop.

[0040] Optionally, the first direction X and the second direction Y are perpendicular, that is, the angle between the extension directions of the P-type strip buried region P and the N-type strip buried region N in the first superjunction structure layer 21 and the extension directions of the P-type strip buried region P and the N-type strip buried region N in the second superjunction structure layer 22 is 90°, so as to improve the uniformity of current distribution in each superjunction structure layer 2 and prevent local current concentration.

[0041] In some alternative embodiments, the semiconductor device includes at least three superjunction structure layers 2 and at least two N-type buried layers 3.

[0042] According to actual needs, the semiconductor device provided in this embodiment of the invention can be provided with more superjunction structure layers 2 to further increase the height of the P-type strip buried region P and the N-type strip buried region N in the whole device, thereby improving the voltage withstand performance of the whole semiconductor device.

[0043] Please see Figure 4 In some optional embodiments, the semiconductor device further includes a second N-type buried layer 32 and a third superjunction structure layer 23 disposed on the side of the second superjunction structure layer 22 away from the substrate 1; the P-type strip buried region P and the N-type strip buried region N of the third superjunction structure layer 23 extend along a third direction, and the third direction intersects with the second direction Y.

[0044] In this embodiment, the third direction and the second direction Y intersect. The extension directions of the P-type strip buried area P and N-type strip buried area N of the third superjunction structure layer 23 are different from the extension directions of the P-type strip buried area P and N-type strip buried area N of the adjacent second superjunction structure layer 22. The extension directions of the P-type strip buried area P and N-type strip buried area N of the third superjunction structure layer 23 and the extension directions of the P-type strip buried area P and N-type strip buried area N of the first superjunction structure layer 21 can be the same or different, and there is no special limitation.

[0045] Of course, depending on actual needs, an N-type buried layer 3 and a super-structure layer 2 can be further added, without any special limitations.

[0046] In some optional embodiments, the doping concentration of each N-type buried layer 3 is the same. This facilitates fabrication and also ensures the uniformity of conductivity of each N-type buried layer 3, making it easier to control and adjust the electrical parameters of the semiconductor device.

[0047] For example, the doping concentration of the first N-type buried layer 31 is the same as that of the second N-type buried layer 32. It can be understood that the higher the doping concentration, the lower the resistivity and the better the conductivity. The fact that the doping concentration of the first N-type buried layer 31 and the second N-type buried layer 32 are the same ensures the uniformity of the conductivity of the first N-type buried layer 31 and the second N-type buried layer 32, which makes it easier to control and adjust the electrical parameters of the semiconductor device.

[0048] In some optional embodiments, the doping concentration of the P-type strip buried regions P in different superjunction structure layers 2 is the same, and the doping concentration of the N-type strip buried regions N in different superjunction structure layers 2 is the same, so as to facilitate preparation, reduce preparation cost, and ensure the uniformity of conductivity of the P-type strip buried regions P and N in different superjunction structure layers 2.

[0049] Optionally, the P-type buried region P and the N-type buried region N in the same superjunction structure layer 2 have the same doping concentration. Through reasonable doping concentration design, the performance of the depletion layer and the superjunction structure layer 2 can be controlled. Of course, considering that the widths of the P-type buried region P and the N-type buried region N may not be the same depending on the fabrication process, their doping concentrations may also not be the same. The specific concentrations can be set according to the actual situation and are not particularly limited.

[0050] In some alternative embodiments, the doping concentration of the N-type buried layer 3 is greater than the doping concentration of the N-type strip buried region N within the first superjunction structure layer 21.

[0051] It is understandable that when the doping concentration of the N-type buried layer 3 is greater than the doping concentration of the N-type strip-shaped buried region N within the first superjunction structure layer 21, the resistivity of the N-type buried layer 3 is correspondingly lower than that of the N-type strip-shaped buried region N within the first superjunction structure layer 21. Reducing the resistivity of the N-type buried layer 3 can enhance the carrier storage capacity of the device and reduce the on-state voltage drop. In traditional IGBT chips, the hole current decreases from the back collector to the front emitter, and the low carrier concentration at the front emitter limits the reduction of the on-state voltage drop. Since high-voltage SJ IGBTs require multiple superjunction structure layers 2, which are relatively long vertically, the carrier decrease is more pronounced during device operation. The introduction of the N-type buried layer 3 can prevent hole outflow, leading to hole accumulation below the N-type buried layer 3. When the number of holes exceeds the number of electrons, this region cannot maintain charge balance, resulting in more electrons being injected into this region from the emitter, locally increasing the carrier concentration and reducing the on-state voltage drop. Figure 5 As shown, compared with the on-state voltage drop of semiconductor devices in the prior art, the on-state voltage drop of the semiconductor devices in the embodiments of the present invention is significantly reduced.

[0052] Please see Figure 7 This invention also provides a method for fabricating a semiconductor device, comprising the following steps:

[0053] S110: Provides substrate 1, such as Figure 8 As shown;

[0054] S120: At least two superjunction structure layers 2 are formed on one side of the substrate 1. The superjunction structure layer 2 includes alternating P-type strip buried regions P and N-type strip buried regions N with the same extension direction. The extension directions of the P-type strip buried regions P in adjacent superjunction structure layers 2 are different. An N-type buried layer 3 is formed between adjacent superjunction structure layers 2. Figure 1 or Figure 4 As shown.

[0055] The semiconductor device fabrication method provided in this invention forms at least two superjunction structure layers 2 on one side of a substrate 1, and an N-type buried layer 3 is formed between adjacent superjunction structure layers 2. This invention can provide two, three, or even more superjunction structure layers 2, increasing the height of the P-type strip buried region P and the N-type strip buried region N in the entire device. By increasing the vertical superjunction structure layers 2, the overall voltage withstand performance of the device is improved, realizing an ultra-high voltage superjunction IGBT. Compared to the high aspect ratio process used in the prior art, this application can use multiple N-type buried layers 3, with each N-type buried layer 3 spaced apart to form a superjunction structure layer 2, effectively saving costs. Because the embodiments of this application employ a multilayer superjunction structure layer 2, the resulting semiconductor device has a longer vertical dimension, and the carrier reduction is more pronounced during device operation. The introduction of the N-type buried layer 3 can prevent the outflow of holes, and holes accumulate below the N-type buried layer 3. When the number of holes is greater than the number of electrons, the region cannot maintain charge balance, so more electrons are injected into the region from the emitter, and the carrier concentration increases locally, thereby reducing the on-state voltage drop.

[0056] In step S110, substrate 1 can be a lightly doped N- substrate or an N+ silicon substrate, and can be selected according to the actual situation without any special limitation.

[0057] In step S120, a superjunction structure layer 2 can be formed on one side of the substrate 1. Specifically, an epitaxial layer of a first conductivity type can be formed on the semiconductor substrate 1 first. Then, multiple parallel trenches extending along the first direction X are etched in the epitaxial layer. Next, a material of a second conductivity type is deposited to fill the trenches, thereby forming multiple alternating P-type buried regions P and multiple N-type buried regions N extending along the first direction X on the substrate 1, i.e., a superjunction structure layer 2. The doping concentrations of the P-type buried regions and the N-type buried regions N are basically the same, such as... Figure 9 As shown;

[0058] Subsequently, an N-type buried layer 3 can be formed on the side of the superjunction structure layer 2 facing away from the substrate 1 using a deposition process, such as... Figure 10 As shown;

[0059] Then, another superjunction structure layer 2 is formed on the side of the N-type buried layer 3 facing away from the substrate 1. This process can be repeated to form multiple superjunction structure layers 2 as needed. Figure 1 or Figure 4 As shown.

[0060] In some optional embodiments, the step of forming at least two superjunction structure layers 2 on one side of the substrate 1 includes: forming a first superjunction structure layer 21 on one side of the substrate 1, the first superjunction structure layer 21 including a P-type strip buried region P and an N-type strip buried region N extending along a first direction X; forming a first N-type buried layer 31 on the side of the first superjunction structure layer 21 away from the substrate 1; forming a second superjunction structure layer 22 on the side of the first N-type buried layer 31 away from the substrate 1, the P-type strip buried region P and the N-type strip buried region N of the second superjunction structure layer 22 extending along a second direction Y, the first direction X and the second direction Y intersecting.

[0061] In this embodiment, two superjunction structure layers 2 can be formed sequentially to increase the height of the P-type strip buried region P and the N-type strip buried region N in the entire device, thereby improving the voltage withstand performance of the entire device. Furthermore, a first N-type buried layer 31 is additionally provided between the first superjunction structure layer 21 and the second superjunction structure layer 22. By providing the first N-type buried layer 31, the local concentration of charge carriers can be increased, thereby reducing the on-state voltage drop.

[0062] Of course, more superjunction structure layers 2 can be set according to actual needs, such as forming a third superjunction structure layer 23, etc., without any special limitations.

[0063] The above are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

[0064] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

Claims

1. A semiconductor device, characterized in that, include: Substrate; At least two superjunction structure layers are disposed on one side of the substrate. The superjunction structure layers include alternating P-type and N-type strip buried regions with the same extension direction, and the extension directions of the P-type strip buried regions in adjacent superjunction structure layers are different. An N-type buried layer is disposed between adjacent superstructure layers; The semiconductor device includes a first superjunction structure layer, a first N-type buried layer, a second superjunction structure layer, and a second N-type buried layer disposed on the side of the second superjunction structure layer away from the substrate. The first superjunction structure layer is disposed close to the substrate relative to the second superjunction structure layer. The P-type and N-type buried regions in the first superjunction structure layer extend along a first direction, and the P-type and N-type buried regions in the second superjunction structure layer extend along a second direction. The doping concentration of the N-type buried layer is greater than the doping concentration of the N-type buried regions in the superjunction structure layer, and the first and second directions intersect.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes at least three superjunction structure layers and at least two N-type buried layers.

3. The semiconductor device according to claim 2, characterized in that, The doping concentration of the N-type buried layers in each layer is the same.

4. The semiconductor device according to claim 1, characterized in that, The doping concentrations of the P-type buried strip regions in different superjunction structure layers are the same, and the doping concentrations of the N-type buried strip regions in different superjunction structure layers are the same.

5. The semiconductor device according to claim 1, characterized in that, The doping concentrations of the P-type and N-type buried regions in the same superjunction structure layer are the same.

6. The semiconductor device according to claim 1, characterized in that, The first direction and the second direction are perpendicular.

7. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to any one of claims 1 to 6, characterized in that, Includes the following steps: Provide substrate; At least two superjunction structure layers are formed on one side of the substrate. The superjunction structure layers include alternating P-type strip buried regions and N-type strip buried regions with the same extension direction. The extension directions of the P-type strip buried regions in adjacent superjunction structure layers are different, and an N-type buried layer is formed between adjacent superjunction structure layers.

8. The semiconductor device fabrication method according to claim 7, characterized in that, The step of forming at least two superjunction structure layers on one side of the substrate includes: A first superjunction structure layer is formed on one side of the substrate, the first superjunction structure layer including the P-type strip buried region and the N-type strip buried region extending along a first direction; A first N-type buried layer is formed on the side of the first superjunction structure layer away from the substrate; A second superjunction structure layer is formed on the side of the first N-type buried layer away from the substrate. The P-type strip buried region and the N-type strip buried region of the second superjunction structure layer extend along a second direction, and the first direction and the second direction intersect.

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