Cell structure integrated with fin structure, preparation method thereof and SiC power device

Abstract

The application relates to a cell structure integrated with a fin structure and a preparation method thereof and a SiC power device, and the structure comprises the following: a substrate; a super-junction epitaxial layer located on the top surface of the substrate and comprising two kinds of doped column gate structures with different conductive types, the doped column gate structures being located on the side of the super-junction epitaxial layer away from the substrate and extending along a first direction and being arranged at intervals along a second direction; a first fin structure located in the super-junction epitaxial layer between adjacent gate structures and comprising a first base region, a source region and a shielding region; the source region and the shielding region are alternately arranged along the first direction through the top surface of the first fin structure, and the first base region is arranged directly below the source region; a second fin structure located on the side of the gate structure away from the first fin structure; wherein the first fin structure is located directly above the doped column of the first conductive type; the bottom surface of the gate structure is not lower than the shielding region, and the top surface of the gate structure is lower than the top surfaces of the first fin structure and the second fin structure. The device channel mobility can be effectively improved, and the chip area can be reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an integrated fin-type cell structure and its fabrication method, and SiC power devices. Background Technology

[0002] With the continuous development of modern electronic technology, higher requirements are being placed on semiconductor materials, especially in fields such as high voltage, high frequency, high power, high temperature, and radiation resistance. Silicon carbide (SiC) has advantages such as a wide bandgap, high critical breakdown field strength, high saturated electron mobility, high melting point, and high thermal conductivity, which can meet the needs of high-performance power electronic devices.

[0003] With the development of semiconductor technology, small size, high power, and high performance have become the main development trends. The continuous miniaturization of the physical size of devices has driven the continuous reduction of the design pitch of their cells. The size of planar cells has approached the process limit, while trench cell designs have problems such as reliability and high on-resistance at high temperatures. Summary of the Invention

[0004] Based on this, it is necessary to address the technical problems in the existing technology by providing an integrated fin-type cellular structure and its fabrication method, as well as a power device, which can at least further reduce the size of SiC-based chips.

[0005] In a first aspect, this application provides a cellular structure with an integrated fin-type structure for SiC power devices, comprising:

[0006] Substrate;

[0007] The superjunction epitaxial layer, located on the top surface of the substrate, consists of two doped pillars with different conductivity types.

[0008] The gate structure is located on the side of the superjunction epitaxial layer away from the substrate and extends along a first direction and is spaced apart along a second direction;

[0009] The first fin structure is located in the superjunction epitaxial layer between adjacent gate structures, and includes a first base region, a source region, and a shielding region; the source region and the shielding region are alternately arranged along a first direction via the top surface of the first fin structure, and the first base region is disposed directly below the source region;

[0010] The second fin structure is located on the side of the gate structure away from the first fin structure;

[0011] The first fin structure is located directly above the doped pillar of the first conductivity type; the bottom surface of the gate structure is not lower than the shielding area, and the top surface is lower than the top surfaces of the first fin structure and the second fin structure.

[0012] In some embodiments, the gate structure includes a gate oxide layer, a gate conductive layer, and a gate dielectric layer arranged sequentially in a direction away from the substrate, and covering the top surface of the gate oxide layer and the gate conductive layer.

[0013] The top surface of the gate dielectric layer is lower than the top surfaces of the first fin structure and the second fin structure;

[0014] The trench sidewalls of the gate structure are (11-20) crystal planes.

[0015] In some embodiments, the gate oxide layer and the gate conductive layer are prepared simultaneously in the same process step.

[0016] In some embodiments, the second fin structure includes a second base region extending inwardly via the top surface of the second fin structure;

[0017] The first fin structure and the second fin structure were prepared simultaneously in the same process steps;

[0018] The top surface of the first fin structure is flush with the top surface of the second fin structure.

[0019] In some embodiments, a metal silicide layer surrounds the upper surface of the first fin structure and the second fin structure above the gate dielectric layer;

[0020] A barrier layer is located on top of the metal silicide layer and the gate dielectric layer;

[0021] The front metal layer is located on top of the barrier layer.

[0022] Secondly, this application provides a method for preparing a cellular structure with an integrated fin-like structure, comprising:

[0023] A substrate is provided; a superjunction epitaxial layer is disposed on the substrate, comprising two doped pillars of different conductivity types;

[0024] A doped region is formed on the side of the superjunction epitaxial layer away from the substrate; the doped region includes a well region extending inward from the top surface of the superjunction epitaxial layer, and a source region and a shielding region alternately arranged in the well region along a first direction;

[0025] A first fin structure is formed, which extends through the well region in a direction toward the substrate, and a superjunction epitaxial layer is formed between adjacent gate structures, and a second fin structure is located on the side of the gate structure away from the first fin structure.

[0026] The first fin structure is located directly above the doped pillar of the first conductivity type; the bottom surface of the gate structure is not lower than the shielding area, and the top surface is lower than the top surfaces of the first fin structure and the second fin structure.

[0027] In some embodiments, forming a gate structure includes:

[0028] A portion of the superjunction epitaxial layer is removed to form a gate trench; the sidewalls of the gate trench are (11-20) crystal planes.

[0029] After forming an oxide layer and a conductive material layer sequentially in the gate trench, the oxide layer and the conductive material layer are etched back to expose part of the sidewall of the gate trench, forming a first fin structure and a second fin structure.

[0030] A gate dielectric layer is formed within the gate trench, the remaining oxide layer constitutes the gate oxide layer, and the conductive material layer constitutes the gate conductive layer.

[0031] In some embodiments, a sputtering process is performed on the exposed top surfaces of the first fin structure and the second fin structure to form a metal silicide layer covering the upper surfaces of the first fin structure and the second fin structure.

[0032] In some embodiments, a barrier layer covering the gate structure, a metal silicide layer, and a front metal layer are sequentially formed using a deposition process.

[0033] Thirdly, this application provides a SiC power device, including the cell structure as described in any of the above embodiments; or the cell structure prepared by the preparation method described in any of the above embodiments;

[0034] The cellular structures are arranged sequentially along the first direction.

[0035] In the above embodiments, based on the structure of the trench MOSFET, this application introduces Fin at the channel generation location by reducing the distance between the gate structures, and further improves the mobility of the trench channel by utilizing the Fin effect generated between the channels of the (11-20) crystal plane, which helps to reduce the on-resistance.

[0036] The introduction of the superjunction epitaxial layer decouples the epitaxial layer doping concentration from the device breakdown voltage capability. While ensuring high breakdown voltage performance, it can further reduce the chip area and improve the device integration. At the same time, the shielding areas arranged between the gate structures can effectively alleviate the electric field concentration phenomenon at the bottom of the gate trench, structurally avoiding the risk of unexpected breakdown at the bottom of the gate oxide layer, and greatly improving the device's operational reliability and stability.

[0037] In addition, the fabrication method provided in some embodiments is well compatible with existing processes, creating a height difference between the first fin structure and the gate structure, forming a low-resistivity metal silicide on the upper surface of the first fin structure as a source contact region, reducing the contact resistance of the source, taking into account both technological innovation and process compatibility, and reducing the cost of large-scale mass production. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the overall structure of the cellular structure provided in one embodiment;

[0040] Figure 2 This is a schematic flowchart of a method for preparing a cellular structure provided in one embodiment;

[0041] Figure 3 This is a schematic cross-sectional view of the structure obtained after forming a superjunction epitaxial layer in step S20 of the preparation method provided in one embodiment;

[0042] Figure 4 This is a cross-sectional schematic diagram of the structure obtained after forming the well region and the source region in step S402 of the preparation method provided in one embodiment;

[0043] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming the shielding region in step S404 of the preparation method provided in one embodiment;

[0044] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming the gate trench in step S602 of the preparation method provided in one embodiment;

[0045] Figure 7 This is a schematic cross-sectional view of the structure obtained after forming the gate oxide layer and the gate conductive layer in step S604 of the preparation method provided in one embodiment;

[0046] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming the gate dielectric layer in step S606 of the fabrication method provided in one embodiment;

[0047] Figure 9 This is a schematic cross-sectional view of the structure obtained after forming a metal silicide layer in step S608 of the preparation method provided in one embodiment;

[0048] Figure 10 This is a cross-sectional schematic diagram of the structure obtained after forming the barrier layer and the front metal layer in step S610 of the preparation method provided in one embodiment;

[0049] Figure 11 This is a partial structural schematic diagram of a SiC power device provided in one embodiment.

[0050] Explanation of reference numerals in the attached figures:

[0051] 1. Substrate; 10. Superjunction epitaxial layer; 11. P-type doped pillar; 12. N-type doped pillar; 21. Well region; 22. Source region; 23. Shielding region; 31. First fin structure; 32. Second fin structure; 41. Gate oxide layer; 42. Gate conductive layer; 43. Gate dielectric layer; 40. Gate structure; 51. Metal silicide layer; 52. Barrier layer; 53. Front metal layer. Detailed Implementation

[0052] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0054] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0055] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0056] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0057] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0058] In advanced manufacturing processes for Si-based logic circuits, starting from 20nm and below, the technology has transitioned from planar transistors to three-dimensional FinFET structures. FinFET technology can drastically reduce chip size, resulting in significant economic benefits. Due to its unique mechanical properties, SiC has much higher hardness and Young's modulus than Si, making the process of realizing 3D structures more challenging. Currently, there are no commercially available SiC three-dimensional FinFET structure devices.

[0059] Based on this Figure 1This embodiment provides a cellular structure with an integrated fin-type structure for SiC power devices. For ease of understanding, the substrate in this embodiment may include a first surface on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. Intersecting (e.g., perpendicular) first and third directions are defined on the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies). The first, second, and third directions may be mutually perpendicular. In this embodiment, the first direction is defined as the X-axis direction, the second direction as the Y-axis direction, and the third direction as the Z-axis direction. Furthermore, it should be understood that the accompanying drawings are not drawn to the actual scale of the device and are only for illustrative purposes.

[0060] like Figure 1 As shown, the cell structure is the minimum repeating unit structure of a SiC power device, mainly including a substrate 1, a superjunction epitaxial layer 10, a gate structure 40, a first fin structure 31, and a second fin structure 32. In this embodiment, the first conductivity type is defined as N-type, and the second conductivity type is defined as P-type; further, P+ type represents heavily doped P-type, P- type represents lightly doped P-type, and so on for N+ and N-. The following is in conjunction with... Figure 2 The above-mentioned cellular structure will be further described.

[0061] Specifically, the substrate 1 is made of SiC material, and the superjunction epitaxial layer 10 is formed by epitaxial growth process combined with trench-epitaxy backfill process. It includes N-type doped pillars 12 (first conductivity type) and P-type doped pillars 11 (second conductivity type) arranged alternately along the OY direction. During breakdown voltage, the high voltage is withstood by mutual depletion of adjacent N-pillars and P-pillars, so that the breakdown voltage of the device is relatively independent of the doping concentration. This allows for the use of higher doping concentration to reduce on-resistance or thinner epitaxial layer thickness to reduce chip size.

[0062] Please see Figure 1 On the side of the superjunction epitaxial layer 10 away from the substrate 1, a gate structure 40 extending along the OX direction and spaced apart in the OY direction is provided. The gate structure 40 internally comprises, from bottom to top, a gate oxide layer 41, a gate conductive layer 42, and a gate dielectric layer 43. The gate oxide layer 41 and the gate conductive layer 42 are formed by a back-etching process, simultaneously reserving space for the gate dielectric layer 43. The top surface of the gate dielectric layer 43 is precisely controlled to be at the height of the top surfaces of the first fin structure and the second fin structure, thereby reserving an exposed contact area for the formation of metal silicides and ensuring the reliability of subsequent metallization processes.

[0063] The gate trench embedded in the gate structure 40 has a (11-20) crystal plane as its sidewall. Compared with the (0001) silicon plane used in traditional devices, the (11-20) crystal plane has a lower interface state density, which can effectively reduce carrier scattering, build a transport path with better mobility for channel carriers, and further optimize the device conduction performance.

[0064] The first fin structure 31 is located within an N-type doped pillar 12 (first conductivity type) between adjacent gate structures 40. It includes a first base region (P-type) extending downward from its top surface, and N+ type source regions 22 and P+ type shielding regions 23 arranged alternately along the OX direction, wherein the first base region is located directly below the source region 22. The source region 22 serves as the electron emitter, while the shielding region 23 is adjacent to the sidewalls and bottom of the gate structure 40, effectively absorbing and shielding the electric field that tends to concentrate at the corners of the gate trench. This significantly alleviates the electric field stress on the gate oxide layer 41, especially at its bottom, fundamentally enhancing the long-term reliability of the device.

[0065] In addition, a second fin structure 32 is provided on the outside of the gate structure 40, that is, on the side away from the first fin structure 31, which includes its second base region (P-type). The first fin structure 31 and the second fin structure 32 are usually formed in the same process, and their top surfaces are kept flush.

[0066] For example, the thickness of the first fin structure 31 ranges from 25 nm to 200 nm;

[0067] For example, the thickness of the second fin structure 32 ranges from 50 nm to 300 nm.

[0068] In the above embodiments, by reducing the spacing of the gate structure 40 in the OY room, a first fin structure 31 is formed. The crystal channel of its sidewall (11-20) is combined with the three-dimensional effect (Fin effect) of the first fin structure 31 itself, so that the effective mobility of the channel is significantly improved, which can be several times higher than that of the traditional single trench structure. Thus, while the cell size is drastically reduced, a lower specific on-resistance is achieved.

[0069] In some embodiments, such as Figure 1 As shown, in order to form a low-resistance, reliable front electrical connection, a contact and interconnect system is further integrated.

[0070] Specifically, by utilizing the height difference between the gate structure 40 and the first fin structure 31, a metal silicide layer 51 is formed that tightly surrounds and contacts the N+ source region 22 and P+ shield region 23 in the first fin structure 31, as well as the corresponding region of the second fin structure 32. This transforms the original semiconductor surface into an ohmic contact region with extremely low contact resistance, thereby significantly reducing the series resistance of the source and improving the current conduction capability of the device.

[0071] Based on this, a barrier layer and a front metal layer are formed. The barrier layer is used to isolate the upper metal from the lower device structure to prevent subsequent metal atoms from diffusing into the semiconductor. The front metal layer is used to realize electrical connections.

[0072] For example, the material of the barrier layer includes a composite layer of titanium nitride and titanium.

[0073] For example, the material of the front metal layer includes, but is not limited to, aluminum and copper.

[0074] The method for fabricating the above-mentioned semiconductor structure is described below. For some embodiments, please refer to... Figures 2-10 The method includes steps S20-S60.

[0075] Step S20: Provide a substrate 1; the substrate 1 has a superjunction epitaxial layer 10, including two doped pillars with different conductivity types.

[0076] Step S40: A doped region is formed on the side of the superjunction epitaxial layer 10 away from the substrate 1; the doped region includes a well region 21 extending inward from the top surface of the superjunction epitaxial layer 10, and a source region 22 and a shielding region 23 alternately arranged in the well region 21 along the first direction.

[0077] Step S60: Form a gate structure 40 that penetrates the well region 21 in the direction toward the substrate 1, and a first fin structure 31 of the superjunction epitaxial layer 10 between adjacent gate structures 40, and a second fin structure 32 located on the side of the gate structure 40 away from the first fin structure 31; wherein, the first fin structure 31 is located directly above the doped pillar of the first conductivity type; the bottom surface of the gate structure 40 is not lower than the shielding region 23, and the top surface is lower than the top surfaces of the first fin structure 31 and the second fin structure 32.

[0078] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0079] Below, in conjunction with Figures 3 to 10 An exemplary method for describing the cellular structure according to this application is described. Figures 3 to 10A step-by-step cross-sectional view illustrating an exemplary method for fabricating a cellular structure according to this application. Figure 3 (a) shows the overall structure of the cellular structure. Figure 3 Figure (b) shows a simulation diagram of the doping concentration of the cell structure; the remaining steps are deduced sequentially from the corresponding figures. It should also be understood that the figures are not drawn to the actual scale of the device and are for illustrative purposes only.

[0080] Please see Figure 3 In the extension step of step S20, an N-type SiC epitaxial layer is formed on the top surface of substrate 1 using an epitaxial process, and a superjunction deep trench is etched. Based on this, a P-type (doped with aluminum) epitaxial backfill is performed. After backfilling, a CMP process is performed to remove excess P-type epitaxial material from the surface, resulting in the superjunction epitaxial layer 10. For example, the depth-to-width ratio of the superjunction trench is not less than 8, and the depth ranges from 8μm to 12μm, such as 8μm, 9μm, 10μm, 11μm, or 12μm, etc.

[0081] For example, the P-type impurity ions can be any one or more of boron (B) ions, gallium (Mg) ions, or aluminum (Al) ions. In this embodiment, Al ion implantation is used to form the P-type doped column, and the preset dose is 1e. 16 cm -2 -1e 17 cm -2 The remaining epitaxial layers in the middle form an N-type doped pillar 12.

[0082] Please see Figures 4-5 Step S40 further includes steps S402-S406.

[0083] Please see Figure 4 Step S402: After directly implanting the P-type well region 21 on the basis of the superjunction epitaxial layer 10, mask deposition, photolithography, development and mask etching are performed, and the implantation of the N+ type source region 22 continues.

[0084] For example, the dopant element of the P-type well region 21 is Al, with a dose range of 1e12cm. -2 -1e14cm -2 Its depth is 0.5μm-1μm, for example 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm or 1μm. In this embodiment, the depth of the P-type well region 21 is 0.7μm.

[0085] For example, N-type impurity ions can be any one or more of phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions. In this embodiment, N-type ion implantation is used to form the source region 22, with a dose range of 3e12cm. -2 -7e14cm -2 The depth of source region 22 ranges from 0.1μm to 2μm, for example, 0.1μm, 0.15μm or 0.2μm, etc. In this embodiment, the depth of source region 22 is 0.2μm.

[0086] Please see Figure 5 Step S404: Continue with mask deposition, photolithography, development, and mask etching for implantation in shielded region 23. Then, perform P-type ion implantation on the hard mask layer.

[0087] For example, in this embodiment, the doping element is aluminum (Al), and the dosage range is 1e12cm. -2 -1e14cm -2 The depth of the shielding area 23 ranges from 0.8μm to 1.2μm, for example, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0 or 1.2μm, and is used to protect the bottom of the grid trench and also serve as an ohmic contact. In this embodiment, the depth is 1μm.

[0088] Please see Figures 6-10 Step S60 further includes:

[0089] Please see Figure 6 Step S602: Grow a silicon dioxide hard mask (TEOS Hard Mask) to define the gate trench etching range, and then perform the gate trench rounding process and sacrificial oxidation process in sequence.

[0090] For example, the depth of the gate trench is not greater than the depth of the shielding area 23. In this embodiment, the depth of the gate trench is about 1 μm.

[0091] Specifically, while the gate trenches are being formed, the well region 21 located between the gate trenches constitutes the first base region, and the well region 21 on the other side constitutes the second base region. The first base region, the source region 22, and the shielding region 23 constitute the first fin structure 31 described above; the second base region constitutes the second fin structure 32.

[0092] Please see Figure 7Step S604: After the sacrificial oxidation process, an oxide layer is grown using a furnace tube process; then, 6000Å-10000Å doped polysilicon is grown as a conductive material layer using an epitaxial process. A dry etch-back process is then used to create the gate pattern and expose part of the top surface of the SiC superjunction epitaxial layer 10. At this point, the remaining oxide layer serves as the gate oxide layer 41, and the remaining conductive material layer serves as the gate conductive layer 42. The top surface of the gate oxide layer 41 is not lower than the bottom surface of the source region 22.

[0093] For example, the thickness of the gate oxide layer 41 is 500 Å, and the thickness of the gate conductive layer 42 is 0.5 μm.

[0094] like Figure 7 As shown, during the growth of doped polysilicon, there is a height difference between the gate structure 40 and the first fin structure 31 and the second fin structure 32, forming a morphological feature that is high on both sides and low in the middle. The gas etching inherits this morphology, and the gate oxide layer 41 is partially etched to have rounded edges.

[0095] In some embodiments, power devices including the above-described cellular structure require an active region (not shown) to be defined by a field oxidation process after the sacrificial oxidation process. Since this is not the focus of this application, it will not be described in detail here.

[0096] Please see Figure 8 Step S606: Deposit dielectric material and perform back etching so that the top surface of the gate dielectric layer 43 is lower than the top surfaces of the first fin structure 31 and the second fin structure 32, but higher than the bottom surface of the well region 21.

[0097] Please see Figure 9 Step S608: A 3000 Å TEOS and a 7000 Å borosilicate glass (BPSG) mask are formed using Chemical Vapor Deposition (CVD). The contact pattern of the source region 22 is etched using photolithography, exposure and development, and dry etching. The photoresist is removed using dry and wet etching. After photoresist removal, a nickel (Ni) magnetron sputtering process is performed, followed by two consecutive annealing processes to form a low-resistivity metal silicide layer 51, used to reduce the contact resistance between the source electrode and the implanted material. The gate pattern is then etched using photolithography, exposure and development, and dry etching. The photoresist is subsequently removed again using dry and wet etching.

[0098] Please see Figure 10Step S610: A composite layer of titanium nitride and titanium, serving as the barrier layer 52, is deposited using physical vapor deposition (PVD). Subsequently, a metal material layer is formed on top of this layer. Photolithography is then used for exposure and development, followed by dry etching to remove excess metal from the non-active region 22, etching out the source and gate electrode patterns to form the front metal layer 53. Finally, dry and wet etching are used to remove the photoresist.

[0099] In some embodiments, after the above steps, the substrate is further subjected to a back-side process, including back-side thinning, Ni Sputter process and laser annealing process to form an ohmic contact, and finally back-side metal evaporation to form a drain electrode (not shown).

[0100] For example, the material of the back metal layer includes, but is not limited to, titanium (Ti), nickel (Ni), or silver (Ag), etc.

[0101] This application also provides a power device, including the cell structure as described in the above embodiments, wherein in the active region, such as Figure 11 As shown, it includes multiple cell structures arranged sequentially along the OY direction. Of course, power devices can also include other electrical structures, as long as the device layout is reasonable, which will not be described in detail here.

[0102] In the above embodiments, the unexpected technical effect of this application is that the combination of the trench channel with the Fin structure and the superjunction epitaxy further improves the mobility of the trench channel, increasing the mobility of the trench channel from 120cm. 2 / V·s-200cm² / V·s increased to 900cm 2 / V·s-1000cm 2 The concentration increases exponentially with respect to V·s. The superjunction structure further enhances epitaxial concentration and reduces epitaxial thickness, thereby significantly reducing chip area.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A cellular structure with an integrated fin-like structure, characterized in that, Used in SiC power devices, including: Substrate; A superjunction epitaxial layer, located on the top surface of the substrate, includes two doped pillars of different conductivity types arranged alternately along a first direction; A gate structure is located on the side of the superjunction epitaxial layer away from the substrate and extends along a first direction and is spaced apart along a second direction; the gate structure includes a gate oxide layer, a gate conductive layer and a gate dielectric layer arranged sequentially along the direction away from the substrate, and a gate oxide layer and the top surface of the gate conductive layer are covered. The first fin structure is located within the superjunction epitaxial layer between adjacent gate structures, and includes a first base region, a source region, and a shielding region; the source region and the shielding region are alternately arranged along the first direction via the top surface of the first fin structure, and the first base region is disposed directly below the source region; the thickness of the first fin structure ranges from 25nm to 200nm. The second fin structure is located on the side of the gate structure away from the first fin structure, and is composed of a second base region extending inward through the top surface of the second fin structure; the thickness of the second fin structure ranges from 50nm to 300nm. Wherein, the first fin structure is located directly above the doped pillar of the first conductivity type; the bottom surface of the gate structure is not lower than the shielding region, and the top surface is lower than the top surfaces of the first fin structure and the second fin structure; the top surface of the gate oxide layer is not lower than the bottom surface of the source region, and the edge is rounded after partial etching; the top surface of the gate conductive layer is lower than the top surface of the gate oxide layer.

2. The cellular structure according to claim 1, characterized in that, The top surface of the gate dielectric layer is lower than the top surfaces of the first fin structure and the second fin structure; The trench sidewalls of the gate structure are (11-20) crystal planes.

3. The cellular structure according to claim 2, characterized in that, The first fin structure and the second fin structure are prepared simultaneously in the same process steps; The top surface of the first fin structure is flush with the top surface of the second fin structure.

4. The cellular structure according to any one of claims 2-3, characterized in that, A metal silicide layer surrounds the first fin structure and the second fin structure above the upper surface of the gate dielectric layer; A barrier layer is located on the top surface of the metal silicide layer and the gate dielectric layer; A front metal layer is located on the top surface of the barrier layer.

5. A method for preparing a cellular structure with an integrated fin-like structure, characterized in that, include: A substrate is provided; the substrate is provided with a superjunction epitaxial layer comprising two doped pillars of different conductivity types arranged alternately along a first direction; A doped region is formed on the side of the superjunction epitaxial layer away from the substrate; the doped region includes a well region extending inward from the top surface of the superjunction epitaxial layer, and a source region and a shielding region extending in the well region along a first direction; the gate structure includes a gate oxide layer and a gate conductive layer arranged sequentially in a direction away from the substrate, and a gate dielectric layer covering the top surface of the gate oxide layer and the gate conductive layer. A first fin structure is formed, which extends through the well region along a direction toward the substrate, and a superjunction epitaxial layer is formed between adjacent gate structures. A second fin structure is located on the side of the gate structure away from the first fin structure. The thickness of the first fin structure ranges from 25nm to 200nm. The thickness of the second fin structure ranges from 50nm to 300nm. The second fin structure is composed of a second base region extending inward through the top surface of the second fin structure. The first fin structure is located directly above the doped pillar of the first conductivity type and includes a first base region, a source region, and a shielding region. The source region and the shielding region are alternately arranged along the first direction via the top surface of the first fin structure, and the first base region is located directly below the source region. The bottom surface of the gate structure is not lower than the shielding region, and the top surface is lower than the top surfaces of the first fin structure and the second fin structure. The top surface of the gate oxide layer is not lower than the bottom surface of the source region, and its edges are partially etched to be rounded. The top surface of the gate conductive layer is lower than the top surface of the gate oxide layer.

6. The preparation method according to claim 5, characterized in that, Forming the gate structure includes: A portion of the superjunction epitaxial layer is removed to form a gate trench; the sidewalls of the gate trench are (11-20) crystal planes. After forming an oxide layer and a conductive material layer sequentially in the gate trench, the oxide layer and the conductive material layer are etched back to expose part of the sidewall of the gate trench, forming the first fin structure and the second fin structure. A gate dielectric layer is formed within the gate trench, the remaining oxide layer constitutes the gate oxide layer, and the conductive material layer constitutes the gate conductive layer.

7. The preparation method according to claim 6, characterized in that, A sputtering process is performed on the exposed top surfaces of the first fin structure and the second fin structure to form a metal silicide layer covering the upper surfaces of the first fin structure and the second fin structure.

8. The preparation method according to claim 7, characterized in that, A barrier layer and a front metal layer covering the gate structure, the metal silicide layer, and the front metal layer are sequentially formed using a deposition process.

9. A SiC power device, characterized in that, Includes the cellular structure as described in any one of claims 1-4; or the cellular structure prepared by any one of claims 5-8; The cellular structures are arranged sequentially along the first direction.

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