A method for fabricating a SiC trench terminal structure

Abstract

This invention discloses a method for fabricating a SiC trench termination structure, belonging to the field of semiconductor manufacturing technology. The method includes the following steps: forming multiple P+ regions in an N-epitaxial layer to divide the N-epitaxial layer into a termination region and multiple cell regions; forming a first Pwell region in the termination region; forming a JFET implantation region, a second Pwell region, and an N+ region in each cell region; defining a gradient trench termination ring in the termination region and a gate trench pattern on the cell region using photoresist; forming multiple termination trenches with gradually increasing depth towards the cell region in the termination region using the above pattern, and forming a gate trench in the cell region; forming sidewalls on the termination trenches and gate trenches, and forming a P-type protection zone at the bottom. Then, the sidewalls and hard mask layer are removed, and the gate, source, and drain are further formed. This method does not increase the number of masks required for the process, is compatible with a single trench + deep pplus scheme, and solves the problem of electric field concentration in the deep pplus transition region during reverse breakdown voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a SiC trench termination structure. Background Technology

[0002] In SiC trench MOSFET design, the design of the termination is crucial. Although research on planar MOS termination structures is relatively mature, in trench MOSFETs, due to the need to strengthen the protection of the gate oxide at the bottom of the gate trench, deep source trenches combined with conventional pplus injection or deep pplus injection are often used for gate oxide protection and to improve cell robustness. However, when deep pplus injection is used to form the transition region, using high-energy pplus injection to form the field limiting ring termination places extremely high demands on the injection mask. High-energy injection means a thicker and more rigid mask is required, which means the mask's CD cannot meet the dimensions required for conventional field limiting rings, resulting in a loss of field limiting ring performance. To reduce reliance on high-energy injection masks and improve termination performance, the industry typically uses JTE termination. However, JTE termination also has significant disadvantages: a small process window, high injection sensitivity, and significant influence from interface charge. To improve the JTE injection window, dual-region JTE can be introduced, but this increases mask costs and adds more process steps. Summary of the Invention

[0003] This invention aims to provide a method for fabricating SiC trench terminal structures to address the shortcomings of existing technologies. The technical problem to be solved by this invention is achieved through the following technical solutions:

[0004] An N+ substrate is provided, and an N- epitaxial layer is formed on the N+ substrate;

[0005] In the N-epitaxial layer, multiple P+ regions are formed by high-energy ion implantation, dividing the N-epitaxial layer into a terminal region and multiple cell regions. A first Pwell region is formed in the terminal region, and a JFET implantation region, a second Pwell region, and an N+ region are formed in the cell regions, respectively.

[0006] A hard mask layer is formed on the N-epitaxial layer, and a gradient trench termination ring is defined in the termination region and a gate trench pattern is defined in the cell region using photoresist; the gradient trench termination ring has multiple termination region trench patterns with the trench width gradually increasing towards the cell region.

[0007] The hard mask layer is further etched using the aforementioned terminal trench pattern and gate trench pattern, and multiple terminal trenches with gradually increasing depth in the direction of the cell region are formed in the terminal region, and gate trenches are formed in the cell region.

[0008] Forming side walls on the terminal area trench and the gate trench, and forming P-type protection area by ion implantation at the bottom of the terminal area trench and the gate trench with the side walls as a mask;

[0009] After the P-type protection area implantation is completed, the side walls in the terminal area trench and the cell area gate trench and the hard mask layer are removed;

[0010] Finally, the terminal area trench and the gate trench are filled with polysilicon to form a gate, and an interlayer dielectric isolation layer and a source metal are formed thereon, and a drain is formed on the back of the N+ substrate.

[0011] Further, the N- epitaxial layer is 4H-SiC, the thickness is 10 μm, and the concentration is 1×10 16 cm -3 The N+ substrate is an N-type 4H-SiC substrate, and the thickness is 180 μm.

[0012] Further, the P+ area is formed by Al ion implantation, the maximum implantation energy reaches 1.8 MeV, and the junction depth reaches 2 μm.

[0013] Further, the first Pwell area and the second Pwell area are formed by Al ion implantation, the implantation energy is 500 KeV, and the junction depth is 0.7 μm.

[0014] Further, the JFET implantation area is formed by N ion implantation, the implantation energy is 600 KeV, and the implantation junction depth is 0.9 μm; and the N+ area is formed by N ion implantation, the implantation energy is 70 KeV, and the junction depth is 0.3 μm.

[0015] Further, the depth-width ratio of the terminal area trench is 1:1.

[0016] Further, the P-type protection area is formed by Al ion implantation, the Al ion dose is 1×10 13 cm -3 , and the implantation energy is 50-70 keV.

[0017] Compared with the related art, the technical scheme of the present application at least has the following advantages:

[0018] The SiC trench terminal structure manufacturing method provided by the present application does not increase the mask required by the process, is compatible with the single trench+deep pplus scheme, does not increase the additional implantation process, is compatible with the conventional scheme, solves the problem of electric field concentration of the deep pplus transition area in reverse voltage resistance, and effectively shortens the terminal length. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1This is a schematic diagram of the formation of terminal regions and cell regions in the N-epitaxial layer;

[0020] Figure 2 This is a schematic diagram of the gradient trench termination ring and gate trench pattern defined by a hard mask layer;

[0021] Figure 3 This is a schematic diagram of the gradient trench terminal ring and gate trench formed by etching.

[0022] Figure 4 This is a schematic diagram of sidewalls formed in a trench;

[0023] Figure 5 This is a schematic diagram showing the formation of the P-protected zone at the bottom of the trench.

[0024] Figure 6 This is a schematic diagram showing the removal of the sidewalls and hard mask layer;

[0025] Figure 7 This is a schematic diagram of the formation of gate oxide, polysilicon gate, interlayer dielectric isolation layer and source / drain metal electrodes. Detailed Implementation

[0026] To make the technical problems, solutions, and beneficial effects of this invention clearer, the invention will be further described in detail with reference to the embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0027] The following is in conjunction with the appendix Figures 1-7 The method for fabricating the SiC trench termination structure of this application is described in detail. An N+ substrate 1 is provided, and an N- epitaxial layer 2 is formed on the N+ substrate 1; the N- epitaxial layer 2 is 4H-SiC with a thickness of 10 μm and a concentration of 1 × 10⁻⁶. 16 cm -3 N+ substrate 1 is an N-type 4H-SiC substrate with a thickness of 180μm.

[0028] In the N-epitaxial layer 2, multiple P+ regions 4 are formed through high-energy ion implantation, dividing the N-epitaxial layer 2 into a terminal region and multiple cell regions. A first Pwell region 3 is formed in the terminal region, and a JFET implantation region 5, a second Pwell region 6, and an N+ region 7 are formed in the cell regions. The P+ region 4 is formed using Al ion implantation, with a maximum implantation energy of 1.8 MeV and a junction depth of 2 μm. The JFET implantation region 5 is formed using N ion implantation, with an implantation energy of 600 keV and an implantation junction depth of 0.9 μm. The first Pwell region 3 and the second Pwell region 6 are formed using Al ion implantation, with an implantation energy of 500 keV and a junction depth of 0.7 μm. The N+ region 7 is formed using N ion implantation, with an implantation energy of approximately 70 keV and a junction depth of approximately 0.3 μm.

[0029] A hard mask layer 9 is formed on the N-epitaxial layer 2, and a gradient trench termination ring is defined in the termination region and a gate trench pattern is defined in the cell region using photoresist 10; the gradient trench termination ring has multiple termination region trench patterns with the trench width gradually increasing towards the cell region. The hard mask layer 9 is made of SiO2.

[0030] The hard mask layer 9 is further etched using the aforementioned terminal trench pattern and gate trench pattern, forming multiple terminal trenches with gradually increasing depth towards the cell region, and gate trenches are formed within the cell region; the aspect ratio of the aforementioned terminal trenches is 1:1. For example, if the active region gate trench depth is 0.8 μm, this etching process requires opening a 0.8 μm width in the hard mask. The terminal region design involves creating a 2 μm window in the hard mask, corresponding to a 2 μm trench depth. From right to left, the window width decreases sequentially in 0.1 μm increments, with the last window width being 0.8 μm. There are a total of 13 windows, corresponding to 13 trenches with progressively decreasing depths, and the spacing between each trench is 2 μm.

[0031] Sidewalls 11 are formed on the terminal trench and the gate trench. For conventional single-trench designs, gate trench bottom protection is required, which is achieved by injecting P-type gate oxide to protect the gate oxide at the bottom of the trench. In this case, the P-protected zone injection requires prior trench sidewall protection to prevent the P-protected zone injection from affecting the Pwell concentration. The trench sidewall protection involves depositing a sidewall after etching the hard mask used for the trench, resulting in a sidewall approximately 0.2 μm wide.

[0032] Using the sidewall 11 as a mask, P-type protection zones 12 are formed at the bottom of the terminal trench and the gate trench by ion implantation; the P-protection zone 12 is implanted with Al ions at a dose of 1×10⁻⁶. 13 cm -3 The injected energy is 50~70keV. The P-protection zones formed above have different functions. The P-protection zone in the cell region mainly reduces the electric field strength of the bottom gate oxide and improves reliability; while the P-protection zone located in the terminal region becomes part of the terminal voltage division design.

[0033] After the P-type protected area 12 is implanted, the sidewalls 11 and hard mask layer 9 in the terminal trench and the cell gate trench are removed; finally, gate oxide 16 and polysilicon filling are formed in the terminal trench and the gate trench to form gate 15, and interlayer dielectric isolation layer 14 and source metal 13 are formed on it, and drain 8 is formed on the back side of the N+ substrate.

[0034] This invention optimizes the existing single-trench SiC MOSFET termination design with deepened P+ implantation, providing a termination structure that reduces the electric field strength at the termination edge of the deep P+ transition region, reduces the termination length, and eliminates the need for additional masks and process steps. This structure employs a gradient trench depth design, with deeper trenches near the transition region and progressively shallower trenches further away. Since the conventional method for protecting the gate oxide at the bottom of the trench is through P-protected zone implantation, a P-protected zone is also implanted at the bottom of the trench in the termination region after the gradient trench is formed. This P-protected zone implantation can generate depletion region expansion under reverse bias, thus mitigating voltage drop.

[0035] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0036] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0037] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0038] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0039] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0040] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a SiC trench termination structure, comprising: The method comprises the following steps: providing an N+ substrate (1), forming an N- epitaxial layer (2) on the N+ substrate (1); forming a plurality of P+ regions (4) in the N- epitaxial layer (2) by high-energy ion implantation to divide the N- epitaxial layer (2) into a terminal region and a plurality of cell regions, forming a first Pwell region (3) in the terminal region, and respectively forming a JFET implantation region (5), a second Pwell region (6) and an N+ region (7) in the cell regions; forming a hard mask layer (9) on the N- epitaxial layer (2), and defining a gradual groove terminal ring in the terminal region and a gate groove pattern on the cell regions by photoresist (10); the gradual groove terminal ring has a plurality of terminal region groove patterns with gradually increasing groove width in the direction of the cell region; further etching the hard mask layer (9) by the above terminal region groove pattern and gate groove pattern, forming a plurality of terminal region grooves with gradually increasing depth in the direction of the cell region in the terminal region, and forming a gate groove in the cell region; forming a side wall (11) on the terminal region groove and the gate groove, and forming a P-type protection region (12) in the terminal region groove and the gate groove by ion implantation with the side wall (11) as a mask; after completing the P-type protection region (12) implantation, removing the side wall (11) and the hard mask layer (9) in the terminal region groove and the gate groove of the cell region; finally forming a gate oxide (16) in the terminal region groove and the gate groove, and filling polysilicon to form a gate (15), and forming an interlayer dielectric isolation layer (14) and a source metal (13) thereon, and forming a drain (8) on the back of the N+ substrate (1).

2. The method of fabricating a SiC trench termination structure of claim 1, wherein, The N-epitaxial layer (2) is 4H-SiC with a thickness of 10 μm and a concentration of 1 × 10⁻⁶. 16 cm -3 The N+ substrate (1) is an N-type 4H-SiC substrate with a thickness of 180 μm.

3. The method of claim 1, wherein the SiC trench termination structure is formed by the steps of: The P+ region (4) is formed by Al ion implantation, the maximum implantation energy reaches 1.8 MeV, and the junction depth reaches 2 μm. ​ 4. The method of fabricating a SiC trench termination structure of claim 1, wherein, The first Pwell region (3) and the second Pwell region (6) are formed by Al ion implantation, the implantation energy is 500 KeV, and the junction depth is 0.7 μm.

5. The method of claim 1, wherein the SiC trench termination structure is formed by the steps of: The JFET implantation region (5) is formed by N ion implantation, the implantation energy is 600 KeV, and the implantation junction depth is 0.9 μm; the N+ region (7) is formed by N ion implantation, the implantation energy is 70 KeV, and the junction depth is 0.3 μm. ​ 6. The method of fabricating a SiC trench termination structure of claim 1, wherein, The depth-to-width ratio of the terminal region groove is 1:

1.

7. The method of fabricating a SiC trench termination structure of claim 1, wherein, The P-type guard band (12) is implanted with Al ions, the Al ion dose is 1×10 13 cm -3 , and the implantation energy is 50-70 keV.

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