Shield gate MOSFET device and preparation method thereof

Abstract

The invention discloses a shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof. The device comprises a substrate; a semiconductor body; the semiconductor body comprises a drift region, a body region and a first active region; in the first direction, the drift region comprises at least three multi-sub concentration peak regions; in the first direction, the peak values of the corresponding multi-sub-concentration in the at least three multi-sub-concentration peak regions are decreased progressively; first grooves are formed in the two sides of the semiconductor body in the second direction; the gate structure is located in the first groove; the source electrode structure is positioned on one side, far away from the substrate, of the semiconductor body; and the drain electrode is positioned on one side, far away from the semiconductor body, of the substrate. According to the invention, the transverse depletion of the shield gate to the drift region is more uniform, the electric field intensity of the concave region in the middle of the longitudinal electric field of the shield gate MOSFET device is improved, and the withstand voltage of the device is also improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a shielded gate MOSFET device and a preparation method thereof. Background Art

[0002] In order to improve the performance of power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices, researchers have proposed a new structure of shielded gate MOSFET devices. Shielded gate MOSFET devices can use their shielded gate electrode as a "field plate in the body" to reduce the electric field in the drift region, so shielded gate MOSFET devices usually have lower on-resistance and higher breakdown voltage. In addition, the shielded gate electrode connected to the source potential can also reduce the gate-drain capacitance of the device and increase the switching speed of the device.

[0003] During reverse withstand voltage, the difference between the potential of the shielded gate electrode connected to the source potential and the potential of the drift region near the substrate side of the conventional shielded gate MOSFET device is large, resulting in excessive lateral depletion of the majority carriers of the drift region near the substrate side by the shielded gate electrode, generating an electric field peak. In the direction from the substrate to the drift region, the potential of the drift region gradually approaches the potential of the shielded gate electrode, and the difference between the potential of the side of the drift region near the body region and the potential of the shielded gate electrode is close to zero, and the shielded gate electrode has almost no lateral depletion of the majority carriers of the side of the drift region near the body region. However, on the side of the drift region near the body region, an electric field peak will also be generated due to the longitudinal depletion between the body region and the drift region, so the longitudinal electric field for conventional shielded gate MOSFET devices is "U" shaped.

[0004] The integral calculation of the longitudinal electric field is the withstand voltage of the device. Due to the uneven lateral depletion of the drift region by the shielded gate electrode, the longitudinal electric field of the shielded gate MOSFET device is "U" shaped. The concave area in the middle of the "U" shaped electric field causes the device to have a lower withstand voltage. Summary of the invention

[0005] The present invention provides a shielded gate MOSFET device and a preparation method thereof, so as to make the shielded gate uniformly deplete the drift region laterally, improve the electric field strength of the concave region in the middle of the "U"-shaped electric field, and solve the problem of low withstand voltage of the device.

[0006] In a first aspect, the present invention provides a shielded gate MOSFET device, the device comprising:

[0007] substrate;

[0008] A semiconductor body; the semiconductor body is located on one side of the substrate, and the semiconductor body includes a drift region, a body region and a first active region; the drift region is located on the side of the semiconductor body close to the substrate; the body region is located on the side of the drift region away from the substrate, and the first active region is located on the side of the body region away from the substrate; along a first direction, the drift region includes at least three majority carrier concentration peak regions; along the first direction, the peak values ​​of the corresponding majority carrier concentrations in at least three majority carrier concentration peak regions decrease gradually; along a second direction, first grooves are arranged on both sides of the semiconductor body; the first direction is the direction from the substrate to the semiconductor body, and the second direction is the direction perpendicular to the thickness of the substrate;

[0009] A gate structure, the gate structure is located in the first groove, the gate structure includes a control gate and a shielding gate, and the shielding gate and the control gate are arranged at intervals along the first direction;

[0010] A source structure, the source structure is located at a side of the semiconductor body away from the substrate; the source structure is in contact with the first active region;

[0011] The drain is located at a side of the substrate away from the semiconductor body.

[0012] Optionally, along the first direction, the majority-carrier concentration in the majority-carrier concentration peak region shows a trend of first increasing and then decreasing.

[0013] Optionally, along the first direction, the drift region includes a first majority carrier concentration peak region, a second majority carrier concentration peak region and a third majority carrier concentration peak region;

[0014] The first multi-carrier concentration peak region is located on a side of the drift region close to the substrate, a side of the first multi-carrier concentration peak region close to the substrate is flush with a side of the first groove close to the substrate, the second multi-carrier concentration peak region is located on a side of the first multi-carrier concentration peak region away from the substrate, and the third multi-carrier concentration peak region is located on a side of the second multi-carrier concentration peak region away from the substrate; the peak values ​​of the multi-carrier concentrations corresponding to the first multi-carrier concentration peak region, the second multi-carrier concentration peak region and the third multi-carrier concentration peak region show a decreasing trend.

[0015] Optionally, the lateral electric field generated between the shielding gate and the drift region depletes all majority carriers at the corresponding peak value of the majority carrier concentration in the majority carrier concentration peak region.

[0016] Optionally, the conductivity types of the substrate, the drift region and the first active region include N type, and the conductivity type of the body region includes P type;

[0017] Alternatively, the conductivity types of the substrate, the drift region, and the first active region include P type, and the conductivity type of the body region includes N type.

[0018] Optionally, when the conductivity types of the substrate, the drift region and the first active region include N-type, and the conductivity type of the body region includes P-type, along the first direction, the injection concentration of hydrogen ions at the corresponding majority carrier concentration peaks in at least three majority carrier concentration peak regions decreases.

[0019] Optionally, when the conductivity types of the substrate, the drift region and the first active region include P type and the conductivity type of the body region includes N type, along the first direction, the implantation concentration of hydrogen ions at the corresponding majority carrier concentration peaks in at least three majority carrier concentration peak regions increases.

[0020] In a second aspect, the present invention provides a method for preparing a shielded gate MOSFET device, the method comprising:

[0021] providing a substrate;

[0022] A semiconductor body is formed on one side of a substrate; the semiconductor body includes a drift region, a body region and a first active region; the drift region is located on a side of the semiconductor body close to the substrate; the body region is located on a side of the drift region away from the substrate, and the first active region is located on a side of the body region away from the substrate; along a first direction, the drift region includes at least three majority carrier concentration peak regions; along the first direction, the peak values ​​of the corresponding majority carrier concentrations in at least three majority carrier concentration peak regions decrease gradually; along a second direction, first grooves are arranged on both sides of the semiconductor body; the first direction is a direction from the substrate to the semiconductor body, and the second direction is a direction perpendicular to the thickness of the substrate;

[0023] A gate structure is formed in the first groove, wherein the gate structure includes a control gate and a shielding gate, and the shielding gate and the control gate are arranged at intervals along a first direction;

[0024] A source structure is formed on a side of the semiconductor body away from the substrate, wherein the source structure is in contact with the first active region;

[0025] A drain is formed on a side of the substrate away from the semiconductor body.

[0026] Optionally, forming a semiconductor body on one side of the substrate, forming a gate structure in the first groove, and forming a source structure on a side of the semiconductor body away from the substrate includes:

[0027] A drift region is formed on one side of the substrate, wherein the drift region includes a first groove; a body region is formed on a side of the drift region away from the substrate; and a first active region is formed on a side of the body region away from the substrate;

[0028] forming a gate structure in the first groove;

[0029] forming a source structure on a side of the first active region away from the substrate;

[0030] A passivation layer is formed on a side of the source structure away from the substrate; the passivation layer includes a second groove, and a vertical projection of the second groove on the substrate does not overlap with a vertical projection of the gate structure on the substrate;

[0031] The hydrogen ions are implanted into the drift region at least three times on the side of the passivation layer away from the substrate; the hydrogen ions implanted into the drift region are annealed; and the annealing temperature is less than 400°C.

[0032] Optionally, forming a semiconductor body on one side of the substrate, forming a gate structure in the first groove, forming a source structure on a side of the semiconductor body away from the substrate, and forming a drain on a side of the substrate away from the semiconductor body, comprises:

[0033] A drift region is formed on one side of the substrate, wherein the drift region includes a first groove; a body region is formed on a side of the drift region away from the substrate; and a first active region is formed on a side of the body region away from the substrate;

[0034] forming a gate structure in the first groove;

[0035] forming a source structure on a side of the first active region away from the substrate;

[0036] Performing a thinning process on a side of the substrate away from the semiconductor body;

[0037] Performing hydrogen ion implantation at least three times in the drift region on a side of the substrate away from the semiconductor body; performing annealing treatment on the hydrogen ions implanted in the drift region; the annealing temperature is less than 400° C.;

[0038] A drain is formed on a side of the substrate away from the semiconductor body.

[0039] According to the technical solution of the embodiment of the present invention, for the drift region between the first grooves, the drift region is set to include at least three multi-carrier concentration peak regions in the first direction, and along the first direction, the peak values ​​of the multi-carrier concentrations corresponding to the at least three multi-carrier concentration peak regions decrease. The difference between the potential of the drift region close to the substrate and the potential of the shielding gate is the largest, and the lateral depletion of the shielding gate to the side of the drift region close to the substrate is the strongest. The difference between the potential of the drift region close to the body region and the potential of the shielding gate is the smallest, and the lateral depletion of the shielding gate to the side of the drift region close to the body region is the weakest. The multi-carrier concentration peak value of the drift region close to the substrate is set to be the largest, and the multi-carrier concentration peak value of the drift region close to the body region is set to be the smallest, and the peak values ​​of the multi-carrier concentrations corresponding to the at least three multi-carrier concentration peak regions decrease in the first direction, so that the lateral depletion of the shielding gate to the drift region can be made more uniform, and the electric field strength of the depression area in the middle of the longitudinal electric field of the shielded gate MOSFET device is improved, thereby improving the withstand voltage of the device.

[0040] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is a structural schematic diagram of a shielded gate MOSFET device provided by the prior art;

[0043] Figure 2 It is a schematic structural diagram of a shielded gate MOSFET device provided by an embodiment of the present invention;

[0044] Figure 3 It is a flow chart of a method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention;

[0045] Figure 4-Figure 7 It is a structural schematic diagram corresponding to some steps in a method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention;

[0046] Figure 8 is a flow chart of another method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention;

[0047] Figure 9-14 It is a structural schematic diagram corresponding to some steps in another method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention;

[0048] Fig.15 is a flow chart of another method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention;

[0049] Figure 16-Figure 17 It is a structural schematic diagram corresponding to some steps in another method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0051] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0052] Figure 1 It is a schematic diagram of the structure of a shielded gate MOSFET device provided by the prior art, such as Figure 1 As shown, the shielded gate MOSFET device includes a first conductive type substrate 10, a first conductive type drift region 11, a second conductive type body region 12, a first conductive type active region 13 and a second conductive type active region 14, a source metal 15, a first dielectric layer 16, a shielded gate electrode 17, a control gate electrode 18, a second dielectric layer 19 and a drain metal 20. The longitudinal electric field E1 of the existing shielded gate MOSFET device is in a "U" shape during reverse withstand voltage, and the longitudinal electric field has two peaks, one of which is located on the side of the first conductive type drift region 11 close to the first conductive type substrate 10, and the other is located on the side of the first conductive type drift region 11 close to the second conductive type body region 12.

[0053] The difference between the potential of the shielding gate electrode 17 connected to the potential of the source metal 15 and the potential of the side of the first conductive type drift region 11 close to the first conductive type substrate 10 is large, resulting in excessive lateral depletion of the majority carriers of the first conductive type drift region 11 close to the first conductive type substrate 10 by the shielding gate electrode 17, generating an electric field peak. In the direction from the first conductive type substrate 10 to the first conductive type drift region 11, the potential of the first conductive type drift region 11 gradually approaches the potential of the shielding gate electrode 17, and the difference between the potential of the side of the first conductive type drift region 11 close to the second conductive type body region 12 and the potential of the shielding gate electrode 17 is close to zero, and the shielding gate electrode 17 has almost no lateral depletion of the majority carriers of the side of the first conductive type drift region 11 close to the second conductive type body region 12. However, on the side of the first conductive type drift region 11 close to the second conductive type body region 12, due to the longitudinal depletion between the second conductive type body region 12 and the first conductive type drift region 11, an electric field peak will also be generated, so the longitudinal electric field E1 of the existing shielded gate MOSFET device is "U" shaped.

[0054] The integral calculation of the longitudinal electric field E1 is the withstand voltage of the device. Since the shielding gate electrode 17 causes uneven lateral depletion of the first conductive type drift region 11, the longitudinal electric field E1 of the shielding gate MOSFET device is "U"-shaped. The middle recessed area of ​​the "U"-shaped electric field causes the device to have a lower withstand voltage.

[0055] In order to solve the above problems, the technical solutions of the embodiments of the present invention are as follows:

[0056] Figure 2 is a schematic diagram of the structure of a shielded gate MOSFET device provided by an embodiment of the present invention, such as Figure 2 As shown, the shielded gate MOSFET device includes: a substrate 1, a semiconductor body 2; the semiconductor body 2 is located on one side of the substrate 1, and the semiconductor body 2 includes a drift region 21, a body region 22 and a first active region 23. The drift region 21 is located on the side of the semiconductor body 2 close to the substrate 1; the body region 22 is located on the side of the drift region 21 away from the substrate 1, and the first active region 23 is located on the side of the body region 22 away from the substrate 1. Along the first direction Y, the drift region 21 includes at least three majority carrier concentration peak regions 210; along the first direction Y, the peak values ​​of the corresponding majority carrier concentrations ND in at least three majority carrier concentration peak regions 210 decrease gradually. Along the second direction X, first grooves are provided on both sides of the semiconductor body 2. The first direction Y is the direction from the substrate 1 to the semiconductor body 2, and the second direction X is the direction perpendicular to the thickness of the substrate 1. The gate structure 4 is located in the first groove, and the gate structure 4 includes a control gate 42 and a shielding gate 41. Along the first direction Y, the shielding gate 41 and the control gate 42 are arranged at intervals. A source structure 3 , the source structure 3 is located on a side of the semiconductor body 2 away from the substrate 1 . The source structure 3 is in contact with the first active region 23 . A drain 5 , the drain 5 is located on a side of the substrate 1 away from the semiconductor body 2 .

[0057] Specifically, the shielded gate MOSFET device may further include a second active region 24, and the shielded gate MOSFET device includes an N-channel shielded gate MOSFET device and a P-channel shielded gate MOSFET device. Exemplarily, when the shielded gate MOSFET device is an N-channel shielded gate MOSFET device, the substrate 1 is an N-substrate, the drift region 21 is an N-drift region, the body region 22 is a P-type body region, the first active region 23 is an N++ active region, and the second active region 24 is a P++ active region. When the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the substrate 1 is a P-substrate, the drift region 21 is a P-drift region, the body region 22 is an N-type body region, the first active region 23 is a P++ active region, and the second active region 24 is an N++ active region.

[0058] The source structure 3 includes a source 31 and a gate-source dielectric layer 32. The gate-source dielectric layer 32 is located on both sides of the source 31 along the second direction X. The source 31 is in contact with the first active region 23. The gate structure 4 may also include a gate dielectric layer 43. The gate dielectric layer 43 is filled in the first groove. Along the first direction Y, the shielding gate 41 and the control gate 42 are spaced apart in the gate dielectric layer 43. The shielding gate MOSFET device may also include a passivation layer ( Figure 2 The passivation layer is located on the side of the source structure 3 away from the substrate 1, and the passivation layer may include a second groove, the second groove exposes the source 31, and the vertical projection of the second groove on the substrate 1 does not overlap with the vertical projection of the gate structure 4 on the substrate 1. An ohmic contact layer may be formed in the second groove.

[0059] Along the first direction Y, the drift region 21 may include a plurality of majority-substance concentration peak regions 210. Figure 2 The drift region 21 is shown to include three majority carrier concentration peak regions 210. Along the first direction Y, the lower surface of the majority carrier concentration peak region 210 close to the substrate 1 side is flush with the lower surface of the first groove. The initial majority carrier concentration ND of the drift region 21 is N0, that is, the drift region 21 is initially uniformly doped, and the impurity concentration is N0. Without considering the influence of the shielded gate structure, the avalanche breakdown theory of the PN junction is used, and the calculation formula of N0 can be obtained from the withstand voltage of the device as follows:

[0060]

[0061] Wherein, BV is the breakdown voltage.

[0062] For an N-channel shielded gate MOSFET device, on the basis that the initial majority carrier concentration ND of the drift region 21 is N0, the region between the first grooves in the drift region 21 is continuously doped to form a plurality of majority carrier concentration peak regions 210. A majority carrier concentration peak is formed in each majority carrier concentration peak region 210, and the majority carrier concentration peak is an N-type impurity peak. Along the first direction Y, for the drift region 21 between the first grooves, from the side of the drift region 21 close to the substrate 1 to the side of the drift region 21 close to the body region 22, a plurality of majority carrier concentration peak regions 210 are sequentially arranged, and from the side of the drift region 21 close to the substrate 1 to the side of the drift region 21 close to the body region 22, the amplitude of the majority carrier concentration peak, i.e., the N-type impurity peak, in the majority carrier concentration peak region 210 decreases.

[0063] Optionally, the following is an exemplary description of the calculation process of the majority carrier concentration peak value in the majority carrier concentration peak region 210 for an N-channel shielded gate MOSFET device, which is doped by hydrogen ion implantation:

[0064] Ideally, the longitudinal electric field E in the drift region 21 is yis uniformly distributed, that is, the electric field in the first direction Y is uniformly distributed, and the potential distribution of the drift region 21 in the first direction Y is linearly distributed. When the device undergoes avalanche breakdown, the longitudinal electric field E of the drift region 21 y Equal to the critical breakdown electric field E c , for example, when the material of the drift region 21 is silicon, the critical breakdown electric field E c is 2*10 5 V / cm. The potential at the majority carrier concentration peak in the majority carrier concentration peak region 210 is:

[0065] V(y n )=V D -E C *Δy n

[0066] It is assumed that the potential of the first groove close to the substrate 1 is close to the drain voltage. n ) is the potential at the majority carrier concentration peak in the majority carrier concentration peak region 210, that is, Figure 2 The potential at y1, y2 or y3, V D is the voltage of drain 5, Δy n is the distance between the majority carrier concentration peak in the majority carrier concentration peak region 210 and the first groove close to the substrate 1 .

[0067] Therefore, the potential difference between the semiconductor at the majority carrier concentration peak in the majority carrier concentration peak region 210 on the center line of the drift region 21 and the shielding gate 41 is:

[0068] V D -V S =V D -E C *Δy n

[0069] Among them, V S is the potential of the shield gate 41. The potential of the shield gate 41 is the same as the potential of the source 31 during reverse withstand voltage, and both are zero potential.

[0070] The electric field in the lateral direction (second direction X) at the majority carrier concentration peak in the majority carrier concentration peak region 210 is:

[0071]

[0072] Among them, E xn is the electric field in the lateral direction at the majority carrier concentration peak in the majority carrier concentration peak region 210 , and W is the width of the drift region 21 between the first grooves.

[0073] In addition, in the lateral direction, when the material of the drift region 21 is silicon, according to the Poisson equation, there is:

[0074]

[0075] Among them, ε si is the dielectric constant of silicon, q is the elementary charge, a n is the majority carrier concentration value at the majority carrier concentration peak in the majority carrier concentration peak region 210 .

[0076] Therefore, the majority carrier concentration value a at the majority carrier concentration peak in the majority carrier concentration peak region 210 can be obtained. n for:

[0077]

[0078] The required majority carrier concentration a can be obtained at the majority carrier concentration peak in the majority carrier concentration peak region 210 by adjusting the energy and dose of hydrogen ion implantation. n .

[0079] For a P-channel shielded gate MOSFET device, on the basis that the initial majority carrier concentration ND of the drift region 21 is N0, the region between the first grooves in the drift region 21 is continuously doped to form a plurality of majority carrier concentration peak regions 210. A majority carrier concentration peak is formed in each majority carrier concentration peak region 210, and the majority carrier concentration peak is a P-type impurity peak. Along the first direction Y, for the drift region 21 between the first grooves, from the side of the drift region 21 close to the substrate 1 to the side of the drift region 21 close to the body region 22, a plurality of majority carrier concentration peak regions 210 are sequentially arranged, and from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22, the amplitude of the majority carrier concentration peak, i.e., the P-type impurity peak, in the majority carrier concentration peak region 210 decreases.

[0080] Continue to refer Figure 2 For the drift region 21 between the first grooves, the difference between the potential of the side of the drift region 21 close to the substrate 1 and the potential of the shielding gate 41 is the largest, and the shielding gate 41 has the strongest lateral depletion of the side of the drift region 21 close to the substrate 1. The difference between the potential of the side of the drift region 21 close to the body region 22 and the potential of the shielding gate 41 is the smallest, and the shielding gate 41 has the weakest lateral depletion of the side of the drift region 21 close to the body region 22. The peak value of the majority carrier concentration of the side of the drift region 21 close to the substrate 1 is set to be the largest, and the peak value of the majority carrier concentration of the side of the drift region 21 close to the body region 22 is set to be the smallest, and the peak values ​​of the corresponding majority carrier concentrations in at least three majority carrier concentration peak regions 210 decrease in the first direction Y, so that the shielding gate 41 can make the lateral depletion of the drift region 21 more uniform, and the electric field strength of the depression area in the middle of the longitudinal electric field E1 of the shielded gate MOSFET device is improved.

[0081] According to the technical solution of the embodiment of the present invention, for the drift region between the first grooves, the drift region is set to include at least three multi-carrier concentration peak regions in the first direction, and along the first direction, the peak values ​​of the multi-carrier concentrations corresponding to the at least three multi-carrier concentration peak regions decrease. The difference between the potential of the drift region close to the substrate and the potential of the shielding gate is the largest, and the lateral depletion of the shielding gate to the side of the drift region close to the substrate is the strongest. The difference between the potential of the drift region close to the body region and the potential of the shielding gate is the smallest, and the lateral depletion of the shielding gate to the side of the drift region close to the body region is the weakest. The multi-carrier concentration peak value of the drift region close to the substrate is set to be the largest, and the multi-carrier concentration peak value of the drift region close to the body region is set to be the smallest, and the peak values ​​of the multi-carrier concentrations corresponding to the at least three multi-carrier concentration peak regions decrease in the first direction, so that the lateral depletion of the shielding gate to the drift region can be made more uniform, and the electric field strength of the depression area in the middle of the longitudinal electric field of the shielded gate MOSFET device is improved, thereby improving the withstand voltage of the device.

[0082] Optionally, based on the above embodiments, continue to refer to Figure 2 For the N-channel shielded gate MOSFET device and the P-channel shielded gate MOSFET device, along the first direction Y, the majority carrier concentration ND in the majority carrier concentration peak region 210 shows a trend of first increasing and then decreasing.

[0083] Specifically, the majority carrier concentration ND in the majority carrier concentration peak region 210 shows a trend of increasing first and then decreasing, which is determined by the doping process. The impurity distribution formed by ion implantation causes the majority carrier concentration ND in the majority carrier concentration peak region 210 to show a trend of increasing first and then decreasing. The majority carrier concentration value at each location in the drift region 21 must be ensured to be fully depleted by the shielding gate 41, so that the shielding gate 41 uniformly depletes the drift region 21 in the lateral direction.

[0084] Optionally, based on the above embodiments, continue to refer to Figure 2 For N-channel shielded gate MOSFET devices and P-channel shielded gate MOSFET devices, along the first direction Y, the drift region 21 includes a first multi-carrier concentration peak region 211, a second multi-carrier concentration peak region 212, and a third multi-carrier concentration peak region 213. The first multi-carrier concentration peak region 211 is located on the side of the drift region 21 close to the substrate 1, and the side of the first multi-carrier concentration peak region 211 close to the substrate 1 is flush with the side of the first groove close to the substrate 1. The second multi-carrier concentration peak region 212 is located on the side of the first multi-carrier concentration peak region 211 away from the substrate 1, and the third multi-carrier concentration peak region 213 is located on the side of the second multi-carrier concentration peak region 212 away from the substrate 1. The peak values ​​of the multi-carrier concentrations ND corresponding to the first multi-carrier concentration peak region 211, the second multi-carrier concentration peak region 212, and the third multi-carrier concentration peak region 213 show a decreasing trend.

[0085] Specifically, the drift region 21 may be provided with three multi-carrier concentration peak regions 210 along the first direction Y. Along the first direction Y, for the drift region 21 between the first grooves, the first multi-carrier concentration peak region 211, the second multi-carrier concentration peak region 212 and the third multi-carrier concentration peak region 213 are provided in sequence. The first multi-carrier concentration peak region 211 may include a first multi-carrier concentration peak, and the first multi-carrier concentration peak is located at y1 on the side of the drift region 21 close to the substrate 1. The second multi-carrier concentration peak region 212 may include a second multi-carrier concentration peak, and the second multi-carrier concentration peak is located at y2 on the side of the first multi-carrier concentration peak region 211 away from the substrate 1. The third multi-carrier concentration peak region 213 may include a third multi-carrier concentration peak, and the third multi-carrier concentration peak is located at y3 on the side of the second multi-carrier concentration peak region 212 away from the substrate 1.

[0086] The corresponding majority carrier concentration ND at y1 is a3, the corresponding majority carrier concentration ND at y2 is a2, and the corresponding majority carrier concentration ND at y3 is a1. The values ​​of a1, a2, and a3 increase in sequence, that is, the peak values ​​of the corresponding majority carrier concentrations ND in the first majority carrier concentration peak region 211, the second majority carrier concentration peak region 212, and the third majority carrier concentration peak region 213 show a decreasing trend. This arrangement makes the shield gate 41 more uniform in the lateral depletion of the drift region 21, and the electric field strength of the concave region in the middle of the longitudinal electric field E1 of the shield gate MOSFET device is improved. Thus, the withstand voltage of the device is also improved.

[0087] Optionally, based on the above embodiments, continue to refer to Figure 2 For N-channel shielded gate MOSFET devices and P-channel shielded gate MOSFET devices, the lateral electric field generated between the shielding gate 41 and the drift region 21 completely depletes all the majority carriers at the peak value of the corresponding majority carrier concentration ND in the majority carrier concentration peak region 210.

[0088] Specifically, the concentration value of majority carriers at each location of the drift region 21 must be guaranteed to be fully depleted by the shielding gate 41, that is, the concentration value of N-type impurities or P-type impurities at each location of the drift region 21 must be guaranteed to be fully depleted by the shielding gate 41, so that the shielding gate 41 uniformly depletes the drift region 21 laterally. The electric field strength of the concave region in the middle of the longitudinal electric field E1 of the shielded gate MOSFET device is improved, thereby improving the withstand voltage of the device.

[0089] Optionally, based on the above embodiments, continue to refer to Figure 2 For an N-channel shielded gate MOSFET device, the conductivity types of the substrate 1, the drift region 21 and the first active region 23 include N-type, and the conductivity type of the body region 22 includes P-type. Or for a P-channel shielded gate MOSFET device, the conductivity types of the substrate 1, the drift region 21 and the first active region 23 include P-type, and the conductivity type of the body region 22 includes N-type.

[0090] Specifically, the shielded gate MOSFET device includes an N-channel shielded gate MOSFET device and a P-channel shielded gate MOSFET device. Exemplarily, when the shielded gate MOSFET device is an N-channel shielded gate MOSFET device, the substrate 1 is an N-substrate, the drift region 21 is an N-drift region, the body region 22 is a P-type body region, the first active region 23 is an N++ active region, and the second active region 24 is a P++ active region. When the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the substrate 1 is a P-substrate, the drift region 21 is a P-drift region, the body region 22 is an N-type body region, the first active region 23 is a P++ active region, and the second active region 24 is an N++ active region.

[0091] Optionally, based on the above embodiments, continue to refer to Figure 2 For an N-channel shielded gate MOSFET device, when the conductivity types of the substrate 1, the drift region 21 and the first active region 23 include N-type, and the conductivity type of the body region 22 includes P-type, along the first direction Y, the injection concentration of hydrogen ions at the peak values ​​of the corresponding majority carrier concentrations ND in at least three majority carrier concentration peak regions 210 decreases.

[0092] Specifically, for an N-channel shielded gate MOSFET device, N-type doping of the drift region 21 can be achieved by injecting hydrogen ions into the drift region 21. The concentration of the injected hydrogen ions is positively correlated with the concentration of majority carriers, and the majority carriers are electrons at this time. After hydrogen ions are injected into the drift region 21, the lattice defects introduced by the hydrogen ion injection can be converted into N-type doping after low-temperature annealing. The drift region 21 is injected with hydrogen ions at least three times, and the concentration of the hydrogen ion injection can have the same trend as the change of the majority carrier concentration ND. The injection of hydrogen ions is equivalent to the introduction of N-type impurities. The higher the concentration of hydrogen ions, the higher the concentration of N-type impurities.

[0093] By at least three hydrogen ion implantations, the implantation dose and energy are adjusted to form a majority carrier concentration peak in the majority carrier concentration peak region 210 in the drift region 21, that is, to form an N-type impurity peak. For the drift region 21 between the first grooves, multiple majority carrier concentration peak regions 210 are sequentially arranged from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22, and the amplitude of the majority carrier concentration peak, that is, the N-type impurity peak, in the majority carrier concentration peak region 210 decreases from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22. The majority carrier concentration peak with the largest amplitude is located on the side of the drift region 21 close to the substrate 1, and the majority carrier concentration peak with the smallest amplitude is located on the side of the drift region 21 close to the body region 22.

[0094] By injecting hydrogen ions, a distribution of N-type impurity peaks that decrease in sequence in the first direction Y is formed. The special impurity distribution formed by the hydrogen ion injection makes the shield gate 41 uniformly deplete the drift region 21 laterally. The electric field strength of the recessed area in the middle of the longitudinal electric field E1 of the shielded gate MOSFET device is improved, and the distribution of the longitudinal electric field E1 during breakdown is improved, so that the withstand voltage of the device is also improved. In addition, the hydrogen injection method is flexible, and the required impurity distribution can be obtained by adjusting the injection dose and energy. At the same time, the defects introduced by hydrogen ion injection will also affect the lifetime of minority carriers. Such a distribution of minority carrier lifetime is conducive to shortening the reverse recovery time of the body diode of the device and improving the reverse recovery softness of the body diode.

[0095] Optionally, based on the above embodiments, continue to refer to Figure 2 For a P-channel shielded gate MOSFET device, when the conductivity types of the substrate 1, the drift region 21 and the first active region 23 include P-type, and the conductivity type of the body region 22 includes N-type, along the first direction Y, the implantation concentration of hydrogen ions at the peak values ​​of the corresponding majority carrier concentrations ND in at least three majority carrier concentration peak regions 210 increases gradually.

[0096] Specifically, for a P-channel shielded gate MOSFET device, P-type doping of the drift region 21 can be achieved by injecting hydrogen ions into the drift region 21. The concentration of the injected hydrogen ions is negatively correlated with the concentration of majority carriers, and the majority carriers are holes. The drift region 21 is injected with hydrogen ions at least three times, and the concentration of the injected hydrogen ions can be opposite to the change trend of the majority carrier concentration ND. The injection of hydrogen ions is equivalent to the introduction of P-type impurities. The higher the concentration of hydrogen ions, the lower the concentration of P-type impurities.

[0097] Through at least three hydrogen ion implantations, a majority carrier concentration peak is formed in the majority carrier concentration peak region 210 in the drift region 21, that is, a P-type impurity peak is formed. For the drift region 21 between the first grooves, multiple majority carrier concentration peak regions 210 are sequentially arranged from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22, and the amplitude of the majority carrier concentration peak, that is, the P-type impurity peak, in the majority carrier concentration peak region 210 decreases from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22. The majority carrier concentration peak with the largest amplitude is located on the side of the drift region 21 close to the substrate 1, and the majority carrier concentration peak with the smallest amplitude is located on the side of the drift region 21 close to the body region 22.

[0098] By injecting hydrogen ions, a distribution of P-type impurity peaks that decrease in sequence in the first direction Y is formed. The special impurity distribution formed by the hydrogen ion injection makes the shield gate 41 uniformly deplete the drift region 21 laterally. The electric field strength of the recessed area in the middle of the longitudinal electric field E1 of the shielded gate MOSFET device is improved, and the distribution of the longitudinal electric field E1 during breakdown is improved, so that the withstand voltage of the device is also improved. In addition, the hydrogen injection method is flexible, and the required impurity distribution can be obtained by adjusting the injection dose and energy. At the same time, the defects introduced by hydrogen ion injection will also affect the lifetime of minority carriers. Such a distribution of minority carrier lifetime is conducive to shortening the reverse recovery time of the body diode of the device and improving the reverse recovery softness of the body diode.

[0099] Figure 3 is a flow chart of a method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention, Figure 4-Figure 7 is a schematic structural diagram corresponding to some steps in a method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention, such as Figure 3 As shown, the method for preparing a shielded gate MOSFET device includes:

[0100] S100: providing a substrate.

[0101] Specifically, Figure 4 As shown, a substrate 1 is first provided, and the semiconductor material of the substrate 1 can be silicon, silicon carbide or gallium nitride. The shielded gate MOSFET device includes an N-channel shielded gate MOSFET device and a P-channel shielded gate MOSFET device. Exemplarily, when the shielded gate MOSFET device is an N-channel shielded gate MOSFET device, the substrate 1 is an N-substrate, and when the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the substrate 1 is a P-substrate.

[0102] S110: A semiconductor body is formed on one side of a substrate; the semiconductor body includes a drift region, a body region and a first active region; the drift region is located on a side of the semiconductor body close to the substrate; the body region is located on a side of the drift region away from the substrate, and the first active region is located on a side of the body region away from the substrate; along a first direction, the drift region includes at least three majority-carrier concentration peak regions; along the first direction, the peak values ​​of the corresponding majority-carrier concentrations in at least three majority-carrier concentration peak regions decrease gradually; along a second direction, first grooves are arranged on both sides of the semiconductor body; the first direction is a direction from the substrate to the semiconductor body, and the second direction is a direction perpendicular to the thickness of the substrate.

[0103] Specifically, Figure 5As shown, a semiconductor body 2 is formed on one side of a substrate 1, and the semiconductor body 2 includes a drift region 21 located on a side of the semiconductor body 2 close to the substrate 1, a body region 22 located on a side of the drift region 21 away from the substrate 1, and a first active region 23 located on a side of the body region 22 away from the substrate 1. The semiconductor body 2 may further include a second active region 24 located in the middle of the first active region 23. First grooves 25 are provided on both sides of the semiconductor body 2.

[0104] The material of the semiconductor body 2 includes silicon, silicon carbide or gallium nitride. Exemplarily, when the shielded gate MOSFET device is an N-channel shielded gate MOSFET device, the drift region 21 is an N-drift region, the body region 22 is a P-type body region, the first active region 23 is an N++ active region, and the second active region 24 is a P++ active region. When the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the substrate 1 is a P-substrate, the drift region 21 is a P-drift region, the body region 22 is an N-type body region, the first active region 23 is a P++ active region, and the second active region 24 is an N++ active region.

[0105] Exemplarily, an epitaxial layer can be formed on one side of the substrate 1 by epitaxial processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) or atomic layer epitaxy (ALE), and then a body region 22, a first active region 23 and a second active region 24 are formed by processes such as ion implantation and annealing. After completing the above steps, a drift region 21 is formed, and the semiconductor material and doping type of the drift region 21 and the epitaxial layer are the same. Then, grooves are cut on both sides of the drift region 21 to form a first groove 25.

[0106] For an N-channel shielded gate MOSFET device, the drift region 21 is doped along the first direction Y to form a plurality of majority carrier concentration peak regions 210. A majority carrier concentration peak is formed in each majority carrier concentration peak region 210, and the majority carrier concentration peak is an N-type impurity peak. Along the first direction Y, for the drift region 21 between the first grooves, from the side of the drift region 21 close to the substrate 1 to the side of the drift region 21 close to the body region 22, a plurality of majority carrier concentration peak regions 210 are sequentially arranged, and from the side of the drift region 21 close to the substrate 1 to the side of the drift region 21 close to the body region 22, the amplitude of the majority carrier concentration peak, that is, the N-type impurity peak, in the majority carrier concentration peak region 210 decreases.

[0107] For a P-channel shielded gate MOSFET device, the drift region 21 is doped along the first direction Y to form a plurality of majority carrier concentration peak regions 210. A majority carrier concentration peak is formed in each majority carrier concentration peak region 210, and the majority carrier concentration peak is a P-type impurity peak. Along the first direction Y, for the drift region 21 between the first grooves, from the side of the drift region 21 close to the substrate 1 to the side of the drift region 21 close to the body region 22, a plurality of majority carrier concentration peak regions 210 are sequentially arranged, and from the side of the drift region 21 close to the substrate 1 to the side of the drift region 21 close to the body region 22, the amplitude of the majority carrier concentration peak, that is, the P-type impurity peak, in the majority carrier concentration peak region 210 decreases.

[0108] For the drift region 21 between the first grooves, the difference between the potential of the side of the drift region 21 close to the substrate 1 and the potential of the shielding gate 41 is the largest, and the shielding gate 41 has the strongest lateral depletion of the side of the drift region 21 close to the substrate 1. The difference between the potential of the side of the drift region 21 close to the body region 22 and the potential of the shielding gate 41 is the smallest, and the shielding gate 41 has the weakest lateral depletion of the side of the drift region 21 close to the body region 22. The peak value of the majority carrier concentration of the side of the drift region 21 close to the substrate 1 is set to be the largest, and the peak value of the majority carrier concentration of the side of the drift region 21 close to the body region 22 is set to be the smallest, and the peak values ​​of the corresponding majority carrier concentrations in at least three majority carrier concentration peak regions 210 decrease in the first direction Y, so that the shielding gate 41 can make the lateral depletion of the drift region 21 more uniform, and the electric field strength of the depression area in the middle of the longitudinal electric field of the shielded gate MOSFET device is improved.

[0109] S120: forming a gate structure in the first groove, the gate structure comprising a control gate and a shielding gate, and the shielding gate and the control gate are spaced apart along the first direction.

[0110] Specifically, Figure 6 As shown, a gate dielectric layer 43 is first formed in the first groove by deposition or other processes, and the gate dielectric layer 43 is subjected to photolithography and etching or other processes to form a shielding gate 41 and a control gate 42. The gate dielectric layer 43 may be a silicon oxide gate dielectric layer, the shielding gate 41 may be a polysilicon shielding gate, and the control gate 42 may be a polysilicon control gate.

[0111] S130: forming a source structure on a side of the semiconductor body away from the substrate, wherein the source structure is in contact with the first active region.

[0112] Specifically, Figure 7 As shown, a gate-source dielectric layer 32 is first formed on the side of the semiconductor body 2 away from the substrate 1 by deposition or other processes, and the gate-source dielectric layer 32 is subjected to photolithography and etching or other processes to form a source electrode 31. The gate-source dielectric layer 32 may be a silicon oxide gate-source dielectric layer, and the source electrode 31 may be a metal source electrode. After the source structure 3 is formed, a passivation layer ( Figure 7(not shown), the passivation layer is opened to expose the source 31, and then hole injection is performed to form an ohmic contact layer.

[0113] S140: forming a drain on a side of the substrate away from the semiconductor body.

[0114] Specifically, Figure 2 As shown, the side of the substrate 1 away from the semiconductor body 2 may be thinned first, and then a drain 5 may be formed on the side of the substrate 1 away from the semiconductor body 2 . The drain 5 may be a metal drain.

[0115] According to the technical solution of the embodiment of the present invention, for the drift region between the first grooves, the drift region is set to include at least three multi-carrier concentration peak regions in the first direction, and along the first direction, the peak values ​​of the multi-carrier concentrations corresponding to the at least three multi-carrier concentration peak regions decrease. The difference between the potential of the drift region close to the substrate and the potential of the shielding gate is the largest, and the lateral depletion of the shielding gate to the side of the drift region close to the substrate is the strongest. The difference between the potential of the drift region close to the body region and the potential of the shielding gate is the smallest, and the lateral depletion of the shielding gate to the side of the drift region close to the body region is the weakest. The multi-carrier concentration peak value of the drift region close to the substrate is set to be the largest, and the multi-carrier concentration peak value of the drift region close to the body region is set to be the smallest, and the peak values ​​of the multi-carrier concentrations corresponding to the at least three multi-carrier concentration peak regions decrease in the first direction, so that the lateral depletion of the shielding gate to the drift region can be made more uniform, and the electric field strength of the depression area in the middle of the longitudinal electric field of the shielded gate MOSFET device is improved, thereby improving the withstand voltage of the device.

[0116] Optionally, based on the above embodiments, Figure 8 is a flow chart of another method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention, Figure 9-14 FIG. 1 is a schematic structural diagram corresponding to some steps in another method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention, such as Figure 8 As shown, the method for preparing a shielded gate MOSFET device includes:

[0117] S200: providing a substrate.

[0118] S210: forming a drift region on one side of the substrate, the drift region including the first groove; forming a body region on a side of the drift region away from the substrate; and forming a first active region on a side of the body region away from the substrate.

[0119] Specifically, Fig. 9As shown, an epitaxial layer can be formed on one side of the substrate 1 by epitaxial processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) or atomic layer epitaxy (ALE), and then a body region 22, a first active region 23 and a second active region 24 are formed by processes such as ion implantation and annealing. After completing the above steps, a drift region 21 is formed, and the semiconductor material and doping type of the drift region 21 and the epitaxial layer are the same. Then, grooves are cut on both sides of the drift region 21 to form a first groove 25.

[0120] S220: forming a gate structure in the first groove.

[0121] Specifically, Fig.10 As shown, a gate dielectric layer 43 is first formed in the first groove by deposition or other processes, and the gate dielectric layer 43 is subjected to photolithography and etching or other processes to form a shielding gate 41 and a control gate 42. The gate dielectric layer 43 may be a silicon oxide gate dielectric layer, the shielding gate 41 may be a polysilicon shielding gate, and the control gate 42 may be a polysilicon control gate.

[0122] S230: forming a source structure on a side of the first active region away from the substrate.

[0123] Specifically, Fig.11 As shown, a gate-source dielectric layer 32 is first formed by deposition or other processes on the side of the semiconductor body 2 away from the substrate 1, and the gate-source dielectric layer 32 is subjected to photolithography and etching processes to form a source electrode 31. The gate-source dielectric layer 32 may be a silicon oxide gate-source dielectric layer, and the source electrode 31 may be a metal source electrode.

[0124] S240: forming a passivation layer on a side of the source structure away from the substrate; the passivation layer comprises a second groove, and a vertical projection of the second groove on the substrate does not overlap with a vertical projection of the gate structure on the substrate.

[0125] Specifically, Fig.12 As shown, after forming the source structure 3, a passivation layer 6 can be formed on the side of the source structure 3 away from the substrate 1, and the passivation layer 6 is opened by photolithography and etching to form a second groove 61 to expose the source 31. Hole injection can be performed in the second groove 61 to form an ohmic contact layer.

[0126] S250: performing hydrogen ion implantation at least three times into the drift region on a side of the passivation layer away from the substrate; performing annealing treatment on the implanted hydrogen ions in the drift region; the annealing temperature is less than 400°C.

[0127] Specifically, Fig.13As shown, for an N-channel shielded gate MOSFET device, hydrogen ions are injected into the drift region 21 on the side of the passivation layer 6 away from the substrate 1 and the hydrogen ions are subjected to low-temperature annealing to achieve N-type doping of the drift region 21. The concentration of the injected hydrogen ions is positively correlated with the concentration of majority carriers, and at this time, the majority carriers are electrons. After hydrogen ions are injected into the drift region 21, low-temperature annealing is performed, and the annealing temperature is less than 400°C, so that the lattice defects introduced by the hydrogen ion injection can be converted into N-type doping. At least three hydrogen ion injections are performed on the drift region 21 on the side of the passivation layer 6 away from the substrate 1. The concentration of the hydrogen ion injection can have the same trend as the variation of the majority carrier concentration ND. The injection of hydrogen ions is equivalent to the introduction of N-type impurities. The higher the concentration of hydrogen ions, the higher the concentration of N-type impurities.

[0128] By at least three hydrogen ion implantations, the implantation dose and energy are adjusted to form a majority carrier concentration peak in the majority carrier concentration peak region 210 in the drift region 21, i.e., an N-type impurity peak. For the drift region 21 between the first grooves, multiple majority carrier concentration peak regions 210 are sequentially arranged from the side of the drift region 21 close to the substrate 1 to the side of the drift region 21 close to the body region 22, and the amplitude of the majority carrier concentration peak, i.e., the N-type impurity peak, in the majority carrier concentration peak region 210 decreases from the side of the drift region 21 close to the substrate 1 to the side of the drift region 21 close to the body region 22. The majority carrier concentration peak with the largest amplitude is located on the side of the drift region 21 close to the substrate 1, and the majority carrier concentration peak with the smallest amplitude is located on the side of the drift region 21 close to the body region 22.

[0129] For a P-channel shielded gate MOSFET device, hydrogen ions are injected into the drift region 21 on the side of the passivation layer 6 away from the substrate 1 and the hydrogen ions are subjected to low temperature annealing to achieve P-type doping of the drift region 21. The concentration of the injected hydrogen ions is negatively correlated with the concentration of majority carriers, and at this time, the majority carriers are holes. The drift region 21 is injected with hydrogen ions at least three times on the side of the passivation layer 6 away from the substrate 1. The concentration of the injected hydrogen ions can be opposite to the trend of the change of the majority carrier concentration ND. The injection of hydrogen ions is equivalent to the introduction of P-type impurities. The higher the concentration of hydrogen ions, the lower the concentration of P-type impurities.

[0130] By at least three hydrogen ion implantations, the implantation dose and energy are adjusted to form a majority carrier concentration peak in the majority carrier concentration peak region 210 in the drift region 21, i.e., a P-type impurity peak. For the drift region 21 between the first grooves, multiple majority carrier concentration peak regions 210 are sequentially arranged from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22, and the amplitude of the majority carrier concentration peak, i.e., the P-type impurity peak, in the majority carrier concentration peak region 210 decreases from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22. The majority carrier concentration peak with the largest amplitude is located on the side of the drift region 21 close to the substrate 1, and the majority carrier concentration peak with the smallest amplitude is located on the side of the drift region 21 close to the body region 22.

[0131] S260: forming a drain on a side of the substrate away from the semiconductor body.

[0132] Specifically, Fig.14 As shown, the side of the substrate 1 away from the semiconductor body 2 may be thinned first, and then a drain 5 may be formed on the side of the substrate 1 away from the semiconductor body 2 . The drain 5 may be a metal drain.

[0133] The technical solution of the embodiment of the present invention is that after forming the source structure, a passivation layer is formed on the side of the source structure away from the substrate, and the passivation layer is opened by processes such as photolithography and etching to form a second groove, and the vertical projection of the second groove on the substrate does not overlap with the vertical projection of the gate structure on the substrate, that is, the vertical projection of the passivation layer on the substrate can cover the vertical projection of the gate structure on the substrate. After the passivation layer is opened and the holes are injected, multiple hydrogen ion injections are performed and the hydrogen ions are subjected to low-temperature annealing, and a multi-carrier concentration peak is formed in the multi-carrier concentration peak area in the drift region, that is, an impurity peak is formed. Since the vertical projection of the passivation layer on the substrate can cover the vertical projection of the gate structure on the substrate, the passivation layer can shield the gate structure during hydrogen ion injection, thereby preventing hydrogen ions from being injected into the gate dielectric layer, the control gate or the shielding gate.

[0134] Optionally, based on the above embodiments, Fig.15 is a flow chart of another method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention, Figure 16-Figure 17 FIG. 1 is a schematic structural diagram corresponding to some steps in another method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention, such as Fig.15 As shown, the method for preparing a shielded gate MOSFET device includes:

[0135] S300: providing a substrate.

[0136] S310: forming a drift region on one side of the substrate, wherein the drift region includes a first groove; forming a body region on a side of the drift region away from the substrate; and forming a first active region on a side of the body region away from the substrate.

[0137] S320: forming a gate structure in the first groove.

[0138] S330: forming a source structure on a side of the first active region away from the substrate.

[0139] S340: performing a thinning process on a side of the substrate away from the semiconductor body.

[0140] Specifically, Fig.12 and Fig.16 As shown, in Fig.12 After forming the passivation layer, the side of the substrate 1 away from the semiconductor body 2 is thinned to form Fig.16The structure shown.

[0141] S350: performing hydrogen ion implantation at least three times into the drift region on a side of the substrate away from the semiconductor body; performing annealing treatment on the implanted hydrogen ions in the drift region; the annealing temperature is less than 400°C.

[0142] Specifically, Fig.17 As shown, for an N-channel shielded gate MOSFET device, hydrogen ions are injected into the drift region 21 on the side of the substrate 1 away from the semiconductor body 2 and the hydrogen ions are subjected to low-temperature annealing to achieve N-type doping of the drift region 21. The concentration of the injected hydrogen ions is positively correlated with the concentration of majority carriers, and the majority carriers are electrons at this time. After hydrogen ions are injected into the drift region 21, low-temperature annealing is performed, and the annealing temperature is less than 400°C, so that the lattice defects introduced by the hydrogen ion injection can be converted into N-type doping. At least three hydrogen ion injections are performed into the drift region 21 on the side of the substrate 1 away from the semiconductor body 2. The concentration of the hydrogen ion injection can have the same trend as the variation of the majority carrier concentration ND. The injection of hydrogen ions is equivalent to the introduction of N-type impurities. The higher the concentration of hydrogen ions, the higher the concentration of N-type impurities.

[0143] By at least three hydrogen ion implantations, the implantation dose and energy are adjusted to form a majority carrier concentration peak in the majority carrier concentration peak region 210 in the drift region 21, i.e., an N-type impurity peak. For the drift region 21 between the first grooves, multiple majority carrier concentration peak regions 210 are sequentially arranged from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22, and the amplitude of the majority carrier concentration peak, i.e., the N-type impurity peak, in the majority carrier concentration peak region 210 decreases from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22. The majority carrier concentration peak with the largest amplitude is located on the side of the drift region 21 close to the substrate 1, and the majority carrier concentration peak with the smallest amplitude is located on the side of the drift region 21 close to the body region 22.

[0144] For a P-channel shielded gate MOSFET device, hydrogen ions are injected into the drift region 21 on the side of the substrate 1 away from the semiconductor body 2 and the hydrogen ions are subjected to low temperature annealing to achieve P-type doping of the drift region 21. The concentration of the injected hydrogen ions is negatively correlated with the concentration of majority carriers, and at this time, the majority carriers are holes. The drift region 21 is injected with hydrogen ions at least three times on the side of the substrate 1 away from the semiconductor body 2. The concentration of the injected hydrogen ions can be opposite to the trend of the change of the majority carrier concentration ND. The injection of hydrogen ions is equivalent to the introduction of P-type impurities. The higher the concentration of hydrogen ions, the lower the concentration of P-type impurities.

[0145] By at least three hydrogen ion implantations, the implantation dose and energy are adjusted to form a majority carrier concentration peak in the majority carrier concentration peak region 210 in the drift region 21, i.e., a P-type impurity peak. For the drift region 21 between the first grooves, multiple majority carrier concentration peak regions 210 are sequentially arranged from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22, and the amplitude of the majority carrier concentration peak, i.e., the P-type impurity peak, in the majority carrier concentration peak region 210 decreases from the side of the drift region 21 close to the substrate to the side of the drift region 21 close to the body region 22. The majority carrier concentration peak with the largest amplitude is located on the side of the drift region 21 close to the substrate 1, and the majority carrier concentration peak with the smallest amplitude is located on the side of the drift region 21 close to the body region 22.

[0146] S360: forming a drain on a side of the substrate away from the semiconductor body.

[0147] Specifically, Fig.14 As shown, a drain 5 is formed on a side of the substrate 1 away from the semiconductor body 2 .

[0148] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0149] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A shielded gate MOSFET device, characterized in that: include: substrate; A semiconductor body; the semiconductor body is located on one side of the substrate, the semiconductor body includes a drift region, a body region and a first active region; the drift region is located on a side of the semiconductor body close to the substrate; the body region is located on a side of the drift region away from the substrate, and the first active region is located on a side of the body region away from the substrate; along a first direction, the drift region includes at least three majority carrier concentration peak regions; along the first direction, the peak values ​​of the majority carrier concentrations corresponding to at least three of the majority carrier concentration peak regions decrease gradually; along a second direction, first grooves are arranged on both sides of the semiconductor body; the first direction is a direction from the substrate to the semiconductor body, and the second direction is a direction perpendicular to the thickness of the substrate; A gate structure, the gate structure is located in the first groove, the gate structure includes a control gate and a shielding gate, and along the first direction, the shielding gate and the control gate are arranged at intervals; A source structure, the source structure is located at a side of the semiconductor body away from the substrate; the source structure is in contact with the first active region; A drain is located at a side of the substrate away from the semiconductor body.

2. The shielded gate MOSFET device according to claim 1, characterized in that: Along the first direction, the majority carrier concentration in the majority carrier concentration peak region shows a trend of first increasing and then decreasing.

3. The shielded gate MOSFET device according to claim 1, characterized in that: Along the first direction, the drift region includes a first majority carrier concentration peak region, a second majority carrier concentration peak region and a third majority carrier concentration peak region; The first multi-carrier concentration peak region is located on a side of the drift region close to the substrate, a side of the first multi-carrier concentration peak region close to the substrate is flush with a side of the first groove close to the substrate, the second multi-carrier concentration peak region is located on a side of the first multi-carrier concentration peak region away from the substrate, and the third multi-carrier concentration peak region is located on a side of the second multi-carrier concentration peak region away from the substrate; the peak values ​​of the multi-carrier concentrations corresponding to the first multi-carrier concentration peak region, the second multi-carrier concentration peak region and the third multi-carrier concentration peak region show a decreasing trend.

4. The shielded gate MOSFET device according to claim 1, characterized in that: The lateral electric field generated between the shielding gate and the drift region completely depletes all majority carriers at the corresponding peak value of the majority carrier concentration in the majority carrier concentration peak region.

5. The shielded gate MOSFET device according to claim 1, characterized in that: The conductivity types of the substrate, the drift region and the first active region include N type, and the conductivity type of the body region includes P type; Alternatively, the conductivity types of the substrate, the drift region, and the first active region include P type, and the conductivity type of the body region includes N type.

6. The shielded gate MOSFET device according to claim 5, characterized in that: When the conductivity types of the substrate, the drift region and the first active region include N-type, and the conductivity type of the body region includes P-type, along the first direction, the injection concentration of hydrogen ions at the peak values ​​of the corresponding majority carrier concentrations in at least three of the majority carrier concentration peak regions decreases.

7. The shielded gate MOSFET device according to claim 5, characterized in that: When the conductivity types of the substrate, the drift region and the first active region include P type, and the conductivity type of the body region includes N type, along the first direction, the injection concentration of hydrogen ions at the peak values ​​of the corresponding majority carrier concentrations in at least three of the majority carrier concentration peak regions increases gradually.

8. A method for preparing a shielded gate MOSFET device, characterized in that: include: providing a substrate; A semiconductor body is formed on one side of the substrate; the semiconductor body includes a drift region, a body region and a first active region; the drift region is located on a side of the semiconductor body close to the substrate; the body region is located on a side of the drift region away from the substrate, and the first active region is located on a side of the body region away from the substrate; along a first direction, the drift region includes at least three majority carrier concentration peak regions; along the first direction, the peak values ​​of the majority carrier concentrations corresponding to at least three of the majority carrier concentration peak regions decrease gradually; along a second direction, first grooves are arranged on both sides of the semiconductor body; the first direction is a direction from the substrate to the semiconductor body, and the second direction is a direction perpendicular to the thickness of the substrate; forming a gate structure in the first groove, the gate structure comprising a control gate and a shielding gate, and the shielding gate and the control gate are spaced apart along the first direction; forming a source structure on a side of the semiconductor body away from the substrate, wherein the source structure is in contact with the first active region; A drain is formed on a side of the substrate away from the semiconductor body.

9. The method for preparing a shielded gate MOSFET device according to claim 8, characterized in that: Forming a semiconductor body on one side of the substrate, forming a gate structure in the first groove, and forming a source structure on a side of the semiconductor body away from the substrate, comprising: The drift region is formed on one side of the substrate, wherein the drift region includes the first groove; the body region is formed on a side of the drift region away from the substrate; and the first active region is formed on a side of the body region away from the substrate; forming the gate structure in the first groove; forming the source structure on a side of the first active region away from the substrate; forming a passivation layer on a side of the source structure away from the substrate; the passivation layer comprises a second groove, and a vertical projection of the second groove on the substrate does not overlap with a vertical projection of the gate structure on the substrate; The drift region is implanted with hydrogen ions at least three times on a side of the passivation layer away from the substrate; the hydrogen ions implanted in the drift region are annealed; and the annealing temperature is less than 400°C.

10. The method for preparing a shielded gate MOSFET device according to claim 8, characterized in that: Forming a semiconductor body on one side of the substrate, forming a gate structure in the first groove, forming a source structure on a side of the semiconductor body away from the substrate, and forming a drain on a side of the substrate away from the semiconductor body, comprising: The drift region is formed on one side of the substrate, wherein the drift region includes the first groove; the body region is formed on a side of the drift region away from the substrate; and the first active region is formed on a side of the body region away from the substrate; forming the gate structure in the first groove; forming the source structure on a side of the first active region away from the substrate; Performing a thinning process on a side of the substrate away from the semiconductor body; Performing hydrogen ion implantation at least three times into the drift region on a side of the substrate away from the semiconductor body; performing annealing treatment on the hydrogen ions implanted into the drift region; the annealing temperature is less than 400° C.; A drain is formed on a side of the substrate away from the semiconductor body.

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