Semiconductor Structure and Method for Preparing the Same

Abstract

The present application relates to a semiconductor structure and a method for manufacturing the same, including: a substrate; a drift region of a first doping type, located within the substrate; a field dielectric layer structure, including a second dielectric layer and a first dielectric layer; the second dielectric layer is located on a surface of the drift region away from the substrate; the first dielectric layer includes a plurality of first dielectric portions, and the plurality of first dielectric portions are inserted into the second dielectric layer along a first direction; wherein, the first direction is perpendicular to the substrate and points to the direction of the field dielectric layer structure; a plurality of top regions of a second doping type are arranged at intervals in the drift region along the first direction, and the top regions are correspondingly arranged with the first dielectric portions; the first doping type is opposite to the second doping type. The first dielectric portion is inserted into the second dielectric layer, which can reduce the electric field strength at the sharp corners of the second dielectric layer and reduce the surface electric field. The top region and the drift region constitute a multiple RESURF structure, which can improve the surface electric field distribution of the device, promote the injection of carriers in the drift region, and reduce the on-resistance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technology, semiconductor devices are evolving towards lower on-resistance and higher breakdown voltage. For a laterally diffused metal oxide semiconductor (LDMOS), currently, the RESURF (reduced surface field) technology is used to increase the breakdown voltage, but the on-resistance and breakdown voltage of the LDMOS transistor still cannot meet the requirements. Summary of the Invention

[0003] Based on this, it is necessary to provide a semiconductor structure with high breakdown voltage and low on-resistance and a method for manufacturing the same.

[0004] In a first aspect, this application provides a semiconductor structure, including:

[0005] A substrate;

[0006] A drift region of a first doping type, located within the substrate;

[0007] A field dielectric layer structure, including a first dielectric layer and a second dielectric layer; the second dielectric layer is located on a surface of the drift region away from the substrate; the first dielectric layer includes a plurality of first dielectric portions, and the plurality of first dielectric portions are inserted into the second dielectric layer along a first direction; wherein, the first direction is perpendicular to the substrate and points towards the field dielectric layer structure;

[0008] A plurality of top regions of a second doping type, arranged at intervals along the first direction within the drift region, and the top regions are correspondingly arranged with the first dielectric portions; the first doping type is opposite to the second doping type.

[0009] In one embodiment, the second dielectric layer includes a plurality of second dielectric portions, and the first dielectric portions and the second dielectric portions are alternately arranged along the first direction.

[0010] In one embodiment, the ion doping concentration of the top region is greater than the ion doping concentration of the drift region.

[0011] In one embodiment, the semiconductor structure further includes:

[0012] A body region is located within the substrate. The body region and the drift region are arranged along a second direction, where the second direction is the same as the first direction, or the second direction is perpendicular to the first direction and perpendicular to the direction in which the substrate points to the field dielectric layer structure.

[0013] In one embodiment, the semiconductor structure further includes:

[0014] A source electrode, located within the body region;

[0015] A drain electrode, located within the drift region and on a side of the field dielectric layer structure away from the body region;

[0016] A gate electrode, located on a surface of the substrate close to the drift region, covering part of the body region and at least part of the second dielectric layer.

[0017] In one embodiment, the gate electrode further covers at least part of the first dielectric portion.

[0018] In one embodiment, the first dielectric layer includes silicon nitride.

[0019] In a second aspect, the present application further provides a method for manufacturing a semiconductor structure, including:

[0020] Providing a substrate;

[0021] Forming a drift region of a first doping type within the substrate;

[0022] Forming a second dielectric layer on a surface of the drift region away from the substrate;

[0023] Forming a plurality of grooves spaced apart along a first direction within the second dielectric layer; the first direction is perpendicular to the direction in which the substrate points to the second dielectric layer;

[0024] Using the second dielectric layer as an implantation blocking layer, and forming a plurality of top regions of a second doping type within the drift region based on the grooves; the first doping type is opposite to the second doping type;

[0025] Forming a first dielectric portion within the grooves; wherein, a plurality of the first dielectric portions form a first dielectric layer, and the first dielectric layer and the second dielectric layer form a field dielectric layer structure.

[0026] In one embodiment, the forming the first dielectric portion within the grooves includes:

[0027] Forming a first dielectric material layer within a plurality of the grooves and on a surface of the second dielectric layer away from the drift region;

[0028] Remove the first dielectric material layer on the surface of the side of the second dielectric layer away from the drift region to form a first dielectric portion, and the thickness of the first dielectric portion is less than the thickness of the second dielectric layer.

[0029] In one embodiment, forming the first dielectric portion in the trench further includes:

[0030] Perform a planarization process on the second dielectric layer to make the surface of the second dielectric layer flush with the surface of the first dielectric layer.

[0031] In the above semiconductor structure and its manufacturing method, the semiconductor structure includes a substrate, a drift region of a first doping type, a field dielectric layer structure, and a plurality of top regions of a second doping type. The drift region is located in the substrate, the field dielectric layer structure is located on the surface of the side of the drift region away from the substrate, and the top regions are arranged at intervals in the drift region along a first direction. The plurality of top regions of the second doping type and the drift region of the first doping type form a multi-RESURF structure, and a plurality of PN junctions are formed at the top of the drift region. The longitudinal depletion of the plurality of PN junctions improves the electric field distribution at the top of the drift region, enhances the depletion ability of the drift region, and reduces the surface electric field strength of the device. In addition, by increasing the doping concentration of the drift region, it is ensured that during the operation of the device, when the ions in the top region are inverted, the net doping concentration of the drift region can be maintained within a preset range (the preset range includes the expected value of the net doping concentration and the allowable error range). The increase in the doping concentration of the drift region can also reduce the on-resistance of the device. Through the mutual cooperation of technical features such as forming a multi-RESURF structure by the top region and the drift region and increasing the doping concentration of the drift region, while reducing the surface electric field strength of the device, the on-resistance of the device is also reduced. Further, the field dielectric layer structure includes a second dielectric layer and a first dielectric layer. The first dielectric layer includes a plurality of first dielectric portions, and the plurality of first dielectric portions are inserted into the second dielectric layer along the first direction. Compared with the structure with only the second dielectric layer, since the dielectric constant of the first dielectric layer is higher than that of the second dielectric layer, the high-dielectric-constant material is more easily polarized by the electric field and weakens the electric field strength. Therefore, the first dielectric layer can improve the electric field at the sharp corners of the second dielectric layer and further reduce the surface electric field strength of the device. The top regions are correspondingly arranged with the first dielectric portions. In this way, when forming the top regions, the second dielectric layer can be used as an implantation blocking layer, and there is no need to design an additional photomask, reducing the manufacturing cost. Description of the Drawings

[0032] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0033] Figure 1 One of the schematic structural diagrams of the semiconductor structure provided in an embodiment;

[0034] Figure 2 Another one of the schematic structural diagrams of the semiconductor structure provided in an embodiment;

[0035] Figure 3 The third one of the schematic structural diagrams of the semiconductor structure provided in an embodiment;

[0036] Figure 4 The schematic flow diagram of the manufacturing method of the semiconductor structure provided in an embodiment;

[0037] Figure 5 The schematic structural diagram of the structure obtained in step S300 of the manufacturing method of the semiconductor structure provided in an embodiment;

[0038] Figure 6 The schematic structural diagram of the structure obtained in step S400 of the manufacturing method of the semiconductor structure provided in an embodiment;

[0039] Figure 7 The schematic structural diagram of the structure obtained in step S500 of the manufacturing method of the semiconductor structure provided in an embodiment;

[0040] Figure 8 The schematic structural diagram of the structure obtained in step S610 of the manufacturing method of the semiconductor structure provided in an embodiment;

[0041] Figure 9 The schematic structural diagram of the structure obtained in step S620 of the manufacturing method of the semiconductor structure provided in an embodiment;

[0042] Figure 10 The schematic structural diagram of the structure obtained in step S600 of the manufacturing method of the semiconductor structure provided in an embodiment.

[0043] Explanation of reference numerals:

[0044] 100 - Substrate, 200 - Drift region, 300 - Field dielectric layer structure, 310 - Second dielectric layer, 311 - Trench, 320 - First dielectric layer, 321 - First dielectric material layer, 400 - Top region, 500 - Body region, 600 - Source electrode, 700 - Drain electrode, 800 - Gate electrode, 900 - Substrate end. Detailed implementation manners

[0045] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0047] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be referred to as the second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0048] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0049] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has / including", etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0050] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, and such variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Thus, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0051] In one embodiment, referring to Figure 1 、 Figure 2 or Figure 3 , the present application provides a semiconductor structure, including a substrate 100, a drift region 200 of a first doping type, a field dielectric layer structure 300, and a plurality of top regions 400 of a second doping type. The first doping type is opposite to the second doping type.

[0052] The material of the substrate 100 can be any suitable substrate material known in the art, for example, at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors, etc., or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or can also be double-sided polished wafers (DSP), or can also be a ceramic substrate, quartz or glass substrate, etc., and this embodiment is not limited herein.

[0053] The drift region 200 is located within the substrate 100. The surface of the drift region 200 is flush with the surface of the substrate 100. The drift region 200 can be an N-type drift region or a P-type drift region.

[0054] The field dielectric layer structure 300 includes a second dielectric layer 310 and a first dielectric layer 320. The second dielectric layer 310 is located on the surface of the drift region 200 away from the substrate 100. The first dielectric layer 320 includes a plurality of first dielectric portions, and the plurality of first dielectric portions are inserted into the second dielectric layer 310 along a first direction. Wherein, the first direction is perpendicular to the substrate 100 and points to the direction of the field dielectric layer structure 300. The extension length of the first dielectric portion in a third direction may be less than or equal to the extension length of the second dielectric layer 310, and the third direction is perpendicular to the first direction. As Figure 1 shown, the first direction may be the OY direction, and the third direction is the OX direction; as Figure 2 or Figure 3 shown, the first direction may be the OX direction, and the third direction may be the OY direction. The second dielectric layer 310 may be a field oxide layer, and the material of the second dielectric layer 310 may be one or a combination of silicon oxide, silicon carbon oxide, etc. The dielectric constant of the first dielectric layer 320 is higher than that of the second dielectric layer 310. Exemplarily, the first dielectric layer 320 may be nitride. In the XOY plane, the cross-sectional shape of the first dielectric layer 320 may be fence-shaped, serrated, diamond-shaped, etc., and the embodiments of the present application do not limit this here.

[0055] A plurality of top regions 400 of the second doping type are arranged at intervals along the first direction in the drift region 200, and the top regions 400 are correspondingly arranged with the first dielectric portions. The surface of the top region 400 away from the substrate 100 is flush with the surface of the drift region 200. In the XOY plane, the cross-sectional shape of the top region 400 is the same as that of the first dielectric portion, and may be fence-shaped, serrated, diamond-shaped, etc.

[0056] In an embodiment of the present application, the semiconductor structure includes a substrate 100, a drift region 200 of a first doping type, a field dielectric layer structure 300, and a plurality of top regions 400 of a second doping type. The drift region 200 is located within the substrate 100. The field dielectric layer structure 300 is located on a surface of the drift region 200 away from the substrate 100. The top regions 400 are arranged at intervals in the drift region 200 along a first direction. The plurality of top regions 400 of the second doping type and the drift region 200 of the first doping type form a multi-RESURF structure, forming a plurality of PN junctions at the top of the drift region 200. The longitudinal depletion of the plurality of PN junctions is utilized to improve the electric field distribution at the top of the drift region 200, enhance the depletion ability of the drift region 200, and reduce the surface electric field strength of the device. In addition, by increasing the doping concentration of the drift region 200, it is ensured that when the ions in the top region 400 are inverted during the operation of the device, the net doping concentration of the drift region 400 can be maintained within a preset range. The increase in the doping concentration of the drift region 200 can also reduce the on-resistance of the device. Through the mutual cooperation of technical features such as forming a multi-RESURF structure by the top region 400 and the drift region 200, and increasing the doping concentration of the drift region 200, while reducing the surface electric field strength of the device, the on-resistance of the device is also reduced. Further, the field dielectric layer structure 300 includes a second dielectric layer 310 and a first dielectric layer 320. The first dielectric layer 320 includes a plurality of first dielectric parts. The plurality of first dielectric parts are inserted into the second dielectric layer 310 along the first direction. Compared with the structure having only the second dielectric layer 310, since the dielectric constant of the first dielectric layer 320 is higher than that of the second dielectric layer 310, the high-dielectric-constant material is more easily polarized by the electric field, weakening the electric field strength. Therefore, the first dielectric layer 320 can improve the electric field at the sharp corners of the second dielectric layer 310, further reducing the surface electric field strength of the device. The top region 400 is correspondingly arranged with the first dielectric part. In this way, when forming the top region 400, the second dielectric layer 310 can be used as an implantation blocking layer, and there is no need to additionally design a photomask, reducing the manufacturing cost.

[0057] In one embodiment, the second dielectric layer 310 includes a plurality of second dielectric parts. The first dielectric parts and the second dielectric parts are alternately arranged along the first direction. Exemplarily, as Figure 1 shown, the first dielectric parts and the second dielectric parts are alternately arranged along the OY direction; as Figure 2 shown, the first dielectric parts and the second dielectric parts are alternately arranged along the OX direction. The arrangement manner of the first dielectric parts and the second dielectric parts can be set according to the actual service scenario, changing the layout manner of the top region 400 in the drift region 200, so as to improve the electric field strength distribution in different directions.

[0058] In one embodiment, the ion doping concentration in the top region 400 is greater than that in the drift region 200, which makes the top region 400 have a second doping type. The specific values of the ion doping concentration in the top region 400 and the ion doping concentration in the drift region 200 can be reasonably set according to the actual service scenario, and the embodiments of the present application do not limit this here.

[0059] In one embodiment, please continue to refer to Figure 1 、 Figure 2 or Figure 3 , the semiconductor structure further includes a body region 500. The body region 500 is located in the substrate 100. The body region 500 and the drift region 200 are arranged along a second direction, and the second direction is the same as the first direction, or the second direction is perpendicular to the first direction and perpendicular to the direction in which the substrate 100 points to the field dielectric layer structure 300. The second direction can be the OY direction. When forming an NMOS transistor, the ion doping type of the body region 500 is P-type; when forming a PMOS transistor, the doping type of the body region 500 is N-type.

[0060] Furthermore, the semiconductor structure further includes a source electrode 600, a drain electrode 700, and a gate electrode 800. The source electrode 600 is located in the body region 500. The drain electrode 700 is located in the drift region 200 and on the side of the field dielectric layer structure 300 away from the body region 500. The gate electrode 800 is located on the surface of the substrate 100 close to the drift region 200, covering part of the body region 500 and at least part of the second dielectric layer 310. Taking an NMOS transistor as an example, both the source electrode 600 and the drain electrode 700 are N-type doped regions. The source electrode 600 is located in the P-type body region 500, the drain electrode 700 is located in the N-type drift region 200, a P-type top region 400 is provided in the N-type drift region 200 between the source electrode 600 and the drain electrode 700, and a field dielectric layer structure 300 composed of the second dielectric layer 310 and the first dielectric layer 320 is provided on the N-type drift region 200 between the source electrode 600 and the drain electrode 700. The gate electrode 800 is located on the surface of the substrate 100 close to the N-type drift region 200, covering part of the P-type body region 500 and at least part of the second dielectric layer 310. The material of the gate electrode 800 can be polysilicon, a metal gate, etc.

[0061] In addition, a substrate end 900 (bulk) is further provided in the body region 500. The substrate end 900 is connected to the source electrode 600, and the ion doping type of the substrate end 900 is opposite to that of the source electrode 600.

[0062] In this embodiment, the field dielectric layer structure 300 between the gate electrode 800 and the drift region 200 can prevent direct current flow between the gate electrode 800 and the drift region 200, playing a role of isolation and protection. In addition, the gate electrode 800 in the embodiments of the present application can also play the role of a field plate, which can improve the electric field distribution and breakdown voltage performance of the device. In some embodiments, the gate electrode 800 also covers at least part of the first dielectric portion.

[0063] In one embodiment, referring to Figure 4 , the present application further provides a method for manufacturing a semiconductor structure, including steps S100 - S600.

[0064] S100, provide a substrate.

[0065] S200, form a drift region of a first doping type in the substrate.

[0066] Referring to Figure 5 , a drift region 200 of a first doping type can be formed in the substrate 100 through doping process, diffusion process, etc.

[0067] S300, form a second dielectric layer on a surface of the drift region away from the substrate.

[0068] Continuing to refer to Figure 5 , a second dielectric layer 310 can be formed on a surface of the drift region 200 away from the substrate 100 through a deposition process, such as an Atomic Layer Deposition (ALD) process, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or a Low Pressure Chemical Vapor Deposition (LPCVD) process, etc. The material of the second dielectric layer 310 can be one or a combination of silicon oxide or silicon oxycarbide.

[0069] S400, form a plurality of trenches spaced along a first direction in the second dielectric layer; the first direction is perpendicular to the direction from the substrate pointing to the second dielectric layer.

[0070] Referring to Figure 6 , a plurality of trenches 311 spaced along a first direction can be formed in the second dielectric layer 310 by using a dry etching process, a wet etching process, or a combination of dry etching and wet etching processes. The first direction can be the OX direction, the OY direction, or other directions. The extension length of the trenches 311 in a third direction can be the same as or less than the extension length of the second dielectric layer 310. The cross-sectional shape of the trenches 311 can be fence-shaped, serrated, or diamond-shaped, etc. The formed trenches 311 can be used to locate the positions of the top region 400 of the second doping type and the first dielectric part formed subsequently. In addition, each part of the second dielectric layer separated by the trenches 311 can be used as a second dielectric part.

[0071] In S500, the second dielectric layer is used as an implantation blocking layer, and multiple top regions of the second doping type are formed in the drift region based on the trench. The first doping type is opposite to the second doping type.

[0072] Please refer to Figure 7 , the second dielectric layer 310 can be used as an implantation blocking layer, and ion implantation is performed on the drift region 200 based on the trench 311 to form multiple top regions 400 of the second doping type in the drift region 200. The concentration, depth, etc. of the ion implantation can be reasonably set according to the actual business scenario, and the embodiments of the present application do not limit this here.

[0073] In S600, a first dielectric part is formed in the trench. Among them, multiple first dielectric parts form a first dielectric layer, and the first dielectric layer and the second dielectric layer form a field dielectric layer structure.

[0074] Please refer to Figure 10 , a deposition process can be used to form the first dielectric part in the trench. The dielectric constant of the first dielectric part is higher than that of the second dielectric layer 310. Exemplarily, the first dielectric part can be silicon nitride (Nitride).

[0075] In an embodiment of the present application, by providing a substrate 100, a drift region 200 of a first doping type is formed in the substrate 100, a second dielectric layer 310 is formed on a surface of the drift region 200 away from the substrate 100, a plurality of grooves spaced along a first direction are formed in the second dielectric layer 310, the second dielectric layer 310 is used as an implantation blocking layer, and based on the grooves, a plurality of top regions 400 of a second doping type are formed in the drift region 200. The plurality of top regions 400 of the second doping type and the drift region 200 of the first doping type form a multi-RESURF structure, a plurality of PN junctions are formed at the top of the drift region 200, the longitudinal depletion of the plurality of PN junctions is used to improve the electric field distribution at the top of the drift region 200, the depletion ability of the drift region 200 is improved, and the surface electric field strength of the device is reduced. By increasing the doping concentration of the drift region 200, it is ensured that during the operation of the device, when the ions in the top region 400 are inverted, the net doping concentration of the drift region 400 can be maintained within a preset range. The increase in the doping concentration of the drift region 400 can also reduce the on-resistance of the device. Through the mutual cooperation of technical features such as forming a multi-RESURF structure by the top region 400 and the drift region 200, and increasing the doping concentration of the drift region 200, while reducing the surface electric field strength of the device, the on-resistance of the device is also reduced. In addition, using the second dielectric layer 310 as an implantation blocking layer does not require an additional mask, which can reduce the manufacturing cost; further, a first dielectric portion is formed in the grooves, wherein the plurality of first dielectric portions form a first dielectric layer 320, and the first dielectric layer 320 and the second dielectric layer 310 form a field dielectric layer structure 300. Since the dielectric constant of the first dielectric layer 320 is higher than that of the second dielectric layer 310, the high-dielectric-constant material is more easily polarized by the electric field, weakening the electric field strength. Therefore, the first dielectric layer 320 can improve the electric field at the sharp corners of the second dielectric layer 310 and further reduce the surface electric field strength of the device.

[0076] In one embodiment, forming a first dielectric portion in the grooves includes steps S610 - S620.

[0077] S610, forming a first dielectric material layer in the plurality of grooves and on a surface of the second dielectric layer away from the drift region.

[0078] Please participate Figure 8, a deposition process can be adopted, such as an Atomic Layer Deposition (ALD) process, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or a Low Pressure Chemical Vapor Deposition (LPCVD) process, etc., to deposit a first dielectric material on the inner sides of multiple trenches 311 and on the surface of the second dielectric layer 310 away from the drift region 200, so as to form a first dielectric material layer 321.

[0079] S620, remove the first dielectric material layer on the surface of the second dielectric layer away from the drift region to form a first dielectric part.

[0080] Please participate Figure 9 , a wet cleaning process (such as cleaning with a hot phosphoric acid solution (H3PO4)) can be adopted to remove the first dielectric material layer 321 on the surface of the second dielectric layer 310 away from the drift region 200, so as to form a first dielectric part. The thickness of the first dielectric part is less than the thickness of the second dielectric layer 310.

[0081] In this embodiment, since the thickness of the first dielectric part is less than the thickness of the second dielectric layer 310, the first dielectric layer 320 and the second dielectric layer 310 form a stepped field dielectric layer structure 300, such that the subsequent formed gate 800 extending above the field dielectric layer structure 300 is a stepped structure. The stepped field plate formed by the gate 800 and the field dielectric layer structure 300 can avoid the formation of a local peak electric field in the drift region 200, make the electric field distribution in the drift region 200 more uniform, reduce the surface electric field of the device, and can also avoid the breakdown of the gate oxide layer.

[0082] In some embodiments, forming a first dielectric part in the trench further includes a step of planarizing the second dielectric layer to make the surface of the second dielectric layer flush with the surface of the first dielectric layer.

[0083] Please refer to Figure 10 , a Chemical Mechanical Polishing (CMP) process can be adopted to planarize the second dielectric layer 310 to make the surface of the second dielectric layer 310 flush with the surface of the first dielectric layer 320, which can improve the flatness of the surface of the field dielectric layer structure 300 composed of the first dielectric layer 320 and the second dielectric layer 310.

[0084] It should be understood that although Figure 4The steps in the flowchart are shown in the order illustrated, but these steps are not necessarily executed in that order. Unless specifically stated herein, there is no strict order requirement for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 4 at least some of the steps in Figure 4 may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0085] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0086] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0087] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A drift region of a first doping type, located in the substrate; A field dielectric layer structure, comprising a first dielectric layer and a second dielectric layer; The second dielectric layer is located on a surface of the drift region away from the substrate; the first dielectric layer includes a plurality of first dielectric portions, and the plurality of first dielectric portions are inserted into the second dielectric layer along a first direction; wherein the first direction is perpendicular to a direction from the substrate to the field dielectric layer structure; the dielectric constant of the first dielectric layer is higher than the dielectric constant of the second dielectric layer; a plurality of second doping type top regions, arranged in the drift region at intervals along a first direction, the top regions being arranged corresponding to the first dielectric portion, and projections of the top regions on the substrate coincide with projections of the first dielectric portion on the substrate; the first doping type is opposite to the second doping type; a body region, located in the substrate, wherein the body region and the drift region are arranged along a second direction, wherein the second direction is the same as the first direction, or the second direction is perpendicular to the first direction and perpendicular to a direction from the substrate to the field dielectric layer structure; A source electrode located in the body region; A drain electrode is located in the drift region and on a side of the field dielectric layer structure away from the body region; The gate is located on a surface of the substrate near the drift region, covering a portion of the body region, a portion of the second dielectric layer and a portion of the first dielectric portion, and the remaining second dielectric layer and the remaining first dielectric portion are not covered by the gate.

2. The semiconductor structure according to claim 1, characterized in that: The second dielectric layer includes a plurality of second dielectric portions, and the first dielectric portions and the second dielectric portions are alternately arranged along a first direction.

3. The semiconductor structure according to claim 1, characterized in that: The ion doping concentration of the top region is greater than the ion doping concentration of the drift region.

4. The semiconductor structure according to claim 1, characterized in that: The surfaces of the first dielectric layer and the second dielectric layer are flush.

5. The semiconductor structure according to claim 1, characterized in that: The cross-sectional shape of the top region is one of fence-shaped, sawtooth-shaped or diamond-shaped.

6. The semiconductor structure according to claim 1, characterized in that The first dielectric layer includes silicon nitride.

7. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a drift region of a first doping type in the substrate; forming a second dielectric layer on a surface of the drift region away from the substrate; forming a plurality of grooves spaced apart along a first direction in the second dielectric layer; The first direction is perpendicular to the direction of the substrate pointing to the second dielectric layer; The second dielectric layer is used as an injection blocking layer, and a plurality of top regions of a second doping type are formed in the drift region based on the trench; the first doping type is opposite to the second doping type; A first dielectric portion is formed in the groove; wherein the first dielectric portions form a first dielectric layer, and the first dielectric layer and the second dielectric layer form a field dielectric layer structure; the dielectric constant of the first dielectric layer is higher than the dielectric constant of the second dielectric layer; and the projection of the top region on the substrate coincides with the projection of the first dielectric portion on the substrate; A body region is formed in the substrate, wherein the body region and the drift region are arranged along a second direction, wherein the second direction is the same as the first direction, or the second direction is perpendicular to the first direction and perpendicular to a direction from the substrate to the field dielectric layer structure; forming a source electrode in the body region; forming a drain in the drift region, wherein the drain is located on a side of the field dielectric layer structure away from the body region; A gate is formed on a surface of the substrate close to the drift region, the gate covers part of the body region, part of the second dielectric layer and part of the first dielectric portion, and the remaining second dielectric layer and the remaining first dielectric portion are not covered by the gate.

8. The method according to claim 7, characterized in that The forming of the first dielectric portion in the groove comprises: forming a first dielectric material layer in the plurality of trenches and on a surface of the second dielectric layer away from the drift region; The first dielectric material layer on a surface of the second dielectric layer away from the drift region is removed to form a first dielectric portion, wherein the thickness of the first dielectric portion is smaller than the thickness of the second dielectric layer.

9. The method according to claim 8, characterized in that The forming of the first dielectric portion in the groove further comprises: The second dielectric layer is planarized to make the second dielectric layer flush with the surface of the first dielectric layer.

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