Quasi-super junction plane gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a quasi-super junction planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, forming a plurality of N-type body regions and a plurality of diffusion regions, and forming a P-type well region, an N-type source region and a current sharing layer; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; the preparation method comprises the following steps of: re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that a quasi-super junction structure and a current sharing layer are constructed in the device, and the voltage endurance capability, the gate reliability and the conduction capability of the device can be effectively improved.

Description

Technical Field

[0001] The invention relates to a quasi-super junction planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, different fields have different requirements for device performance, but the overall requirements are higher voltage resistance, lower on-resistance, faster switching speed and higher reliability (including gate reliability, drain voltage impact reliability, short circuit reliability, etc.); and silicon carbide VDMOS constructs an insulating dielectric region directly below the planar gate, and the N-type drift region directly below the P-type well region and the gate metal layer naturally forms a space charge region, but as the distance from the P-type well region increases, the depth of the space charge region decreases, and it is more difficult to withstand the drain voltage. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a quasi-superjunction planar gate silicon carbide VDMOS and a preparation method thereof, in which a quasi-superjunction structure and a current equalizing layer are constructed inside the device, which can effectively improve the voltage resistance, gate reliability and conduction capability of the device.

[0004] In a first aspect, the present invention provides a method for preparing a quasi-superjunction planar gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form through holes, and implanting ions into the drift layer to form a plurality of N-type body regions;

[0007] Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form through holes, and performing ion implantation into the drift layer to form multiple diffusion regions;

[0008] Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region;

[0009] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region;

[0010] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a current balancing layer;

[0011] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer;

[0012] Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

[0013] Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0014] In a second aspect, the present invention provides a quasi-super junction planar gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a quasi-super junction planar gate silicon carbide VDMOS described in the first aspect.

[0015] The advantages of the present invention are:

[0016] 1. The present invention constructs a quasi-superjunction device structure, specifically including a P-type diffusion region and an N-type body region that are laterally cross-distributed, and transforms the vertically distributed electric field into a horizontally and vertically combined electric field distribution, thereby improving the voltage resistance of the device;

[0017] Second, a current-balancing layer is constructed directly below the planar gate, which increases the doping concentration of the JFET region of the device and can effectively reduce the JFET resistance and overall on-resistance of the device;

[0018] 3. The gate of the device adopts a convex structure, and the thickness of the gate dielectric is increased above the N-type current balancing layer, which can effectively improve the gate reliability of the N-type current balancing layer area and improve the ability to resist drain voltage shock. At the same time, the thickness of the gate dielectric remains unchanged from the N-type source area to the JFET area (including the N-type current balancing layer directly below the gate and the N-type drift layer on its left and right sides), and does not affect the gate control capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0020] Figure 1 The schematic diagram of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention is shown in FIG.

[0021] Figure 2 A cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention Figure 1 .

[0022] Figure 3 A cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention Figure 2 .

[0023] Figure 4A cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention Figure 3 .

[0024] Figure 5 A cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention Figure 4 .

[0025] Figure 6 A cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention Figure 5 .

[0026] Figure 7 A cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention Figure 6 .

[0027] Figure 8 A cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention Figure 7 .

[0028] Fig. 9 A cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention Figure 8 .

[0029] Fig.10 A cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention Figure 9 .

[0030] Fig.11 A cross-sectional view of the process of a quasi-superjunction planar gate silicon carbide VDMOS of the present invention Figure 10 . DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0034] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] like Figures 1 to 11 As shown, the embodiment of the present application provides a method for preparing a quasi-superjunction planar gate silicon carbide VDMOS, comprising the following steps:

[0037] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 7; epitaxially growing the side of the silicon carbide substrate 1 to form a drift layer 2;

[0038] Step 2, forming a barrier layer 8 on the drift layer 2, etching the barrier layer 8 to form through holes, and performing ion implantation into the drift layer 2 to form a plurality of N-type body regions 21;

[0039] Step 3, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form through holes, and performing ion implantation into the drift layer 2 to form a plurality of diffusion regions 22;

[0040] Step 4, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation into the drift layer 2 to form a P-type well region 3;

[0041] Step 5, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation into the P-type well region 3 to form an N-type source region 31;

[0042] Step 6, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation into the drift layer 2 to form a current balancing layer 231, wherein the current balancing layer 231 is located in the protruding portion 23 of the drift layer 2;

[0043] Step 7, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and depositing to form a first insulating dielectric layer 42; removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and depositing to form a second insulating dielectric layer 43; the gate dielectric layer 4 includes the first insulating dielectric layer 42 and the second insulating dielectric layer 43; the width of the second insulating dielectric layer 43 is equal to the width of the current-balancing layer 231; the second insulating layer 43 is the protrusion 41 of the gate dielectric layer 4;

[0044] Step 8, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, depositing metal to form a gate metal layer 5, wherein the gate metal layer 5 is an inverted concave shape;

[0045] Step 9, remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, deposit metal to form a source metal layer 6, remove the barrier layer 8, and complete the preparation.

[0046] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0047] Silicon carbide substrate 1,

[0048] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, and a plurality of N-type body regions 21 are provided at the lower part of the drift layer 2; a plurality of P-type diffusion regions 22 are provided at the upper part of the drift layer 2, and the lower side of each of the N-type body regions 21 is connected to the upper side of the silicon carbide substrate 1, and a convex portion 23 is provided on the drift layer 2, and a current equalizing layer 231 is provided in the convex portion 23;

[0049] A P-type well region 3, wherein the lower side of the P-type well region 3 is connected to the upper side of the drift layer 2 and the upper side of the P-type diffusion region 22, and the inner side of the P-type well region 3 is connected to the outer side of the protrusion 23; an N-type source region 31 is provided in the P-type well region 4;

[0050] A gate dielectric layer 4, wherein the gate dielectric layer 4 is respectively connected to the P-type well region 3, the drift layer 2 and the current balancing layer 231;

[0051] A gate metal layer 5, wherein the gate metal layer 5 is connected to the gate dielectric layer 4;

[0052] A source metal layer 6, wherein the source metal layer 6 is connected to the P-type well region 3 and the N-type source region 31 respectively;

[0053] and a drain metal layer 7 , wherein the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1 .

[0054] In this embodiment, preferably, the gate dielectric layer 4 is provided with a protrusion 41, the width of the protrusion 41 is equal to the width of the current equalizing layer 231, and the gate metal layer 5 is an inverted concave shape; the thickness of the N-type body region 21 is 50% of the thickness of the drift layer; the thickness of the P-type diffusion region 22 is 30% of the thickness of the drift layer 2; the N-type body region 21 and the P-type diffusion region 22 are arranged at intervals in the vertical direction, that is, the diffusion region 22 is not directly above the N-type body region 21; the doping concentration of the N-type body region 21 is greater than the doping concentration of the drift layer 2, and the doping concentration of the P-type diffusion region 22 is greater than the doping concentration of the N-type body region 21.

[0055] In another embodiment of the present invention, the silicon carbide substrate 1, the drift layer 2 and the current balancing layer 231 are all N-type; the diffusion region 22 is P-type; the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e17cm -3 The doping concentration of the N-type current balancing layer 231 is 0.8-1.2e18cm -3 , the doping concentration of the N-type body region 21 is 5-8e17cm -3 , the doping concentration of the P-type diffusion region 22 is 0.8-2e18 cm -3 , the doping concentration of P-type well region 3 is 5-8e17 cm -3The gate dielectric layer 4 is silicon dioxide, and the doping concentration of the N-type source region 31 is 2-8e18cm -3 ;

[0056] The doping concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 7, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device; the function of the N-type current balancing layer 231 is to increase the doping concentration of the JFET region of the device, reduce the resistance of the JFET region of the device, and thereby reduce the on-resistance of the device; the N-type body region 21 is to transfer the potential of the drain upward, thereby forming a horizontally and vertically combined withstand voltage structure with the P-type diffusion region 22, thereby improving the withstand voltage of the device; the P-type well region 3 is to form the vertical withstand voltage structure of the device and the gate control structure of the device; the N-type source region 31 is to form a low-resistance ohmic contact with the source metal layer 6.

[0057] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, and the thickness of the N-type drift layer 2 is 10-30 μm. The thickness is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device. The thickness of the N-type body region 21 is 50% of the thickness of the N-type drift layer 2, which is to achieve the upward transfer of potential; the thickness of the P-type diffusion region 22 is 30% of the thickness of the N-type drift layer 2, which is to form a horizontal and vertical combined electric field distribution with the N-type body region 21, thereby realizing a structure that can withstand voltage in both the horizontal and vertical directions of the device, and improving the withstand voltage capability of the device; N-type The thickness of the current balancing layer 231 is 300nm, the thickness of the N-type source region 31 is 100nm, the thickness of the P-type well region 3 below the N-type source region 31 is 200nm, and the thickness of the P-type well region 3 is 300nm. This is to ensure the voltage resistance and gate control capability of the device. The gate dielectric thickness directly above the N-type current balancing layer 231 is 100nm, and the gate dielectric thickness in other areas is 50nm. This is to improve the reliability of the gate above the N-type source region. The thickness of the source metal layer 6 is 200nm, and the thickness of the gate metal layer 5 is 150nm.

[0058] The gate dielectric layer 4 of the present invention is convex-shaped and has the ability to withstand high voltage, which can effectively improve the gate's ability to withstand the impact of drain voltage and improve device reliability; the distance from the bottom of the P-type diffusion region 22 to the top of the N-type body 21 region is 20% of the thickness of the N-type drift layer, and the small thickness of the P-type diffusion region 22 is because the doping concentrations of the N-type drift layer 2 and the N-type body region 21 are both lower than the P-type diffusion layer 22, and the doping concentration relationship can ensure that the distribution of the space charge region during reverse withstand voltage will not affect the structure of the device's P-type well region 3; the P-type diffusion region 22 and the N-type body region 21 are cross-distributed, and the cross-distribution method allows the space charge region to diffuse upward and diffuse horizontally in the P-type diffusion region 22 and the N-type body region 21 during reverse withstand voltage, converting the vertically distributed electric field into a horizontally and vertically combined electric field distribution, constructing a quasi-super junction structure, thereby improving the device's withstand voltage capability;

[0059] An N-type current balancing layer 231 is constructed directly below the planar gate, which increases the doping concentration of the device JFET region, and can effectively reduce the JFET resistance and overall on-resistance of the device. The gate dielectric layer 4 of the device adopts a convex structure, and the thickness of the gate dielectric is increased above the N-type current balancing layer 231, which can effectively improve the gate reliability of the N-type current balancing layer 231 area and improve the ability to resist drain voltage shock. At the same time, the gate dielectric thickness from the N-type source region to the JFET region (including the N-type current balancing layer directly below the gate and the N-type drift layers on its left and right sides) remains unchanged, which does not affect the gate control ability of the device;

[0060] The device of this embodiment realizes a quasi-super junction structure to improve the voltage resistance of the device, the N-type current balancing layer 231 reduces the on-resistance of the device, and the convex gate dielectric improves the gate reliability of the device.

[0061] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a quasi-superjunction planar gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form through holes, and performing ion implantation into the drift layer to form a plurality of N-type body regions; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form through holes, and performing ion implantation into the drift layer to form multiple diffusion regions; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a current balancing layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a quasi-superjunction planar gate silicon carbide VDMOS according to claim 1, characterized in that: The step 7 is specifically as follows: removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a first insulating dielectric layer; removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a second insulating dielectric layer; the gate dielectric layer includes the first insulating dielectric layer and the second insulating dielectric layer; the width of the second insulating dielectric layer is equal to the width of the current equalizing layer, and the gate metal layer is an inverted concave shape.

3. The method for preparing a quasi-superjunction planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the N-type body region is 50% of the thickness of the drift layer.

4. The method for preparing a quasi-superjunction planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the P-type diffusion region is 30% of the thickness of the drift layer.

5. The method for preparing a quasi-superjunction planar gate silicon carbide VDMOS according to claim 1, characterized in that: The N-type body region and the P-type diffusion region are arranged at intervals in the vertical direction.

6. The method for preparing a quasi-superjunction planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the N-type body region is greater than the doping concentration of the drift layer, and the doping concentration of the P-type diffusion region is greater than the doping concentration of the N-type body region.

7. A quasi-superjunction planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods of claim 1 to claim 6.

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