Thin film transistors and electronic devices

Abstract

The application provides a thin film transistor and an electronic device; the thin film transistor is characterized in that: an effective part is arranged on the sidewall of a barrier layer, a first connecting part and a second connecting part are respectively in contact with a first ohmic contact layer and a second ohmic contact layer located above and below the barrier layer, the channel length can be controlled by the thickness and angle of the barrier layer, the channel length is reduced by using an existing process, the volume of the thin film transistor is reduced, and the mobility is improved; the second electrode is in contact with the second ohmic contact layer through the channel layer, so that even if the second ohmic contact layer is over-etched, the second electrode can still work normally with the second ohmic contact layer; and / or the first electrode is in contact with the first ohmic contact layer through the barrier layer or the first electrode is in contact with the first ohmic contact layer through the channel layer, so that even if the first ohmic contact layer is over-etched, the first electrode can still work normally with the first ohmic contact layer, the yield of the display panel is improved, and the size of the thin film transistor is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a thin film transistor and an electronic device. BACKGROUND

[0002] The integration of pixel driving circuit, gate driving circuit, source driving circuit, timing controller and other circuits on a glass substrate (system on glass, SOG) can greatly improve the integration of the display panel, reduce the dependence on integrated circuit chips, and reduce the cost. To realize SOG, the integration, maximum operating frequency and current density of the thin film transistor in the existing display panel need to be improved, which requires the thin film transistor to have a shorter channel length, higher mobility and smaller volume.

[0003] To reduce the channel length, the existing display device designs a thin film transistor with a vertical structure. The channel is deposited on the side of the protrusion, and the contact layers are arranged above and below the protrusion, so that the channel length is determined by the distance between the upper and lower contact layers and the angle of the protrusion. Therefore, the channel length can be controlled by controlling the thickness and angle of the protrusion. The thickness and angle of the protrusion are relatively easy to control in the existing process (can reach an accuracy of less than 1 micrometer), thereby reducing the channel length and improving the mobility. The above design requires two contact layers to extend beyond the channel to connect the source and drain layers. However, in the actual preparation process, it is found that it is difficult to preserve the two contact layers during etching of the channel, and the part of the contact layer extending beyond the channel is easily etched off during etching of the channel, resulting in that the thin film transistor cannot work normally, the yield of the thin film transistor is low, and the yield of the display panel is low.

[0004] Therefore, the existing display device has the technical problem of low yield of the display panel caused by etching off the contact layer during etching of the channel of the thin film transistor with a vertical structure. SUMMARY

[0005] The embodiments of the present application provide a thin film transistor and an electronic device to solve the technical problem of low yield of the display panel caused by etching off the contact layer during etching of the channel of the thin film transistor with a vertical structure in the existing display device.

[0006] The embodiments of the present application provide a thin film transistor, which comprises:

[0007] a substrate;

[0008] a first ohmic contact layer arranged on one side of the substrate;

[0009] a barrier layer arranged on the side of the first ohmic contact layer away from the substrate, the barrier layer comprising at least one sidewall;

[0010] a second ohmic contact layer, disposed on a side of the barrier layer away from the first ohmic contact layer;

[0011] a channel layer comprising a first connecting portion, a second connecting portion and an effective portion located on the sidewall, wherein the first connecting portion contacts the first ohmic contact layer, and the second connecting portion is disposed on the second ohmic contact layer;

[0012] a gate insulating layer, disposed on a side of the channel layer away from the second ohmic contact layer;

[0013] a gate layer, disposed on a side of the gate insulating layer away from the channel layer, wherein an orthographic projection of the gate layer in a direction perpendicular to the substrate covers the effective portion;

[0014] an interlayer insulating layer, disposed on a side of the gate layer away from the gate insulating layer;

[0015] a source-drain electrode layer, disposed on a side of the interlayer insulating layer away from the gate layer, the source-drain electrode layer comprising a first electrode and a second electrode;

[0016] Wherein, the second electrode passes through the channel layer and contacts the second ohmic contact layer;

[0017] and / or, the first electrode contacts the first ohmic contact layer through the barrier layer;

[0018] Alternatively, the first connection portion is provided on the first ohmic contact layer, and the first electrode passes through the channel layer and contacts the first ohmic contact layer.

[0019] In some embodiments, when the second electrode passes through the channel layer and contacts the second ohmic contact layer, at the contact surface between the second ohmic contact layer and the second connecting portion, the upper surface of the second ohmic contact layer coincides with the lower surface of the second connecting portion, and the slopes of the three side surfaces of the second ohmic contact layer that are not in contact with the effective portion are equal to the slope corresponding to the second connecting portion.

[0020] In some embodiments, at the contact surface between the first ohmic contact layer and the barrier layer, the upper surface of the first ohmic contact layer coincides with the lower surface of the barrier layer, and any side surface of the first ohmic contact layer has the same slope as the corresponding side surface of the barrier layer.

[0021] In some embodiments, a side surface of the first ohmic contact layer has the same slope as a side surface of the first connecting portion.

[0022] In some embodiments, the thin film transistor comprises a first connection hole, the first connection hole at least penetrating the interlayer insulating layer and the gate insulating layer, the first electrode being in contact with the first ohmic contact layer through the first connection hole.

[0023] In some embodiments, the first connection hole further penetrates the barrier layer; or the first connection hole penetrates the barrier layer and the first ohmic contact layer.

[0024] In some embodiments, the first connection hole further penetrates the first connection portion; or the first connection hole penetrates the first connection portion and the first ohmic contact layer.

[0025] In some embodiments, the thin film transistor comprises a second connection hole, the second connection hole at least penetrating the interlayer insulating layer, the gate insulating layer and the second connection portion, the second electrode being in contact with the second ohmic contact layer through the second connection hole.

[0026] In some embodiments, the second connection hole further penetrates the second connection portion.

[0027] In some embodiments, in the lateral direction, the width of the second connection portion is less than the width of the barrier layer, in the area of the barrier layer beyond the second connection portion, the first electrode is in contact with the first ohmic contact layer.

[0028] In some embodiments, the ratio of the ion doping concentration of the first ohmic contact layer to the ion doping concentration of the channel layer is greater than or equal to ten to the fifth power.

[0029] In some embodiments, the material of the channel layer comprises intrinsic silicon.

[0030] Meanwhile, the embodiments of the present application provide an electronic device, which comprises the thin film transistor according to any one of the above embodiments.

[0031] Beneficial effects: the application provides a thin film transistor and an electronic device; the thin film transistor comprises a substrate, a first ohmic contact layer, a barrier layer, a second ohmic contact layer, a channel layer, a gate insulating layer, a gate layer, an interlayer insulating layer and a source-drain layer, the first ohmic contact layer is arranged on one side of the substrate, the barrier layer is arranged on the side of the first ohmic contact layer away from the substrate, the barrier layer comprises at least one sidewall, the second ohmic contact layer is arranged on the side of the barrier layer away from the first ohmic contact layer, the channel layer comprises a first connecting part, a second connecting part and an effective part located on the sidewall, the first connecting part is in contact with the first ohmic contact layer, the second connecting part is arranged on the second ohmic contact layer, the gate insulating layer is arranged on the side of the channel layer away from the second ohmic contact layer, the gate layer is arranged on the side of the gate insulating layer away from the channel layer, the gate layer covers the effective part in the vertical projection direction of the substrate, the interlayer insulating layer is arranged on the side of the gate layer away from the gate insulating layer, the source-drain layer is arranged on the side of the interlayer insulating layer away from the gate layer, and the source-drain layer comprises a first electrode and a second electrode; wherein the second electrode is in contact with the second ohmic contact layer through the channel layer; and / or the first electrode is in contact with the first ohmic contact layer through the barrier layer; or the first connecting part is arranged on the first ohmic contact layer, and the first electrode is in contact with the first ohmic contact layer through the channel layer. By arranging the effective part on the sidewall of the barrier layer and arranging the first connecting part and the second connecting part to be in contact with the first ohmic contact layer and the second ohmic contact layer located above and below the barrier layer respectively, the channel length can be controlled by the thickness and angle of the barrier layer, the channel length can be reduced by using the existing process, the volume of the thin film transistor can be reduced, and the mobility can be improved; and by making the second electrode in contact with the second ohmic contact layer through the channel layer, even if the second ohmic contact layer is over-etched, the second electrode can still work normally with the second ohmic contact layer; and / or by making the first electrode in contact with the first ohmic contact layer through the barrier layer or the first electrode in contact with the first ohmic contact layer through the channel layer, even if the first ohmic contact layer is over-etched, the first electrode can still work normally with the first ohmic contact layer, the yield of the display panel is improved, and the size of the thin film transistor is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0032] The technical solutions and other beneficial effects of the application will become apparent from the following detailed description of the application, taken in conjunction with the accompanying drawings.

[0033] Figure 1 It is a perspective view of the existing display panel.

[0034] Figure 2 It is a B1-B2 cross-sectional view of the display panel in Figure 1

[0035] Figure 3 It is an A1-A2 cross-sectional view of the display panel in Figure 1

[0036] ​​Figure 4 A top view of a first film layer structure of a thin film transistor provided in an embodiment of the present application.

[0037] Figure 5 for Figure 4 An exploded view of the film layers of a thin-film transistor.

[0038] Figure 6 for Figure 4 A first B1-B2 cross-sectional view of the thin film transistor in FIG.

[0039] Figure 7 for Figure 4 A1-A2 cross-sectional view of the thin film transistor in FIG.

[0040] Figure 8 A top view of the second film layer structure of the thin film transistor provided in an embodiment of the present application.

[0041] Figure 9 for Figure 8 An exploded view of the film layers of a thin-film transistor.

[0042] Figure 10 for Figure 8 B1-B2 cross-sectional view of the thin film transistor in FIG.

[0043] Figure 11 for Figure 4 A second B1-B2 cross-sectional view of the thin film transistor in FIG.

[0044] Figure 12 for Figure 4 Schematic diagram of the structure of the thin film transistor corresponding to each step in the method for preparing the thin film transistor.

[0045] Figure 13 for Figure 8 Schematic diagram of the structure of the thin film transistor corresponding to each step in the method for preparing the thin film transistor. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0047] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0048] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0049] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0050] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0051] Figure 1 is a perspective view of an existing display panel. Figure 2 for Figure 1 B1-B2 cross-sectional view of the display panel, Figure 3 for Figure 1 A1-A2 cross-sectional view of the display panel.

[0052] like Figures 1 to 3 As shown, the position of the hole is indicated by reference numeral 23. The conventional vertical structure display panel includes a substrate 11, a light shielding metal 12, a buffer material 13, a first contact layer 14, a boss 15, a second contact layer 16, a channel 17, a first insulating layer 18, a gate 19, a second insulating layer 21 and a source and drain layer 22. Figure 2 As can be seen in the figure, by setting the channel 17 on the side of the boss 15 and setting the first contact layer 14 and the second contact layer 16 on the upper and lower sides of the boss 15, the channel length can be controlled by the thickness of the boss 15 and the angle of the boss 15. The thickness of the boss 15 can be easily controlled to less than 1 micron under the existing process, which makes the channel length smaller and improves the mobility. Figures 1 to 3 As can be seen, in order to connect the source and drain in the source-drain layer 22 to the first contact layer 14 and the second contact layer 16 respectively, it is necessary to retain the first contact layer 14 and the second contact layer 16 when etching the channel 17. The process is difficult and the first contact layer 14 and the second contact layer 16 are easily etched away when etching the channel 17, resulting in the source-drain layer 22 being unable to connect to the first contact layer 14 and the second contact layer 16. The yield of the thin-film transistor is low, and the yield of the display panel is low. Therefore, the existing display device has a technical problem that the contact layer is easily etched away when etching the channel of the vertical thin-film transistor, resulting in a low yield of the display panel.

[0053] In order to solve the above technical problems, the embodiments of the present application provide a thin film transistor and a display panel.

[0054] Figure 4 A top view of a first film layer structure of a thin film transistor provided in an embodiment of the present application. Figure 5 forFigure 4 An exploded view of the film layers of the thin film transistor in FIG. Figure 5 (a) in Figure 4 An exploded view of a first ohmic contact layer of a thin film transistor; Figure 5 (b) in Figure 4 An exploded view of a barrier layer of a thin film transistor in FIG.

[0055] Figure 5 (c) in Figure 4 An exploded view of a second ohmic contact layer of a thin film transistor; Figure 5 (d) in Figure 4 An exploded view of the channel layer of the thin film transistor in FIG. Figure 5 (e) in Figure 4 Exploded view of the gate layer of a thin-film transistor in Figure 1. Figure 6 for Figure 4 A first B1-B2 cross-sectional view of the thin film transistor in FIG. Figure 7 for Figure 4 A1-A2 cross-sectional view of the thin film transistor in FIG. Figure 8 A top view of the second film layer structure of the thin film transistor provided in an embodiment of the present application. Figure 9 for Figure 8 An exploded view of the film layers of the thin film transistor in FIG. Figure 9 (a) in Figure 8 An exploded view of a first ohmic contact layer of a thin film transistor; Figure 9 (b) in Figure 8 An exploded view of a barrier layer of a thin film transistor in FIG. Figure 9 (c) in Figure 8 An exploded view of a second ohmic contact layer of a thin film transistor; Figure 9 (d) in Figure 8 An exploded view of the channel layer of the thin film transistor in FIG. Figure 9 (e) in Figure 8 Exploded view of the gate layer of a thin-film transistor in Figure 1. Figure 10 for Figure 8 B1-B2 cross-sectional view of the thin film transistor in FIG. Figure 8 The A1-A2 cross-sectional view of the thin film transistor in FIG. Figure 7 same. Figure 11 for Figure 4 A second B1-B2 cross-sectional view of the thin film transistor in FIG. Figure 12 for Figure 4 Schematic diagram of the structure of the thin film transistor corresponding to each step in the method for preparing the thin film transistor. Figure 13 for Figure 8 Schematic diagram of the structure of the thin film transistor corresponding to each step in the method for preparing the thin film transistor.

[0056] As Figures 4 to 10 shown, embodiments of the present application provide a thin film transistor, which comprises:

[0057] a substrate 31;

[0058] a first ohmic contact layer 34 disposed on one side of the substrate 31;

[0059] a barrier layer 35 disposed on a side of the first ohmic contact layer 34 away from the substrate 31, the barrier layer 35 comprising at least one sidewall (e.g. Figure 6 the sidewall on the left side of the middle);

[0060] a second ohmic contact layer 36 disposed on a side of the barrier layer 35 away from the first ohmic contact layer 34;

[0061] a channel layer 37 comprising a first connecting portion 371, a second connecting portion 372, and an effective portion 373 located on a sidewall, the first connecting portion 371 being in contact with the first ohmic contact layer 34, and the second connecting portion 372 being disposed on the second ohmic contact layer 36;

[0062] a gate insulating layer 38 disposed on a side of the channel layer 37 away from the second ohmic contact layer 36;

[0063] a gate layer 39 disposed on a side of the gate insulating layer 38 away from the channel layer 37, the gate layer 39 having a vertical projection on the substrate 31 covering the effective portion 373;

[0064] an interlayer insulating layer 41 disposed on a side of the gate layer 39 away from the gate insulating layer 38;

[0065] a source-drain layer 42 disposed on a side of the interlayer insulating layer 41 away from the gate layer 39, the source-drain layer 42 comprising a first electrode 421 and a second electrode 422;

[0066] wherein the second electrode 422 passes through the channel layer 37 and is in contact with the second ohmic contact layer 36;

[0067] and / or the first electrode 421 passes through the barrier layer 35 and is in contact with the first ohmic contact layer 34;

[0068] Alternatively, the first connecting portion 371 is disposed on the first ohmic contact layer 34, and the first electrode 421 passes through the channel layer 37 and is in contact with the first ohmic contact layer 34.

[0069] The embodiment of the present application provides a thin film transistor, by arranging the effective part on the sidewall of the barrier layer, and arranging the first connecting part and the second connecting part to contact the first ohmic contact layer and the second ohmic contact layer respectively, the channel length can be controlled by the thickness and the angle of the barrier layer, the channel length is reduced by using the existing process, the volume of the thin film transistor is reduced, and the mobility is improved; and by arranging the second electrode to contact the second ohmic contact layer through the channel layer, even if the second ohmic contact layer is over-etched, the second electrode can still work normally with the second ohmic contact layer; and / or by arranging the first electrode to contact the first ohmic contact layer through the barrier layer, or by arranging the first electrode to contact the first ohmic contact layer through the channel layer, even if the first ohmic contact layer is over-etched, the first electrode can still work normally with the first ohmic contact layer, the yield of the display panel is improved, and the size of the thin film transistor is reduced.

[0070] Specifically, the second electrode contacts the second ohmic contact layer through the channel layer; and / or the first electrode contacts the first ohmic contact layer through the barrier layer; or, the first connecting part is arranged on the second ohmic contact layer, and the first electrode contacts the first ohmic contact layer through the channel layer, and at least one of the following technical solutions is included:

[0071] The second electrode contacts the second ohmic contact layer through the channel layer, and the arrangement mode of the first electrode is not limited; the first electrode contacts the first ohmic contact layer through the barrier layer, and the arrangement mode of the second electrode is not limited; the first connecting part is arranged on the second ohmic contact layer, the first electrode contacts the first ohmic contact layer through the channel layer, and the arrangement mode of the second electrode is not limited; the second electrode contacts the second ohmic contact layer, and the first electrode contacts the first ohmic contact layer through the barrier layer; the second electrode contacts the second ohmic contact layer, and the first connecting part is arranged on the second ohmic contact layer, and the first electrode contacts the first ohmic contact layer through the channel layer.

[0072] Specifically, in Figure 4 and Figure 8 , the setting position of the via hole is indicated by a reference sign 43, and the film layers through which the via hole passes are subject to actual design, for example, in Figure 4 , one via hole passes through the interlayer insulation layer 41, the gate insulation layer 38, the channel layer 37 and the first ohmic contact layer 34, and the other via hole passes through the interlayer insulation layer 41, the gate insulation layer 38, the channel layer 37 and the second ohmic contact layer 36, and the arrangement mode of the via hole is specifically described in the following embodiment.

[0073] In some embodiments, as Figure 6As shown, when the second electrode 422 passes through the channel layer 37 and contacts the second ohmic contact layer 36, at the interface between the second ohmic contact layer 36 and the second connecting portion 372, the upper surface of the second ohmic contact layer 36 coincides with the lower surface of the second connecting portion 372, and the slopes of the three side surfaces of the second ohmic contact layer 36 not in contact with the effective portion 373 are equal to the slopes corresponding to the second connecting portion 372. By aligning the upper surface of the second ohmic contact layer with the lower surface of the second connecting portion and ensuring that the slopes of the three side surfaces of the second ohmic contact layer not in contact with the effective portion are equal to the slopes corresponding to the second connecting portion, the portion of the second ohmic contact layer that extends beyond the channel layer is removed, reducing process difficulty. Furthermore, the channel layer and the second ohmic contact layer can be etched using the same mask. Furthermore, the second electrode passes through the channel layer and contacts the second ohmic contact layer, ensuring proper contact and connection between the second electrode and the second ohmic contact layer. This ensures proper operation of the second electrode and the second ohmic contact layer, thereby improving the yield of the thin film transistor.

[0074] Specifically, such as Figure 6 As shown, one end portion of the second ohmic contact layer 36 (eg Figure 6 The right end of the channel layer 37 (eg Figure 6 The second electrode 422 is located in the same plane as the second ohmic contact layer 36. By locating one end of the second ohmic contact layer and one end of the channel layer in the same plane, the portion of the second ohmic contact layer that extends beyond the channel layer is removed, thereby reducing process difficulty and improving the yield of the thin film transistor. Furthermore, the second electrode 422 is in contact with the second ohmic contact layer through the channel layer, ensuring normal contact and connection between the second electrode and the second ohmic contact layer, and the second electrode and the second ohmic contact layer function normally.

[0075] Specifically, compared with the current display device that needs to retain the portion of the second ohmic contact layer that extends beyond the channel during channel etching, the embodiment of the present application does not need to retain the portion of the second ohmic contact layer that extends beyond the channel layer, so the process difficulty can be reduced when etching the channel layer of the thin film transistor; and by allowing the second electrode to pass through the channel layer to connect to the second ohmic contact layer, the second electrode can still transmit signals to the second ohmic contact layer, and there is no need to reserve the portion of the second ohmic contact layer that extends beyond the channel layer, so the volume of the thin film transistor can be reduced; and because the signal is still transmitted from the second ohmic contact layer to the channel layer, the channel length can still be controlled by the thickness and angle of the blocking layer, which can improve the mobility of the thin film transistor. While keeping the mobility of the thin film transistor unchanged, the process difficulty is reduced, the yield of the thin film transistor is improved, and the volume of the thin film transistor is reduced.

[0076] Specifically, when designing the second electrode and the second ohmic contact layer, the design of the first electrode and the first ohmic contact layer can not be changed, i.e., the first electrode and the first ohmic contact layer are still arranged beyond the barrier layer, for example, the first electrode and the first ohmic contact layer are arranged beyond the barrier layer and the channel layer. Figure 3 The design of the middle source-drain layer and the first contact layer.

[0077] Specifically, one end of the first ohmic contact layer 34 and one end of the barrier layer 35 are in the same plane, which means that the first ohmic contact layer and the barrier layer on one side can be etched by the same mask plate, so that the etched first ohmic contact layer and the barrier layer have one end of the first ohmic contact layer and one end of the barrier layer in the same inclined plane or vertical plane, thereby removing the first ohmic contact layer beyond the barrier layer and the channel layer. Similarly, one end of the second ohmic contact layer and one end of the channel layer are in the same plane, which means that one end of the second ohmic contact layer and one end of the barrier layer are in the same inclined plane or vertical plane; one end of the first ohmic contact layer and one end of the channel layer are in the same plane, which means that one end of the first ohmic contact layer and one end of the channel layer are in the same inclined plane or vertical plane.

[0078] Specifically, the drawings of the embodiments of the present application take the end of two film layers as an inclined plane or a vertical plane as an example for illustration. It can be understood that the end of any two contact film layers can be an inclined plane or a vertical plane, and the drawings of the embodiments of the present application do not show all designs.

[0079] It should be noted that in actual process, considering the instability of etching, the end of two film layers can not be in the same plane, for example, due to process limitations, the angle of one end of the first ohmic contact layer and one end of the barrier layer is different, or the ends of the two can be partially misaligned, but at this time, one end of the first ohmic contact layer and one end of the barrier layer are still considered to be in the same plane, only due to the error of the process to cause slight difference.

[0080] In some embodiments, as Figure 10As shown, at the interface between the first ohmic contact layer 34 and the barrier layer 35, the upper surface of the first ohmic contact layer 34 overlaps with the lower surface of the barrier layer 35, and any side surface of the first ohmic contact layer 34 has the same slope as the corresponding side surface of the barrier layer 35. By ensuring that the upper surface of the first ohmic contact layer overlaps with the lower surface of the barrier layer and that any side surface of the first ohmic contact layer has the same slope as the corresponding side surface of the barrier layer, the first ohmic contact layer does not extend beyond the barrier layer, eliminating the portion of the first ohmic contact layer that extends beyond the channel layer and barrier layer, reducing process complexity. Furthermore, the first electrode can pass through the barrier layer to contact the first ohmic contact layer, ensuring proper contact and connection between the first electrode and the first ohmic contact layer. This ensures normal operation of the first electrode and the first ohmic contact layer, thereby improving the yield of the thin film transistor.

[0081] Specifically, such as Figure 10 As shown, one end portion of the first ohmic contact layer 34 (eg Figure 10 the right end in FIG) and one end of the barrier layer 35 (eg Figure 10 The right end in FIG) is located in the same plane, and the other end of the first ohmic contact layer 34 (eg Figure 10 The left end of the barrier layer 35 (eg Figure 10 The left end of the channel layer (in the left end) is located in the same plane, and the first electrode 421 passes through the barrier layer 35 and contacts the first ohmic contact layer 34. By arranging one end of the first ohmic contact layer and one end of the barrier layer in the same plane, and the other end of the first ohmic contact layer and the other end of the barrier layer in the same plane, the first ohmic contact layer does not extend beyond the barrier layer, and the portion of the first ohmic contact layer that extends beyond the channel layer and the barrier layer is removed, thereby reducing the process difficulty and improving the yield of the thin film transistor. In addition, the first electrode passes through the barrier layer and contacts the first ohmic contact layer, ensuring normal contact and connection between the first electrode and the first ohmic contact layer, and the first electrode and the first ohmic contact layer function normally.

[0082] Specifically, compared with the process of etching the channel in the current display device, the part of the first ohmic contact layer beyond the channel layer and the barrier layer does not need to be reserved in the embodiment of the application, so that the process difficulty can be reduced when the channel layer of the thin film transistor is etched; and by making the first electrode pass through the barrier layer to connect the first ohmic contact layer, the first electrode can still transmit signals to the first ohmic contact layer, and there is no need to reserve the part of the first ohmic contact layer beyond the channel layer and the barrier layer, so that the volume of the thin film transistor can be reduced; and since the signals are still transmitted from the first ohmic contact layer to the channel layer, the channel length can still be controlled by the thickness and angle of the barrier layer, so that the mobility of the thin film transistor can be improved, the process difficulty is reduced, the yield of the thin film transistor is improved, and the volume of the thin film transistor is reduced while the mobility of the thin film transistor is kept unchanged.

[0083] Specifically, when the first electrode and the first ohmic contact layer are designed, the design of the second electrode and the second ohmic contact layer can not be changed, that is, the second electrode and the second ohmic contact layer are still arranged beyond the channel layer, for example, the second electrode and the second ohmic contact layer are arranged beyond the channel layer. Figure 3 The middle source-drain layer and Figure 2 the design of the second contact layer.

[0084] In some embodiments, as shown in Figure 6 , one side of the first ohmic contact layer 34 is equal in slope to the side of the first connecting part 371. By making one side of the first ohmic contact layer equal in slope to the side of the first connecting part, the first ohmic contact layer is not arranged beyond the channel layer, the part of the first ohmic contact layer beyond the channel layer is removed, the process difficulty is reduced, and the first electrode contacts the first ohmic contact layer through the channel layer, so that the first electrode and the first ohmic contact layer are normally connected and work, and the yield of the thin film transistor is improved.

[0085] Specifically, as shown in Figure 6 , one end of the first ohmic contact layer 34 (for example, the right end in Figure 6 ) is located in the same plane as one end of the barrier layer 35 (for example, the right end in Figure 6 ), and the other end of the first ohmic contact layer 34 (for example, the left end in Figure 6 ) is located in the same plane as the other end of the channel layer 37 (for example, the left end in Figure 6The left end of the first electrode 421 is located in the same plane, and the first electrode 421 passes through the channel layer 37 and contacts the first ohmic contact layer 34. By arranging one end of the first ohmic contact layer and one end of the barrier layer in the same plane, and the other end of the first ohmic contact layer and the other end of the channel layer in the same plane, the first ohmic contact layer does not extend beyond the barrier layer and the channel layer. This removes the portion of the first ohmic contact layer that extends beyond the channel layer and the barrier layer, reduces process difficulty, and improves the yield of the thin film transistor. The first electrode passes through the channel layer and contacts the first ohmic contact layer, ensuring normal contact and connection between the first electrode and the first ohmic contact layer, and the first electrode and the first ohmic contact layer function normally.

[0086] Specifically, compared with the current display device in which the portion of the first ohmic contact layer that extends beyond the channel and the barrier layer needs to be retained during the channel etching process, the embodiment of the present application does not need to retain the portion of the first ohmic contact layer that extends beyond the channel layer and the barrier layer, so when etching the channel layer of the thin film transistor, the process difficulty can be reduced; and by allowing the first electrode to pass through the channel layer to connect to the first ohmic contact layer, the first electrode can still transmit signals to the first ohmic contact layer, and there is no need to retain the portion of the first ohmic contact layer that extends beyond the channel layer and the barrier layer, so the volume of the thin film transistor can be reduced; and because the signal is still transmitted from the first ohmic contact layer to the channel layer, the channel length can still be controlled by the thickness and angle of the barrier layer, which can improve the mobility of the thin film transistor. While keeping the mobility of the thin film transistor unchanged, the process difficulty is reduced, the yield of the thin film transistor is improved, and the volume of the thin film transistor is reduced.

[0087] Specifically, when designing the first electrode and the first ohmic contact layer, the design of the second electrode and the second ohmic contact layer may not be changed, that is, the second electrode and the second ohmic contact layer are still arranged beyond the channel layer. For example, the second electrode and the second ohmic contact layer are arranged Figure 3 The source and drain layers Figure 2 Design of the second contact layer.

[0088] In some embodiments, as Figure 6 As shown, the thin film transistor 3 includes a first connection hole 421 a , which at least penetrates the interlayer insulating layer 41 and the gate insulating layer 38 , and the first electrode 421 contacts the first ohmic contact layer 34 through the first connection hole 421 a .

[0089] In some embodiments, as Figure 10As shown in the figure, the first connecting hole 421a also penetrates the barrier layer 35; or the first connecting hole 421a penetrates the barrier layer 35 and the first ohmic contact layer 34. By making the first connecting hole penetrate the barrier layer, the contact area of the first electrode with the first ohmic contact layer is larger, and the contact stability of the first electrode with the first ohmic contact layer is better. By making the first connecting hole penetrate the barrier layer and the first ohmic contact layer, the first electrode is in ring contact with the first ohmic contact layer, so that when the channel layer is etched, the first ohmic contact layer 34 is etched at the same time, avoiding that the first electrode 421 cannot contact or poorly contacts the first ohmic contact layer 34, and improving the yield of the thin film transistor.

[0090] In some embodiments, the first connecting hole 421a also penetrates the first connecting part 371; or as Figure 6 shown in the figure, the first connecting hole 421a penetrates the first connecting part 371 and the first ohmic contact layer 34. By making the first connecting hole penetrate the first connecting part, the contact area of the first electrode with the first ohmic contact layer is larger, and the contact stability of the first electrode with the first ohmic contact layer is better. By making the first connecting hole penetrate the first connecting part and the first ohmic contact layer, the first electrode is in ring contact with the first ohmic contact layer, so that when the channel layer is etched, the first ohmic contact layer 34 is etched at the same time, avoiding that the first electrode 421 cannot contact or poorly contacts the first ohmic contact layer 34, and improving the yield of the thin film transistor.

[0091] Specifically, as Figure 6 shown in the figure, one end (for example, the right end in Figure 6 ) of the first ohmic contact layer 34 is located in the same plane as one end (for example, the right end in Figure 6 ) of the barrier layer 35, and the other end (for example, the left end in Figure 6 ) of the first ohmic contact layer 34 is located in the same plane as the other end (for example, the left end in Figure 6 ) of the channel layer 37, and the first electrode 421 contacts the first ohmic contact layer 34 at the contact surface of the first ohmic contact layer 34 and the channel layer 37; or as Figure 6 shown in the figure, the first electrode 421 penetrates the first ohmic contact layer 34, and the first electrode 421 is in ring contact with the first ohmic contact layer 34.

[0092] Specifically, by making the first electrode contact the first ohmic contact layer at the contact surface of the first ohmic contact layer and the channel layer, the contact area of the first electrode with the first ohmic contact layer is larger, and the contact stability of the first electrode with the first ohmic contact layer is better.

[0093] Specifically, considering that the channel layer and the first ohmic contact layer are made of the same material, and there is no selection ratio in dry etching, if the first ohmic contact layer is reserved when the channel layer is etched, the channel layer may not be etched completely, which causes the first ohmic contact layer to not contact or to have poor contact with the first electrode. In the embodiment of the present application, the first electrode 421 penetrates through the first ohmic contact layer 34, and the first electrode 421 is in annular contact with the first ohmic contact layer 34, so that the first ohmic contact layer 34 is etched at the same time when the channel layer is etched, thereby avoiding the first electrode 421 from not contacting or having poor contact with the first ohmic contact layer 34, and improving the yield of the thin film transistor.

[0094] Specifically, as shown in Figure 10 one end (for example, the right end in Figure 10 ) of the first ohmic contact layer 34 is located in the same plane as one end (for example, the right end in Figure 10 ) of the barrier layer 35, and the other end (for example, the left end in Figure 10 ) of the first ohmic contact layer 34 is located in the same plane as the other end (for example, the left end in Figure 10 ) of the barrier layer 35. In the part of the barrier layer 35 that exceeds the second ohmic contact layer 36, the first electrode 421 penetrates through the barrier layer 35 to contact the first ohmic contact layer 34, and there is a spacing between the first electrode 421 and the second ohmic contact layer 36. By locating one end of the first ohmic contact layer in the same plane as one end of the barrier layer and locating the other end of the first ohmic contact layer in the same plane as the other end of the barrier layer, the first ohmic contact layer is not arranged to exceed the barrier layer, the part of the first ohmic contact layer that exceeds the channel layer and the barrier layer is removed, the process difficulty is reduced, the yield of the thin film transistor is improved, the size of the thin film transistor can be further reduced by making the first electrode penetrate through the part of the barrier layer that exceeds the second ohmic contact layer to contact the first ohmic contact layer, the first electrode can normally contact and connect with the first ohmic contact layer, and the first electrode and the first ohmic contact layer can normally work.

[0095] Specifically, compared with making the first electrode penetrate through the channel layer to connect the first ohmic contact layer, making the first electrode penetrate through the part of the barrier layer that exceeds the second ohmic contact layer can further reduce the size of the thin film transistor.

[0096] In some embodiments, as shown in Figure 10 , the first electrode 421 contacts the first ohmic contact layer 34 at the contact surface between the first ohmic contact layer 34 and the barrier layer 35. By making the first electrode contact the first ohmic contact layer at the contact surface between the first ohmic contact layer and the barrier layer, the contact area between the first electrode and the first ohmic contact layer is larger, and the stability is better.

[0097] Specifically, since the material of the first ohmic contact layer is different from the material of the barrier layer, there can be a selectivity when dry etching the barrier layer, so that only the barrier layer can be etched without etching the first ohmic contact layer, so that the contact area between the first electrode and the first ohmic contact layer is larger, the stability is better, and the yield of the thin film transistor is improved.

[0098] Specifically, the first electrode passes through the first ohmic contact layer, and the first electrode is in ring contact with the first ohmic contact layer. When the first electrode is in contact with the first ohmic contact layer, the first electrode can also pass through the first ohmic contact layer and be in ring contact with the first ohmic contact layer.

[0099] The above embodiment is described by taking the first electrode penetrating the first ohmic contact layer as an example, but the embodiment of the present application is not limited thereto. For example, Figure 11 As shown, the depth of the via hole of the first ohmic contact layer can be one tenth to nine tenths of the thickness of the first ohmic contact layer, and this process can be achieved by controlling the etching time, that is, ensuring that the etching time is greater than the time required to etch the channel layer, and the process difficulty is relatively low.

[0100] In some embodiments, as Figure 6 As shown, the thin film transistor 3 includes a second connection hole 422a. The second connection hole 422a penetrates at least the interlayer insulating layer 41, the gate insulating layer 38, and the second connection portion 372. The second electrode 422 contacts the second ohmic contact layer 36 through the second connection hole 422a. By having the second connection hole penetrate the interlayer insulating layer, the gate insulating layer, and the second connection portion, the second electrode can contact the second ohmic contact layer, and the second electrode and the second ohmic contact layer are properly connected.

[0101] In some embodiments, as Figure 6 As shown, the second connecting hole also passes through the second connecting portion.

[0102] In some embodiments, the second electrode 422 contacts the second ohmic contact layer 36 at the interface between the second ohmic contact layer 36 and the channel layer 37; or Figure 6 As shown, the second electrode 422 passes through the second ohmic contact layer 36 , and the second electrode 422 is in ring contact with the second ohmic contact layer 36 .

[0103] Specifically, by making the second electrode contact the second ohmic contact layer at the contact surface between the second ohmic contact layer and the channel layer, the contact area between the second electrode and the second ohmic contact layer is increased, and the contact stability between the second electrode and the second ohmic contact layer is improved.

[0104] Specifically, considering that the materials of the channel layer and the second ohmic contact layer are the same, and there is no selection ratio in dry etching, if the second ohmic contact layer is reserved when the channel layer is etched, the channel layer may not be etched completely, which causes the second ohmic contact layer to not contact or to have poor contact with the second electrode. In the embodiment of the present application, the second electrode 422 penetrates through the second ohmic contact layer 36, and the second electrode 422 is in annular contact with the second ohmic contact layer 36, so that the second ohmic contact layer 36 is etched at the same time when the channel layer is etched, thereby avoiding that the second electrode 422 cannot contact or has poor contact with the second ohmic contact layer 36, and improving the yield of the thin film transistor.

[0105] The above embodiment is described by taking that the second electrode penetrates through the second ohmic contact layer as an example, but the embodiment of the present application is not limited thereto. For example, as shown in FIG. 6, the second ohmic contact layer 36 has a via hole, and the second electrode 422 is in contact with the second ohmic contact layer 36 through the via hole. The depth of the via hole of the second ohmic contact layer can be one-tenth to nine-tenths of the thickness of the second ohmic contact layer, and the process can be realized by controlling the etching time, that is, ensuring that the etching time is greater than the time required for etching the channel layer, and the process difficulty is relatively low. Figure 11

[0106] In some embodiments, as shown in FIG. 5, in the lateral direction, the width of the second connecting part 372 is less than the width of the blocking layer 35, and the first electrode 421 is in contact with the first ohmic contact layer 34 in the area where the blocking layer 35 exceeds the second connecting part 372. By making the width of the blocking layer greater than the width of the second connecting part, at least part of the blocking layer is arranged to exceed the second ohmic contact layer, so that the first electrode can pass through the blocking layer to connect with the first ohmic contact layer, thereby reducing the volume of the thin film transistor. Figure 10

[0107] In view of the problem that the direct contact between the first electrode and / or the second electrode and the channel layer may cause the thin film transistor to be always in an open state. In some embodiments, the ratio of the ion doping concentration of the first ohmic contact layer to the ion doping concentration of the channel layer is greater than or equal to ten to the fifth power. By making the ion doping concentration of the channel layer be 5 orders of magnitude less than the ion doping concentration of the first ohmic contact layer, the ion doping concentration of the channel layer is relatively low, the channel layer is a near-insulating material, the thin film transistor will not be always in a conductive state, and the electrical signal can still be transmitted from the first electrode to the first ohmic contact layer, from the first ohmic contact layer to the second ohmic contact layer, and from the second ohmic contact layer to the second electrode, so that the channel length can still be controlled by the thickness and angle of the blocking layer, the channel length is reduced, and the mobility of the thin film transistor is improved.

[0108] Specifically, the ion doping concentration is the ion doping concentration per unit area.

[0109] ​​Specifically, the difference between the ion doping concentration of the first ohmic contact layer and the ion doping concentration of the second ohmic contact layer is less than one order of magnitude. More specifically, the ion doping concentration of the first ohmic contact layer is equal to the ion doping concentration of the second ohmic contact layer.

[0110] In some embodiments, the material of the channel layer includes intrinsic silicon. By making the material of the channel layer intrinsic silicon, the insulation of the channel layer can be further improved, thereby preventing the thin film transistor from being in an on state all the time and improving the yield of the thin film transistor.

[0111] Specifically, the material of the channel layer includes polysilicon.

[0112] In some embodiments, the material of the first ohmic contact layer includes polysilicon.

[0113] In some embodiments, the material of the second ohmic contact layer includes polysilicon.

[0114] In some embodiments, the material of the barrier layer includes silicon oxide.

[0115] In some embodiments, as Figure 6 As shown, the thin film transistor 3 further includes a light shielding layer 32 , a buffer layer 33 , a gate insulating layer 38 and an interlayer insulating layer 41 .

[0116] In some embodiments, the first electrode is a source electrode and the second electrode is a drain electrode; or the first electrode is a drain electrode and the second electrode is a source electrode.

[0117] The above embodiments describe thin film transistors from the perspective of each film layer and the connection relationship between each film layer. It is understood that when there is no conflict between the embodiments, the embodiments can be combined to achieve better technical effects, or the embodiments can be described in a complete manner. For example, to further reduce the process difficulty and reduce the volume of the thin film transistor, one end of the second ohmic contact layer and one end of the channel layer can be located in the same plane, the second electrode can pass through the channel layer to contact the second ohmic contact layer, and one end of the first ohmic contact layer and one end of the barrier layer can be located in the same plane, the other end of the first ohmic contact layer and the other end of the barrier layer can be located in the same plane, and the first electrode can pass through the barrier layer to contact the first ohmic contact layer; or one end of the second ohmic contact layer and one end of the channel layer can be located in the same plane, the second electrode can pass through the channel layer to contact the second ohmic contact layer, one end of the first ohmic contact layer and one end of the barrier layer can be located in the same plane, the other end of the first ohmic contact layer and the other end of the channel layer can be located in the same plane, and the first electrode can pass through the channel layer to contact the first ohmic contact layer.

[0118] Meanwhile, the embodiment of the present application provides a preparation method of the thin film transistor.

[0119] Specifically, the preparation method of the thin film transistor comprises:

[0120] providing a substrate; the structure of the thin film transistor corresponding to the step is shown as (a) in FIG. 1; Figure 12

[0121] forming a light shielding layer on the substrate; the structure of the thin film transistor corresponding to the step is shown as (a) in FIG. 2; Figure 12

[0122] forming a buffer layer and a first ohmic contact layer on the light shielding layer in sequence; the B1-B2 cross-sectional view of the thin film transistor corresponding to the step is shown as (b1) in FIG. 3, and the A1-A2 cross-sectional view of the thin film transistor corresponding to the step is shown as (b2) in FIG. 4; Figure 12 Figure 12

[0123] forming a barrier layer and a second ohmic contact layer on the first ohmic contact layer; the B1-B2 cross-sectional view of the thin film transistor corresponding to the step is shown as (c1) in FIG. 5, and the A1-A2 cross-sectional view of the thin film transistor corresponding to the step is shown as (c2) in FIG. 6; Figure 12 Figure 12

[0124] forming a channel layer on the second ohmic contact layer, and etching the channel layer and the second ohmic contact layer; the B1-B2 cross-sectional view of the thin film transistor corresponding to the step is shown as (d1) in FIG. 7, and the A1-A2 cross-sectional view of the thin film transistor corresponding to the step is shown as (d2) in FIG. 8; Figure 12 Figure 12

[0125] forming a gate insulating layer and a gate layer on the channel layer; the B1-B2 cross-sectional view of the thin film transistor corresponding to the step is shown as (e1) in FIG. 9, and the A1-A2 cross-sectional view of the thin film transistor corresponding to the step is shown as (e2) in FIG. 10; Figure 12 Figure 12

[0126] forming an interlayer insulating layer on the gate layer, and etching the interlayer insulating layer, the gate insulating layer, the channel layer, the first ohmic contact layer and the second ohmic contact layer to form a via hole; the B1-B2 cross-sectional view of the thin film transistor corresponding to the step is shown as (f1) in FIG. 11, and the A1-A2 cross-sectional view of the thin film transistor corresponding to the step is shown as (f2) in FIG. 12; Figure 12 Figure 12

[0127] ​​​​​​​​​​​​Forming a source-drain layer on the interlayer insulating layer; the B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in (e1) of FIG. 4, and the A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in (e2) of FIG. 4. Figure 6 Figure 7

[0128] Specifically, another method for manufacturing a thin film transistor includes:

[0129] Providing a substrate; the structure of the thin film transistor corresponding to this step is shown in (a) of FIG. 1; Figure 13

[0130] Forming a light shielding layer on the substrate; the structure of the thin film transistor corresponding to this step is shown in (a) of FIG. 1; Figure 13

[0131] Forming a buffer layer, a first ohmic contact layer, a barrier layer and a second ohmic contact layer on the light shielding layer in sequence; the structure of the thin film transistor corresponding to this step is shown in (b) of FIG. 1; Figure 13

[0132] Forming a channel layer on the second ohmic contact layer, and etching the channel layer and the second ohmic contact layer; the structure of the thin film transistor corresponding to this step is shown in (c) of FIG. 1; Figure 13

[0133] Forming a gate insulating layer and a gate layer on the channel layer; the structure of the thin film transistor corresponding to this step is shown in (d) of FIG. 1; Figure 13

[0134] Forming an interlayer insulating layer on the gate layer, and etching the interlayer insulating layer, the gate insulating layer, the channel layer and the second ohmic contact layer to form a via hole; the B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in (e1) of FIG. 4, and the A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in (e2) of FIG. 4. Figure 13 Figure 13

[0135] Etching the interlayer insulating layer, the gate insulating layer and the barrier layer to form a via hole; the B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in (f1) of FIG. 5, and the A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in (f2) of FIG. 5. Figure 13 Figure 13

[0136] Forming a source-drain layer on the interlayer insulating layer; the B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in (e1) of FIG. 4, and the A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in (e2) of FIG. 4. Figure 10 Figure 7

[0137] ​​​​​​​​​​​​​Meanwhile, the application provides an electronic device, which comprises the thin film transistor according to any one of the above embodiments.

[0138] According to the above embodiments, it is known that:

[0139] The application provides a thin film transistor and an electronic device. The thin film transistor comprises a substrate, a first ohmic contact layer, a barrier layer, a second ohmic contact layer, a channel layer, a gate insulating layer, a gate layer, an interlayer insulating layer and a source-drain layer. The first ohmic contact layer is arranged on one side of the substrate. The barrier layer is arranged on a side of the first ohmic contact layer away from the substrate. The barrier layer comprises at least one sidewall. The second ohmic contact layer is arranged on a side of the barrier layer away from the first ohmic contact layer. The channel layer comprises a first connecting part, a second connecting part and an effective part on the sidewall. The first connecting part is in contact with the first ohmic contact layer. The second connecting part is arranged on the second ohmic contact layer. The gate insulating layer is arranged on a side of the channel layer away from the second ohmic contact layer. The gate layer is arranged on a side of the gate insulating layer away from the channel layer. The gate layer covers the effective part in a vertical projection on the substrate. The interlayer insulating layer is arranged on a side of the gate layer away from the gate insulating layer. The source-drain layer is arranged on a side of the interlayer insulating layer away from the gate layer. The source-drain layer comprises a first electrode and a second electrode. The second electrode is in contact with the second ohmic contact layer through the channel layer. The first electrode is in contact with the first ohmic contact layer through the barrier layer. Or the first connecting part is arranged on the first ohmic contact layer, and the first electrode is in contact with the first ohmic contact layer through the channel layer. According to the application, the effective part is arranged on the sidewall of the barrier layer, and the first connecting part and the second connecting part are in contact with the first ohmic contact layer and the second ohmic contact layer arranged above and below the barrier layer, respectively. The channel length can be controlled by the thickness and angle of the barrier layer. The channel length is reduced by using the existing process, the volume of the thin film transistor is reduced, and the mobility is improved. The second electrode is in contact with the second ohmic contact layer through the channel layer, so that the second electrode can work normally even if the second ohmic contact layer is over-etched. The first electrode is in contact with the first ohmic contact layer through the barrier layer or the channel layer, so that the first electrode can work normally even if the first ohmic contact layer is over-etched. The yield of the display panel is improved, and the size of the thin film transistor is reduced.

[0140] In the above embodiments, the description of each embodiment has its own focus. The parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0141] The above has carried out the detailed introduction to the thin film transistor and electronic device provided by the embodiment of the application, the principle and implementation mode of the application are described by applying specific examples in this paper, the above embodiment is only used to help understanding the technical scheme of the application and its core idea; the ordinary skilled in the art should understand that: it can still modify the technical scheme recorded by the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical scheme deviate from the scope of the technical scheme of the embodiments of the application.

Claims

1. A thin film transistor, characterized in that: include: substrate; A first ohmic contact layer is provided on one side of the substrate; a barrier layer, disposed on a side of the first ohmic contact layer away from the substrate, the barrier layer comprising at least one sidewall; a second ohmic contact layer, disposed on a side of the barrier layer away from the first ohmic contact layer; a channel layer comprising a first connecting portion, a second connecting portion and an effective portion located on the sidewall, wherein the first connecting portion contacts the first ohmic contact layer, and the second connecting portion is disposed on the second ohmic contact layer; a gate insulating layer, disposed on a side of the channel layer away from the second ohmic contact layer; a gate layer, disposed on a side of the gate insulating layer away from the channel layer, wherein an orthographic projection of the gate layer in a direction perpendicular to the substrate covers the effective portion; an interlayer insulating layer, disposed on a side of the gate layer away from the gate insulating layer; a source-drain electrode layer, disposed on a side of the interlayer insulating layer away from the gate layer, the source-drain electrode layer comprising a first electrode and a second electrode; The first connecting portion is provided on the first ohmic contact layer, and the first electrode passes through the channel layer and contacts the first ohmic contact layer.

2. The thin film transistor according to claim 1, wherein The second electrode contacts the second ohmic contact layer through the channel layer.

3. The thin film transistor according to claim 2, wherein: At the contact surface between the second ohmic contact layer and the second connecting portion, the upper surface of the second ohmic contact layer coincides with the lower surface of the second connecting portion, and the slopes of the three side surfaces of the second ohmic contact layer that are not in contact with the effective portion are equal to the slope corresponding to the second connecting portion.

4. The thin film transistor according to claim 1, wherein A side surface of the first ohmic contact layer has the same slope as a side surface of the first connecting portion.

5. The thin film transistor according to claim 1, wherein The thin film transistor includes a first connection hole, the first connection hole at least penetrating the interlayer insulating layer and the gate insulating layer, and the first electrode contacts the first ohmic contact layer through the first connection hole.

6. The thin film transistor according to claim 5, wherein The first connection hole also passes through the first connection portion; or the first connection hole passes through the first connection portion and the first ohmic contact layer.

7. The thin film transistor according to claim 2, wherein: The thin film transistor includes a second connection hole, the second connection hole at least penetrates the interlayer insulating layer, the gate insulating layer and the second connection portion, and the second electrode contacts the second ohmic contact layer through the second connection hole.

8. The thin film transistor according to claim 7, wherein: The second connecting hole also passes through the second connecting portion.

9. The thin film transistor according to claim 1, wherein A ratio of an ion doping concentration of the first ohmic contact layer to an ion doping concentration of the channel layer is greater than or equal to ten to the fifth power.

10. The thin film transistor according to claim 1, wherein The material of the channel layer includes intrinsic silicon.

11. An electronic device, characterized in that: The electronic device comprises the thin film transistor according to any one of claims 1 to 10.

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