Thin film transistor device, display panel and display device

Abstract

The invention provides a thin film transistor device, a display panel and a display device. The thin film transistor device comprises a source electrode, a drain electrode, a first grid electrode and a second grid electrode, a channel region is arranged between the drain electrode and the source electrode; the first grids are arranged on the channel region at intervals, and the first grids are in short circuit with the source electrode; the second gate is arranged on one side, deviating from the first gate, of the channel region; that is to say, on one hand, the first grid is arranged as the top grid, the second grid is arranged as the bottom grid, electric field distribution in the channel region can be optimized through the top grid and the bottom grid, and then the switching performance of the thin film transistor device can be improved; and on the other hand, the first grid electrode and the source electrode are short-circuited, so that the saturation speed of the IDVD can be improved, and the power consumption of the thin film transistor device can be reduced.

Description

Technical Field

[0001] The present application belongs to the field of display driving technology, and in particular, relates to a thin film transistor device, a display panel and a display apparatus. Background Art

[0002] Active-matrix organic light emitting diode (AMOLED) and flat panel display devices based on light emitting diode (LED) technologies have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the process performance of current display products needs to be improved. Summary of the invention

[0004] The purpose of the present application is to provide a thin film transistor device, a display panel and a display apparatus, aiming to solve the problem of low process performance of display products in traditional technologies.

[0005] A first aspect of an embodiment of the present application provides a thin film transistor device, the thin film transistor device comprising:

[0006] source;

[0007] A drain electrode, wherein a channel region is disposed between the drain electrode and the source electrode;

[0008] A first gate electrode is disposed on the channel region at intervals, and the first gate electrode is short-circuited with the source electrode;

[0009] The second gate is arranged on a side of the channel region away from the first gate.

[0010] In some embodiments of the present application, the thin film transistor device includes a first insulating layer, the source, the drain and the channel region are all arranged on the first insulating layer, and the second gate is arranged on a side of the first insulating layer away from the channel region.

[0011] In some embodiments of the present application, the thin film transistor device also includes a second insulating layer, which is arranged on the first insulating layer and covers the source, the drain and the channel region, and the first gate is arranged on a side of the second insulating layer away from the channel region.

[0012] In some embodiments of the present application, the thin film transistor device further includes a first functional layer, wherein the first functional layer covers a side of the first gate away from the second insulating layer;

[0013] The thin film transistor device further includes a first via structure and a second via structure, wherein one end of the first via structure is exposed from the first functional layer, and the other end of the first via structure passes through the first functional layer and is electrically connected to the first gate;

[0014] One end of the second via structure is exposed from the first functional layer, and the other end of the second via structure passes through the first functional layer and is electrically connected to the source electrode;

[0015] The exposed end of the first via structure and the exposed end of the second via structure are set at the same potential;

[0016] Preferably, the first via structure and the second via structure are connected via a conductive structure.

[0017] In some embodiments of the present application, the first functional layer includes:

[0018] a first dielectric layer, wherein the first dielectric layer is disposed on the second insulating layer and covers the first gate;

[0019] The second dielectric layer is arranged on a side of the first dielectric layer away from the second insulating layer.

[0020] In some embodiments of the present application, the material of the first insulating layer is selected from one or more of SiOx, SiNx and HfOx.

[0021] In some embodiments of the present application, the thin film transistor device includes a second functional layer, the first insulating layer and the second gate are both arranged on the second functional layer, and the first insulating layer covers the second gate.

[0022] In some embodiments of the present application, the first insulating layer includes a plurality of sub-layers, and the plurality of sub-layers are stacked on the second functional layer.

[0023] In a second aspect, the present application also provides a display panel, comprising the above-mentioned thin film transistor device.

[0024] In a third aspect, the present application also provides a display device, comprising the above-mentioned display panel.

[0025] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned thin film transistor device, display panel and display device, the thin film transistor device includes a source, a drain, a first gate and a second gate; a channel region is arranged between the drain and the source; the first gate is arranged on the channel region at intervals, and the first gate is short-circuited with the source; the second gate is arranged on the side of the channel region away from the first gate; that is, in the present application, on the one hand, by setting the first gate as the top gate and the second gate as the bottom gate, the electric field distribution in the channel region can be optimized by the top gate and the bottom gate, which is beneficial to improving the switching performance of the thin film transistor device; on the other hand, by short-circuiting the first gate and the source, it is beneficial to improve the saturation speed of IDVD, which is beneficial to reduce the power consumption of the thin film transistor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of a thin film transistor device provided in one embodiment of the present application;

[0027] Figure 2 A schematic diagram of the structure of a thin film transistor device provided in another embodiment of the present application;

[0028] Figure 3 A schematic structural diagram of a thin film transistor device provided in yet another embodiment of the present application;

[0029] Figure 4 A schematic structural diagram of a thin film transistor device provided in yet another embodiment of the present application;

[0030] Figure 5 A schematic structural diagram of a thin film transistor device provided in yet another embodiment of the present application.

[0031] Explanation of specific element symbols: 100 - thin film transistor device, 110 - source, 120 - drain, 130 - channel region, 140 - first gate, 150 - second gate, 160 - first via structure, 170 - second via structure, 180 - conductive structure, 200 - first insulating layer, 300 - second insulating layer, 400 - first functional layer, 410 - first dielectric layer, 420 - second dielectric layer, 500 - second functional layer, 510 - glass substrate, 520 - PI layer, 530 - BL layer. DETAILED DESCRIPTION

[0032] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0033] It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0034] It should be understood that the terms "length", "width", "up", "down", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0036] It is important to know that in current display panel technology, the performance of thin film transistor devices has a crucial impact on the efficiency and effect of the entire display system. In particular, the length of time that the thin film transistor device enters the saturation region is directly related to the response speed and power consumption performance of the display panel. Traditionally, the 7T1C (seven transistors and one capacitor) circuit is widely used to control the brightness of OLED (organic light emitting diode), in which the driver tube DTFT (driving thin film transistor) plays a key role.

[0037] The working state of DTFT is carefully designed in the saturation region to ensure that the voltage difference change of Vds (drain-source voltage) will not affect the current passing through DTFT. This feature minimizes the impact of factors such as aging and potential changes of OLED devices on the display effect of the screen. However, although this design has significant advantages in display effect, from the IDVD curve (characteristic curve related to drain current Ids and drain-source voltage Vds), the current saturation speed of DTFT is relatively slow.

[0038] The slow saturation speed of the current means that the DTFT will experience a long transition phase before reaching the stable current. During this phase, because the current has not yet fully reached the saturation state, it will cause additional power consumption. Especially in display panels with high frame rates or high resolutions, this additional power consumption will significantly affect the energy efficiency of the entire display system.

[0039] Based on this, the present application improves the related thin film transistor devices, display panels and display devices.

[0040] See also Figure 1 , Figure 1 The schematic diagram of the structure of the thin film transistor device 100 provided in this embodiment is shown. The thin film transistor device 100 in this embodiment includes a source 110, a drain 120, a first gate 140 and a second gate 150; a channel region 130 is arranged between the drain 120 and the source 110; the first gate 140 is arranged on the channel region 130 at intervals, and the first gate 140 is short-circuited with the source 110; and the second gate 150 is arranged on the side of the channel region 130 away from the first gate 140.

[0041] It should be explained that in the display panel, by adjusting the on or off of multiple thin film transistor devices 100, the luminescence of the pixel structure can be adjusted. Exemplarily, the driving circuit can be a 2T1C, 3T1C, 7T1C and other circuits. In the thin film transistor device 100, the channel region 130 is arranged between the source 110 and the drain 120, and the carriers in the channel region 130 can be adjusted by the gate to adjust the on and off between the source 110 and the drain 120. Specifically, the source 110 and the drain 120 are respectively arranged on both sides of the channel region 130, and they together constitute the main current path of the thin film transistor device 100. When the thin film transistor device 100 is working, the current flows from the source 110, passes through the channel region 130, and finally flows out from the drain 120. The channel region 130 is a key area for current flow in the thin film transistor device 100, and its conductivity is regulated by the gate voltage. When the gate voltage reaches or exceeds a certain threshold, the channel region 130 will become conductive, allowing current to pass.

[0042] It can be understood that the first gate 140 is used as a top gate (TG, Top Gate), and the second gate 150 is used as a bottom gate (BG, Bottom Gate). The first gate 140 and the second gate 150 can simultaneously control the channel region 130. This dual gate control can more effectively adjust the charge distribution and conductivity in the channel region 130, thereby achieving precise control of the device performance. In addition, the synergistic effect of the top gate and the bottom gate can significantly improve the switching speed of the device, reduce power consumption, and improve the current driving capability. For example, in a dual-gate thin-film transistor, the top gate and the bottom gate can jointly adjust the conductivity of the channel, so that the device can achieve a higher current output at a lower voltage. This helps to reduce power consumption and improve the working efficiency of the device. In addition, setting the top gate and the bottom gate at the same time can also enhance the stability of the device. In some application scenarios, such as high temperature or high radiation environment, the performance of the device may be affected. By controlling the top gate and the bottom gate at the same time, the electric field distribution inside the device can be more effectively balanced, thereby reducing the negative impact on the device performance.

[0043] It is understandable that when the thin film transistor device 100 is in the saturation region, the drain 120 current Ids no longer increases significantly with the increase of the drain 120-source 110 voltage Vds. If the saturation speed of the thin film transistor device 100 is slow, it means that before reaching the saturation state, Ids may remain at a relatively high level for a period of time. During this period, due to the large Ids, the power consumption will also be relatively high. Since the thin film transistor device 100 needs to perform high-frequency switching actions in the display panel, each switching process will cause the above-mentioned excess power consumption. As the number of switching times increases, the power consumption will also increase. Exemplarily, an IDVD curve is usually used to characterize the correlation between the drain 120 current Ids and the drain 120-source 110 voltage Vds; the IDVD curve includes an ohmic region, a saturation region, and a breakdown region. In the ohmic region (Vds is low), Ids is proportional to Vds, and the transistor exhibits resistive behavior; in the saturation region, as Vds increases, the transistor enters a saturated state, at which time Ids no longer increases significantly with the increase in Vds. The saturation region is the main working area of ​​the transistor for digital circuit switching operations. In the breakdown region, if Vds continues to increase, the transistor may enter the breakdown region, resulting in a breakdown of the drain 120-substrate, a sharp increase in current, and possible damage to the transistor.

[0044] Specifically, in this embodiment, the source 110 and the first gate 140 are short-circuited, which is conducive to the faster formation of the conductive channel in the channel region 130 under the same gate voltage, and is conducive to improving the transmission efficiency of carriers; thereby, the speed at which the thin film transistor device 100 enters the saturation region can be increased, thereby reducing power consumption. In addition, the short-circuit between the top gate and the source 110 may also increase the carrier concentration inside the transistor. The increase in carrier concentration will increase the conductivity of the conductive channel, thereby further accelerating the saturation speed of the IDVD.

[0045] In the related art, the thin film transistor device 100 is controlled by only one gate, and the gate and the source 110 are not short-circuited, resulting in a slow saturation speed of the thin film transistor device 100, which in turn leads to higher power consumption. However, in the present application, on the one hand, by setting the first gate 140 as the top gate and the second gate 150 as the bottom gate, the electric field distribution in the channel region 130 can be optimized by the top gate and the bottom gate, which is beneficial to improving the switching performance of the thin film transistor device 100; on the other hand, by short-circuiting the first gate 140 and the source 110, it is beneficial to improve the saturation speed of IDVD, which is beneficial to reduce the power consumption of the thin film transistor device 100.

[0046] In some embodiments, the thin film transistor device 100 is a driving thin film transistor.

[0047] In some embodiments of this application, please continue to refer to Figure 2 The thin film transistor device 100 of this embodiment includes a first insulating layer 200 , a source 110 , a drain 120 and a channel region 130 are all arranged on the first insulating layer 200 , and a second gate 150 is arranged on a side of the first insulating layer 200 away from the channel region 130 .

[0048] It should be explained that the first insulating layer 200 serves to isolate the source 110 , the drain 120 and the channel region 130 from the second gate 150 thereunder, thereby avoiding unnecessary electrical interference or short circuit.

[0049] In some embodiments, the SS (subthreshold swing) of the device can be quantitatively adjusted by adjusting the thickness and material of the first insulating layer 200 .

[0050] In some embodiments, the first insulating layer 200 is made of an inorganic material.

[0051] In some embodiments of the present application, the material of the first insulating layer 200 is selected from one or more of SiOx, SiNx and HfOx. Exemplarily, the first insulating layer 200 is prepared by CVD (Chemical Vapor Deposition).

[0052] In some embodiments of this application, please continue to refer to Figure 2 The thin film transistor device 100 of this embodiment further includes a second insulating layer 300 , which is disposed on the first insulating layer 200 and covers the source 110 , the drain 120 and the channel region 130 , and the first gate 140 is disposed on a side of the second insulating layer 300 away from the channel region 130 .

[0053] It should be explained that the second insulating layer 300 serves to isolate the source 110 , the drain 120 and the channel region 130 from the first gate 140 thereon, thereby avoiding unnecessary electrical interference or short circuit.

[0054] In some embodiments of this application, please continue to refer to Figure 2The thin film transistor device 100 of this embodiment further includes a first functional layer 400, which covers the side of the first gate electrode 140 away from the second insulating layer 300; the thin film transistor device 100 further includes a first via structure 160 and a second via structure 170, one end of the first via structure 160 is exposed from the first functional layer 400, and the other end of the first via structure 160 passes through the first functional layer 400 and is electrically connected to the first gate electrode 140; one end of the second via structure 170 is exposed from the first functional layer 400, and the other end of the second via structure 170 passes through the first functional layer 400 and is electrically connected to the source electrode 110; the exposed end of the first via structure 160 and the exposed end of the second via structure 170 are set at the same potential.

[0055] It should be explained that the first functional layer 400 can be used to provide additional electrical properties, such as protection, shielding or enhanced conductivity. The first via structure 160 and the second via structure 170 can connect the source 110 and the first gate 140 together. The exposed end of the first via structure 160 is set at the same potential as the exposed end of the second via structure 170, which means that they are set to the same potential, which helps to ensure the stability and performance of the circuit.

[0056] In some embodiments, one end of the first via structure 160 away from the first gate 140 extends out of the first functional layer 400 , and one end of the second via structure 170 away from the source 110 extends out of the first functional layer 400 to facilitate connection with the conductive structure 180 .

[0057] In some embodiments, please refer to Figure 2 The first via structure 160 and the second via structure 170 are connected through the conductive structure 180 to achieve the same potential setting of the first via structure 160 and the second via structure 170, thereby achieving the same potential setting between the source 110 and the first gate 140.

[0058] In some embodiments, the first via structure 160 and the second via structure 170 are connected via a conductive structure.

[0059] In some embodiments, the conductive structure 180 is a conductive line.

[0060] In some embodiments of this application, please refer to Figure 3 , Figure 3 The schematic diagram of the structure of the thin film transistor device 100 provided in this embodiment is shown. The first functional layer 400 of this embodiment includes a first dielectric layer 410 and a second dielectric layer 420; the first dielectric layer 410 is disposed on the second insulating layer 300 and covers the first gate 140; the second dielectric layer 420 is disposed on the side of the first dielectric layer 410 away from the second insulating layer 300.

[0061] It should be explained that the first dielectric layer 410 (CI, Capacitor Insulator) is an insulating structure in the thin film transistor device 100. The second dielectric layer 420 (ILD, Inter Layer Dielectric) is also an insulating structure in the thin film transistor device 100, which can be used to isolate different metal layers or conductive layers. In this embodiment, the second dielectric layer 420 can be used to play an insulating role together with the first dielectric layer 410.

[0062] In some embodiments of this application, please refer to Figure 4 , Figure 4 A schematic structural diagram of a thin film transistor device 100 provided in this embodiment is shown; the thin film transistor device 100 of this embodiment includes a second functional layer 500 , a first insulating layer 200 and a second gate 150 are both arranged on the second functional layer 500 , and the first insulating layer 200 covers the second gate 150 .

[0063] In some embodiments, the second functional layer 500 includes a glass substrate 510 , a PI layer 520 , and a BL layer 530 arranged in sequence from bottom to top. The first insulating layer 200 and the second gate 150 are both arranged on the BL layer 530 .

[0064] It should be explained that the PI layer 520 can be a flat layer, and the material can include polyimide, which can provide a higher flatness growth environment for the subsequent structure and can also play a certain insulation effect. The BL layer 530 is a buffer layer, which can improve the characteristics of the substrate surface or provide additional electrical isolation. The BL layer 530 can contain specific materials, such as oxides or nitrides, to optimize the interface characteristics with the upper circuit elements. The BL layer 530 can also serve as a barrier layer for subsequent deposition processes to prevent impurities from diffusing into the upper circuit.

[0065] In some embodiments of the present application, the first insulating layer 200 includes a plurality of sub-layers, and the plurality of sub-layers are stacked on the second functional layer 500 .

[0066] In some embodiments, the thin film transistor device 100 is a DTFT (driven thin film transistor) device, and the material of the channel region of the DTFT device includes a semiconductor material. The semiconductor material is not limited to LTPS (low temperature polycrystalline silicon). The semiconductor material may also be oxide (metal oxide, mainly a type of material containing some or all of In, Ga, Zn, O, and may contain other elements), carbon nanotubes, and other semiconductor materials that can be used to prepare TFTs.

[0067] Specifically, the thin film transistor device 100 of this embodiment is applicable to TFTs made of different semiconductor materials.

[0068] Furthermore, in order to better implement the thin film transistor device 100 in any of the above embodiments, based on the above thin film transistor device 100 , the present application also provides a display panel including the above thin film transistor device 100 .

[0069] In some embodiments, the display panel may be an OLED display panel or other flexible display structures.

[0070] Furthermore, in order to better implement the display panel in any of the above embodiments, based on the above display panel, the present application also provides a display device including the above display panel.

[0071] In some embodiments, the display device may be a mobile phone, a tablet, a desktop computer, a laptop computer, a wearable device, a car screen, a sensor device, etc.

[0072] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0073] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0074] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0075] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more embodiments of the invention, in the above description of the embodiments of this application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0076] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A thin film transistor device, characterized in that: include: source; A drain electrode, wherein a channel region is disposed between the drain electrode and the source electrode; A first gate electrode is disposed on the channel region at intervals, and the first gate electrode is short-circuited with the source electrode; The second gate is arranged on a side of the channel region away from the first gate.

2. The thin film transistor device according to claim 1, characterized in that: The thin film transistor device comprises a first insulating layer, the source electrode, the drain electrode and the channel region are all arranged on the first insulating layer, and the second gate electrode is arranged on a side of the first insulating layer away from the channel region.

3. The thin film transistor device according to claim 2, characterized in that: The thin film transistor device further includes a second insulating layer, which is disposed on the first insulating layer and covers the source electrode, the drain electrode and the channel region. The first gate electrode is disposed on a side of the second insulating layer away from the channel region.

4. The thin film transistor device according to claim 3, characterized in that: The thin film transistor device further comprises a first functional layer, wherein the first functional layer covers a side of the first gate away from the second insulating layer; The thin film transistor device further includes a first via structure and a second via structure, wherein one end of the first via structure is exposed from the first functional layer, and the other end of the first via structure passes through the first functional layer and is electrically connected to the first gate; One end of the second via structure is exposed from the first functional layer, and the other end of the second via structure passes through the first functional layer and is electrically connected to the source electrode; The exposed end of the first via structure and the exposed end of the second via structure are set at the same potential; Preferably, the first via structure and the second via structure are connected via a conductive structure.

5. The thin film transistor device according to claim 4, characterized in that: The first functional layer comprises: a first dielectric layer, wherein the first dielectric layer is disposed on the second insulating layer and covers the first gate; The second dielectric layer is arranged on a side of the first dielectric layer away from the second insulating layer.

6. The thin film transistor device according to claim 2, characterized in that: The material of the first insulating layer is selected from one or more of SiOx, SiNx and HfOx.

7. The thin film transistor device according to claim 2, characterized in that: The thin film transistor device includes a second functional layer, the first insulating layer and the second gate are both arranged on the second functional layer, and the first insulating layer covers the second gate.

8. The thin film transistor device according to claim 7, characterized in that: The first insulating layer includes a plurality of sub-layers, and the plurality of sub-layers are stacked on the second functional layer.

9. A display panel, characterized in that: A thin film transistor device comprising any one of claims 1 to 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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