Goa circuit, driving method thereof, display panel and display device

Abstract

The application discloses a GOA circuit and a driving method thereof, a display panel and a display device, and relates to the technical field of display. The circuit comprises a stage transmission module integrated with a stage transmission transistor. The drain of the stage transmission transistor is electrically connected with a first node. The source of the stage transmission transistor is electrically connected with a second node. The gate control end of an output module is electrically connected with the second node. The two side transmission ends of a potential control module are respectively electrically connected with the first node and a low potential line. The high potential end of the potential control module is electrically connected with a high potential line. The potential control module is used for transmitting the high potential signal of the high potential line to the first node in the stage transmission stage, so that the stage transmission transistor transmits the high potential signal to the output module through the second node. After the stage transmission is completed, the low potential signal of the low potential line is transmitted to the first node, so that the potential of the second node, to which the source of the stage transmission transistor is electrically connected, is continuously pulled down. The threshold voltage drift of the stage transmission transistor caused by voltage imbalance is eliminated, so that the display quality is improved.

Description

GOA circuits and their driving methods, display panels and display devices Technical Field

[0001] This application relates to the field of display technology, and in particular to a GOA circuit and its driving method, a display panel, and a display device. Background Technology

[0002] The rapid development of display technology has led to increasingly higher demands from users for the display quality of display panels.

[0003] In current display panels using GOA (Gate Driver on Array) driving, the stage transistors in the stage transmission module are constantly under negative bias, causing the first node P of the drain connection of the stage transistor to maintain a high potential. This results in a long-term voltage imbalance across the three terminals of the stage transistor. This voltage imbalance further causes the threshold voltage of the stage transistor to drift, severely affecting its switching performance. When the threshold voltage drift of the stage transistor is severe, the stage transistor may not be able to turn off effectively when it needs to be turned off, causing abnormal high-potential leakage to the second node Q. The second node Q is the electrical connection node between the stage transmission module and the output module. When its potential is pulled high, it will abnormally turn on the output module, leading to disordered output of the timing control signals connected to the output module. This severely affects the normal display of the display panel, causing abnormal display problems such as screen flickering, ghosting, or uneven brightness.

[0004] Therefore, how to eliminate the threshold voltage drift caused by voltage imbalance in the transistor to improve the display quality of the display panel is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a GOA circuit and its driving method, a display panel, and a display device, which aims to eliminate the threshold voltage drift problem caused by long-term negative bias of the stage transistor to improve the display quality of the display panel.

[0006] To achieve the above objectives, this application provides a GOA circuit, the GOA circuit comprising:

[0007] A cascade module, the cascade module including a cascade transistor, the drain of the cascade transistor being electrically connected to a first node, and the source of the cascade transistor being electrically connected to a second node;

[0008] An output module, wherein the gate control terminal of the output module is electrically connected to the second node;

[0009] A potential control module is provided, wherein its two transmission terminals are electrically connected to the first node and the low-potential line, respectively, and its high-potential terminal is electrically connected to the high-potential line. The potential control module is configured to transmit the high-potential signal of the high-potential line to the first node during the cascading stage so that the cascading transistor can transmit the high-potential signal to the output module via the second node, and after the cascading is completed, transmit the low-potential signal of the low-potential line to the first node so that the potential of the second node, which is electrically connected to the source of the cascading transistor, is continuously pulled low.

[0010] In one embodiment, the GOA circuit includes a low-potential control terminal, and the potential control module includes a first thin-film transistor and a second thin-film transistor;

[0011] The first path terminal of the first thin film transistor forms the high potential terminal of the potential control module and is electrically connected to the high potential line. The gate terminal of the first thin film transistor is electrically connected to the gate signal terminal of the previous stage. The second path terminal of the first thin film transistor forms one of the two transmission terminals and is electrically connected to the first node.

[0012] The first path terminal of the second thin-film transistor is electrically connected to the first node, the second path terminal of the second thin-film transistor constitutes the other transmission terminal of the two sides and is electrically connected to the low potential line, and the gate terminal of the second thin-film transistor is electrically connected to the potential pull-down control terminal.

[0013] In one embodiment, when the potential pull-down control terminal is any one of the current stage gate signal terminal, the subsequent stage gate signal terminal, and the timing control terminal, the gate of the stage transistor is electrically connected to the previous stage gate signal terminal.

[0014] In one embodiment, when the low-potential control terminal is the gate signal terminal of the subsequent stage, the gate of the stage transistor is electrically connected to the drain of the stage transistor.

[0015] In one embodiment, the cascading module further includes a third thin-film transistor, wherein a first terminal of the third thin-film transistor is electrically connected to the low-potential line, and a second terminal of the third thin-film transistor is electrically connected to the second node.

[0016] The output module includes a fourth thin-film transistor and a capacitor. The gate terminal of the fourth thin-film transistor and the first terminal of the capacitor are electrically connected to the second node. The first path terminal of the fourth thin-film transistor is electrically connected to the timing control terminal. The second path terminal of the fourth thin-film transistor and the second terminal of the capacitor are respectively electrically connected to the current stage gate signal terminal.

[0017] Furthermore, to achieve the above objectives, this application also provides a GOA circuit driving method, which is applied to the GOA circuit described in any of the above claims, and the GOA circuit driving method includes:

[0018] During the cascading stage, the high-potential signal of the high-potential line is transmitted to the first node through the potential control module, so that the cascading transistor in the cascading module can transmit the high-potential signal to the output module via the second node.

[0019] After the cascading is completed, the low-potential signal of the low-potential line is transmitted to the first node through the potential control module so that the potential of the second node, which is electrically connected to the source of the cascading transistor, is continuously pulled low.

[0020] In one embodiment, the potential control module includes a second thin-film transistor, and the cascade module includes a third thin-film transistor. The step of transmitting the low-potential signal of the low-potential line to the first node through the potential control module to continuously pull down the potential of the second node, which is electrically connected to the source of the cascade transistor, includes:

[0021] When both the gate signal at the gate signal terminal and the pull-down control signal at the pull-down control terminal are at active levels, the third thin-film transistor is enabled to transmit the low-potential signal of the low-potential line to the second node electrically connected to the source of the stage transistor under the drive of the gate signal at the gate signal at the gate, and the second thin-film transistor is enabled to transmit the low-potential signal to the first node electrically connected to the source of the stage transistor under the drive of the pull-down control signal.

[0022] The potential of the second node is continuously pulled low based on the low potential signals received by the first node and the second node.

[0023] In one embodiment, the step of maintaining the potential of the second node continuously low based on the low-potential signals received by the first node and the second node includes:

[0024] In response to the front-stage gate signal provided by the front-stage gate signal terminal to the gate of the cascade transistor switching from an effective level to an ineffective level, it is determined that the gate potential of the cascade transistor is a low potential of the ineffective level, the drain potential of the cascade transistor is a low potential signal connected to the first node, and the drain potential of the cascade transistor is a low potential signal connected to the second node, so as to maintain the cut-off state of the cascade transistor.

[0025] This enables the potential of the second node to be continuously pulled low in the off state.

[0026] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the GOA circuit described in any of the above claims.

[0027] In addition, to achieve the above objectives, this application also provides a display device, which includes the display panel described above;

[0028] Alternatively, a memory, a processor, and a charging driver stored in the memory and executable on the processor, wherein the processor, when executing the charging driver, implements the steps of the GOA circuit driving method described above.

[0029] This application incorporates a potential control module in the GOA circuit. During the stage of stage transmission, the high-potential signal of the high-potential line is transmitted to the first node through the potential control module. This ensures that when the stage transmission transistor in the stage transmission module is turned on, the high-potential signal can be transmitted to the output module through the electrically connected first node to achieve normal display driving. After stage transmission is completed, the low-potential signal of the low-potential line is transmitted to the first node through the potential control module, causing the potential of the second node connected to the source of the stage transmission transistor to be continuously pulled low. This allows a zero-bias state to be formed between the drain (connected to the first node) and the source (connected to the second node) of the stage transmission transistor, effectively avoiding threshold voltage drift caused by voltage imbalance of the stage transmission transistor. This stabilizes the switching performance of the stage transmission transistor and completely blocks the abnormal leakage path of the high-potential signal to the second node, thereby preventing the output module from being mistakenly turned on due to abnormal increase in the potential of the second node. Ultimately, this ensures the accuracy of the timing output of the GOA circuit and significantly improves the display quality of the display panel. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 is a structural block diagram of the first embodiment of the GOA circuit of this application;

[0033] Figure 2 is a schematic diagram of the GOA circuit involved in the embodiment of this application;

[0034] Figure 3 is the GOA circuit diagram involved when the low potential control terminal is the gate signal terminal of the current stage;

[0035] Figure 4 is a schematic diagram of the signal waveforms involved in the circuit diagram shown in Figure 3;

[0036] Figure 5 is the GOA circuit diagram involved when the low potential control terminal is the gate signal terminal of the subsequent stage;

[0037] Figure 6 is a schematic diagram of the signal waveforms involved in the circuit diagram shown in Figure 5;

[0038] Figure 7 is the GOA circuit diagram involved when the low potential control terminal is the timing control terminal;

[0039] Figure 8 is a schematic diagram of the signal waveforms involved in the circuit diagram shown in Figure 7;

[0040] Figure 9 is another GOA circuit diagram involving the low potential control terminal being the gate signal terminal of the subsequent stage;

[0041] Figure 10 is a schematic diagram of the structure of the display device involved in the embodiment of this application.

[0042] Explanation of icon numbers:

[0043] 10. Stage Transmission Module; 20. Output Module; 30. Potential Control Module; V0. Potential Pull-Down Control Terminal; T0. Stage Transmission Transistor; T1. First Thin Film Transistor; T2. Second Thin Film Transistor; T3. Third Thin Film Transistor; T4. Fourth Thin Film Transistor; C1. Capacitor; VGH. High Potential Line; VGL. Low Potential Line.

[0044] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0046] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0047] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0049] In recent years, with the rapid development of display technology, high refresh rate monitors have gradually become the mainstream demand in the market due to their advantages such as a smoother visual experience in dynamic scenes, faster response speed, and reduced eye fatigue. However, high refresh rates also bring higher power consumption issues, especially in application scenarios such as mobile devices and laptops where battery life is a high priority. High power consumption has become one of the key factors restricting the widespread adoption of high refresh rates.

[0050] The rapid development of display technology has led to increasingly higher demands from users for the display quality of display panels.

[0051] In current display panels using GOA (Gate Driver on Array) driving, the stage transistors in the stage transmission module are constantly under negative bias, causing the first node P of the drain connection of the stage transistor to maintain a high potential. This results in a long-term voltage imbalance across the three terminals of the stage transistor. This voltage imbalance further causes the threshold voltage of the stage transistor to drift, severely affecting its switching performance. When the threshold voltage drift of the stage transistor is severe, the stage transistor may not be able to turn off effectively when it needs to be turned off, causing abnormal high-potential leakage to the second node Q. The second node Q is the electrical connection node between the stage transmission module and the output module. When its potential is pulled high, it will abnormally turn on the output module, leading to disordered output of the timing control signals connected to the output module. This severely affects the normal display of the display panel, causing abnormal display problems such as screen flickering, ghosting, or uneven brightness.

[0052] Therefore, in order to solve the technical problem of threshold voltage drift caused by voltage imbalance in cascade transistors, this application provides a GOA circuit and its driving method, a display panel, and a display device.

[0053] This application provides a GOA circuit. Referring to Figure 1, which is a structural block diagram of a first embodiment of the GOA circuit of this application, the GOA circuit includes:

[0054] The cascading module 10 includes a cascading transistor T0, the drain of which is electrically connected to a first node and the source of which is electrically connected to a second node.

[0055] In this embodiment, referring to FIG1, the cascading module 10 is provided with a cascading transistor T0, and the drain of the cascading transistor T0 is electrically connected to the first node, and the source of the cascading transistor T0 is electrically connected to the second node, thereby undertaking the function of signal cascading transmission between adjacent GOA units. Specifically, when the cascade transistor T0 is connected to the preceding GOA unit of its GOA unit via the preceding gate signal Gn-1 output from the preceding gate signal terminal, it is determined that the GOA unit containing the cascade transistor T0 is in the cascade stage. During this cascade stage, the cascade transistor T0 and the potential control module 30 electrically connected to the first node are synchronously turned on according to the preceding gate signal Gn-1. This allows the high potential signal of the high potential line VGH to be transmitted sequentially through the turned-on potential control module 30, the first node, and the turned-on cascade transistor T0 to the second node, providing a stable trigger signal for the output module 20 electrically connected to the second node. This avoids the signal delay or loss problem caused by poor cascade path in traditional GOA circuits. At the same time, in conjunction with the low potential adjustment of the subsequent potential control module 30, the voltage difference across the three terminals of the cascade transistor T0 is reduced to zero during the non-working phase, fundamentally solving the voltage offset problem caused by long-term voltage imbalance. This completely eliminates display defects such as high / low temperature flicker and horizontal lines caused by the voltage offset problem, ensuring the long-term stability of the cascaded signal transmission of the GOA circuit.

[0056] Output module 20, the gate control terminal of output module 20 is electrically connected to the second node.

[0057] In this embodiment, referring to FIG1, precise control of the current stage gate signal Gn output is achieved through the electrical connection between the gate control terminal of the output module 20 and the second node. Specifically, the output module 20 is turned on and off in real time based on the potential change of the second node received by the gate control terminal of the output module 20. When the second node is at a high level due to the transmission high potential signal from the transmission module 10, the output module 20 is effectively turned on, converting the timing control signal input to the output module 20 into the current stage gate signal Gn that meets the display requirements, and transmitting it to the display area of ​​the display panel to drive the pixel units electrically connected to the current stage gate, thereby realizing the normal display driving of the display panel. Conversely, when the second node is pulled down to a low potential signal, the output module 20 immediately switches from the on state to the off state to stop the output of the current stage gate signal Gn, ensuring the normal row-by-row driving of the display panel.

[0058] A potential control module 30 is provided, wherein its two transmission terminals are electrically connected to the first node and the low potential line VGL, respectively, and its high potential terminal is electrically connected to the high potential line VGH. The potential control module 30 is configured to transmit the high potential signal of the high potential line VGH to the first node during the cascading stage so that the cascading transistor T0 can transmit the high potential signal to the output module 20 via the second node. After the cascading is completed, the low potential signal of the low potential line VGL is transmitted to the first node so that the potential of the second node, which is electrically connected to the source of the cascading transistor T0, is continuously pulled low.

[0059] In this embodiment, the two transmission terminals of the potential control module 30 are electrically connected to the first node and the low-potential line VGL, respectively, and the high-potential terminal of the potential control module 30 is electrically connected to the high-potential line VGH. This allows the high-potential signal of the high-potential line VGH to be transmitted to the first node during the cascading stage, ensuring that a high-potential signal can be provided to the output module 20 electrically connected to the second node when the cascading transistor T0 is turned on. This achieves compatibility with the original working logic of the GOA circuit and ensures the normal operation of the cascading signal transmission. After the cascading is completed, the low-potential signal of the low-potential line VGL is transmitted to the first node through the potential control module 30, thereby continuously pulling down the potential of the second node electrically connected to the source of the cascading transistor T0. This fundamentally avoids the voltage offset problem caused by long-term voltage imbalance of the cascading transistor T0, stabilizes the switching performance of the cascading transistor T0, and completely blocks the abnormal leakage path of the high-potential signal to the second node. This prevents the output module 20 from being mistakenly turned on due to abnormal increase in the potential of the second node, ultimately ensuring the accuracy of the timing output of the GOA circuit and significantly improving the display quality of the display panel.

[0060] Furthermore, in some feasible embodiments, referring to FIG2, the GOA circuit includes a potential pull-down control terminal V0, and the potential control module 30 includes a first thin-film transistor T1 and a second thin-film transistor T2;

[0061] The first path terminal of the first thin film transistor T1 forms the high potential terminal of the potential control module 30 and is electrically connected to the high potential line VGH. The gate terminal of the first thin film transistor T1 is electrically connected to the gate signal terminal of the previous stage. The second path terminal of the first thin film transistor T1 forms one of the two transmission terminals and is electrically connected to the first node.

[0062] In this embodiment, the application combines the coordinated control of the low-potential control terminal V0 and the front-stage gate signal terminal to set the gate terminal of the first thin-film transistor T1 to be electrically connected to the front-stage gate signal terminal, the first path terminal of the first thin-film transistor T1 to be electrically connected to the high-potential line VGH, and the second path terminal of the first thin-film transistor T1 to be electrically connected to the first node. Since the front-stage gate signal provided by the front-stage gate signal terminal is at an effective level during the stage transmission phase, the first thin-film transistor T1 switches from the off state to the on state, thereby allowing the high-potential signal of the high-potential line VGH to be stably transmitted to the first node without loss through the on-state first thin-film transistor T1. The stage transmission transistor T0 in the stage transmission module 10 will also be turned on when the front-stage gate signal is at an effective level or when the potential signal of the first node is at a high level, thereby smoothly transmitting the high-potential signal of the first node to the second node, ensuring that the output module 20 normally outputs the current stage gate signal Gn when the second node is at a high level.

[0063] The first path terminal of the second thin film transistor T2 is electrically connected to the first node, the second path terminal of the second thin film transistor T2 constitutes the other transmission terminal of the two sides and is electrically connected to the low potential line VGL, and the gate terminal of the second thin film transistor T2 is electrically connected to the potential pull-down control terminal V0.

[0064] In this embodiment, the pull-down control signal output from the potential pull-down control terminal V0 is directly transmitted to the gate terminal of the second thin-film transistor T2. During the stage transfer phase, this pull-down control signal is at an invalid level to continuously maintain the cutoff state of the second thin-film transistor T2, thereby avoiding interference from the low potential line VGL to the high potential state of the second node and ensuring that the signal transmission during the stage transfer phase is not affected. After the stage transfer is completed, the pull-down control signal switches from an invalid level to an active level to turn on the second thin-film transistor T2, and provides the low potential signal of the low potential line VGL to the first node through the active second thin-film transistor T2, thereby pulling down the drain potential of the stage transfer transistor T0 electrically connected to the first node. Since the gate signal of the previous stage switches from an active level to an invalid level when the stage transfer is completed, and the gate of the stage transfer transistor T0 is affected by the gate signal of the previous stage or the first stage, the pull-down control signal is affected by the gate signal of the previous stage or the first stage. The first node potential control is synchronously cut off when the gate signal of the preceding stage fails or the potential of the first node is pulled low. That is, the gate potential of the cascade transistor T0 is also pulled low. The second node connected through the source of the cascade transistor T0 will also drop to a low potential synchronously due to the cutoff of the cascade transistor T0. Ultimately, the potentials of the drain, source and gate of the cascade transistor T0 are all stably maintained at a low potential, that is, the voltage of the three terminals of the cascade transistor T0 is completely zero. This not only completely avoids the voltage deviation problem caused by the cascade transistor T0 being subjected to voltage difference for a long time, eliminating display abnormalities such as high temperature flickering and low temperature horizontal lines from the root, but also ensures that the output module 20 is completely shut down after the cascade is completed through timely cutoff of the cascade transistor T0 and maintenance of the low potential of the second node, preventing abnormal current stage gate signal output, eliminating image ghosting or disorder, and significantly improving display quality.

[0065] Furthermore, in some other feasible embodiments, when the potential pull-down control terminal V0 is any one of the current stage gate signal terminal, the subsequent stage gate signal terminal, and the timing control terminal, the gate of the stage transistor T0 is electrically connected to the previous stage gate signal terminal.

[0066] In this embodiment, referring to Figures 3 and 4, when the gate of the stage transfer transistor T0 is electrically connected to the gate signal terminal of the previous stage, the low-potential control terminal V0 can be flexibly configured as the gate signal terminal of the current stage. During the stage transfer phase, the gate signal Gn-1 of the previous stage is at an effective level. The stage transfer transistor T0 and the first thin-film transistor T1 are synchronously turned on when the gate signal of the previous stage is at an effective level, so as to transmit the high-potential signal of the high-potential line VGH to the first node, and conduct it to the second node through the stage transfer transistor T0, triggering the output module 20 to output the current stage gate signal Gn; next, when the current stage gate signal Gn is output (i.e., when the stage transfer is completed), the current stage gate signal Gn switches from an invalid level to an effective level, directly triggering the second thin-film transistor T2 to turn on, turning on the low-potential line VGL. The low-potential signal is transmitted to the first node; at this time, the gate signal Gn-1 of the preceding stage is already at an invalid low level, the gate potential of the stage transistor T0 drops to a low level and is cut off, the drain of the stage transistor T0 electrically connected to the first node is pulled low to a low potential, and the source of the stage transistor T0 electrically connected to the second node drops to a low potential synchronously with the discharge of the output module 20. Finally, the stage transistor T0 achieves zero voltage difference across its three terminals because the gate, drain and source are all at low potentials, completely suppressing the voltage offset problem and eliminating display abnormalities such as high-temperature flickering and low-temperature flickering caused by this, significantly improving display quality. In addition, this application sets the potential pull-down control terminal V0 as the current stage gate signal terminal, ensuring that the pull-down action is strictly synchronized with the completion time of the current stage gate signal Gn output, with fast response speed and no additional timing delay, suitable for small and medium-sized panels with high driving accuracy requirements, and avoiding the pull-down lag problem caused by external signal interference.

[0067] In a specific embodiment, the current stage gate signal Gn provided by the current stage gate signal terminal serves as the turn-on trigger signal for the second thin-film transistor T2. When in stage 1 of Figure 4, since the signal waveform of the previous stage gate signal Gn-1 switches from a low potential to a high potential, i.e., the previous stage gate signal Gn-1 is at an effective level, the stage transmission transistor T0 and the first thin-film transistor T1 are turned on under the drive of the previous stage gate signal Gn-1 being at an effective level, so as to charge the second node with the high potential signal provided by the high potential line VGH sequentially through the first thin-film transistor T1, the first node, and the stage transmission transistor T0, thereby enabling the second node to trigger the fourth thin-film transistor T4 in the output module 20 to be turned on normally according to the obtained high potential signal; next, when in stage 2 of Figure 4, the signal waveform of the previous stage gate signal Gn-1 switches from a high potential to a low potential, i.e., the previous stage gate signal Gn-1 is at an ineffective level, at which time the stage transmission transistor T0 and the first thin-film transistor T1 are turned on. Transistor T1 remains in the off state. Since capacitor C1 in output module 20 continues to supply power to the fourth thin-film transistor T4 through its stored capacitance when the stage-transfer transistor T0 is off, the fourth thin-film transistor T4 remains in the on state. It outputs the timing signal CKA (i.e., the waveform involved in stage 2 of CKA in Figure 4, also known as the effective level) provided by the timing control terminal as the current stage gate signal Gn. At this time, the second thin-film transistor T2 is turned on when the current stage gate signal Gn is at an effective level, allowing the low-potential signal provided by the low-potential line VGL to be written to the first node via the turned-on second thin-film transistor T2. Subsequently, when in stage 3 of Figure 4, the first node remains in a low-potential state until the previous stage gate signal Gn-1 of the next frame is at an effective level, repeating steps 1 to 3. In other words, this application sets the stage-transfer transistor T0 to remain in stage 3 of Figure 4 for an extended period after stage-transfer, ensuring that the three-terminal voltage difference of the stage-transfer transistor T0 is 0 and that Vth shift (i.e., voltage offset) does not occur. This effectively improves the display problem caused by voltage offset in the stage-transfer transistor T0.

[0068] In another embodiment, referring to Figures 5 and 6, when the gate of the stage transfer transistor T0 is electrically connected to the gate signal terminal of the previous stage, the low-voltage control terminal V0 can be flexibly configured as the gate signal terminal of the subsequent stage. This application utilizes the inherent timing characteristic that the gate signal Gn+1 of the subsequent stage naturally lags behind the gate signal Gn of the current stage to ensure that the second thin-film transistor T2 only conducts after the current stage gate signal Gn is fully output, avoiding interference from the pull-down action on the high potential of the second node during the signal Gn output stage. Simultaneously, the gate of the stage transfer transistor T0 is controlled by the gate signal Gn-1 of the previous stage, reliably conducting during the stage transfer phase and turning off upon the failure of the gate signal Gn-1 after the stage transfer is completed. This forms a timing closed loop with the pull-down action triggered by the gate signal Gn+1 of the subsequent stage, further ensuring the integrity of signal transmission. This is suitable for display panels in wide-temperature complex environments, which can be understood as low-temperature display scenarios or high-temperature display scenarios.

[0069] In a specific embodiment, the subsequent gate signal Gn+1 provided by the subsequent gate signal terminal serves as the turn-on trigger signal for the second thin-film transistor T2. When in stage 1 of Figure 6, since the signal waveform of the preceding gate signal Gn-1 switches from a low potential to a high potential, i.e., the preceding gate signal Gn-1 is at an effective level, the stage transistor T0 and the first thin-film transistor T1 are turned on under the drive of the preceding gate signal Gn-1 being at an effective level, so as to charge the second node with the high potential signal provided by the high potential line VGH sequentially through the first thin-film transistor T1, the first node, and the stage transistor T0, thereby enabling the second node to trigger the fourth thin-film transistor T4 in the output module 20 to be turned on normally according to the obtained high potential signal. Next, when in stage 2 of Figure 6, the signal waveform of the preceding gate signal Gn-1 switches from a high potential to a low potential, i.e., the preceding gate signal Gn-1 is at an ineffective level, and the stage transistor T0 and the first thin-film transistor T1 remain in the off state. Since the capacitor C1 in the output module 20 can continue to supply the fourth thin-film transistor when the stage transistor T0 is off, the stored capacitance C1 can continue to supply the fourth thin-film transistor. Transistor T4 is powered, keeping the fourth thin-film transistor T4 in the on state. It outputs the timing signal CKA (the waveform involved in stage 2 of the waveform CKA in Figure 6, also known as the effective level) provided by the timing control terminal as the current stage gate signal Gn. At this time, the second thin-film transistor T2 remains in the off state when the subsequent stage gate signal Gn+1 is inactive (the waveform involved in stage 2 of the waveform Gn+1 in Figure 6). That is, the potential of the first node remains high in stage 2. Subsequently, when in stage 3 of Figure 6, since the subsequent stage gate signal Gn+1 switches from inactive to active (the waveform involved in stage 3 of the waveform Gn+1 in Figure 6), the second thin-film transistor T2 is turned on when the subsequent stage gate signal Gn+1 is active. The low potential signal provided by the low potential line VGL is written to the first node through the active second thin-film transistor T2 until the previous stage gate signal Gn-1 of the next frame is active, and the steps of stages 1 to 3 are repeated. In other words, this application sets the stage transfer transistor T0 to remain in stage 3 in Figure 6 for a long time after the stage transfer is completed, ensuring that the voltage difference across the three terminals of the stage transfer transistor T0 is 0 and that Vthshift (i.e., voltage offset) does not occur, which can effectively improve the display problem caused by voltage offset of the stage transfer transistor T0.

[0070] In another embodiment, referring to Figures 7 and 8, when the gate of the stage transfer transistor T0 is electrically connected to the gate signal terminal of the previous stage, the low potential control terminal V0 can be flexibly configured as a timing control terminal. During the stage transfer phase, the stage transfer transistor T0 and the first thin film transistor T1 are synchronously turned on when the gate signal of the previous stage is at an effective level, so as to transmit the high potential signal of the high potential line VGH to the first node, and conduct it to the second node through the stage transfer transistor T0, triggering the output module 20 to output the current stage gate signal Gn; when the stage transfer is completed, since the timing signal CKA of the timing control terminal has a stable periodic characteristic, the effective level of the timing signal CKA is strictly synchronized with the overall panel driving rhythm. The second thin film transistor T2 is only triggered to turn on when the current stage gate signal Gn is at an effective level to pull down the potential of the first node, so that the stage transfer transistor T0 achieves zero voltage difference at the three terminals due to the low potential of the gate, drain and source, completely suppressing the voltage offset problem, eliminating display abnormalities such as high temperature flicker and low temperature flicker caused by this, and significantly improving the display quality. Furthermore, this application utilizes the periodic characteristics of the timing signal CKA to adapt to the driving requirements of panels with different resolutions (such as 4K and 8K) by adjusting the timing signal period, and the pull-down action is highly matched with the overall scanning rhythm of the panel, further reducing circuit power consumption.

[0071] In a specific embodiment, the timing signal CKA provided by the timing control terminal serves as the turn-on trigger signal for the second thin-film transistor T2. When in stage 1 of Figure 8, since the signal waveform of the front-stage gate signal Gn-1 switches from a low potential to a high potential, i.e., the front-stage gate signal Gn-1 is at an effective level, the stage transistor T0 and the first thin-film transistor T1 are turned on under the drive of the front-stage gate signal Gn-1 being at an effective level, so as to charge the second node with the high-potential signal provided by the high-potential line VGH sequentially through the first thin-film transistor T1, the first node, and the stage transistor T0, thereby enabling the second node to trigger the fourth thin-film transistor T4 in the output module 20 to be turned on normally according to the obtained high-potential signal; next, when in stage 2 of Figure 8, the signal waveform of the front-stage gate signal Gn-1 switches from a high potential to a low potential, i.e., the front-stage gate signal Gn-1 is at an ineffective level, at which time the stage transistor T0 and the first thin-film transistor T1 are turned on. The membrane transistor T1 remains in the off state. Since the capacitor C1 in the output module 20 continues to supply power to the fourth membrane transistor T4 through its stored capacitance when the stage transistor T0 is off, the fourth membrane transistor T4 remains in the on state. It outputs the timing signal CKA (i.e., the waveform involved in stage 2 of CKA in Figure 8, also known as the effective level) provided by the timing control terminal as the current stage gate signal Gn. At this time, the second membrane transistor T2 is turned on when the timing signal CKA is at an effective level, allowing the low-potential signal provided by the low-potential line VGL to be written to the first node via the turned-on second membrane transistor T2. Subsequently, when in stage 3 of Figure 8, the first node remains in a low-potential state until the previous stage gate signal Gn-1 of the next frame is at an effective level, repeating steps 1 to 3. In other words, this application sets the stage transistor T0 to remain in stage 3 of Figure 8 for an extended period after stage transmission, ensuring that the three-terminal voltage difference of the stage transistor T0 is 0 and that Vth shift (i.e., voltage offset) does not occur. This effectively improves the display problem caused by voltage offset in the stage transistor T0.

[0072] Furthermore, in some feasible embodiments, referring to FIG9, when the potential pull-down control terminal V0 is the gate signal terminal of the subsequent stage, the gate of the stage transmission transistor T0 is electrically connected to the drain of the stage transmission transistor T0.

[0073] In this embodiment, since the drain of the cascade transistor T0 is electrically connected to the first node, if the gate of the cascade transistor T0 is electrically connected to the drain of the cascade transistor T0, that is, when the gate of the cascade transistor T0 is shorted to the first node, in order to prevent the second thin-film transistor T2 from pulling down the potential of the second node and affecting the normal turn-on of the output module 20 when it is not turned on during the current stage gate signal Gn output phase, this application limits the potential pull-down control terminal V0 of the gate terminal of the second thin-film transistor T2 to be only the subsequent stage gate signal terminal, ensuring that the conduction of the second thin-film transistor T2 is controlled only by the subsequent stage gate signal (i.e., effective level) provided by the subsequent stage gate signal terminal, thereby making the second node stably maintain a high potential during the current stage gate signal Gn output phase. In other words, the hysteresis characteristic of the subsequent stage gate signal Gn+1 ensures that the second Thin-film transistor T2 only turns on after the current stage gate signal Gn is output. At this time, the first node is pulled low to the low potential line VGL. Since the gate and drain of the stage transmission transistor T0 are electrically connected to the first node, the gate potential and drain potential of the stage transmission transistor T0 will be pulled low synchronously as the first node is pulled low. The third thin-film transistor T3, which is electrically connected to the second node in the stage transmission module 10, turns on synchronously under the drive of the subsequent stage gate signal Gn+1 to pull the potential of the second node, which is electrically connected to the source of the stage transmission transistor T0, down to the low potential line VGL. As a result, the three-terminal voltage difference of the stage transmission transistor T0 is reduced to zero because the gate, drain and source are all at low potentials. This completely suppresses the voltage offset problem and eliminates display abnormalities such as high temperature flicker and low temperature flicker caused by it, significantly improving the display quality.

[0074] Furthermore, in some other feasible embodiments, referring to FIG2, the cascading module 10 further includes a third thin-film transistor T3, the first path terminal of the third thin-film transistor T3 being electrically connected to the low potential line VGL, and the second path terminal of the third thin-film transistor T3 being electrically connected to the second node; the output module 20 includes a fourth thin-film transistor T4 and a capacitor C1, the gate terminal of the fourth thin-film transistor T4 and the first terminal of the capacitor C1 being electrically connected to the second node, the first path terminal of the fourth thin-film transistor T4 being electrically connected to the timing control terminal, and the second path terminal of the fourth thin-film transistor T4 and the second terminal of the capacitor C1 being electrically connected to the current stage gate signal terminal respectively.

[0075] In this embodiment, referring to FIG2, the application further includes a third thin-film transistor T3 in the transmission module 10, which, together with the output module 20 integrating a fourth thin-film transistor T4 and a capacitor C1, and the pull-down sustaining module shown in FIG2, further improves the display quality. Specifically, the first path terminal of the third thin-film transistor T3 is electrically connected to the low potential line VGL, and the second path terminal of the third thin-film transistor T3 is electrically connected to the second node. The third thin-film transistor T3 can be turned on when the transmission is completed, so that the potential of the second node can be quickly pulled down to a low potential through the turned-on third thin-film transistor T3, avoiding the abnormal start-up of the output module 20 due to the residual high potential of the second node, thus enhancing the precise control of the potential of the second node. In the output module 20, the gate of the fourth thin-film transistor T4 and the first terminal of the capacitor C1 are connected to the second node. The first path terminal of the fourth thin-film transistor T4 is connected to the timing control terminal, and the second path terminal of the fourth thin-film transistor T4 and the second terminal of the capacitor C1 are connected to the current stage gate signal terminal, so that the capacitor C1 can maintain the stability of the second node potential through charge storage after obtaining a high potential at the second node. This ensures that the fourth thin-film transistor T4 remains reliably powered on, stably converting the timing signal CKA at the timing control terminal into the current stage gate signal Gn output, avoiding distortion of the current stage gate signal Gn caused by the potential fluctuation of the second node; and through the pull-down sustaining module, in conjunction with the output module 20 and the stage transmission module 10, it not only maintains the high potential of the second node during the stage transmission phase to drive the current stage gate signal Gn output, but also quickly pulls down the potential of the second node through the third thin-film transistor T3 after the stage transmission is completed. In conjunction with the pull-down action of the potential control module 30 on the first node, the stage transmission transistor T0 achieves zero voltage difference across its three terminals due to the low potential of its gate, drain, and source, completely suppressing the voltage offset problem. At the same time, it ensures accurate timing and stable signal output of the current stage gate signal Gn, significantly improving the driving reliability and display quality of the GOA circuit.

[0076] Furthermore, based on the first embodiment of the GOA circuit of this application, a second embodiment of the GOA circuit driving method of this application is proposed.

[0077] The GOA circuit driving method of this application is applied to the GOA circuit of any of the above claims. The GOA circuit driving method of this application is executed by a display device applied to the GOA circuit. The GOA circuit driving method of this application includes the following implementation steps S10 to S20.

[0078] Step S10: During the stage of transmission, the high potential signal of the high potential line VGH is transmitted to the first node through the potential control module 30 so that the transmission transistor T0 in the transmission module 10 can transmit the high potential signal to the output module 20 via the second node.

[0079] In this embodiment, a high-potential signal of the high-potential line VGH is transmitted to the first node during the cascading stage, ensuring that a high-potential signal can be provided to the output module 20 electrically connected to the second node when the cascading transistor T0 is turned on. This achieves compatibility with the original working logic of the GOA circuit and ensures the normal operation of the cascading signal transmission.

[0080] Step S20: After the stage transfer is completed, the low potential signal of the low potential line VGL is transmitted to the first node through the potential control module 30 so that the potential of the second node, which is electrically connected to the source of the stage transfer transistor T0, is continuously pulled low.

[0081] In this embodiment, after the cascade is completed, the low-potential signal of the low-potential line VGL is transmitted to the first node through the potential control module 30, thereby continuously pulling down the potential of the second node that is electrically connected to the source of the cascade transistor T0. This fundamentally avoids the voltage offset problem caused by long-term voltage imbalance of the cascade transistor T0, stabilizes the switching performance of the cascade transistor T0, and completely blocks the abnormal leakage path of the high-potential signal to the second node. This prevents the output module 20 from being mistakenly turned on due to the abnormal increase of the potential of the second node, and ultimately ensures the accuracy of the timing output of the GOA circuit, significantly improving the display quality of the display panel.

[0082] Furthermore, in some other feasible embodiments, the potential control module 30 includes a second thin-film transistor T2, and the cascade module 10 includes a third thin-film transistor T3. The above step S20, which transmits the low-potential signal of the low-potential line VGL to the first node through the potential control module 30 so that the potential of the second node to which the source of the cascade transistor T0 is electrically connected is continuously pulled low, may also include the following implementation steps S201 to S202.

[0083] Step S201: When both the gate signal at the gate terminal and the pull-down control signal at the pull-down control terminal V0 are at active levels, the third thin-film transistor T3 is enabled to transmit the low-potential signal of the low-potential line VGL to the second node electrically connected to the drain of the stage transistor T0 under the drive of the gate signal at the gate terminal, and the second thin-film transistor T2 is enabled to transmit the low-potential signal to the first node electrically connected to the source of the stage transistor T0 under the drive of the pull-down control signal.

[0084] In this embodiment, referring to Figure 2, when both the subsequent gate signal and the pull-down control signal are at active levels, the third thin-film transistor T3, driven by the subsequent gate signal, transmits the low-potential signal of the low-potential line VGL to the second node connected to the drain of the cascade transistor T0. Simultaneously, the second thin-film transistor T2, driven by the pull-down control signal, transmits the low-potential signal to the first node connected to the source of the cascade transistor T0. This allows for the rapid elimination of residual high potentials at the first and second nodes, causing the drain and source potentials of the cascade transistor T0 to drop to low levels synchronously. Combined with the low-potential state of the gate of the cascade transistor T0 at this time, the three-terminal voltage difference is instantly reduced to zero, suppressing the generation of voltage deviation from the source. At the same time, the pull-down of the second node can immediately cut off the output module 20, preventing the abnormal continuous output of the current gate signal Gn, ensuring the accuracy of signal timing, and effectively preventing defects such as screen flickering and horizontal lines on the display panel caused by the drift of the characteristics of the cascade transistor T0.

[0085] It should be noted that the pull-low control signal can be any one of the current stage gate signal Gn, the subsequent stage gate signal Gn+1, and the timing signal CKA.

[0086] Step S202: Based on the low potential signals received by the first node and the second node, maintain the potential of the second node continuously low.

[0087] In this embodiment, a "dual maintenance" mechanism is constructed based on the stable low-potential signals of the first and second nodes to keep the second node at a continuously low potential. Specifically, the low potential of the first node keeps the stage transfer transistor T0 in the off state, blocking the transmission path of the high-potential signal to the second node and preventing the potential of the second node from rising from the source. Meanwhile, the low potential of the second node itself directly suppresses the potential drift caused by parasitic capacitance C1 or interference, thereby ensuring that the second node always maintains a low level after the stage transfer is completed. This provides a clean initial state for the stage transfer process of the next GOA unit and completely eliminates the risk of the output module 20 being turned on by mistake due to the abnormal potential of the second node. This further ensures the stability of the timing control of the GOA circuit and improves the reliability of the display panel and the picture quality.

[0088] Furthermore, in some other feasible embodiments, the above step S202: maintaining the potential of the second node continuously low based on the low potential signal connected to the first node and the second node may also include the following implementation steps S2021 to S2022.

[0089] Step S2021: In response to the front-stage gate signal provided by the front-stage gate signal terminal to the gate of the cascade transistor T0 switching from an effective level to an ineffective level, it is determined that the gate potential of the cascade transistor T0 is a low potential of the ineffective level, the drain potential of the cascade transistor T0 is a low potential signal connected to the first node, and the source potential of the cascade transistor T0 is a low potential signal connected to the second node, so as to maintain the off state of the cascade transistor T0.

[0090] In this embodiment, in response to the switching of the front-stage gate signal provided to the gate of the stage-transfer transistor T0 from an effective potential to an ineffective level, it can be accurately determined that the gate potential of the stage-transfer transistor T0 drops to a low potential synchronously when the front-stage gate signal is ineffective. The drain potential of the stage-transfer transistor T0 is the low potential signal connected to the first node, and the source potential of the stage-transfer transistor T0 is the low potential signal connected to the second node. This results in a balanced state where the three terminals of the stage-transfer transistor T0 are all at low potentials, ensuring that the stage-transfer transistor T0 quickly and stably maintains the cutoff state after the stage-transfer is completed. This completely blocks the abnormal leakage path of the high-potential signal from the first node to the second node, fundamentally avoiding the voltage offset problem caused by the incomplete cutoff of the stage-transfer transistor T0, and significantly improving the display quality of the display panel.

[0091] Step S2022: Enable the second node to continuously pull its potential low in the cut-off state.

[0092] In this embodiment, the potential of the second node is continuously pulled low when the stage transfer transistor T0 is in the off state, which avoids the output module 20 from being turned on by an abnormal potential of the second node, eliminates the disorder of the current stage gate signal Gn output, and provides a clean and stable initial potential environment for the stage transfer process of the next stage GOA unit.

[0093] In summary, this application incorporates a potential control module 30 in the GOA circuit. During the stage of transmission, the high-potential signal of the high-potential line VGH is transmitted to the first node through the potential control module 30. This ensures that when the transmission transistor T0 in the transmission module 10 is turned on, it can transmit the high-potential signal to the output module 20 through the electrically connected first node to achieve normal display driving. After the transmission is completed, the low-potential signal of the low-potential line VGL is transmitted to the first node through the potential control module 30, causing the potential of the second node connected to the source of the transmission transistor T0 to be continuously pulled low. This allows a zero-bias state to be formed between the drain (connected to the first node) and the source (connected to the second node) of the transmission transistor T0, effectively preventing threshold voltage drift caused by voltage imbalance in the transmission transistor T0. This stabilizes the switching performance of the transmission transistor T0, completely blocks the abnormal leakage path of the high-potential signal to the second node, and prevents the output module 20 from being mistakenly turned on due to abnormal increase in the potential of the second node. Ultimately, this ensures the accuracy of the timing output of the GOA circuit and significantly improves the display quality of the display panel.

[0094] In addition, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the GOA circuit of any of the above.

[0095] Furthermore, this application also provides a display device. Please refer to Figure 10, which is a schematic diagram of the structure of a display device according to an embodiment of this application. Specifically, the display device in this embodiment may be a device for locally running a GOA circuit driving method.

[0096] As shown in Figure 10, the display device in this embodiment may include: a display panel; or a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0097] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk storage device. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0098] Those skilled in the art will understand that the display device structure shown in FIG10 does not constitute a limitation on the display device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0099] As shown in Figure 10, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a charging driver.

[0100] In the display device shown in Figure 10, the processor 1001 can be used to call the charging driver stored in the memory 1005 and execute the steps of the GOA circuit driving method as described above.

[0101] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0102] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0103] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0104] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A GOA circuit, characterized in that, The GOA circuit includes: a transmission module, which includes a transmission transistor, the drain of which is electrically connected to a first node, and the source of which is electrically connected to a second node; an output module, the gate control terminal of which is electrically connected to the second node; and a potential control module, the two transmission terminals of which are electrically connected to the first node and a low-potential line, respectively, and the high-potential terminal of which is electrically connected to the high-potential line. The potential control module is configured to transmit the high-potential signal of the high-potential line to the first node during the transmission stage so that the transmission transistor can transmit the high-potential signal to the output module via the second node, and to transmit the low-potential signal of the low-potential line to the first node after the transmission is completed so that the potential of the second node, which is electrically connected to the source of the transmission transistor, is continuously pulled low. The transmission module also includes a third thin-film transistor, the first path terminal of which is electrically connected to the low-potential line, the second path terminal of which is electrically connected to the second node, and the gate of which is connected to the gate signal of the subsequent stage.

2. The GOA circuit as described in claim 1, characterized in that, The GOA circuit includes a low-potential control terminal, and the potential control module includes a first thin-film transistor and a second thin-film transistor. The first path terminal of the first thin-film transistor forms the high-potential terminal of the potential control module and is electrically connected to the high-potential line. The gate terminal of the first thin-film transistor is electrically connected to the gate signal terminal of the previous stage. The second path terminal of the first thin-film transistor forms one of the two transmission terminals and is electrically connected to the first node. The first path terminal of the second thin-film transistor is electrically connected to the first node. The second path terminal of the second thin-film transistor forms the other transmission terminal of the two transmission terminals and is electrically connected to the low-potential line. The gate terminal of the second thin-film transistor is electrically connected to the low-potential control terminal.

3. The GOA circuit as described in claim 2, characterized in that, When the low-voltage control terminal is any one of the current stage gate signal terminal, the subsequent stage gate signal terminal, and the timing control terminal, the gate of the stage transistor is electrically connected to the previous stage gate signal terminal.

4. The GOA circuit as described in claim 2, characterized in that, When the low-potential control terminal is the gate signal terminal of the subsequent stage, the gate of the stage transistor is electrically connected to the drain of the stage transistor.

5. The GOA circuit as described in claim 1, characterized in that, The output module includes a fourth thin-film transistor and a capacitor. The gate terminal of the fourth thin-film transistor and the first terminal of the capacitor are electrically connected to the second node. The first path terminal of the fourth thin-film transistor is electrically connected to the timing control terminal. The second path terminal of the fourth thin-film transistor and the second terminal of the capacitor are respectively electrically connected to the current stage gate signal terminal.

6. A method for driving a GOA circuit, characterized in that, The GOA circuit driving method is applied to the GOA circuit according to any one of claims 1 to 5. The GOA circuit driving method includes: in the stage of stage transmission, transmitting a high-potential signal of a high-potential line to a first node through a potential control module so that the stage transmission transistor in the stage transmission module transmits the high-potential signal to the output module via a second node; after stage transmission is completed, transmitting a low-potential signal of a low-potential line to the first node through the potential control module so that the potential of the second node, which is electrically connected to the source of the stage transmission transistor, is continuously pulled low.

7. The GOA circuit driving method as described in claim 6, characterized in that, The potential control module includes a second thin-film transistor, and the cascade transmission module includes a third thin-film transistor. The step of transmitting the low-potential signal of the low-potential line to the first node through the potential control module to continuously pull down the potential of the second node, which is electrically connected to the source of the cascade transmission transistor, includes: when both the gate signal at the gate signal terminal and the pull-down control signal at the potential pull-down control terminal are at active levels, enabling the third thin-film transistor to transmit the low-potential signal of the low-potential line to the second node, which is electrically connected to the source of the cascade transmission transistor, under the drive of the gate signal at ...

8. The GOA circuit driving method as described in claim 7, characterized in that, The step of maintaining the potential of the second node continuously low based on the low potential signals connected to the first node and the second node includes: in response to the front-stage gate signal provided to the gate of the cascade transistor from the front-stage gate signal terminal switching from an effective level to an ineffective level, determining that the gate potential of the cascade transistor is the low potential of the ineffective level, the drain potential of the cascade transistor is the low potential signal connected to the first node, and the drain potential of the cascade transistor is the low potential signal connected to the second node, so as to maintain the off state of the cascade transistor; enabling the potential of the second node to be continuously low in the off state.

9. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes the GOA circuit according to any one of claims 1 to 5.

10. A display device, characterized in that, The display device includes the display panel of claim 9; or, a memory, a processor, and a charging driver stored in the memory and executable on the processor, wherein the processor, when executing the charging driver, implements the steps of the GOA circuit driving method of any one of claims 6 to 8.

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