Semiconductor structure, preparation method of semiconductor structure and double-gate semiconductor device
By bringing out the source and drain contact layers from opposite sides of the wafer in the semiconductor structure, the problem of low switching efficiency caused by parasitic capacitance in MOS devices is solved, achieving higher switching performance and signal transmission efficiency.
Patent Information
- Application Number
- CN202512059417.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-03
AI Technical Summary
Existing MOS devices suffer from low switching efficiency due to parasitic capacitance, especially after the technology node is below 90nm, the RC delay problem caused by parasitic capacitance becomes more significant.
By employing a semiconductor structure design, the source and drain contact layers are led out from opposite sides of the wafer and connected to the metal interconnect layer through conductive vias, thus avoiding the formation of parallel plate capacitors and reducing parasitic capacitance.
It significantly reduces parasitic capacitance, improves the switching performance of semiconductor devices, reduces energy loss during signal transmission, and enhances current drive capability and long-term reliability.
Smart Images
Figure CN121793397A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, specifically to a semiconductor structure, a method for fabricating the semiconductor structure, and a dual-gate semiconductor device. Background Technology
[0002] In fields such as electronics, communications, and power control, metal-oxide-semiconductor field-effect transistors (MOS transistors) are one of the core components of signal processing. For example, N-type MOS transistors and P-type MOS transistors can be combined to form a complementary metal-oxide-semiconductor (CMOS) inverter to achieve the conversion between logic 1 and logic 0.
[0003] MOS devices, with their three terminals—source (S), drain (D), and gate (G)—are typically connected to a metal interconnect layer on the same side (the front side of the wafer) due to planar fabrication processes. However, a potential difference exists between these three terminals during operation. Consequently, each pair of terminals forms a parallel-plate capacitor, resulting in parasitic capacitance. This parasitic capacitance causes switching delay, reducing the switching efficiency of the MOS device. Especially at technology nodes smaller than 90nm, the resistive-capacitive (RC) delay caused by parasitic capacitance may further increase, even exceeding the delay caused by the MOS device itself. Summary of the Invention
[0004] This invention provides a semiconductor structure, a method for fabricating the semiconductor structure, and a dual-gate semiconductor device to solve the problem of low switching efficiency of MOS devices caused by parasitic capacitance.
[0005] In a first aspect, the present invention provides a semiconductor structure comprising: a first substrate, a first dielectric layer, a device layer, and a second dielectric layer stacked from bottom to top; the first dielectric layer covering a front gate contact layer; the device layer including a plurality of shallow trench isolation structures spaced apart and an active region located between the shallow trench isolation structures; the active region forming an active electrode contact layer and a drain contact layer; and the second dielectric layer covering a back gate structure and a back gate contact layer located on the back gate structure; the front gate contact layer and the source contact layer are led out from the first dielectric layer and connected to a metal interconnect layer, and the drain contact layer and the back gate contact layer are led out from the second dielectric layer and connected to the metal interconnect layer; or, the front gate contact layer and the drain contact layer are led out from the first dielectric layer and connected to the metal interconnect layer, and the source contact layer and the back gate contact layer are led out from the second dielectric layer and connected to the metal interconnect layer.
[0006] The semiconductor structure provided by this invention has source and drain contact layers that are not led out from the same side, but from two sides of the wafer respectively. This makes it difficult for parallel plate capacitors to be formed between the gate and the source (or drain) or between the source and the drain, thereby significantly reducing parasitic capacitance and improving the switching performance of the semiconductor device.
[0007] In one optional embodiment, the semiconductor structure further includes: a first conductive via and a second conductive via, both of which penetrate the first dielectric layer, the non-active region of the device layer, and the second dielectric layer; a first contact hole located in the first dielectric layer, a second contact hole penetrating the first dielectric layer, a third contact hole penetrating the second dielectric layer, and a fourth contact hole located in the second dielectric layer; when the front gate contact layer and the source contact layer are led out from the first dielectric layer and connected to the metal interconnect layer, one end of the first contact hole is connected to the front gate contact layer, and the other end is electrically connected to the metal interconnect layer through the first conductive via; one end of the second contact hole is connected to the source contact layer, and the other end is electrically connected to the metal interconnect layer through the second conductive via; one end of the third contact hole is connected to the drain contact layer, and the other end is connected to the metal interconnect layer; one end of the fourth contact hole is connected to the back gate contact layer, and the other end is connected to the metal interconnect layer.
[0008] In one alternative embodiment, when the front gate contact layer and drain contact layer are led out from the first dielectric layer and connected to the metal interconnect layer, one end of the first contact hole is connected to the front gate contact layer, and the other end is electrically connected to the metal interconnect layer through the first conductive hole; one end of the second contact hole is connected to the drain contact layer, and the other end is electrically connected to the metal interconnect layer through the second conductive hole; one end of the third contact hole is connected to the source contact layer, and the other end is connected to the metal interconnect layer.
[0009] In one optional embodiment, both the first conductive hole and the second conductive hole are tungsten through holes.
[0010] In this embodiment, tungsten has a lower resistivity than other metal materials, which can effectively reduce the series resistance of the via and reduce energy loss during signal transmission. The tungsten via uses titanium nitride as a barrier layer, which can effectively prevent tungsten atoms from diffusing with atoms in the dielectric layer (such as silicon atoms and oxygen atoms) and improve contact stability.
[0011] In a second aspect, the present invention provides a method for fabricating a semiconductor structure, comprising: providing an initial semiconductor structure and a first substrate, wherein the initial semiconductor structure includes a second substrate, a buried oxide layer, a second dielectric layer, a device layer, and a first dielectric layer stacked from bottom to top, the first dielectric layer covering a front gate contact layer, the device layer including a plurality of spaced shallow trench isolation structures and an active region located between the shallow trench isolation structures, the active region forming an active electrode contact layer and a drain contact layer, the second dielectric layer covering a back gate structure and a back gate contact layer located on the back gate structure; bonding the side of the first dielectric layer away from the second substrate to the first substrate; removing the second substrate after the bonding process; forming a third dielectric layer on the side of the buried oxide layer away from the second dielectric layer; leading out the front gate contact layer and the source contact layer from the first dielectric layer, and leading out the drain contact layer and the back gate contact layer from the second dielectric layer; or, leading out the front gate contact layer and the drain contact layer from the first dielectric layer, and leading out the source contact layer and the back gate contact layer from the second dielectric layer.
[0012] In an optional embodiment, the method for fabricating the semiconductor structure further includes: before bonding, performing a first etching process on the first dielectric layer to form a first contact hole and a second contact hole, wherein the first contact hole is connected to the front gate contact layer and the second contact hole penetrates the first dielectric layer; after removing the second substrate, performing a second etching process on the third dielectric layer to form a third contact hole, a fourth contact hole, a first conductive hole, and a second conductive hole, wherein both the first conductive hole and the second conductive hole penetrate the third dielectric layer, the buried oxide layer, the second dielectric layer, the non-active region of the device layer, and the first dielectric layer; wherein the first conductive hole is electrically connected to the first contact hole, the second conductive hole is electrically connected to the second contact hole, and the fourth contact hole is connected to the back gate contact layer; wherein, when the source contact layer is led out from the first dielectric layer, the second contact hole is connected to the source contact layer, and the third contact hole is connected to the drain contact layer.
[0013] In one alternative embodiment, when the drain contact layer is led out from the first dielectric layer, the second contact hole is connected to the drain contact layer, and the third contact hole is connected to the source contact layer.
[0014] In an optional embodiment, before forming the initial semiconductor structure, the method for fabricating the semiconductor structure further includes: obtaining a first semiconductor structure, wherein the first semiconductor structure includes a third substrate, a barrier layer, and an initial device layer stacked from bottom to top; forming a first oxide layer, a back gate structure, a back gate contact layer, and a second dielectric layer on the side of the initial device layer away from the barrier layer; performing ion implantation on the side of the second dielectric layer away from the third substrate to form a first ion damage layer on the third substrate; performing bonding and annealing processes on the side of the second dielectric layer away from the third substrate and the side of the second substrate where the buried oxide layer is formed; removing the remaining third substrate and barrier layer after the annealing process; forming a plurality of spaced shallow trench isolation structures and an active region located in the shallow trench isolation structures within the initial device layer, and forming a source contact layer, a drain contact layer, and a front gate structure located on the active region in the active region to obtain the initial semiconductor structure.
[0015] In an optional embodiment, before forming the initial semiconductor structure, the method for fabricating the semiconductor structure further includes: obtaining a second semiconductor structure, wherein the second semiconductor structure includes a fourth substrate, a doped layer, and an initial device layer stacked from bottom to top, the doping concentration of the doped layer being greater than the doping concentration of the initial device layer; forming a first oxide layer, a back gate structure, a back gate contact layer, and a second dielectric layer on the side of the initial device layer away from the doped layer; performing ion implantation on the side of the second dielectric layer away from the fourth substrate to form a second ion-damaged layer in the doped layer; performing bonding and annealing on the side of the second dielectric layer away from the fourth substrate and the side of the second substrate where the buried oxide layer is formed; removing the remaining doped layer after the annealing; forming a plurality of spaced shallow trench isolation structures and an active region located in the shallow trench isolation structures within the initial device layer, and forming a source contact layer, a drain contact layer, and a front gate structure located on the active region in the active region to obtain the initial semiconductor structure.
[0016] Thirdly, the present invention provides a dual-gate semiconductor device, which includes the semiconductor structure of the first aspect or any corresponding embodiment described above. Attached Figure Description
[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of a conventional semiconductor structure; Figure 2This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of another semiconductor structure according to an embodiment of the present invention; Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 5 This is a schematic diagram of an initial semiconductor structure according to an embodiment of the present invention; Figure 6 This is a schematic diagram of another initial semiconductor structure according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the first substrate according to an embodiment of the present invention; Figure 8 This is a schematic diagram of an initial semiconductor structure and a first substrate bonded according to an embodiment of the present invention; Figure 9 This is a schematic diagram of another initial semiconductor structure and a first substrate bonded according to an embodiment of the present invention; Figure 10 Is Figure 8 A schematic diagram after removing the second substrate; Figure 11 Is Figure 9 A schematic diagram after removing the second substrate; Figure 12 Is Figure 10 A schematic diagram showing the formation of the third dielectric layer based on the existing structure. Figure 13 Is Figure 11 A schematic diagram showing the formation of the third dielectric layer based on the existing structure. Figure 14 Is Figure 12 A schematic diagram showing the formation of the third and fourth contact holes based on this; Figure 15 Is Figure 13 A schematic diagram showing the formation of the third and fourth contact holes based on this; Figure 16 This is a schematic diagram of a first semiconductor structure according to an embodiment of the present invention; Figure 17 Is Figure 16 A schematic diagram showing the formation of a first oxide layer, a back gate structure, a back gate contact layer, and a second dielectric layer based on the above. Figure 18 Is Figure 17 A schematic diagram of the ion implantation process performed on the basis of the above. Figure 19 It is Figure 18 A schematic diagram of bonding to a second substrate having a buried oxide layer; Figure 20 Is Figure 19 A schematic diagram showing the removal of the remaining third substrate and barrier layer based on the above. Figure 21 This is a schematic diagram of the second semiconductor structure according to an embodiment of the present invention; Figure 22 Is Figure 21 A schematic diagram showing the formation of a first oxide layer, a back gate structure, a back gate contact layer, and a second dielectric layer based on the above. Figure 23 Is Figure 22 A schematic diagram of the ion implantation process performed on the basis of the above. Figure 24 It is Figure 23 A schematic diagram of bonding to a second substrate having a buried oxide layer.
[0019] Reference numerals: 101, Source contact layer; 102, Drain contact layer; 103, Front gate contact layer; 104, First substrate; 105, First dielectric layer; 106, Device layer; 1061, Shallow trench isolation structure; 1062, Active region; 107, Second dielectric layer; 108, Back gate structure; 109, Back gate contact layer; 110, Well region; 111, Source region; 112, Drain region; 113, First gate oxide layer; 114, Gate structure; 115, Second gate oxide layer. 116. First conductive via; 117. Second conductive via; 118. First contact via; 119. Second contact via; 120. Third contact via; 121. Fourth contact via; 122. Sidewall structure; 123. Second substrate; 124. Buried oxide layer; 125. Third dielectric layer; 126. Third substrate; 1261. First ion damage layer; 127. Barrier layer; 128. Initial device layer; 129. Fourth substrate; 130. Doped layer; 1301. Second ion damage layer. Detailed Implementation
[0020] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the invention, not the entire structure.
[0021] In the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the invention. Various structural schematic diagrams according to embodiments of the invention are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity, and some details may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0022] A schematic diagram of a MOS device can be shown as follows: Figure 1 As shown, following the fabrication logic of planar technology, the source contact layer 101, drain contact layer 102, and front gate contact layer 103 are typically led out (connected) from the same side through contact holes (CTs). However, when a MOS device is operating, there is a potential difference between the three ports, which may cause parasitic capacitances to form parallel-plate capacitors between the three ports, for example, as... Figure 1 The gate-source capacitance C shown GS and gate-drain capacitance C GD The presence of parasitic capacitance can cause switching delays, thereby reducing the switching efficiency of MOS devices.
[0023] In view of this, the present invention provides a semiconductor structure, a method for fabricating the semiconductor structure, and a dual-gate semiconductor device. By introducing back-side engineering, the source contact layer 101 of the source and the drain contact layer 102 of the drain are led out from the front and back sides of the wafer, respectively, thereby making it difficult to form a parallel plate capacitor between the gate and the source (or drain) and between the source and the drain, and significantly reducing parasitic capacitance.
[0024] It should be noted that, in order to optimize device performance, this invention forms semiconductor devices such as MOS on a silicon-on-insulator (SOI) substrate containing a back gate structure. The back gate structure can be set in a buried oxide layer. Through the back gate structure, the threshold voltage of the semiconductor device can be adjusted, and key radio frequency (RF) performance indicators such as gain, noise and linearity of the semiconductor device can be flexibly optimized.
[0025] The semiconductor structure provided by the present invention will now be described in detail with reference to the accompanying drawings.
[0026] like Figure 2 As shown, the semiconductor structure provided by the present invention includes a first substrate 104, a first dielectric layer 105, a device layer 106, and a second dielectric layer 107 stacked from bottom to top. The first dielectric layer 105 covers the front gate contact layer 103. The device layer 106 includes a plurality of shallow trench isolation (STI) structures 1061 spaced apart and an active region 1062 located between two adjacent shallow trench isolation structures. The active region 1062 forms an active electrode contact layer 101 and a drain contact layer 102. The second dielectric layer 107 covers a back gate structure 108 and a back gate contact layer 109 located on the back gate structure 108.
[0027] For example, the first substrate 104 can be a silicon substrate, the first dielectric layer 105 and the second dielectric layer 107 can be silicon dioxide, and the shallow trench isolation structure 1061 includes a shallow trench and an insulating material (such as silicon dioxide) filled in the shallow trench. The shallow trench isolation structure 1061 is used to isolate adjacent MOS transistors or other active regions to avoid crosstalk of current or signals and ensure the independence of each transistor unit.
[0028] The source contact layer 101 is a metal silicide layer formed in the source region, the drain contact layer 102 is a metal silicide layer formed on the surface of the drain region, and the front gate contact layer 103 and the back gate contact layer 109 are metal silicide layers formed on the gate surface. These features can reduce the contact resistance of the electrodes and improve the current drive capability of the semiconductor device.
[0029] Specifically, the active region 1062 is located between two adjacent shallow trench isolation structures 1061. The active region 1062 includes a well region 110, a source region 111, and a drain region 112. The source region 111 and the drain region 112 are located at opposite ends of the well region 110. The source contact layer 101 is disposed on the source region 111, and the drain contact layer 102 is disposed on the drain region 112. A first gate oxide layer 113 and a gate structure 114 located on one side of the first gate oxide layer 113 are disposed on the side of the active region 1062 closest to the first dielectric layer 105. A front gate contact layer 103 is disposed on the gate structure 114. The first dielectric layer 105 is formed after the front gate contact layer 103 and covers the first gate oxide layer 113, the gate structure 114, and the front gate contact layer 103. A second gate oxide layer 115 is disposed on the side of the active region 1062 near the second dielectric layer 107. The back gate structure 108 is located on the second gate oxide layer 115. The second dielectric layer 107 is formed after the back gate contact layer 109 and covers the second gate oxide layer 115, the back gate structure 108 and the back gate contact layer 109.
[0030] The first gate oxide layer 113 and the second gate oxide layer 115 are insulating layers and can be made of silicon dioxide. The gate structure 114 can be made of polysilicon, metal, or metal silicide. The source and drain regions are typically heavily doped N-type or P-type semiconductor regions. The source region 111 provides charge carriers (electrons or holes), and the drain region 112 receives charge carriers, thus forming a current path when the transistor is operating. The conductivity type (N-type or P-type) of the source region 111 and the drain region 112 depends on the type of MOSFET (N-type MOSFET or P-type MOSFET).
[0031] The gate structure 114 is used to control the conductivity state of the channel when a voltage is applied. When the gate voltage is higher than the threshold voltage, the conductive channel formed by the active region 1062 is in the on state, allowing current to flow from the source region to the drain region; when the gate voltage is lower than the threshold voltage, the conductive channel is closed, preventing current flow.
[0032] In this invention, the source contact layer 101 and the drain contact layer 102 are not led out from the same side, but from two different sides of the wafer. For example, as Figure 2 As shown, in the semiconductor structure, the front gate contact layer 103 and source contact layer 101 are led out from the first dielectric layer 105 and connected to the metal interconnect layer (not shown in the figure), while the drain contact layer 102 and back gate contact layer 109 are led out from the second dielectric layer 107 and connected to the metal interconnect layer. Alternatively, as... Figure 3 As shown, the front gate contact layer 103 and drain contact layer 102 are led out from the first dielectric layer 105 and connected to the metal interconnect layer, and the source contact layer 101 and back gate contact layer 109 are led out from the second dielectric layer 107 and connected to the metal interconnect layer.
[0033] The semiconductor structure provided by the present invention has a source contact layer 101 and a drain contact layer 102 that are not led out from the same side, but are led out from two sides of the wafer respectively. This makes it difficult for a parallel plate capacitor to be formed between the gate and the source (or drain) and between the source and the drain, thereby greatly reducing parasitic capacitance and improving the switching performance of the semiconductor device.
[0034] In order to bring out the source contact layer 101 and the drain contact layer 102 from different surfaces, such as Figure 2 and Figure 3 As shown, the semiconductor structure also includes a first conductive hole 116, a second conductive hole 117, a first contact hole 118, a second contact hole 119, a third contact hole 120, and a fourth contact hole 121.
[0035] Specifically, the first conductive hole 116 and the second conductive hole 117 both penetrate the non-active region of the first dielectric layer 105, the device layer 106, and the second dielectric layer 107. The non-active region of the device layer 106 can be the area where multiple shallow trench isolation structures 1061 are located. The first conductive hole 116 and the second conductive hole 117 respectively pass through the insulating material filled in the shallow trench isolation structures 1061 on both sides of the active region. The first contact hole 118 is located in the first dielectric layer 105, the second contact hole 119 penetrates the first dielectric layer 105, the third contact hole 120 penetrates the second dielectric layer 107, and the fourth contact hole 121 is located in the second dielectric layer 107. The first contact hole 118, the second contact hole 119, the third contact hole 120, and the fourth contact hole 121 are filled with conductive material, which can be a metal material such as tungsten.
[0036] When the front gate contact layer 103 and source contact layer 101 are led out from the first dielectric layer 105 and connected to the metal interconnect layer, such as Figure 2 As shown, one end of the first contact hole 118 is connected to the front gate contact layer 103, and the other end is electrically connected to the metal interconnect layer through the first conductive hole 116. One end of the second contact hole 119 is connected to the source contact layer 101, and the other end is electrically connected to the metal interconnect layer through the second conductive hole 117. One end of the third contact hole 120 is connected to the drain contact layer 102, and the other end is connected to the metal interconnect layer. One end of the fourth contact hole 121 is connected to the back gate contact layer 109, and the other end is connected to the metal interconnect layer.
[0037] When the front gate contact layer 103 and drain contact layer 102 are led out from the first dielectric layer 105 and connected to the metal interconnect layer, such as Figure 3 As shown, one end of the first contact hole 118 is connected to the front gate contact layer 103, and the other end is electrically connected to the metal interconnect layer through the first conductive hole 116. One end of the second contact hole 119 is connected to the drain contact layer 102, and the other end is electrically connected to the metal interconnect layer through the second conductive hole 117. One end of the third contact hole 120 is connected to the source contact layer 101, and the other end is connected to the metal interconnect layer. One end of the fourth contact hole 121 is connected to the back gate contact layer 109, and the other end is connected to the metal interconnect layer.
[0038] For example, both the first conductive hole 116 and the second conductive hole 117 are tungsten through-holes. Tungsten has a lower resistivity than other metal materials, which can effectively reduce the series resistance of the through-hole and reduce energy loss during signal transmission. The tungsten through-hole uses titanium nitride (TiN) as a barrier layer, which can effectively prevent tungsten atoms from diffusing with atoms in the dielectric layer (such as silicon atoms and oxygen atoms) and improve contact stability.
[0039] Optionally, the source contact layer 101, drain contact layer 102, front gate contact layer 103, and back gate contact layer 109 can be nickel cobalt silicon compounds (such as NiCoSi). Nickel cobalt silicon compounds have lower resistivity than single metal silicides, which can effectively reduce the contact resistance between the electrode and the silicon substrate. Moreover, nickel cobalt compounds have better melting point and thermal stability than single metal silicides. They are less prone to agglomeration or decomposition in subsequent high-temperature processes (such as annealing and metal wiring), thus maintaining a stable contact interface, reducing contact resistance degradation, and improving the long-term reliability of semiconductor devices.
[0040] For example, such as Figure 2 and Figure 3 As shown, the semiconductor structure also includes a spacer structure 122 located at both ends of the gate structure 114 and the front gate contact layer 103. The spacer structure 122 may include a polysilicon oxide layer and a silicon nitride (SiN) layer, with the polysilicon oxide layer bonded to the gate structure 114 and the front gate contact layer 103.
[0041] This embodiment also provides a method for fabricating a semiconductor structure. The method for fabricating the semiconductor structure provided in any of the above embodiments will be described in detail below with reference to the accompanying drawings. Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention, as shown below. Figure 4 As shown, the process includes the following steps: Step S401, providing an initial semiconductor structure and a first substrate.
[0042] Among them, such as Figure 5 or Figure 6 As shown, the initial semiconductor structure includes a second substrate 123, a buried oxide layer 124, a second dielectric layer 107, a device layer 106, and a first dielectric layer 105 stacked from bottom to top. The first dielectric layer 105 covers the front gate contact layer 103. The device layer 106 includes a plurality of shallow trench isolation structures 1061 spaced apart and an active region 1062 located between the shallow trench isolation structures. The active region 1062 forms an active electrode contact layer 101 and a drain contact layer 102. The second dielectric layer 107 covers the back gate structure 108, the back gate contact layer 109, and the second gate oxide layer 115.
[0043] like Figure 7 As shown, the first substrate 104 can be a silicon substrate.
[0044] Step S402: Bond the side of the first dielectric layer away from the second substrate to the first substrate.
[0045] For example, firstly, at room temperature, the surface of the first dielectric layer 105 away from the second substrate 123 and the surface of the first substrate are pre-bonded to form a temporary connection; then, the bonded initial semiconductor structure and the first substrate are annealed, and the atomic diffusion and chemical reaction are activated by high temperature to transform the pre-bonded temporary connection into a stable chemical bond, while eliminating residual moisture and bubbles at the interface, improving the bonding strength and reliability, resulting in... Figure 8 or Figure 9 The semiconductor structure shown.
[0046] In some embodiments, prior to prebonding, the bonding interface of the initial semiconductor structure (the side of the first dielectric layer away from the second substrate) and the bonding interface of the first substrate are pretreated, such as by cleaning and surface activation.
[0047] Surface activation of the bonding interface (such as plasma activation) can generate active groups at the bonding interface, providing chemical binding sites for subsequent bonding, or break the surface atomic valence bonds through physical methods to enhance the attraction between atoms.
[0048] Step S403: After the bonding process, the second substrate is removed.
[0049] Specifically, after the bonding process, the second substrate 123 can be removed by processes such as wet etching, mechanical chemical polishing, or dry etching, stopping at the buried oxide layer 124, to obtain the desired result. Figure 10 or Figure 11 The semiconductor structure shown.
[0050] Step S404: A third dielectric layer is formed on the side of the buried oxygen layer away from the second dielectric layer.
[0051] For example, such as Figure 12 or Figure 13 As shown, a third dielectric layer 125 can be formed on the buried oxide layer 124 by chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. The material of the third dielectric layer 125 can be silicon dioxide.
[0052] Step S405: The front gate contact layer and the source contact layer are led out from the first dielectric layer, and the drain contact layer and the back gate contact layer are led out from the second dielectric layer; or, the front gate contact layer and the drain contact layer are led out from the first dielectric layer, and the source contact layer and the back gate contact layer are led out from the second dielectric layer.
[0053] Specifically, in order to bring out the source contact layer 101 and the drain contact layer 102 from different surfaces, step S405 includes: Step a1: Before the bonding process, the first dielectric layer is etched to form the first contact hole and the second contact hole.
[0054] The first contact hole 118 connects to the front gate contact layer 103, and the second contact hole 119 penetrates the first dielectric layer 105. When the source contact layer 101 is led out from the first dielectric layer 105, as... Figure 5 As shown, the second contact hole 119 connects to the source contact layer 101; when the drain contact layer 102 is led out from the first dielectric layer 105, as... Figure 6 As shown, the second contact hole 119 is connected to the drain contact layer 102.
[0055] For example, photolithography and anisotropic etching can be used to form the first contact hole 118 and the second contact hole 119 in the first dielectric layer. Specifically, photoresist is first coated on the first dielectric layer to form a photoresist layer. Then, the photoresist layer is exposed and developed to form a mask pattern with openings at the locations of the first and second contact holes. Then, plasma dry etching is performed on the first dielectric layer using the mask pattern. The etching endpoint of the opening corresponding to the first contact hole is the front gate contact layer, and the etching endpoint of the opening corresponding to the second contact hole is the source contact layer or the drain contact layer. After forming the first and second contact holes, conductive material is filled into the first and second contact holes.
[0056] Step a2: After removing the second substrate, the third dielectric layer is etched a second time to form a third contact hole, a fourth contact hole, a first conductive hole, and a second conductive hole.
[0057] Specifically, photolithography and anisotropic etching can be used to form a structure like the third dielectric layer 125. Figure 14 or Figure 15 The third contact hole 120 and the fourth contact hole 121 are shown. The third contact hole 120 penetrates the third dielectric layer 125, the buried oxide layer 124 and the second dielectric layer 107. The fourth contact hole 121 is connected to the back gate contact layer 109. The third contact hole 120 and the fourth contact hole 121 are filled with conductive material.
[0058] When the source contact layer 101 is led out from the first dielectric layer 105, as Figure 14 As shown, the third contact hole 120 connects to the drain contact layer 102; when the drain contact layer 102 is led out from the first dielectric layer 105, as... Figure 15 As shown, the third contact hole 120 is connected to the source contact layer 101.
[0059] After forming the third and fourth contact holes, photolithography and anisotropic etching can be used to form the first and second conductive holes in the third dielectric layer. For example... Figure 2 and Figure 3As shown, the first conductive hole 116 and the second conductive hole 117 both penetrate the third dielectric layer 125, the buried oxide layer 124, the second dielectric layer 107, the non-active region of the device layer 106 and the first dielectric layer 105. The first conductive hole 116 is electrically connected to the first contact hole 118, and the second conductive hole 117 is electrically connected to the second contact hole 119.
[0060] In some embodiments, the method for fabricating the semiconductor structure further includes: forming a metal interconnect layer on the side of the third dielectric layer away from the buried oxide layer, wherein the metal interconnect layer connects a third contact hole, a fourth contact hole, a first conductive hole, and a second conductive hole. The method of forming the metal interconnect layer is the same as the conventional method for forming metal interconnect layers in the art, and will not be specifically described here.
[0061] In some embodiments, the method for fabricating the semiconductor structure further includes, prior to forming the initial semiconductor structure: Step b1: Obtain the first semiconductor structure.
[0062] Among them, such as Figure 16 As shown, the first semiconductor structure includes a third substrate 126, a barrier layer 127, and an initial device layer 128 stacked from bottom to top.
[0063] For example, the third substrate 126 can be a silicon substrate. The third substrate 126 is equivalent to a temporary carrier, serving as the support for the barrier layer 127 and the initial device layer 128, and will eventually be removed. The initial device layer 128 can be monocrystalline silicon. The present invention does not limit the material of the barrier layer 127, as long as the initial device layer 128 with uniformity meeting the processing requirements can be formed on the barrier layer 127, and the etching rate of the etching solution on the third substrate 126, the barrier layer 127, and the initial device layer 128 is different. For example, the material of the barrier layer 127 can be a silicon (Si) germanium (Ge) alloy or a boron (B) doped silicon-germanium alloy.
[0064] Step b2: A first oxide layer, a back gate structure, a back gate contact layer, and a second dielectric layer are formed on the side of the initial device layer away from the barrier layer.
[0065] Specifically, such as Figure 17 As shown, silicon dioxide can be grown on the side of the initial device layer away from the barrier layer based on a thermal oxidation process to form a first oxide layer. Then, a polysilicon layer and a metal silicide layer are sequentially deposited on the first oxide layer. The polysilicon layer, the metal silicide layer and the first oxide layer are processed by a photolithography etching process to form a second gate oxide layer, a back gate structure and a back gate contact layer. Then, a second dielectric layer covering the second gate oxide layer, the back gate structure and the back gate contact layer is formed on the first oxide layer.
[0066] Step b3 involves performing ion implantation on the side of the second dielectric layer away from the third substrate to form a first ion-damaged layer on the third substrate.
[0067] Specifically, upon obtaining such Figure 17 After the structure shown, ion implantation can be performed on the surface of the second dielectric layer away from the third substrate using an ion implanter to form a structure within the third substrate 126 as shown. Figure 18 The first ion-damaged layer 1261 is shown. The ion implantation type during ion implantation can be hydrogen (H) ions or helium (He) ions.
[0068] It should be understood that due to the different materials of the back gate structure and the second dielectric layer, there is a difference in ion implantation depth. Therefore, the first ion damage layer 1261 is not flush.
[0069] Step b4 involves bonding and annealing the side of the second dielectric layer away from the third substrate and the side of the second substrate where the buried oxide layer is formed.
[0070] Specifically, the bonding process is used to bond such as Figure 18 The structure shown is combined with a second substrate having a buried oxide layer to obtain, as shown below. Figure 19 The bonding structure shown is then placed in a heating furnace for annealing. After annealing, the third substrate separates at the first ion-damaged layer 1261.
[0071] Step b5: After annealing, remove the remaining third substrate and barrier layer.
[0072] Specifically, after annealing, the side of the third substrate furthest from the second dielectric layer is first chemically and mechanically polished to obtain a smooth surface; then, a first chemical solution is used to etch the third substrate and the barrier layer to remove the third substrate; after removing the third substrate, a second chemical solution is used to etch the barrier layer and the initial device layer to remove the barrier layer, resulting in the desired surface. Figure 20 The structure shown.
[0073] The first chemical solution exhibits a high selectivity for the third substrate and the barrier layer, while the second chemical solution exhibits a high selectivity for the barrier layer and the initial device layer. In other words, the etching rate of the first chemical solution on the third substrate is greater than that on the barrier layer, and the etching rate of the second chemical solution on the barrier layer is greater than that on the initial device layer. For example, the ratio of the etching rate of the first chemical solution on the third substrate to that on the barrier layer is greater than a preset value (such as 10, 15, or 20), and the ratio of the etching rate of the second chemical solution on the barrier layer to that on the initial device layer is also greater than a preset value.
[0074] When the barrier layer material is a silicon-germanium alloy, the first chemical solution can be a mixed solution of ammonium hydroxide (NH4OH) and deionized water. The first chemical solution can corrode all the third substrates on the barrier layer and stop at the barrier layer. The second chemical solution can be a mixed solution of nitric acid (or hydrogen peroxide), hydrofluoric acid (HF) and water. The second chemical solution can corrode all the barrier layers on the initial device layer and stop at the initial device layer.
[0075] Step b6: A plurality of shallow trench isolation structures spaced apart and an active region located between the shallow trench isolation structures are formed in the initial device layer, and a source contact layer, a drain contact layer and a front gate structure located on the active region are formed in the active region to obtain the initial semiconductor structure.
[0076] Specifically, upon obtaining such Figure 20 After the SOI substrate with the back gate structure shown, a shallow trench isolation structure and an active region are formed on the SOI substrate with the back gate structure, and CMOS and other devices are formed in the active region. The initial device layer with the shallow trench isolation structure and active region is the device layer.
[0077] In other embodiments, the method for fabricating the semiconductor structure further includes, prior to forming the initial semiconductor structure: Step c1: Obtain the second semiconductor structure.
[0078] Among them, such as Figure 21 As shown, the second semiconductor structure includes a fourth substrate 129, a doped layer 130, and an initial device layer 128 stacked from bottom to top, with the doping concentration of the doped layer being greater than that of the initial device layer.
[0079] For example, the fourth substrate 129 can be a silicon substrate, the doped layer 130 can be a heavily p-type doped layer, and the initial device layer 128 can be a lightly p-type epitaxial layer. Both the doped layer 130 and the initial device layer 128 are silicon layers doped with p-type elements, but the doping concentration of the doped layer 130 is greater than that of the initial device layer 128. The difference in concentration creates a difference in etch rate, which facilitates the removal of the doped layer without damaging the initial device layer 128.
[0080] Step c2: A first oxide layer, a back gate structure, a back gate contact layer, and a second dielectric layer are formed on the side of the initial device layer away from the doped layer.
[0081] Specifically, such as Figure 22As shown, silicon dioxide can be grown on the side of the initial device layer away from the barrier layer based on a thermal oxidation process to form a first oxide layer. Then, a polysilicon layer and a metal silicide layer are sequentially deposited on the first oxide layer. The polysilicon layer, the metal silicide layer and the first oxide layer are processed by a photolithography etching process to form a second gate oxide layer, a back gate structure and a back gate contact layer. Then, a second dielectric layer covering the second gate oxide layer, the back gate structure and the back gate contact layer is formed on the first oxide layer.
[0082] Step c3 involves performing ion implantation on the side of the second dielectric layer away from the fourth substrate to form a second ion-damaged layer in the doped layer.
[0083] Specifically, ion implantation can be performed on the surface of the second dielectric layer away from the fourth substrate using an ion implanter to form a doped layer 130 such as Figure 23 The second ion-damaged layer 1301 is shown. The ion implantation type during ion implantation can be hydrogen (H) ions or helium (He) ions.
[0084] It should be understood that due to the different materials of the back gate structure and the second dielectric layer, there is a difference in ion implantation depth. Therefore, the second ion damage layer 1301 is not flush.
[0085] Step c4 involves bonding and annealing the side of the second dielectric layer away from the fourth substrate and the side of the second substrate where the buried oxide layer is formed.
[0086] Specifically, the bonding process is used to bond such as Figure 23 The structure shown is combined with a second substrate having a buried oxide layer to obtain the following: Figure 24 The bonding structure shown is then placed in a heating furnace for annealing. After annealing, the doped layer 130 separates at the second ion-damaged layer 1301.
[0087] Step c5: After annealing, remove the remaining doped layer.
[0088] Specifically, after annealing, the remaining doped layer is first chemically and mechanically polished to obtain a smooth surface; then a third chemical solution is used to etch the doped layer and the initial device layer to remove the doped layer.
[0089] The third chemical solution has a higher selectivity for the doped layer and the initial device layer, meaning that the corrosion rate of the third chemical solution on the doped layer is greater than that on the initial device layer. For example, the ratio of the corrosion rate of the third chemical solution on the doped layer to that on the initial device layer is greater than a preset value.
[0090] For example, the third chemical solution may be a mixture of tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) solution and propanol (IPA) solution, or other solutions.
[0091] Step c6: A plurality of shallow trench isolation structures spaced apart and an active region located between the shallow trench isolation structures are formed in the initial device layer, and a source contact layer, a drain contact layer and a front gate structure located on the active region are formed in the active region to obtain the initial semiconductor structure.
[0092] Specifically, after obtaining an SOI substrate with a back gate structure, a shallow trench isolation structure and an active region are formed on the SOI substrate with the back gate structure, and devices such as CMOS are formed in the active region. The initial device layer with the shallow trench isolation structure and the active region is the device layer.
[0093] Optionally, the step of removing the second substrate may include: Step d1: When the thickness of the second substrate is greater than the preset thickness, the second substrate is removed by a grinding and polishing process so that the thickness of the second substrate is less than or equal to the preset thickness.
[0094] Specifically, the grinding and polishing process includes mechanical grinding and chemical mechanical polishing (CMP). After the bonding process, the second substrate is ground and polished, and the thickness of the second substrate is monitored during the grinding process. When the thickness of the second substrate is less than or equal to the preset thickness, the grinding is stopped.
[0095] The preset thickness can range from 3μm to 10μm, for example, the preset thickness can be 3μm, 5μm, 8μm or 10μm. If the preset thickness is greater than 10μm, the removal efficiency is low; if the preset thickness is less than 3μm, the mechanical stress during grinding may be transmitted to the lower layer, causing lattice damage to the active region. The second substrate should retain at least 3μm to act as a buffer layer to protect the active region.
[0096] Step d2 involves removing the remaining second substrate using a wet etching process.
[0097] In the wet etching process, the etching solution has a higher etching rate on the second substrate than on the active region, thus avoiding damage to the active region.
[0098] In this embodiment, the second substrate is first removed using a grinding and polishing process until the thickness of the second substrate is less than or equal to a preset thickness. Then, a wet etching process is used to remove the remaining second substrate. This can improve the removal efficiency while avoiding damage to the active region.
[0099] This embodiment also provides a dual-gate semiconductor device, which includes the semiconductor structure provided in any of the above embodiments.
[0100] In the description of this specification, the references to terms such as "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples, without contradiction.
[0101] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0102] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be effectively combined.
[0103] The above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described above, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention.
[0104] Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention.
Claims
1. A semiconductor structure, characterized in that, include: The first substrate, the first dielectric layer, the device layer, and the second dielectric layer are stacked from bottom to top. The first dielectric layer covers the front gate contact layer. The device layer includes a plurality of shallow trench isolation structures spaced apart and an active region located between the shallow trench isolation structures. The active region forms an active electrode contact layer and a drain contact layer. The second dielectric layer covers the back gate structure and the back gate contact layer located on the back gate structure. The front gate contact layer and the source contact layer are led out from the first dielectric layer and connected to the metal interconnect layer, and the drain contact layer and the back gate contact layer are led out from the second dielectric layer and connected to the metal interconnect layer; or, the front gate contact layer and the drain contact layer are led out from the first dielectric layer and connected to the metal interconnect layer, and the source contact layer and the back gate contact layer are led out from the second dielectric layer and connected to the metal interconnect layer.
2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The first conductive hole and the second conductive hole both penetrate the first dielectric layer, the non-active region of the device layer and the second dielectric layer; A first contact hole located in the first dielectric layer, a second contact hole penetrating the first dielectric layer, a third contact hole penetrating the second dielectric layer, and a fourth contact hole located in the second dielectric layer; When the front gate contact layer and the source contact layer are led out from the first dielectric layer and connected to the metal interconnect layer, one end of the first contact hole is connected to the front gate contact layer, and the other end is electrically connected to the metal interconnect layer through the first conductive hole; one end of the second contact hole is connected to the source contact layer, and the other end is electrically connected to the metal interconnect layer through the second conductive hole; one end of the third contact hole is connected to the drain contact layer, and the other end is connected to the metal interconnect layer. One end of the fourth contact hole is connected to the back gate contact layer, and the other end is connected to the metal interconnect layer.
3. The semiconductor structure according to claim 2, characterized in that, When the front gate contact layer and the drain contact layer are led out from the first dielectric layer and connected to the metal interconnect layer, one end of the first contact hole is connected to the front gate contact layer, and the other end is electrically connected to the metal interconnect layer through the first conductive hole; one end of the second contact hole is connected to the drain contact layer, and the other end is electrically connected to the metal interconnect layer through the second conductive hole; one end of the third contact hole is connected to the source contact layer, and the other end is connected to the metal interconnect layer.
4. The semiconductor structure according to claim 2 or 3, characterized in that, Both the first conductive hole and the second conductive hole are tungsten through holes.
5. A method for fabricating a semiconductor structure, characterized in that, include: An initial semiconductor structure and a first substrate are provided, wherein the initial semiconductor structure includes a second substrate, a buried oxide layer, a second dielectric layer, a device layer and a first dielectric layer stacked from bottom to top, the first dielectric layer covering a front gate contact layer, the device layer including a plurality of spaced shallow trench isolation structures and an active region located between the shallow trench isolation structures, the active region forming an active electrode contact layer and a drain contact layer, and the second dielectric layer covering a back gate structure and a back gate contact layer located on the back gate structure; The side of the first dielectric layer away from the second substrate is bonded to the first substrate; After the bonding process, the second substrate is removed; A third dielectric layer is formed on the side of the buried oxide layer away from the second dielectric layer; The front gate contact layer and the source contact layer are led out from the first dielectric layer, and the drain contact layer and the back gate contact layer are led out from the second dielectric layer; or, the front gate contact layer and the drain contact layer are led out from the first dielectric layer, and the source contact layer and the back gate contact layer are led out from the second dielectric layer.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The method for preparing the semiconductor structure further includes: Before the bonding process, the first dielectric layer is etched to form a first contact hole and a second contact hole. The first contact hole is connected to the front gate contact layer, and the second contact hole penetrates the first dielectric layer. After removing the second substrate, the third dielectric layer is subjected to a second etching process to form a third contact hole, a fourth contact hole, a first conductive hole, and a second conductive hole. The first conductive hole and the second conductive hole both penetrate the third dielectric layer, the buried oxide layer, the second dielectric layer, the non-active region of the device layer, and the first dielectric layer. The first conductive hole is electrically connected to the first contact hole, the second conductive hole is electrically connected to the second contact hole, and the fourth contact hole is connected to the back gate contact layer. Wherein, when the source contact layer is led out from the first dielectric layer, the second contact hole is connected to the source contact layer, and the third contact hole is connected to the drain contact layer.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that, When the drain contact layer is led out from the first dielectric layer, the second contact hole connects to the drain contact layer, and the third contact hole connects to the source contact layer.
8. The method for preparing a semiconductor structure according to any one of claims 5 to 7, characterized in that, Prior to forming the initial semiconductor structure, the method for fabricating the semiconductor structure further includes: A first semiconductor structure is obtained, wherein the first semiconductor structure includes a third substrate, a barrier layer and an initial device layer stacked from bottom to top; A first oxide layer, the back gate structure, the back gate contact layer, and the second dielectric layer are formed on the side of the initial device layer away from the barrier layer; Ion implantation is performed on the side of the second dielectric layer away from the third substrate to form a first ion-damaged layer on the third substrate; Bonding and annealing processes are performed on the side of the second dielectric layer away from the third substrate and on the side of the second substrate where the buried oxide layer is formed. After annealing, the remaining third substrate and the barrier layer are removed; A plurality of shallow trench isolation structures spaced apart and an active region located between the shallow trench isolation structures are formed in the initial device layer, and a source contact layer, a drain contact layer and a front gate structure located on the active region are formed in the active region to obtain the initial semiconductor structure.
9. The method for preparing a semiconductor structure according to any one of claims 5 to 7, characterized in that, Prior to forming the initial semiconductor structure, the method for fabricating the semiconductor structure further includes: A second semiconductor structure is obtained, wherein the second semiconductor structure includes a fourth substrate, a doped layer and an initial device layer stacked from bottom to top, and the doping concentration of the doped layer is greater than the doping concentration of the initial device layer; A first oxide layer, the back gate structure, the back gate contact layer, and the second dielectric layer are formed on the side of the initial device layer away from the doped layer; Ion implantation is performed on the side of the second dielectric layer away from the fourth substrate to form a second ion-damaged layer in the doped layer; Bonding and annealing processes are performed on the side of the second dielectric layer away from the fourth substrate and on the side of the second substrate where the buried oxide layer is formed. After annealing, remove the remaining doped layer; A plurality of shallow trench isolation structures spaced apart and an active region located between the shallow trench isolation structures are formed in the initial device layer, and a source contact layer, a drain contact layer and a front gate structure located on the active region are formed in the active region to obtain the initial semiconductor structure.
10. A dual-gate semiconductor device, characterized in that, The dual-gate semiconductor device comprises the semiconductor structure according to any one of claims 1 to 4.