A self-biased split-gate bipolar transistor and a manufacturing method thereof

Abstract

The present application belongs to the technical field of power semiconductor devices, and relates to a self-bias split gate bipolar transistor and a manufacturing method thereof. The present application provides a bias potential for the split gate (11) through the potential of the floating P region (18), thereby forming the electron accumulation ability below the trench, enhancing the conductance modulation ability, and thus enhancing the forward conduction ability of the device. Compared with the traditional split gate structure, the diode and capacitor structure of the self-bias structure are integrated into the IGBT structure, which can simultaneously improve the conduction ability and switching performance of the device without affecting the device size and IGBT operation, eliminates the negative effects brought by the split gate, improves the switching loss and enhances the switching speed, optimizes the forward conduction ability of the device, and improves the compromise characteristics between the forward conduction voltage drop and the off-state loss of the device.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, and specifically relates to a self-biased split insulated gate bipolar transistor. Background Technology

[0002] The advent of electricity has spurred the rapid development of modern science and technology, and how to process electricity more efficiently has always been a hot topic in scientific research worldwide. The efficient utilization of electricity relies heavily on power electronic systems, and the core electronic components of various power electronic systems are semiconductor power devices. Semiconductor power devices are widely used in various household appliances and various industrial equipment that primarily use electricity. Since the beginning of the 21st century, global warming has received increasing attention, making energy conservation, emission reduction, and improved energy efficiency even more crucial. With the increasing proportion of clean and renewable energy sources, society as a whole has higher expectations for energy conversion efficiency, placing higher demands on the performance of power semiconductor devices, the core of energy control.

[0003] Insulated-gate bipolar transistors (IGBTs), as a new generation of power electronic devices, combine the advantages of field-effect transistors (MOSFETs) and bipolar junction transistors (BJTs). They possess the advantages of MOSFETs, such as ease of driving, low input impedance, and fast switching speed, while also having the advantages of BJTs, such as high on-state current density, low on-state voltage drop, low loss, and good stability. Therefore, they have become one of the core electronic components in modern power electronic circuits and are widely used in transportation, power grids, communications, home appliances, and aerospace. The application of IGBTs has greatly improved the performance of power electronic systems.

[0004] Since the invention of the IGBT, people have been committed to improving its performance. Over the past two decades, multiple generations of IGBT device structures have been proposed, resulting in a steady improvement in device performance. Traditional trench IGBTs (such as...) Figure 1 By transforming the gate from a lateral planar MOS structure to a vertical trench MOS structure, not only is power density and structural design space improved, but the adverse effects of the JFET region and the latch-up effect caused by parasitic NPN are also eliminated. Furthermore, a shielded-gate trench IGBT (such as...) is proposed based on the trench IGBT. Figure 2 The SGT structure features lower gate capacitance, resulting in faster switching speeds and lower switching losses. Furthermore, compared to the high peak electric field at the bottom of traditional trench gate structures, the SGT structure offers the advantage of optimized electric field and increased voltage withstand capability. Therefore, SGT-IGBTs have greater application value in high-reliability, high-performance applications. Figure 2This demonstrates a cellular structure of a traditional SGT-IGBT device. As an insulated gate controlled structure, the IGBT's gate attracts electrons in the non-channel region through the gate voltage while forming the channel, creating an electron accumulation layer and further reducing the forward voltage drop. However, in the SGT-IGBT, because the shielding gate is connected to the emitter, it cannot attract electrons to form an electron accumulation layer, resulting in a decrease in channel electron injection efficiency. Therefore, its conductivity modulation effect is weaker than that of a traditional trench IGBT, and the forward voltage drop is higher. Summary of the Invention

[0005] To reduce the on-state voltage drop and improve device performance, this invention proposes a three-dimensional self-biased split-gate insulated-gate bipolar transistor, as shown in the schematic diagram below. Figure 3 As shown in the diagram, this structure draws a potential from the floating P-region 18. When the IGBT is blocked, the capacitor is charged through surface-integrated polydiodes 14 and 15. When the IGBT is turned on, the voltage on the capacitor provides a self-biasing potential for SG, causing electron accumulation below the trench of the split gate 11, thereby enhancing the forward conduction capability of the IGBT device. Its equivalent circuit is shown in the diagram. Figure 4 As shown. Simultaneously, the separating gate 11 forms an internal field plate structure when blocked, optimizing the peak electric field at the bottom of the trench and improving the forward withstand voltage capability of the IGBT. Furthermore, the presence of the separating gate 11 weakens the capacitive effect between the gate and the collector, accelerating the switching speed of the IGBT, reducing the switching losses of the device, and further optimizing the device characteristics.

[0006] The technical solution of this invention is:

[0007] A self-biased split-gate bipolar transistor includes a collector metal 10, a P-type collector region 9, an N-type electric field blocking layer 8, an N-drift region 7, and an active region stacked sequentially from bottom to top. The active region includes a P-type base region 4 and a P-type region 20 located at both ends of the upper surface of the N-drift region 7, a trench gate structure located between the P-type base region 4 and the P-type region 20, a floating P-type region 18, and a trench emitter structure. The floating P-type region 18 is located between the trench gate structure and the trench emitter structure. The trench gate structure is in contact with the P-type base region 4, and the trench emitter structure is in contact with the P-type region 20. At the same time, the lower surface junction depth of the trench gate structure, the floating P-type region 18, and the trench emitter structure is greater than the lower surface junction depth of the P-type base region 4 and the P-type region 20.

[0008] The upper surface of the P-type base region 4 is provided with P+ emitter region 2 and N+ emitter region 3 arranged side by side, wherein the N+ emitter region 3 is located on the side close to the trench gate structure, and a first metal 1-1 is provided on the upper surface of the P+ emitter region 2 and the N+ emitter region 3.

[0009] The trench gate structure includes a trench gate 5, a split gate 11, and a gate oxide layer 6. The split gate 11 is located directly below the trench gate 5 and is isolated by the gate oxide layer 6. At the same time, the trench gate 5, the split gate 11, the P-type base region 4, the floating P-region 18, and the N-drift region 7 are also isolated by the gate oxide layer 6.

[0010] A three-dimensional coordinate system is defined by the device's lateral direction, vertical direction, and longitudinal direction. The lateral direction refers to the direction from the P-type base region 4 to the P-type region 20, and the vertical direction refers to the direction from the collector metal 10 to the active region. Along the longitudinal direction, a P+ ohmic contact region 17 is embedded on one end of the floating P-type region 18, and an oxide layer 16 is present on the upper surface of the other end of the floating P-type region 18. A second metal 13 is present on the upper surface of the P+ ohmic contact region 17, and a polycrystalline silicon diode is present on the upper surface of the oxide layer 16. The polycrystalline silicon diode consists of a P-type region 14 and an N-type region 15 arranged side-by-side along the longitudinal direction of the device. The P-type region 14 and the second metal 13 are connected along the longitudinal direction of the device. A dielectric layer 12 is present on the upper surface of the second metal 13 and the upper surface of the polycrystalline silicon diode, and a third metal 1-3 is present on the upper surface of the dielectric layer 12.

[0011] The trench emitter structure includes a trench emitter 21 and a gate oxide layer 6, wherein the gate oxide layer 6 isolates the trench emitter 21 from the floating P region 18, the P+ ohmic contact region 17, the P region 20, and the N- drift region 7; the upper surface of the trench emitter 21 has a fourth metal 1-2.

[0012] The upper surface of the P region 20 has an N+ contact region 19, and the fourth metal 1-2 also covers the upper surface of the N+ contact region 19.

[0013] The split gate 11 is electrically connected to the N-type region 15 of the polysilicon diode, and a capacitor C is connected in series between the split gate 11 and the first metal 1-1, so that the potential of the floating P region 18 is charged by the capacitor C, thereby realizing the self-biasing of the split gate.

[0014] In the above scheme, the potential of the floating P-region 18 is used to charge the capacitor through the polycrystalline PN junction, thereby increasing the capacitor voltage and achieving self-biasing of the split gate. Furthermore, the diode and capacitor structures of the self-biasing structure are integrated into the IGBT structure, allowing the structure to improve the device's conduction capability and switching performance with almost no impact on device size or IGBT operation.

[0015] Furthermore, the P-region 20 and the N+ contact region 19 also have an N-type region 22, which blocks hole extraction when the device is forward-biased, increases the carrier concentration in the drift region 7, and provides a carrier extraction path when the device is turned off, thereby improving the device's turn-off speed.

[0016] Furthermore, the trench width of the trench emitter structure is smaller than the trench width of the trench gate structure, and the junction depth of the trench emitter structure is smaller than the junction depth of the trench gate structure. That is, there is a gap between the bottom of the trench emitter structure and the bottom of the floating P-region 18, while the bottom of the trench gate structure is flush with the bottom of the floating P-region 18. This reduces the etching window width of the emitter trench 21, utilizes the load effect to form a shallower emitter trench, and improves the clamping capability of the floating P-region.

[0017] Furthermore, the trench emitter 14 is split into a first trench emitter 21-1 and a second trench emitter 21-2, and the first trench emitter 21-1 and the trench gate 5, and the second trench emitter 21-2 and the split gate 11 are symmetrically structured. This scheme has better process consistency, and the emitter trench and the gate trench are symmetrical, which can be achieved through a unified process step.

[0018] Furthermore, the N-drift region 7 also includes P-pillars 23, which together with the N-drift region 7 form an N / P pillar superjunction drift region. Replacing the N-drift region 7 with a superjunction structure of higher concentration N / P pillars, where the N-pillars serve as the substrate and the P-pillars 23 are achieved through trench filling, results in similar concentrations for both, with pillar widths ranging from 2μm to 12μm. The drift region thickness is reduced by 20-30% depending on the breakdown voltage requirements. The introduction of the superjunction structure improves the device's breakdown voltage and trade-off performance. Simultaneously, the laterally depleted drift pillar region assists in the longitudinal depletion layer expansion during device switching, further enhancing the device's switching speed.

[0019] Furthermore, the N-type electric field blocking layer 8 is formed by hydrogen implantation, with the number of hydrogen implantations set to four, each using 1×10⁻⁶ hydrogen atoms. 12 cm -3 -1×10 15 cm -3 The injection dose and injection energy ranged from 20-200 keV. Hydrogen injection, due to its advantages of deep injection at lower energies and lower annealing temperatures, is well-suited to replace high-temperature pre-diffusion processes for deep IGBT implantation. The back-side high-energy H injection was performed four times, each using 1×10⁻⁶ keV. 12 -1×10 15 The implantation dose and implantation energy selection range from 20-200 keV are considered. The N-drift region formed by the hydrogen-implanted field stop layer and the NN-junction of the N+FS layer have a gentler concentration gradient, which can effectively increase the dynamic avalanche tolerance of the device.

[0020] Furthermore, the collector region P-region 9 also includes an N-region 24, which is arranged side-by-side with the collector region P-region 9 and located below the P-region 20. Introducing a portion of the N-region 24 into the collector region P-region 9 realizes an RC-IGBT structure, thereby integrating the diode within the IGBT module into the IGBT structure. The N-region 24 is achieved through back-side implantation with a doping concentration of 1×10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The introduction of the N-region collector integrates the diodes within the IGBT module into the IGBT structure, improving the module's integration density.

[0021] Furthermore, the materials of the structure include silicon, silicon carbide, gallium nitride, gallium oxide, diamond, etc.

[0022] The method for fabricating the self-biased split-gate bipolar transistor of the present invention includes:

[0023] Step 1: Select an N-type lightly doped FZ silicon wafer of a certain thickness and concentration as the N-drift region 7 of the device; grow a field oxide layer, such as... Figure 11 As shown;

[0024] Step 2: Photolithography, using high-temperature ion implantation of P-type impurities followed by annealing to create the floating P-region 18 of the device, and growing a pre-oxide layer on the silicon wafer surface, such as... Figure 12 As shown;

[0025] Step 3: Form the active region by photolithography etching of field oxygen, such as... Figure 13 As shown;

[0026] Step 4: Using photolithography, trenches are etched, and sacrificial oxygen is grown to remove surface contaminants after etching. Figure 14 As shown;

[0027] Step 5: Thermal oxidation is used to form the gate oxide layer 6, followed by N-doped polysilicon deposition and photolithography etching to form the gate polysilicon layers 5 and 21, and the substrate 15 of the polysilicon PN diode, as shown below. Figure 15 As shown;

[0028] Step 6: First, thermal oxidation is performed to form an oxide shielding layer. Using photolithography, the oxide layer on the surface of 5 and the upper polysilicon layer of 5 are etched away to form SGT polysilicon 11. Thermal oxidation is then performed to form an oxide isolation layer, which is then deposited again to form the polysilicon gate 5. Metal connections are then made to form the gate electrode, such as... Figure 16 , 17 As shown;

[0029] Step 7: Photolithography. The P-type base regions 4 and 20 of the device are fabricated by high-temperature ion implantation of P-type impurities followed by annealing. The N+ emitter region 3 of the device is fabricated by high-temperature ion implantation of N-type impurities followed by annealing. Figure 18 As shown;

[0030] Step 8: High-temperature ion implantation of P-type impurities followed by annealing to fabricate the P+ emitter region 2, floating P-ohmic contact region 17, P-region 14 in the polycrystalline PN junction, and P+ region 17 of the device. Al metal deposition is performed to form the emitter electrode 1-1 and the metal connection 13 connecting the polycrystalline silicon diode P-region 14 and the floating P-ohmic contact region 17, and the metal connection 1-2 connecting the emitter 14, as shown below. Figure 19 As shown;

[0031] Step 9: Deposit high dielectric constant material 12, such as Figure 20 As shown;

[0032] Step 10: Deposit emitter metals 1-3, such as... Figure 21 As shown;

[0033] Step 11: Flip the silicon wafer, reduce its thickness, and form an N-type electric field blocking layer 8 and a P-type collector region 9 on its lower surface by high-energy ion implantation of N-type impurities and ion implantation of P-type impurities followed by annealing on the back side of the silicon wafer. Deposit metal on the back side of the silicon wafer to form a metal collector electrode 10 on the lower surface of the P-type collector region 9. This yields the self-biased split insulated gate bipolar transistor of the present invention. Figure 21 As shown.

[0034] To simplify the description, the above device structure and fabrication method are illustrated using an N-channel IGBT device as an example, but the present invention is also applicable to the fabrication of P-channel IGBT devices.

[0035] The principle of this invention is illustrated by using an N-channel self-biased split IGBT:

[0036] When the gate electrode 5 is connected to a high potential higher than the device threshold voltage, the collector electrode 10 is connected to a high potential, and the emitters 1-1 and 1-2 are connected to a low potential, the device operates in the on state. The P+ collector region 9 injects holes into the N- drift region 7, and the N+ emitter region 3 injects electrons into the N- drift region 7. The presence of electron-hole pairs causes a conductivity modulation effect in the drift region.

[0037] The polysilicon diode structure has a P-region 18 connected to a floating P-ohmic contact region 15 above the floating P-region 12 via a metal 17. The potential below the floating P-region 12 is clamped by a reverse-biased PN junction formed by the P-type base region 20 and the N-drift region 1. This potential charges the integrated capacitor through the PN diode. Since the diode can maintain the charge on the capacitor and the floating P-region has a relatively stable clamping voltage, the N-region 19 of the diode is kept at a stable value. The N-region 19 of the diode is connected to the SG gate 11, so the SG gate also has a stable potential. This potential attracts electrons near the SG gate to accumulate and form an electron accumulation layer. This accumulation layer improves the channel injection efficiency, further enhances the drift region conductance modulation effect, and reduces the forward voltage drop of the device.

[0038] The beneficial effects of this invention are as follows: This invention utilizes the potential of the floating P-region to provide a bias potential for the split gate 11, thereby forming an electron accumulation capability below the trench, enhancing the conductivity modulation capability, and thus enhancing the forward conduction capability of the device. Compared with the traditional split gate structure, the introduction of the self-biasing structure is beneficial to simultaneously improve the device's conduction capability and switching performance, eliminating the negative impact of the split gate. While improving switching losses and increasing switching speed, it can also optimize the device's forward conduction capability, improving the trade-off characteristics between the device's forward conduction voltage drop and turn-off loss.

[0039] The gate oxide layer 6 surrounding the isolated polysilicon gate 11 is not limited by the threshold voltage design, so its thickness can be further increased to improve the device's withstand voltage and oxide layer reliability, thereby enhancing device performance. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the cell structure of a traditional trench gate IGBT;

[0041] Figure 2 This is a schematic diagram of the cellular structure of a traditional shielded trench IGBT.

[0042] Figure 3 This is a schematic diagram of the self-biased splitting IGBT cell structure provided in Embodiment 1 of the present invention;

[0043] Figure 4 It is along Figure 3 Schematic diagram of the cross section of line AA' in the middle;

[0044] Figure 5 This is the equivalent circuit diagram of the self-biased split IGBT cell structure provided in Embodiment 1 of the present invention;

[0045] Figure 6 This is a schematic diagram of a self-biased split IGBT cell structure with symmetrical emitter trench and gate trench provided in Embodiment 2 of the present invention.

[0046] Figure 7 This is a schematic diagram of the self-biased split IGBT cell structure with adaptive carrier pathway provided in Embodiment 3 of the present invention;

[0047] Figure 8 This is a schematic diagram of a self-biased splitting IGBT cell structure with a shallow trench emitter provided in Embodiment 4 of the present invention;

[0048] Figure 9 This is a schematic diagram of the IGBT cell structure provided in Embodiment 5 of the present invention, in which the N-drift region is replaced with a higher concentration of N / P pillar superjunction structure.

[0049] Figure 10 This is a schematic diagram of the IGBT cell structure with an introduced back collector region RC structure provided in Embodiment 7 of the present invention.

[0050] Figures 11-22 This is a schematic diagram of the structure of the device obtained in each step of the manufacturing process of this invention. Detailed Implementation

[0051] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0052] Example 1

[0053] A three-dimensional self-biased split-gate insulated-gate bipolar transistor, the cell structure of which is as follows: Figure 3 As shown, it includes: collector metal 10, P-type collector region 9, N-type electric field blocking layer 8, N-drift region 7, P-type base region 4, N+ emitter region 3, floating P-region 18, P+ ohmic contact region 17, floating P-region and polycrystalline diode connection metal 13, polycrystalline diode structure P-type region 14, polycrystalline diode structure P-type region 15, high dielectric constant material 12, P-region 20 (P-type clamping region), P+ contact region 19, trench gate structure 5, split gate structure 11, trench emitter 12 and emitter metals 1-1, 1-2, 1- 3; Collector metal 10 is located on the back of P-type collector region 9, N-type electric field blocking layer 8 is located on the front of P-type collector region 9, N-drift region 7 is located on the front of N-type electric field blocking layer 8; P-type base region 4 is located above N-drift region 7; P-type floating region 18 is located between trench emitter 20 and trench gate 5; polycrystalline diodes 14 and 15 are located above P-type floating region 18; P-region 20 (P-type clamping region) is located to the right of trench emitter 21; N+ emitter region 3 is located on the top layer of P-type base region 4, and is separated from N-drift region 7 by P-type base region 4. This structure uses metal 13 to connect polycrystalline diode 14 and floating P-region 18, and at the same time, the deposition of high dielectric constant material 12 makes a large capacitance form between polycrystalline diode and emitter metals 1-3, such as Figure 4 As shown. The split gate 11 is also connected to the N-type region 15 of the polycrystalline diode.

[0054] In this embodiment, the doping concentration of the P-type base region 4 is 3 × 10⁻⁶. 16 cm -3 ~2×10 17 cm -3 The depth is 3~3.5μm; the doping concentration of N+ emitter region 3 is 5×10⁻⁶. 18 cm -3 ~1×10 21 cm -3 The depth of the gate dielectric layer 6 is 0.2~0.5μm; the thickness of the gate dielectric layer 6 is 80~120nm; the depth of the trench gate electrode 5 is 4~6μm; the depth of the split gate electrode 11 is 0.5~2μm; the depth of the trench emitter 21 is 5~8μm; and the doping concentration of the N-drift region 7 is 5×10⁻⁶. 12 cm -3 ~2×10 14 cm -3 The thickness is 60~700μm; the doping concentration of the N-type electric field blocking layer 8 is 5×10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness is 5~20μm; the doping concentration of the P-type collector region 9 is 1×10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The thickness is 0.5~5μm; the high dielectric constant material 12 can be selected from alumina, hafnium oxide, zirconium dioxide, titanium dioxide, lanthanum trioxide, lutetium trioxide, niobium pentoxide, tantalum pentoxide, etc.; the cell width is 20~40μm.

[0055] Example 2

[0056] An embodiment of a three-dimensional self-biased split-gate insulated-gate bipolar transistor, such as... Figure 6 As shown, based on Example 1, the emitter trench is split into two. The thickness of the emitter 21-2 at the bottom of the trench is the same as the thickness of the split gate electrode 11, which is 0.5~2μm. The thickness of the emitter 21-1 at the top is the same as the thickness of the trench gate electrode 5, which is 4~6μm.

[0057] Compared with Example 1, this scheme has better process consistency, and the emitter trench and gate trench are symmetrical, which can be achieved through a unified process step.

[0058] Example 3

[0059] An embodiment of a three-dimensional self-biased split-gate insulated-gate bipolar transistor, such as... Figure 7As shown, based on Example 1, an N-type region 22 is buried above the P-type region 20, which blocks hole extraction when the device is forward-biased, increases the carrier concentration in the drift region 7, and provides a carrier extraction path when the device is turned off, thereby improving the device's turn-off speed.

[0060] Example 4

[0061] An embodiment of a three-dimensional self-biased split-gate insulated-gate bipolar transistor, such as... Figure 8 As shown, based on Example 1, the etching window width of the emitter trench 21 is reduced, and a shallower emitter trench is formed by utilizing the load effect, thereby improving the clamping capability of the floating P region.

[0062] Example 5

[0063] An embodiment of a three-dimensional self-biased split-gate insulated-gate bipolar transistor, such as... Figure 9 As shown, based on Example 4, the N-drift region 7 is replaced with a superjunction structure of N / P pillars with a higher concentration. The N-pillar 7 serves as the substrate, and the P-pillar 23 is achieved by trench filling of single-crystal silicon or multiple epitaxial growths followed by ion implantation. The concentrations of both are similar, and the doping concentration is set to 1×10⁻⁶. 14 cm -3 -2×10 16 cm -3 The column width is 2μm-12μm, and the thickness of the drift region is reduced by 20-30% according to the pressure resistance requirements.

[0064] Compared with Example 1, the introduction of the superjunction structure is beneficial to improving the device's breakdown voltage and trade-off performance. At the same time, the laterally depleted drift pillar region assists in the longitudinal depletion layer expansion during device switching, further improving the device's switching speed.

[0065] Example 6

[0066] An embodiment of a three-dimensional self-biased split-gate insulated-gate bipolar transistor (IGBT) is presented. Based on Embodiment 1, a thick hydrogen-implanted FS layer 8 is introduced between the N-drift region and the P+ collector region. Hydrogen implantation, due to its advantages of large implantation depth at lower energies and low annealing temperatures, is well-suited to replace high-temperature pre-diffusion processes for deep implantation in IGBTs. The number of high-energy H implantations on the back side is set to four, each using 1×102... 12 -1×10 15 Selection of injection dose within the range and injection energy from 20-200 keV.

[0067] Compared with Example 1, the N-drift region formed by the hydrogen-injected field stop layer and the NN-junction of the N+FS layer have a gentler concentration gradient, which can effectively increase the dynamic avalanche tolerance of the device.

[0068] Example 7

[0069] An embodiment of a three-dimensional self-biased split-gate insulated-gate bipolar transistor, such as... Figure 10 As shown, based on Example 1, a portion of the N-region 24 is introduced into the collector region P-region 9 to realize an RC-IGBT structure, thereby integrating the diodes within the IGBT module into the IGBT structure. The N-region 24 is achieved through back-side implantation with a doping concentration of 1×10⁻⁶. 17 cm -3 ~1×10 19 cm -3 .

[0070] Compared to Example 1, the introduction of the N-region collector integrates the diodes within the IGBT module into the IGBT structure, thereby improving the module integration.

Claims

1. A self-biased split-gate bipolar transistor, comprising a collector metal (10), a P-type collector region (9), an N-type electric field blocking layer (8), an N-drift region (7), and an active region stacked sequentially from bottom to top; the active region includes a P-type base region (4) and a P-region (20) located at both ends of the upper surface of the N-drift region (7), a trench gate structure, a floating P-region (18), and a trench emitter structure located between the P-type base region (4) and the P-region (20), wherein the floating P-region (18) is located between the trench gate structure and the trench emitter structure, the trench gate structure is in contact with the P-type base region (4), the trench emitter structure is in contact with the P-region (20), and the lower surface junction depth of the trench gate structure, the floating P-region (12), and the trench emitter structure is greater than the lower surface junction depth of the P-type base region (4) and the P-region (20); The upper surface of the P-type base region (4) is provided with a P+ emitter region (2) and an N+ emitter region (3) arranged side by side, wherein the N+ emitter region (3) is located on the side close to the trench gate structure, and a first metal (1-1) is provided on the upper surface of the P+ emitter region (2) and the N+ emitter region (3). The trench gate structure includes a trench gate (5), a split gate (11) and a gate oxide layer (6), wherein the split gate (11) is located directly below the trench gate (5) and is isolated by the gate oxide layer (6). At the same time, the trench gate (5), the split gate (11) and the P-type base region (4), the floating P region (18) and the N-drift region (7) are also isolated by the gate oxide layer (6). A three-dimensional coordinate system is defined by the device's lateral direction, vertical direction, and longitudinal direction. The lateral direction refers to the direction from the P-type base region (4) to the P-region (20), and the vertical direction refers to the direction from the collector metal (10) to the active region. Along the longitudinal direction, a P+ ohmic contact region (17) is embedded on one end of the floating P-region (18), and an oxide layer (16) is on the upper surface of the other end of the floating P-region (18). A second metal (13) is on the upper surface of the P+ ohmic contact region (17), and a polycrystalline silicon diode is on the upper surface of the oxide layer (16). The polycrystalline silicon diode is composed of a polycrystalline silicon diode P-type region (14) and a polycrystalline silicon diode N-type region (15) arranged side by side along the longitudinal direction of the device. The polycrystalline silicon diode P-type region (14) and the second metal (13) are connected along the longitudinal direction of the device. A dielectric layer (12) is on the upper surface of the second metal (13) and the upper surface of the polycrystalline silicon diode, and a third metal (1-3) is on the upper surface of the dielectric layer (12). The trench emitter structure includes a trench emitter (21) and a gate oxide layer (6), wherein the gate oxide layer (6) isolates the trench emitter (21) from the floating P region (18), the P+ ohmic contact region (17), the P region (20), and the N- drift region (7); the upper surface of the trench emitter (21) has a fourth metal (1-2). The upper surface of the P region (20) has an N+ contact region (19), and the fourth metal (1-2) also covers the upper surface of the N+ contact region (19); The split gate (11) is electrically connected to the N-type region (15) of the polysilicon diode, and a capacitor C is connected in series between the split gate (11) and the first metal (1-1), so that the potential of the floating P region (18) is charged by the capacitor C, thereby realizing the self-biasing of the split gate.

2. The self-biased split-gate bipolar transistor according to claim 1, characterized in that: The P region (20) and the N+ contact region (19) also have an N-type region (22).

3. A self-biased split-gate bipolar transistor according to claim 1, characterized in that: The trench width of the trench emitter structure is smaller than the trench width of the trench gate structure, and the junction depth of the trench emitter structure is smaller than the junction depth of the trench gate structure. That is, there is a gap between the bottom of the trench emitter structure and the bottom of the floating P region (18), while the bottom of the trench gate structure is flush with the bottom of the floating P region (18).

4. A self-biased split-gate bipolar transistor according to claim 1, characterized in that: The trench emitter (14) is split into a first trench emitter (21-1) and a second trench emitter (21-2), and the first trench emitter (21-1) and the trench gate (5), and the second trench emitter (21-2) and the split gate (11) are symmetrical.

5. A self-biased split-gate bipolar transistor according to claim 1, characterized in that: The N-drift region (7) also has a P-pillar (23), and the P-pillar (23) and the N-drift region (7) form an N / P-pillar superjunction drift region.

6. A self-biased split-gate bipolar transistor according to claim 1, characterized in that: The N-type electric field blocking layer (8) is formed by hydrogen implantation, with the number of hydrogen implantations set to four, each using 1×10⁻⁶ hydrogen peroxide. 12 cm -3 -1×10 15 cm -3 The injection dose and injection energy are within the range of 20-200 keV.

7. A self-biased split-gate bipolar transistor according to claim 1, characterized in that: The collector area P (9) also has an N (24) which is arranged in parallel with the collector area P (9) and is located below the collector area P (20).

8. A method for fabricating a self-biased split-gate bipolar transistor as described in claim 1, characterized in that, Includes the following steps: Step 1: Select an N-type lightly doped FZ silicon wafer with set thickness and concentration as the N-drift region of the device (7) according to the requirements, and grow a field oxygen layer on its surface; Step 2: Using photolithography, the floating P-region of the device is fabricated by high-temperature ion implantation of P-type impurities and annealing, and a pre-oxidation layer is grown on the silicon wafer surface; Step 3: Form the active region by photolithography etching of field oxygen; Step 4: Through photolithography, trenches are etched and sacrificial oxygen is grown to remove surface contaminants after etching, followed by thermal oxidation to form a gate oxide layer (6). Step 5: Deposit N-doped polysilicon and etch it using photolithography to form the trench gate structure, trench emitter structure, and substrate of the polysilicon diode; Step 6: First, thermal oxidation is performed to form an oxide shielding layer. Photolithography is used to etch away the oxide layer on the surface of the trench gate structure and the polysilicon in the upper layer of the trench gate structure. A split gate electrode (11) is formed at the bottom of the trench gate structure. Thermal oxidation is performed to form an oxide isolation layer and it is deposited again. Metal connection is performed to form the trench gate (5). Step 7: Photolithography, fabricating the P-type base region (4) and P-region (20) of the device by high-temperature ion implantation of P-type impurities and annealing; fabricating the N+ emitter region (3) of the device by high-temperature ion implantation of N-type impurities and annealing. Step 8: High-temperature ion implantation of P-type impurities and annealing to fabricate the P+ emitter region (2), P+ ohmic contact region (17), P-type region (14) in the polysilicon diode, and P+ region (17) on the P region (20); Al metal deposition to form the first metal (1-1) and the second metal (13) connecting the P-type region (11) and P+ ohmic contact region (17) of the polysilicon diode, and the third metal (1-2) connecting the trench emitter (14); Step 9: Deposit a high dielectric constant material to form a dielectric layer (12); Step 10: Deposit the fourth metal (1-3); Step 11: Flip the silicon wafer, reduce the thickness of the silicon wafer, implant N-type impurities with high-energy ions and P-type impurities with ions and anneal on the back of the silicon wafer to form an N-type electric field blocking layer (8) and a P-type collector region (9); deposit metal on the back of the silicon wafer and form a collector metal (10) on the lower surface of the P-type collector region (9).

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