Semiconductor device, method for manufacturing the same, power module, power conversion circuit, and vehicle

Abstract

The present application discloses a semiconductor device, a method for manufacturing the same, a power module, a power conversion circuit, and a vehicle, relating to the field of semiconductor technologies. The semiconductor device includes: a substrate; an epitaxial layer; the epitaxial layer includes a first surface on a side away from the substrate, and the epitaxial layer further includes a well region and a first region; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the epitaxial layer; a gate structure located in the gate trench, the gate structure includes a first insulating layer formed on the surface of the gate trench, and a first polysilicon layer and a first conductive material layer formed in the first insulating layer, and the conductivity of the first conductive material layer is greater than the conductivity of the first polysilicon layer; a source electrode formed on the first surface and electrically connected to the first region; and a drain electrode provided on a side of the substrate away from the epitaxial layer. The technical solution disclosed in the present application reduces the sheet resistance of the gate structure, thereby reducing the on-resistance of the device during the turn-on transient.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device, a method for manufacturing the same, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] In the field of semiconductor technology, trench-type power devices have advantages such as large current density and small cell size of a single device. Such devices usually have a trench gate structure, and a gate is formed by filling polysilicon in the trench. However, for the trench gate structure, its gate is relatively long. When a gate bias voltage is applied to the device, the gate resistance is large, and the gate voltage cannot reach the end of the gate immediately, resulting in a delay. This delay in the propagation of the gate voltage will cause a relatively large on-resistance during the device turn-on transient. Summary of the Invention

[0003] Embodiments of this application provide a semiconductor device, a method for manufacturing the same, a power module, a power conversion circuit, and a vehicle, which can reduce the sheet resistance of the gate structure, thereby reducing the on-resistance during the device turn-on transient.

[0004] On the one hand, embodiments of this application provide a semiconductor device, including:

[0005] A substrate; an epitaxial layer disposed on the substrate, the epitaxial layer being set to a first conductivity type. The epitaxial layer includes a first surface on a side away from the substrate, and the epitaxial layer further includes a well region and a first region. The first region is disposed on the first surface and is of the first conductivity type. The well region is set to a second conductivity type and is disposed on a side of the first region away from the first surface. The first surface is provided with a gate trench that extends from the first surface into the epitaxial layer and penetrates through the first region and the well region;

[0006] A gate structure located in the gate trench, the gate structure including a first insulating layer formed on the surface of the gate trench, and a first polysilicon layer and a first conductive material layer formed in the first insulating layer. The conductivity of the first conductive material layer is greater than that of the first polysilicon layer;

[0007] A source electrode formed on the first surface and electrically connected to the first region;

[0008] A drain electrode disposed on a side of the substrate away from the epitaxial layer.

[0009] In some embodiments, the above-mentioned first polysilicon layer is formed between the first insulating layer and the first conductive material layer.

[0010] In some embodiments, the first polysilicon layer includes an end portion adjacent to the first surface, and the first conductive material layer covers the end portion.

[0011] In some embodiments, the first insulating layer includes an extension extending to the first surface, and the first polysilicon layer at least partially covers the extension.

[0012] In some embodiments, the first conductive material layer is a metal material layer.

[0013] In some embodiments, the metal material layer includes molybdenum, tungsten, or titanium.

[0014] In some embodiments, a source trench is provided on the first surface, the source extends into the source trench, and the semiconductor device further includes a second insulating layer provided on the surface of the source trench, and a second polysilicon layer provided between the second insulating layer and the source.

[0015] In some embodiments, the epitaxial layer further includes a second region provided on the first surface and located outside the first region and the well region. The second region is of a second conductivity type, and the source trench is formed in the second region.

[0016] In some embodiments, the portion of the source extending into the source trench is a second conductive material layer, and the second polysilicon layer is formed between the second conductive material layer and the second insulating layer.

[0017] The technical solution provided by the embodiments of the present application, the semiconductor device therein includes a gate structure formed in the gate trench. The gate structure specifically includes a first insulating layer formed on the surface of the gate trench, a first polysilicon layer and a first conductive material layer formed in the first insulating layer, and the conductivity of the first conductive material layer is greater than the conductivity of the first polysilicon layer. Therefore, compared with the prior art, this structure can effectively reduce the sheet resistance of the gate, thereby reducing the on-resistance of the device turn-on transient, and improving the charging ability of the gate, that is, at the same gate voltage, the gate can be charged to the required potential level faster, thereby improving the response speed and performance of the semiconductor device.

[0018] On the other hand, the embodiments of the present application further provide a method for manufacturing a semiconductor device, including:

[0019] Form an epitaxial layer on the substrate. The epitaxial layer includes a first surface on the side away from the substrate. The epitaxial layer further includes a well region and a first region. The first region is located on the first surface, and the well region is located on the side of the first region away from the first surface. Form a gate trench in the first surface. The gate trench extends from the first surface into the epitaxial layer and penetrates through the first region and the well region;

[0020] Form a gate structure in the gate trench. The gate structure includes a first insulating layer formed on the surface of the gate trench, a first polysilicon layer and a first conductive material layer formed in the first insulating layer, and the conductivity of the first conductive material layer is greater than the conductivity of the first polysilicon layer;

[0021] A source electrode is formed on the first surface, and the source electrode is electrically connected to the first region and the second region;

[0022] A drain electrode is formed, and the drain electrode is located on the side of the substrate away from the epitaxial layer.

[0023] In the manufacturing method provided by the embodiments of the present application, during the process of forming the gate structure of the semiconductor device, by forming a first insulating layer on the surface of the gate trench, and forming a first polysilicon layer and a first conductive material layer in the first insulating layer, and the conductivity of the first conductive material layer is greater than the conductivity of the first polysilicon layer. Therefore, the fabricated gate structure can reduce the sheet resistance of the effective gate, thereby reducing the on-resistance of the device turn-on transient, and improving the charging ability of the gate, that is, at the same gate voltage, the gate can be charged to the required potential level faster, thereby improving the response speed and performance of the semiconductor device.

[0024] In some embodiments, forming the gate structure in the gate trench includes:

[0025] Forming a first insulating layer on the surface of the gate trench, and sequentially forming a first polysilicon layer and a first conductive material layer in the first insulating layer, and the first polysilicon layer is disposed between the first conductive material layer and the first insulating layer.

[0026] On the other hand, the embodiments of the present application further provide a power module, which includes a substrate and a semiconductor device as described in any of the above embodiments, and the substrate is used to carry the semiconductor device.

[0027] On another aspect, the embodiments of the present application further provide a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as described in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0028] On yet another aspect, the embodiments of the present application further provide a vehicle, which includes a load and a power conversion circuit as described in the above embodiments. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0029] The above power module, power conversion circuit, and vehicle have the same structure and beneficial technical effects as the semiconductor device provided in some of the above embodiments, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present application will become apparent and easy to understand from the description of the embodiments in conjunction with the following drawings, where:

[0031] Figure 1 Structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0032] Figure 2 Structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0033] Figure 3 Flow schematic diagram of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0034] Figure 4 Flow schematic diagram of another method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0035] Figures 5 - 15 Structural schematic diagram corresponding to each step in the manufacturing method provided by an embodiment of the present application;

[0036] Figure 16 Structural schematic diagram of a power module provided by an embodiment of the present application;

[0037] Figure 17 Structural schematic diagram of a power conversion circuit provided by an embodiment of the present application;

[0038] Figure 18 Structural schematic diagram of a vehicle provided by an embodiment of the present application. Detailed implementation manners

[0039] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0040] Unless otherwise required by the context, in the whole specification and claims, the term "comprising" is interpreted as an open and inclusive meaning, that is, "including, but not limited to".

[0041] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0042] In describing some embodiments, the term "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral one; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0043] In addition, the use of "based on" implies openness and inclusiveness because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0044] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0045] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused, for example, by manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0046] Examples of the embodiments are shown in the drawings, where like or similar reference numerals designate like or similar elements or elements having like or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0047] In the semiconductor technology field, a semiconductor device, such as a SiC power device, can be provided with a trench gate structure. Generally, polysilicon is filled in the trench to form the gate for the trench gate structure. However, for the trench gate structure, its gate is relatively long. When a gate bias voltage is applied to the device, the gate resistance is relatively large, and the gate voltage cannot reach the end of the gate immediately, resulting in a delay. This delay in the propagation of the gate voltage will cause a relatively large on-resistance during the device turn-on transient.

[0048] In view of the above problems, an embodiment of the present application provides a semiconductor device, which may be a SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET for short). Figure 1 FIG. 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.

[0049] As Figure 1 shown, the semiconductor device 10 includes a substrate 101, an epitaxial layer 102, a gate structure 103, a source 104, and a drain 105. Among them, the epitaxial layer 102 is disposed on the substrate 101. The epitaxial layer 102 includes a first surface P1 on a side away from the substrate 101. The epitaxial layer 102 further includes a well region 107 and a first region 108. The first region 108 is disposed on the first surface P1. The well region 107 is disposed on a side of the first region 108 away from the first surface P1. A second region 109 is disposed on the first surface P1 and outside the first region 108 and the well region 107. In this embodiment, the "outside" refers to a side away from the gate structure 103.

[0050] In an embodiment of the present application, a gate trench T1 is formed in the first surface P1. The gate trench T1 extends from the first surface P1 into the epitaxial layer 102 and penetrates through the first region 108 and the well region 107.

[0051] Exemplarily, as Figure 1 shown, a gate structure 103 is disposed in the gate trench T1. The gate structure 103 includes a first insulating layer 1031 formed on the surface of the gate trench T1, and a first polysilicon layer 1032 and a first conductive material layer 1033 formed in the first insulating layer 1031. In addition, in some embodiments, there is a first passivation layer 106 on the first surface P1. The first passivation layer 106 may cover the gate structure 103 to play a role of isolation and protection.

[0052] Furthermore, the source 104 is formed on the first surface P1 and is electrically connected to the first region 108 and the second region 109 described above. The drain 105 is disposed on a side of the substrate 101 away from the epitaxial layer 102. In an embodiment of the present application, the substrate 101, the epitaxial layer 102, and the first region 108 have the same conductivity type, and may all be of the first conductivity type. The well region 107 may be of the second conductivity type. For example, Al ions are implanted in the well region 107, and the conductivity type is P-type. The well region 107 may also be referred to as a "P-well". The substrate 101, the epitaxial layer 102, and the first region 108 are all of N-type conductivity. P (phosphorus) or N + (nitrogen) ions are implanted in the first region 108. The first region 108 may also be referred to as "N+ "Contact area".

[0053] By transmitting a turn-on voltage to the gate structure 103, when the semiconductor device 10 conducts forwardly and the working current is small, the working current flows from the source 104 through the first region 108, the well region 107, the epitaxial layer 102, and the substrate 101 to the drain 105.

[0054] The technical solution provided by the embodiments of the present application, wherein the gate structure 103 of the semiconductor device includes a first insulating layer 1031, and a first polysilicon layer 1032 and a first conductive material layer 1033 formed in the first insulating layer 1031. Among them, the conductivity of the first conductive material layer 1033 is greater than that of the first polysilicon layer 1032, so that the sheet resistance of the gate structure 103 becomes smaller, thereby reducing the sheet resistance of the gate and the on-resistance of the semiconductor device turn-on transient; through the above technical solution, the charging ability of the gate can be improved, that is, at the same gate voltage, the gate can be charged to the required potential level faster, thereby improving the response speed and performance of the semiconductor device.

[0055] In some embodiments, still referring to the above Figure 1 As shown, the first polysilicon layer 1032 therein may be formed between the first insulating layer 1031 and the first conductive material layer 1033, that is, in the gate trench T1, the first insulating layer 1031, the first polysilicon layer 1032, and the first conductive material layer 1033 are sequentially formed. In this embodiment, due to the direct contact between the first insulating layer 1031 and the first polysilicon layer 1032, there are some discrete or continuous energy levels at the interface between the first insulating layer 1031 and the first polysilicon layer 1032, and these energy levels can act as traps to capture carriers (electrons or holes), thereby affecting the gate's control ability over channel carriers. The threshold voltage can be regulated by changing the doping concentration of the first polysilicon layer 1032, so as to maintain good interface characteristics.

[0056] In the embodiments of the present application, the first conductive material layer 1033 is mainly used to reduce its gate resistance. As long as its conductivity is greater than that of the above-mentioned polysilicon material, there is no limitation on its specific type. For example, it can be a metal material or other oxide materials. For example, if the first conductive material layer 1033 is a metal material layer, the metal material layer can include molybdenum, tungsten or titanium, all of which have high temperature resistance and a small sheet resistance, and can achieve the technical effect of reducing the total gate resistance. When using an oxide material for the first conductive material layer 1033 to form an oxide material layer, it can be indium tin oxide (ITO), fluorine-doped tin oxide (FTO), etc. Among them, the main components of ITO are indium oxide (In2O3) and tin oxide (SnO2). The crystal structure of ITO is a cubic crystal system. The presence of oxygen vacancies provides free electrons and enhances the conductivity of the material. At the same time, In2O3, as a semiconductor matrix, brings good light transmittance and a large optical band gap, while the doping of SnO2 changes the carrier concentration and electronic structure of the material, making it have ideal electrical properties. Therefore, the ITO material not only maintains good transparency but also has certain conductivity. FTO is a transparent conductive oxide formed by doping fluorine elements into tin dioxide (SnO2). In FTO, fluoride ions (F - ) are incorporated into the tin dioxide lattice in the form of replacing oxygen ions (O 2- ). Doping fluorine elements introduces extra free electrons into the crystal, which become the carriers of the material, thus enhancing the conductivity.

[0057] In some embodiments, the first insulating layer 1031 includes an extension portion 113 extending to the first surface P1, and the first polysilicon layer 1032 includes an end portion 114 adjacent to the first surface P1. The first conductive material layer 1033 covers the end portion 114 and at least partially covers the extension portion 113, which can prevent the first polysilicon layer 1032 and the first insulating layer 1031 from being etched simultaneously when etching the first conductive material layer 1033, and can also protect the corner of the first insulating layer 1031, where it is relatively thin and easily etched through. In some embodiments, a source trench T2 is provided on the first surface, the source 104 extends into the source trench T2, and the semiconductor device further includes a second insulating layer 1121 provided on the surface of the source trench T2 and a second polysilicon layer 1122 provided between the second insulating layer 1121 and the source 104.

[0058] In some embodiments, the epitaxial layer 102 further includes a second region 109. The second region 109 is disposed on the first surface P1 and is located outside the first region 108 and the well region 107. The second region 109 is of a second conductivity type, and a source trench T2 is formed within the second region 109. Since the P-type ion concentration of the second region 109 is higher than that of the well region 107, more PN junctions are formed between the second region 109 and the epitaxial layer 102. When the working current is relatively large, the working current flows from the source 104 through the second region 109, the epitaxial layer 102, and the substrate 101 to reach the drain 105, avoiding the large working current from flowing through the well region 107, thereby playing a role in protecting the channel in the well region 107.

[0059] The second region 109 penetrates through the first region 108 and the well region 107 and extends to the epitaxial layer 102, which can optimize the electric field distribution within the device and protect the gate structure 103.

[0060] In some embodiments, a source structure 112 may also be formed within the second region 109. For details, reference may be made to Figure 2 as shown, which is different from Figure 1 in that a source trench T2 is formed within the second region 109. The source structure 112 within the source trench T2 includes a second insulating layer 1121 formed on the surface of the source trench T2, and a second polysilicon layer 1122 and a second conductive material layer 1123 formed within the second insulating layer 1121. The above-mentioned second conductive material layer 1123 is the part of the source 104 extending into the source trench T2. The above-mentioned source trench T2 may also be referred to as a "Dummy Trench", and the source structure 112 is disposed within the source trench T2.

[0061] Moreover, in some embodiments, the second polysilicon layer 1122 may be formed between the second insulating layer 1121 and the second conductive material layer 1123. In some embodiments of the present application, the source structure 112 may be formed simultaneously with the formation of the gate structure 103, or may be formed successively, or at least some layers of the gate structure 103 and the source structure 112 may be formed synchronously. There is no limitation in the embodiments of the present application. In the embodiments of the present application, the second insulating layer 1121 and the first insulating layer 1031 may be of the same material, the second polysilicon layer 1122 and the first crystalline polysilicon layer 1032 may be of the same material, and the second conductive material layer 1123 and the source 104 may be of the same material, for example, all are the same metal material.

[0062] The embodiments of the present application further provide a method for manufacturing a semiconductor device. Using this manufacturing method, the semiconductor device in the above Figure 1 shown embodiments can be manufactured. Figure 3Schematic flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application. For the specific structure, reference can be made to Figure 1 as shown in Figure 3 As shown, the manufacturing method includes the following steps:

[0063] Step 301: Form an epitaxial layer 102 on a substrate 101;

[0064] In this step, a substrate 101 can be provided first, and then an epitaxial layer 102 is formed on the substrate 101. Finally, a specific structure is formed on the epitaxial layer 102. Specifically, the epitaxial layer 102 includes a first surface P1 on a side away from the above substrate 101. A well region 107 and a first region 108 can be formed in the epitaxial layer 102. The first region 108 is located on the first surface P1, and the well region 107 is located on a side of the first region 108 away from the first surface P1;

[0065] Step 302: Form a gate trench T1 in the first surface P1. The gate trench T1 extends from the first surface P1 into the epitaxial layer 102 and penetrates through the first region 108 and the well region 107 in the epitaxial layer;

[0066] In the embodiment of the present application, SiC material can be used. The substrate 101, the epitaxial layer 102, and the first region 108 have the same conductivity type, and can all be the first conductivity type. The well region 107 can be the second conductivity type. For example, Al ions are implanted in the well region 107, and the conductivity type is P-type. The well region 107 can also be referred to as a "P-type well". The conductivity types of the substrate 101, the epitaxial layer 102, and the first region 108 are all N-type. P (phosphorus) or N (nitrogen) ions are implanted in the first region 108. The first region 108 can also be referred to as an "N + contact region".

[0067] Step 303: Form a gate structure 103 in the gate trench T1. The gate structure 103 includes a first insulating layer 1031 formed on the surface of the gate trench T1, and a first polysilicon layer 1032 and a first conductive material layer 1033 formed in the first insulating layer 1031. The conductivity of the first conductive material layer 1033 is greater than that of the first polysilicon layer 1032;

[0068] As described in the above embodiment, in the embodiment of the present application, the specific type of the material used for the first conductive material layer 1033 is not limited. For example, it can be a metal material or other oxide materials, etc. If a metal material is used, it can be molybdenum, tungsten, or titanium, all of which have high temperature resistance and a small sheet resistance.

[0069] Step 304: Form a source electrode 104 on the first surface P1. The source electrode 104 is electrically connected to the first region 108;

[0070] Step 305: Form a drain 105 on the side of the substrate 101 away from the epitaxial layer 102. By the above preparation method provided by the embodiments of the present application, a semiconductor device as shown can be prepared. And in the process of forming the gate structure 103, by forming a first insulating layer 1031 on the surface of the gate trench T1, a first polysilicon layer 1032 and a first conductive material layer 1033 are formed in the first insulating layer 1031. Among them, the conductivity of the first conductive material layer 1033 is greater than that of the first polysilicon layer 1032, so that in the prepared semiconductor device, compared with the prior art, the sheet resistance of the gate can be effectively reduced, thereby improving the charging ability of the gate. That is, at the same gate voltage, the gate can be charged to the required potential level faster, thus improving the response speed and performance of the semiconductor device. Figure 1 In the embodiments of the present application, in step 303, forming the gate structure 103 in the gate trench T1 may specifically include:

[0071] Form a first insulating layer 1031 on the surface of the gate trench T1, and sequentially form a first polysilicon layer 1032 and a first conductive material layer 1033 in the first insulating layer 1031. The first polysilicon layer 1032 is disposed between the first conductive material layer 1033 and the first insulating layer 1031. Therefore, through the direct contact between the first insulating layer 1031 and the first polysilicon layer 1032, since there are some discrete or continuous energy levels at the interface contact between the first insulating layer 1031 and the first polysilicon layer 1032, these energy levels can act as traps to capture carriers (electrons or holes), thereby affecting the gate's control ability over channel carriers. The threshold voltage can be adjusted by changing the doping concentration of the first polysilicon layer 1032, so as to maintain good interface characteristics.

[0072] In some embodiments, in addition to including the above steps, it can also be as shown above. A source trench T2 may be formed in the second region 109, and a source structure 112 may be formed in the source trench T2. The specific source structure 112 includes a second insulating layer 1121 formed on the surface of the source trench T2, and a second polysilicon layer 1122 and a second conductive material layer 1123 formed in the second insulating layer 1121. For the formation steps of the source trench T2 and the source structure 112, they can be formed synchronously with the gate trench T1 and the gate structure 103, partially synchronously formed, or formed in separate sequential steps.

[0073] In some embodiments, in addition to the above steps, it can also be as shown above. Figure 2 A source trench T2 may be formed in the second region 109, and a source structure 112 may be formed in the source trench T2. The specific source structure 112 includes a second insulating layer 1121 formed on the surface of the source trench T2, and a second polysilicon layer 1122 and a second conductive material layer 1123 formed in the second insulating layer 1121. For the formation steps of the source trench T2 and the source structure 112, they can be formed synchronously with the gate trench T1 and the gate structure 103, partially synchronously formed, or formed in separate sequential steps.

[0074] Figure 4 It is a specific flowchart of a preparation method of a semiconductor device provided by the embodiments of the present application, which can be combined with Figures 5 - 15The schematic diagram of the preparation process shown is used to understand the method for preparing a semiconductor device in an embodiment of the present application.

[0075] As Figure 4 shown, and with reference to Figures 5 - 15 simultaneously, the method for preparing a semiconductor device provided in an embodiment of the present application may include the following steps:

[0076] Step S10: As Figure 5 shown, an epitaxial layer 102 is formed on a substrate 101.

[0077] Exemplarily, the substrate 101 in an embodiment of the present application may be a SiC substrate and may be N-type heavily doped; in this step, an N-type lightly doped semiconductor material may be deposited on the substrate 101 to form the epitaxial layer 102.

[0078] Step S20: As Figure 6 shown, a well region 107 and a first region 108 are formed in a first surface P1 of the epitaxial layer 102, where the first surface P1 is located on a side away from the substrate 101. The first region 108 formed in this step is located on the first surface P1, and the well region 107 is located on a side of the first region 108 away from the first surface P1.

[0079] Exemplarily, in this step, a mask may be formed on the first surface P1 through a photolithography process, an ion implantation region may be defined, and P + ion implantation may be performed to form the well region 107. After removing the mask, a mask is formed again through a photolithography process, an ion implantation region is defined, and N + ion implantation is performed to form the first region 108. Among them, by controlling the implantation energy, the ion implantation depth is controlled, and finally, the first region 108 is located on the first surface P1, and the well region 107 is located on a side of the first region 108 away from the first surface P1.

[0080] Step S30: As Figure 7 shown, a second region 109 is formed in the epitaxial layer 102. The second region 109 is located on the first surface P1 and is located outside the first region 108 and the well region 107.

[0081] Exemplarily, a mask may be formed through a photolithography process, an ion implantation region may be defined, and P + ion implantation may be performed to form the second region 109.

[0082] Step S40: As Figure 8 shown, a gate trench T1 is formed. The gate trench T1 extends from the first surface P1 into the epitaxial layer 102 and penetrates through the first region 108 and the well region 107.

[0083] In some embodiments, during the process of forming the gate trench T1, a source trench T2 may also be formed on the first surface P1, and the source trench T2 is formed within the second region 109. In this step, the gate trench T1 and the source trench T2 may be formed synchronously through an etching process.

[0084] Step S50: As Figure 9 shown, a first insulating layer 1031 is formed within the gate trench T1, and a second insulating layer 1121 is formed within the source trench T2. In this step, the above-mentioned insulating layers may be formed through a gate oxide process. Among them, the first insulating layer 1031 includes an extension portion 113 extending onto the first surface P1.

[0085] Step S60: As Figure 10 shown, polysilicon is deposited and the excess is removed, and the deposited polysilicon material is patterned into a specific shape, that is, finally, a first polysilicon layer 1032 is formed within the gate trench T1. The first polysilicon layer 1032 includes an end portion 114 adjacent to the first surface P1. And a second polysilicon layer 1122 is formed within the source trench T2.

[0086] Step S70: As Figure 11 shown, a first conductive material layer 1033 is formed within the gate trench T1. The conductivity of the first conductive material layer 1033 is greater than that of the first polysilicon layer 1032. The first conductive material layer 1033 covers the end portion 114 of the first polysilicon layer 1032 adjacent to the first surface P1 and at least partially covers the extension portion 113 of the first insulating layer 1031 extending onto the first surface P1, which can avoid etching the first polysilicon layer 1032 and the first insulating layer 1031 simultaneously when etching the first conductive material layer 1033, and can also protect the corner of the first insulating layer 1031, where it is relatively thin and easily etched through.

[0087] Through the above steps S50 - S70, a first insulating layer 1031, a first polysilicon layer 1032, and a first conductive material layer 1033 are formed within the gate trench T1. The above-mentioned first insulating layer 1031, first polysilicon layer 1032, and first conductive material layer 1033 constitute the gate structure 103 of the semiconductor device. Since the conductivity of the first conductive material layer 1033 is greater than that of the first polysilicon layer 1032, the gate structure 103 can effectively reduce the sheet resistance of the gate, thereby improving the charging ability of the gate. Optionally, the above-mentioned first conductive material layer 1033 may generally be a metal material layer, including molybdenum, tungsten, or titanium, all of which have the advantages of high temperature resistance and low sheet resistance.

[0088] Step S80: Isolate and protect the gate structure 103. As Figure 12 shown, a first passivation layer 106 is deposited on the first surface P1.

[0089] Step S90: As Figure 13 shown, a source electrode 104 is formed on the first surface, and the above-mentioned source electrode 104 synchronously enters the source trench T2, thereby obtaining the second conductive material layer 1123.

[0090] Through the above steps S50, S60 and step S90, a second insulating layer 1121, a second polysilicon layer 1122 and a second conductive material layer 1123 are formed in the source trench T2, thereby forming the source structure 112.

[0091] Exemplarily, the above-mentioned source electrode 104 can be formed by sputtering or evaporation to deposit a metal.

[0092] Step S100: As Figure 14 shown, a second passivation layer 110 is deposited and a pad window is formed by etching. An insulating material is spin-coated on the surface of the second passivation layer 110, developed and exposed, and then cured to form an insulating dielectric layer 111 on the surface. The pad window is used for subsequent electrical connection with other components.

[0093] Step S110: As Figure 15 shown, a drain electrode 105 is formed. The drain electrode 105 is located on the side of the substrate 101 away from the epitaxial layer 102.

[0094] Specifically, by thinning the substrate 101, reducing the thickness of the substrate 101 and forming a relatively flat surface, and then depositing a metal and performing an annealing process, an ohmic contact of the drain electrode 105 is formed.

[0095] So far, the semiconductor device 10 shown in the above Figure 2 embodiment of the present application is fabricated. It can be understood that the above fabrication method is only an example, and some of its steps can be adjusted to implement the fabrication of the above semiconductor device 10.

[0096] On the other hand, an embodiment of the present application further provides a power module, Figure 16 which is a schematic structural diagram of the power module provided by the embodiment of the present application.

[0097] As Figure 16 shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments. The substrate 201 is used to carry the semiconductor device 10.

[0098] Exemplarily, the power module 200 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is a device used to control the power flow. The power management module is used to manage the power supply to ensure stable and efficient distribution of power to different parts of an electronic device. The power regulator is used to regulate the power output to meet the requirements of a specific application.

[0099] On the other hand, an embodiment of the present application also provides a power conversion circuit. Figure 17 It is a schematic structural diagram of the power conversion circuit provided by the embodiment of the present application.

[0100] As Figure 17 shown, the power conversion circuit 300 includes a circuit board 310 and the semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 310. The power conversion circuit 300 can be used for current conversion, voltage conversion, or power factor correction.

[0101] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit. Among them, the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce harmonic pollution of the power grid.

[0102] On the other hand, an embodiment of the present application also provides a vehicle. Figure 18 It is a schematic structural diagram of the vehicle provided by the embodiment of the present application.

[0103] As Figure 18 shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment. After the power conversion circuit 300 converts alternating current into direct current, converts alternating current into alternating current, converts direct current into direct current, or converts direct current into alternating current, it is input to the load 401 to supply power to the load 401.

[0104] The above power module, power conversion circuit, and vehicle have the same structure and beneficial technical effects as the semiconductor device provided in some of the above embodiments, and will not be elaborated here.

[0105] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, who thinks of changes or substitutions, should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described above.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; An epitaxial layer disposed on the substrate, the epitaxial layer being of a first conductivity type, the epitaxial layer including a first surface on a side away from the substrate, the epitaxial layer further including a well region and a first region, the first region being disposed on the first surface, the first region being of a first conductivity type, the well region being of a second conductivity type, the well region being disposed on a side of the first region away from the first surface, a gate trench being provided on the first surface, the gate trench extending from the first surface into the epitaxial layer and penetrating through the first region and the well region; A gate structure located in the gate trench, the gate structure including a first insulating layer formed on the surface of the gate trench, and a first polysilicon layer and a first conductive material layer formed in the first insulating layer, the conductivity of the first conductive material layer being greater than the conductivity of the first polysilicon layer; A source electrode formed on the first surface and electrically connected to the first region; A drain electrode disposed on a side of the substrate away from the epitaxial layer; Wherein, a source trench is further provided on the first surface, the source trench extending from the first surface into the epitaxial layer, and the semiconductor device further includes a source structure disposed in the source trench; The source structure includes a second insulating layer disposed on the surface of the source trench, a second polysilicon layer disposed inside the second insulating layer, and a second conductive material layer disposed inside the second polysilicon layer, the second conductive material layer being of the same material as the source electrode.

2. The semiconductor device according to claim 1, wherein, The first polysilicon layer is formed between the first conductive material layer and the first insulating layer.

3. The semiconductor device according to claim 2, wherein The first polysilicon layer includes an end portion adjacent to the first surface, and the first conductive material layer covers the end portion.

4. The semiconductor device according to claim 3, wherein The first insulating layer includes an extension portion extending onto the first surface, and at least a part of the first polysilicon layer covers the extension portion.

5. The semiconductor device according to claim 1, wherein, The first conductive material layer is a metal material layer or an oxide material layer.

6. The semiconductor device according to claim 5, wherein, The metal material layer includes molybdenum, tungsten or titanium, and the oxide material layer includes indium tin oxide or fluorine-doped tin oxide.

7. The semiconductor device according to claim 1, wherein The epitaxial layer further includes a second region, the second region being disposed on the first surface and located outside the first region and the well region, the second region being of a second conductivity type, and the source trench being formed in the second region.

8. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming an epitaxial layer on a substrate, the epitaxial layer including a first surface on a side away from the substrate, the epitaxial layer further including a well region and a first region, the first region being located on the first surface, the well region being located on a side of the first region away from the first surface; Forming a gate trench and a source trench on the first surface, the gate trench extending from the first surface into the epitaxial layer and penetrating through the first region and the well region; The source trench extends from the first surface into the epitaxial layer; Forming a gate structure in the gate trench and forming a source structure in the source trench; The gate structure includes a first insulating layer formed on the surface of the gate trench, a first polysilicon layer and a first conductive material layer formed in the first insulating layer, and the conductivity of the first conductive material layer is greater than that of the first polysilicon layer; the source structure includes a second insulating layer formed on the surface of the source trench, a second polysilicon layer formed inside the second insulating layer, and a second conductive material layer formed inside the second polysilicon layer; A source is formed on the first surface, and the source is electrically connected to the first region; the material of the second conductive material layer is the same as that of the source; A drain is formed, and the drain is located on the side of the substrate away from the epitaxial layer.

9. The preparation method according to claim 8, characterized in that, A gate structure is formed in the gate trench, including: A first insulating layer is formed on the surface of the gate trench, and a first polysilicon layer and a first conductive material layer are sequentially formed in the first insulating layer, and the first polysilicon layer is disposed between the first conductive material layer and the first insulating layer.

10. A power module, characterized in that, Including: At least one semiconductor device as described in any one of claims 1 to 7; A substrate for carrying the semiconductor device.

11. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 7, and the semiconductor device is electrically connected to the circuit board.

12. A vehicle, characterized in that, Including: A load and the power conversion circuit as described in claim 11, and the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it to the load.

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