Transistor preparation method, transistor and semiconductor device

Abstract

The invention provides a preparation method of a transistor, the transistor and a semiconductor device. The preparation method comprises the following steps: forming a stack structure on a semiconductor substrate; the stacking structure is etched to form a plurality of fin-shaped structures, the fin-shaped structures are sequentially arranged in the first direction, and a first groove is formed between any two adjacent fin-shaped structures in the fin-shaped structures; forming a first side wall covering the side walls of the plurality of fin-shaped structures in the first groove; etching the semiconductor substrate below the first groove to obtain a second groove; depositing a dielectric material in the first trench and the second trench to form an isolation structure; removing the first side wall to separate the isolation structure and the plurality of fin-shaped structures to obtain a first semiconductor structure; a plurality of first transistors are formed based on the plurality of fin-shaped structures in the first semiconductor structure, the isolation structure is used for electrically isolating any two adjacent first transistors in the plurality of first transistors, and the polarities of any two adjacent first transistors are the same or different.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a method for manufacturing a transistor, a transistor, and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. In order to further improve the integration density of transistors and promote the miniaturization of integrated circuits. In related technologies, an isolation structure can be formed at the boundary of transistor cells, such as direct back contact-cell boundary isolation (DBC-CBI), so as to facilitate the close arrangement of adjacent transistor cells.

[0003] However, there is no isolation structure between the multiple transistors in the transistor unit, which requires a larger spacing to be left inside the transistor unit to avoid circuits between the transistors. Therefore, there is a problem of low space utilization inside the transistor unit. Summary of the invention

[0004] The present application provides a method for manufacturing a transistor, a transistor and a semiconductor device to improve the integration density of the transistor.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a transistor, the method comprising: forming a stacked structure on a semiconductor substrate; etching the stacked structure to form a plurality of fin structures, wherein the plurality of fin structures are arranged in sequence along a first direction, and a first groove is formed between any two adjacent fin structures among the plurality of fin structures, and the first direction is perpendicular to a direction perpendicular to the semiconductor substrate; forming a first sidewall covering the sidewalls of the plurality of fin structures in the first groove; etching the semiconductor substrate below the first groove to obtain a second groove; depositing a dielectric material in the second groove to form an isolation structure; removing the first sidewall to separate the isolation structure and the plurality of fin structures to obtain a first semiconductor structure; forming a plurality of first transistors based on the plurality of fin structures in the first semiconductor structure, wherein one fin structure corresponds to forming one first transistor, and the isolation structure is used to electrically isolate any two adjacent first transistors among the plurality of first transistors, and the polarities of any two adjacent first transistors are the same or different.

[0006] In some embodiments, based on the multiple fin structures in the first semiconductor structure, multiple first transistors are formed, including: in the gate region, forming a first dummy gate structure covering the multiple fin structures and the isolation structure; in the source and drain region, etching the fin structures not covered by the first dummy gate structure to retain the isolation structure; based on the multiple fin structures in the gate region, multiple first source and drain structures are epitaxially formed in the source and drain region, wherein in a first direction, two adjacent first source and drain structures are isolated by the isolation structure; removing the first dummy gate structure to expose the multiple fin structures and the isolation structure, and forming multiple first gate structures on the exposed multiple fin structures, wherein a first source and drain structure and a first gate structure constitute a first transistor, and in the first direction, two adjacent first gate structures are isolated by the isolation structure.

[0007] In some embodiments, the fin structure includes: sacrificial layers and active layers stacked alternately; forming multiple first gate structures on the exposed multiple fin structures, including: removing the sacrificial layers in the exposed multiple fin structures to retain the active layers in the multiple fin structures; and forming a first gate structure surrounding the active layer for each of the multiple fin structures.

[0008] In some embodiments, the multiple fin structures include a first fin structure, a second fin structure, a third fin structure and a fourth fin structure arranged in sequence in a first direction; based on the multiple fin structures in the gate region, multiple first source-drain structures are epitaxially formed in the source-drain region, including: based on the first fin structure, the second fin structure, the third fin structure and the fourth fin structure in the gate region, a first sub-source-drain structure, a second sub-source-drain structure, a third sub-source-drain structure and a fourth sub-source-drain structure are respectively epitaxially formed in the source-drain region; wherein the first sub-source-drain structure, the second sub-source-drain structure, the third sub-source-drain structure and the fourth sub-source-drain structure are all first source-drain structures, the material forming the first sub-source-drain structure is the same as the material forming the second sub-source-drain structure, the material forming the second sub-source-drain structure is different from the material forming the third sub-source-drain structure, and the material forming the third sub-source-drain structure is the same as the material forming the fourth sub-source-drain structure.

[0009] In some embodiments, after forming multiple first transistors based on multiple fin structures in the first semiconductor structure, the method also includes: after forming a gate direct connection structure connected to the first gate structure, flipping over and removing the semiconductor substrate and forming a source-drain direct connection structure connected to the first source-drain structure; or, after forming the source-drain direct connection structure connected to the first source-drain structure, flipping over and removing the semiconductor substrate and forming a gate direct connection structure connected to the first gate structure.

[0010] In some embodiments, a first sidewall covering the sidewalls of multiple fin structures is formed in the first trench, including: depositing an oxide material on the first trench and the multiple fin structures to form a first oxide layer, wherein the first oxide layer covers the upper surface of the semiconductor substrate and the sidewalls and upper surface of the multiple fin structures; and etching the first oxide layer using an isotropic etching process until the semiconductor substrate and the multiple fin structures are exposed to form the first sidewall.

[0011] In some embodiments, a dielectric material is deposited in the second trench to form an isolation structure, including: depositing the dielectric material until the second trench is filled to form an initial isolation structure; etching the initial isolation structure using an isotropic etching process until multiple fin structures are exposed to form an isolation structure.

[0012] In some embodiments, the first transistor is any one of the following: a fin field effect transistor, a gate-all-around field effect transistor, and a planar field effect transistor.

[0013] In a second aspect, an embodiment of the present application provides a transistor, which is prepared using the method for preparing a transistor in any embodiment of the first aspect. The transistor includes: a plurality of first transistors; an isolation structure is provided between the active structures of any two adjacent first transistors in the plurality of first transistors, wherein the active structure includes a first gate structure and a first source-drain structure in the first transistor; the isolation structure is used to electrically isolate any two adjacent first transistors in the plurality of first transistors, and the polarities of any two adjacent first transistors are the same or different.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor device, including: a semiconductor structure as described in the above embodiment.

[0015] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0016] The technical solution provided by this application may have the following beneficial effects:

[0017] In an embodiment of the present application, a plurality of fin structures arranged in sequence are formed by etching a stacked structure on a semiconductor substrate, and then an isolation structure is formed between any two adjacent fin structures among the plurality of fin structures, so that any two adjacent fin structures can be electrically isolated, thereby forming a plurality of first transistors through a plurality of mutually isolated fin structures. In this process, since an isolation structure is formed between any two adjacent first transistors, the spacing between the plurality of first transistors can be effectively reduced. In particular, when two adjacent first transistors can constitute a transistor unit, the space inside the transistor unit can be further compressed by the isolation structure, thereby improving the integration density of the transistor.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0020] Figure 1 A schematic diagram of the implementation process of a method for preparing a transistor provided in an embodiment of the present application.

[0021] Figure 2 A top view of a transistor provided in an embodiment of the present application.

[0022] Figures 3 to 21 for Figure 2 A schematic diagram of the structure of a transistor during the preparation process is shown.

[0023] Fig. 22 A schematic diagram of the structure of the first transistor provided in an embodiment of the present application.

[0024] Fig.23 A schematic diagram of the structure of a second transistor provided in an embodiment of the present application.

[0025] Fig.24 A schematic diagram of the structure of the third transistor provided in an embodiment of the present application.

[0026] The above pictures:

[0027] 11. first transistor; 11a. first sub-transistor; 11b. second sub-transistor; 11c. third sub-transistor; 11d. fourth sub-transistor; 111. first pseudo-gate spacer; 112. first source-drain structure; 112a. first source-drain structure in N-type field effect transistor; 112b. first source-drain structure in P-type field effect transistor; 113. first interlayer dielectric layer; 114. first gate structure; 115. gate direct connection structure; 116. source-drain direct connection structure; 12. first semiconductor structure; 20. semiconductor substrate; 21. stacked structure ; 22. oxide layer; 23. hard mask layer; 24. first trench; 25. first oxide layer; 26. first sidewall; 27. second trench; 28. initial isolation structure; 29. ​​isolation structure; 30. first dummy gate structure; 31. dummy gate etching layer; 32. internal sidewall; 33. placeholder layer; 34. gate gap; 35. spacing structure; 36. fin structure; 36a. first fin structure; 36b. second fin structure; 36c. third fin structure; 36d. fourth fin structure; 38. dielectric layer; 211. active layer; 212. sacrificial layer. DETAILED DESCRIPTION

[0028] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0029] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. However, there is a problem of low space utilization inside the transistor unit in the related technology. In order to solve the above technical problems, the present application provides a method for preparing a transistor, a transistor and a semiconductor device to improve the integration density of the transistor.

[0030] In a first aspect, an embodiment of the present application provides a method for manufacturing a transistor.

[0031] Figure 1 A schematic diagram of the implementation process of a method for preparing a transistor provided in an embodiment of the present application. Figure 2 A top view of a transistor provided in an embodiment of the present application. Here, only the source-drain structure and the gate structure are shown in the top view; Figures 3 to 21 for Figure 2 The schematic diagram of the structure of a transistor during the preparation process is shown. Here, Figure 3 (a) to Fig.21 (a) is along Figure 2 Schematic diagram of the structure of the AA' section; Figure 3 (b) to Fig.21 (b) is along Figure 2 The structural diagram of the BB' section in FIG. Figure 3 (c) to Fig.21 (c) is along Figure 2 Schematic diagram of the CC' section structure. Figures 1 to 21 , a method for preparing a transistor may include:

[0032] Step S101 : forming a stack structure 21 on a semiconductor substrate 20 .

[0033] It is understandable that material layer deposition, epitaxial growth, photolithography and other processes may be performed on the semiconductor substrate 20 to form a stacked structure 21 .

[0034] In some embodiments, the semiconductor substrate 20 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, etc., which is not limited in the embodiments of the present application.

[0035] In some embodiments, the stacked structure 21 may be formed by multiple material layers or by one material layer, which is not limited in the embodiments of the present application. In one embodiment, when the stacked structure 21 is formed by multiple material layers, the first transistor 11 may be a gate-all-around field effect transistor (GAAFET). In one embodiment, when the stacked structure 21 is formed by one material layer, the first transistor 11 is a finfield effect transistor (FinFET) or a planar field effect transistor.

[0036] In some embodiments, the plurality of first transistors 11 in the transistors may be transistors of the same type, for example, they may all be fin field effect transistors or all-around gate transistors.

[0037] In one embodiment, the steps of the photolithography process in the embodiment of the present application may include: depositing photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove the material layer corresponding to the portion of the photoresist material, etc.

[0038] Step S102 , etching the stacked structure 21 to form a plurality of fin structures 36 .

[0039] It is understandable that after the stack structure 21 is formed on the semiconductor substrate 20 , the stack structure 21 may be subjected to an etching process such as dry etching, wet etching, reactive ion etching, etc. until the semiconductor substrate 20 is exposed to form a plurality of fin structures 36 .

[0040] In some embodiments, the plurality of fin structures 36 are sequentially arranged along a first direction, and a first trench 24 is formed between any two adjacent fin structures 36 among the plurality of fin structures 36. In one embodiment, the first direction is perpendicular to a direction perpendicular to the semiconductor substrate 20. Figure 2 As shown, the first direction is Figure 2 The direction of travel is from top to bottom.

[0041] In one example, see Figure 4 In (a), a plurality of fin-shaped structures 36 are arranged sequentially from left to right, and a first trench 24 is formed between any two adjacent fin-shaped structures 36 .

[0042] Step S103 , forming a first spacer 26 in the first trench 24 to cover the sidewalls of the plurality of fin structures 36 .

[0043] It can be understood that the sidewall of each fin structure 36 in the plurality of fin structures 36 may be exposed through the first trench 24. Subsequently, an oxide material may be deposited in the first trench 24 to form a first spacer 26 covering the sidewalls of the plurality of fin structures 36.

[0044] In some embodiments, the oxide material forming the first sidewall spacer 26 may be silicon oxide, aluminum oxide or the like, which is not limited in the embodiments of the present application.

[0045] In some embodiments, step S103 may include: depositing an oxide material on the first trench 24 and the multiple fin structures 36 to form a first oxide layer 25, wherein the first oxide layer 25 covers the upper surface of the semiconductor substrate 20 and the sidewalls and upper surfaces of the multiple fin structures 36; and etching the first oxide layer 25 using an isotropic etching process until the semiconductor substrate 20 and the multiple fin structures 36 are exposed to form a first sidewall 26.

[0046] It can be understood that by depositing an oxide material on the first trench 24 and the multiple fin structures 36, a first oxide layer 25 covering the first trench 24 and the multiple fin structures 36 can be formed. Here, the first oxide layer 25 covering the first trench 24 and the multiple fin structures 36 can also be understood as the first oxide layer 25 covering the exposed upper surface of the semiconductor substrate 20 and the sidewalls and upper surfaces of the multiple fin structures 36. After the first oxide layer 25 is formed, the first oxide layer 25 is etched by an isotropic etching process until the upper surface of the semiconductor substrate 20 and the upper surfaces of the multiple fin structures 36 are exposed, so as to form a first sidewall 26 covering the sidewalls of the multiple fin structures 36.

[0047] Step S104 , etching the semiconductor substrate 20 below the first trench 24 to obtain a second trench 27 .

[0048] It can be understood that, in the process of forming the first spacer 26 , the semiconductor substrate 20 located below the first trench 24 may be exposed, and then the semiconductor substrate 20 may be etched to obtain the second trench 27 . Here, the second trench 27 includes the first trench 24 .

[0049] In some embodiments, a third trench may be obtained by forming a first sidewall 26 in the first trench 24. Etching the semiconductor substrate 20 below the first trench 24 to obtain a second trench 27 includes etching the semiconductor substrate 20 below the third trench to obtain a second trench 27 below the third trench. Here, the second trench 27 includes the third trench.

[0050] It should be noted that the etching process used for etching the semiconductor substrate can be selected according to actual needs, and the embodiments of the present application do not limit this.

[0051] Step S105 , depositing a dielectric material in the second trench 27 to form an isolation structure 29 .

[0052] It can be understood that after forming the second trench 27 , a dielectric material may be deposited in the second trench 27 to form an isolation structure 29 .

[0053] In some embodiments, the dielectric material may be a nitride material.

[0054] In some embodiments, when each fin structure 36 includes a plurality of active layers 211 (nanosheets), the isolation structure 29 may be a forksheet structure.

[0055] In some embodiments, step S105 may include: depositing a dielectric material until the second trench 27 is filled to form an initial isolation structure 28 ; and etching the initial isolation structure 28 using an isotropic etching process until the plurality of fin structures 36 are exposed to form an isolation structure 29 .

[0056] It can be understood that by depositing dielectric material until the second trench 27 is filled, an initial isolation structure 28 covering multiple fin structures 36 can be formed, and then the initial isolation structure 28 can be etched using an isotropic etching process until the multiple fin structures 36 are exposed to form an isolation structure 29.

[0057] Step S106 , removing the first spacer 26 to separate the isolation structure 29 and the plurality of fin structures 36 , and obtaining the first semiconductor structure 12 .

[0058] It can be understood that by removing the first sidewall 26, the space between the isolation structure 29 and the plurality of fin structures 36 can be released, thereby separating the isolation structure 29 and the plurality of fin structures 36 to obtain the first semiconductor structure 12. The first semiconductor structure 12 is prepared by steps S101 to S106. The first semiconductor structure 12 includes a semiconductor substrate 20, a plurality of fin structures 36 and an isolation structure 29.

[0059] Step S107 , forming a plurality of first transistors 11 based on the plurality of fin structures 36 in the first semiconductor structure 12 .

[0060] It can be understood that after the first semiconductor structure 12 is obtained through the above steps, a plurality of first transistors 11 can be formed based on the plurality of fin structures 36 in the first semiconductor structure 12 by using a standard semiconductor manufacturing process.

[0061] It can be understood that the first transistor 11 includes a first source-drain structure 112 and a first gate structure 114. The preparation process for forming the first source-drain structure 112 and the first gate structure 114 can be selected according to actual needs, and the embodiment of the present application does not limit this.

[0062] In one embodiment, one fin structure 36 forms one first transistor 11 , and a plurality of fin structures 36 form a plurality of first transistors 11 .

[0063] It can be understood that the multiple fin structures 36 are separated from the isolation structure 29, and the space between the multiple fin structures 36 and the isolation structure 29 can be used to form the structure of the first transistor 11 (including the first source-drain structure 112 and the first gate structure 114), so that the isolation structure 29 is used to isolate any two adjacent first transistors 11 among the multiple first transistors 11, thereby realizing electrical isolation of any adjacent first transistors 11 among the multiple first transistors 11.

[0064] In some embodiments, the transistor structures of the multiple first transistors 11 may be the same or different. When the transistor structures of the multiple first transistors 11 are the same, the polarities of the multiple first transistors 11 may be the same, for example, the multiple first transistors 11 are all P-type field effect transistors (P-channel Field Effect Transistor). When the transistor structures of the multiple first transistors 11 are different, the polarities of the multiple first transistors 11 may be different, for example, the first sub-transistor 11a in the multiple first transistors 11 is a P-type field effect transistor (P-channel Field Effect Transistor), and the second sub-transistor 11b is an N-type field effect transistor (N-channel Field Effect Transistor).

[0065] It can be understood that when the structures of the two first transistors 11 are different, the first source-drain structures 112 of the two first transistors 11 may be different, that is, the materials forming the first source-drain structures 112 may be different.

[0066] In some embodiments, step S107 may include: forming a first dummy gate structure 30 covering multiple fin structures 36 and isolation structures 29 in the gate region; etching the fin structures 36 not covered by the first dummy gate structure 30 in the source and drain region, retaining the isolation structure 29; based on the multiple fin structures 36 in the gate region, epitaxially forming multiple first source and drain structures 112 in the source and drain region; removing the first dummy gate structure 30 to expose the multiple fin structures 36 and isolation structures 29, and forming multiple first gate structures 114 on the exposed multiple fin structures 36.

[0067] It can be understood that in the process of forming multiple first transistors 11, a first dummy gate structure 30 covering multiple fin structures 36 and isolation structures 29 can be first formed in the gate region, and then the fin structures 36 not covered by the first dummy gate structure 30 are etched in the source and drain regions to expose the isolation structures 29. At this time, there are no multiple fin structures 36 in the source and drain regions, but there are fin structures 36 in the gate region, and multiple first source and drain structures 112 can be epitaxially grown in the source and drain regions using the multiple fin structures 36 in the gate region. After the first source and drain structures 112 are formed, the first dummy gate structure 30 in the gate region can be removed to expose the multiple fin structures 36 and isolation structures 29 in the gate region. After the multiple fin structures 36 in the gate region are exposed, multiple first gate structures 114 can be formed on the multiple fin structures 36.

[0068] It can be understood that the gate region refers to the region in the transistor for forming the gate structure, and the source-drain region refers to the region in the transistor for forming the source-drain structure. In the second direction, the gate structure and the source-drain structure of the transistor are arranged alternately in sequence, so that the gate region and the source-drain region of the transistor are arranged alternately in sequence. Here, the second direction is perpendicular to the direction perpendicular to the semiconductor substrate, and the second direction is perpendicular to the first direction.

[0069] For example, Figure 2 As shown, the second direction may be a direction traveling from left to right.

[0070] In some embodiments, a first source-drain structure 112 and a first gate structure 114 constitute a first transistor 11 . In a first direction, two adjacent first gate structures 114 are isolated by an isolation structure 29 , and two adjacent first source-drain structures 112 are isolated by an isolation structure 29 .

[0071] In some embodiments, after forming the first dummy gate structure 30, a first dummy gate spacer 111 may be formed to cover the sidewall of the first dummy gate structure 30. Here, the first dummy gate spacer 111 is located at the intersection of the gate region and the source and drain region.

[0072] In some embodiments, the material forming the dummy gate structure may be polysilicon, amorphous silicon, etc.; the material forming the dummy gate sidewall may be silicon oxide, silicon nitride, etc. In one example, the first dummy gate sidewall 111 may have a single-layer structure, and the entire structure may be made of the same material (e.g., porous silicon carbon oxyhydride (SiCOH)).

[0073] In some embodiments, according to the polarity of the first transistor, the first source-drain structure 112 can be divided into a first source-drain structure 112a and a first source-drain structure 112b, wherein the first source-drain structure 112a is the first source-drain structure in the N-type field effect transistor, and the first source-drain structure 112b is the first source-drain structure in the P-type field effect transistor.

[0074] For example, Fig.14 As shown in (b), the embodiment of the present application can epitaxially generate the first source-drain structure 112a and the first source-drain structure 112b.

[0075] In some embodiments, after the first source-drain structure 112 is formed, an insulating material may be deposited on the first source-drain structure 112 to form a first interlayer dielectric layer 113 .

[0076] In some embodiments, before forming the first source-drain structure 112 , the semiconductor substrate 20 may be etched in the source-drain region to form a fourth trench, and a placeholder layer material such as silicon dioxide or silicon nitride may be deposited in the fourth trench to form a placeholder layer 33 .

[0077] It can be understood that the placeholder layer 33 is used to position the first source-drain structure 112 after flipping the wafer, so that based on the position of the placeholder layer 33 , a source-drain direct connection structure 116 can be formed by self-alignment.

[0078] In some embodiments, after removing the plurality of first dummy gate structures 30 , a metal material may be deposited at the locations of the removed first dummy gate structures 30 , and the deposited metal material is used to form the first gate structure 114 .

[0079] The first gate structure 114 at least includes: a first gate dielectric layer and a first gate electrode layer. The materials of the gate dielectric layer and the gate electrode layer can be set according to actual needs, and the embodiment of the present application does not specifically limit this.

[0080] Exemplarily, the first gate dielectric layer may be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the first transistor. The first gate electrode layer may be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0081] In one example, the first gate dielectric layer may include: a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0082] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the source-drain direct connection metal is similar, and the "source-drain" is an abbreviation for "source and / or drain".

[0083] In some embodiments, the fin structure 36 includes: alternatingly stacked sacrificial layers 212 and active layers 211; forming multiple first gate structures 114 on the exposed multiple fin structures 36, including: removing the sacrificial layers 212 in the exposed multiple fin structures 36 to retain the active layers 211 in the multiple fin structures 36; for each fin structure 36 in the multiple fin structures 36, forming a first gate structure 114 surrounding the active layer 211.

[0084] It can be understood that each fin includes alternately stacked sacrificial layers 212 and active layers 211, and the stacking direction of the sacrificial layers 212 and the active layers 211 is perpendicular to the direction of the semiconductor substrate 20. When forming multiple first gate structures 114, the sacrificial layers 212 in the exposed multiple fin structures 36 can be removed to complete channel release, thereby retaining the active layers 211 in the multiple fin structures 36, and forming the first gate structure 114 surrounding the active layer 211.

[0085] It can be understood that after the first gate structure 114 surrounding the active layer 211 is formed, the first transistor 11 can be a full surrounding gate field effect transistor.

[0086] At this point, the preparation of multiple first transistors 11 is completed. It can be understood that an isolation structure 29 is provided between the multiple first transistors 11, and the isolation structure 29 can electrically isolate the active structures of the multiple first transistors 11, thereby eliminating the need to set a large spacing between the multiple first transistors 11, thereby improving the integration of the transistors.

[0087] In an embodiment of the present application, a plurality of fin structures arranged in sequence are formed by etching a stacked structure on a semiconductor substrate, and then an isolation structure is formed between any two adjacent fin structures among the plurality of fin structures, so that any two adjacent fin structures can be electrically isolated, thereby forming a plurality of first transistors through a plurality of mutually isolated fin structures. In this process, since an isolation structure is formed between any two adjacent first transistors, the spacing between the plurality of first transistors can be effectively reduced. In particular, when two adjacent first transistors can constitute a transistor unit, the space inside the transistor unit can be further compressed by the isolation structure, thereby improving the integration density of the transistor.

[0088] In some possible implementations, after step S107 , the process may include: after forming a gate direct connection structure 115 connected to the first gate structure 114 , flipping over and removing the semiconductor substrate 20 and forming a source-drain direct connection structure 116 connected to the first source-drain structure 112 .

[0089] It can be understood that after forming the first gate structure 114, a gate direct connection structure 115 can be formed on the first gate structure 114, and an upper metal interconnection layer can be formed on the gate direct connection structure 115. Here, the gate direct connection structure 115 can connect the first gate structure 114 and the upper metal interconnection layer. Subsequently, the first transistor 11 is flipped and the semiconductor substrate 20 is removed. After removing the semiconductor substrate 20, a source-drain direct connection structure 116 is formed on the first source-drain structure 112, and a lower metal interconnection layer is formed on the source-drain direct connection structure 116. Here, the source-drain direct connection structure 116 can connect the first source-drain structure 112 and the lower metal interconnection layer.

[0090] In some embodiments, forming the gate connection structure 115 on the first gate structure 114 may include: depositing a dielectric material on the first gate structure 114 to form a dielectric layer 38. Etching the dielectric layer 38 until the first gate structure 114 is exposed to form a through hole, and depositing a metal material in the through hole to form the gate connection structure 115.

[0091] In some embodiments, forming the source-drain direct connection structure 116 on the first source-drain structure 112 may include: depositing a metal material on the exposed first source-drain structure 112 to form the source-drain direct connection structure 116 .

[0092] In some embodiments, forming the source-drain direct connection structure 116 on the first source-drain structure 112 may include: depositing a dielectric material on the first source-drain structure 112 to form a dielectric layer 38. Etching the dielectric layer 38 until the first source-drain structure 112 is exposed to form a through hole, and depositing a metal material in the through hole to form the source-drain direct connection structure 116.

[0093] In some embodiments, forming a source-drain direct connection structure 116 on the first source-drain structure 112 may include: removing the placeholder layer 33 on the first source-drain structure 112 to expose the first source-drain structure 112 , and depositing a metal material on the exposed first source-drain structure 112 to form the source-drain direct connection structure 116 .

[0094] In some embodiments, an upper metal interconnection layer and a lower metal interconnection layer are formed through back-end processes (such as deposition of dielectric between interconnection lines, formation of metal lines, formation of lead pads, etc.).

[0095] In some embodiments, the lower metal interconnect layer may be a backside power distribution network (BSPDN).

[0096] In some possible implementations, after step S107 , the process may include: after forming a source-drain direct connection structure 116 connected to the first source-drain structure 112 , flipping and removing the semiconductor substrate 20 and forming a gate direct connection structure 115 connected to the first gate structure 114 .

[0097] It can be understood that after forming the first source-drain structure 112, a source-drain direct connection structure 116 can be formed on the first source-drain structure 112, and an upper metal interconnection layer can be formed on the source-drain direct connection structure 116. Here, the source-drain direct connection structure 116 can connect the first source-drain structure 112 and the upper metal interconnection layer. Subsequently, the first transistor 11 is flipped, and the semiconductor substrate 20 is removed. After removing the semiconductor substrate 20, a gate direct connection structure 115 is formed on the first gate structure 114, and a lower metal interconnection layer is formed on the gate direct connection structure 115. Here, the gate direct connection structure 115 can connect the first gate structure 114 and the lower metal interconnection layer.

[0098] In some embodiments, forming the source-drain direct connection structure 116 on the first source-drain structure 112 may include: depositing a dielectric material on the first source-drain structure 112 to form a dielectric layer 38. Etching the dielectric layer 38 until the first source-drain structure 112 is exposed to form a through hole, and depositing a metal material in the through hole to form the source-drain direct connection structure 116.

[0099] In some embodiments, forming the gate connection structure 115 on the first gate structure 114 may include: depositing a metal material on the exposed first gate structure 114 to form the gate connection structure 115 .

[0100] In some embodiments, forming the gate connection structure 115 on the first gate structure 114 may include: depositing a dielectric material on the first gate structure 114 to form a dielectric layer 38. Etching the dielectric layer 38 until the first gate structure 114 is exposed to form a through hole, and depositing a metal material in the through hole to form the gate connection structure 115.

[0101] In the embodiment of the present application, the back power supply network can be connected to different structures of transistors as needed, thereby improving the flexibility of integrated circuit wiring. At the same time, transistors using the back power supply network can effectively alleviate the current drop (IR-Drop) effect and improve the space utilization of the circuit.

[0102] In some possible embodiments, the multiple fin structures 36 include a first fin structure 36a, a second fin structure 36b, a third fin structure 36c and a fourth fin structure 36d arranged in sequence in a first direction; based on the multiple fin structures 36 in the gate region, multiple first source-drain structures 112 are epitaxially formed in the source-drain region, including: based on the first fin structure 36a, the second fin structure 36b, the third fin structure 36c and the fourth fin structure 36d in the gate region, a first sub-source-drain structure, a second sub-source-drain structure, a third sub-source-drain structure and a fourth sub-source-drain structure are respectively epitaxially formed in the source-drain region.

[0103] It can be understood that when the plurality of fin structures 36 include a first fin structure 36a, a second fin structure 36b, a third fin structure 36c, and a fourth fin structure 36d arranged in sequence in the first direction, a first sub-transistor 11a, a second sub-transistor 11b, a third sub-transistor 11c, and a fourth sub-transistor 11d can be formed based on the first fin structure 36a, the second fin structure 36b, the third fin structure 36c, and the fourth fin structure 36d, respectively. The first sub-transistor 11a, the second sub-transistor 11b, the third sub-transistor 11c, and the fourth sub-transistor 11d are all first transistors 11.

[0104] It can be understood that in the process of forming the first sub-transistor 11a, the second sub-transistor 11b, the third sub-transistor 11c and the fourth sub-transistor 11d, based on the first fin structure 36a, the second fin structure 36b, the third fin structure 36c and the fourth fin structure 36d in the gate region, the first sub-source-drain structure, the second sub-source-drain structure, the third sub-source-drain structure and the fourth sub-source-drain structure can be respectively formed by epitaxial growth in the source-drain region.

[0105] In some embodiments, the material forming the first sub-source-drain structure is the same as the material forming the second sub-source-drain structure, the material forming the second sub-source-drain structure is different from the material forming the third sub-source-drain structure, and the material forming the third sub-source-drain structure is the same as the material forming the fourth sub-source-drain structure.

[0106] It can be understood that the material forming the first sub-source-drain structure is the same as the material forming the second sub-source-drain structure, and the polarity of the first sub-transistor 11a and the second sub-transistor 11b is the same; the material forming the second sub-source-drain structure is different from the material forming the third sub-source-drain structure, and the polarity of the second sub-transistor 11b and the third sub-transistor 11c is different; the material forming the third sub-source-drain structure is the same as the material forming the fourth sub-source-drain structure, and the polarity of the third sub-transistor 11c and the fourth sub-transistor 11d is the same.

[0107] For example, see Fig.21As shown in the figure, a first sub-transistor 11a, a second sub-transistor 11b, a third sub-transistor 11c and a fourth sub-transistor 11d are shown, wherein the source-drain structure in the first sub-transistor 11a and the second sub-transistor 11b is made of the same material, and the source-drain structure in the first sub-transistor 11a and the second sub-transistor 11b is a first source-drain structure 112a; the source-drain structure in the third sub-transistor 11c and the fourth sub-transistor 11d is made of the same material, and the source-drain structure in the third sub-transistor 11c and the fourth sub-transistor 11d is a second source-drain structure 112b; the source-drain structure in the second sub-transistor 11b and the third sub-transistor 11c is made of different materials, and the source-drain structure in the second sub-transistor 11b is the first source-drain structure 112a, and the source-drain structure in the third sub-transistor 11c is the second source-drain structure 112b.

[0108] In the embodiment of the present application, there is an isolation structure between every two transistors. Since an isolation structure is formed between every two transistors, the spacing between transistors can be effectively reduced, thereby further compressing the distribution of transistors and improving space utilization. At the same time, the manufacturing process can be optimized by using the preparation method in the embodiment of the present application, that is, the isolation structure can also serve as a shallow trench isolation and a gate isolation thin layer, thereby eliminating the steps of shallow trench isolation material filling and gate isolation thin layer formation.

[0109] Next, combine Figures 3 to 21 The preparation process shown is used as a specific example to illustrate the preparation method in the examples of the present application.

[0110] In one example, a process for preparing a transistor may include the following steps:

[0111] The first step, such as Figure 3 As shown, a stacked structure 21 , an oxide layer 22 and a hard mask layer 23 are formed on a semiconductor substrate 20 .

[0112] It can be understood that the preparation process of the transistor is described by taking the stacked structure 21 as a nanosheet structure as an example. The nanosheet structure includes a sacrificial layer 212 and an active layer 211 that are alternately stacked. The stacked structure 21 can be formed by a deposition process. After the stacked structure 21 is formed, an oxide layer 22 and a hard mask layer 23 can be deposited. Among them, the hard mask layer 23 is used to prevent the stacked structure 21 below from being etched.

[0113] The second step is, Figure 4 As shown, the stack structure 21 is etched to form a plurality of fin structures 36 .

[0114] It can be understood that the shapes of the multiple fin structures 36 can be controlled by the hard mask layer 23. Here, a first trench 24 can be formed between any two adjacent fin structures 36 among the multiple fin structures 36. The groove wall of the first trench 24 is formed by the side walls of the multiple fin structures 36, and the groove bottom of the first trench 24 is formed by the semiconductor substrate 20.

[0115] The third step is Figure 5 As shown, a first oxide layer 25 is deposited and formed.

[0116] It can be understood that an oxide material can be deposited on the structure formed in the second step to form a first oxide layer 25. The first oxide layer 25 covers the first trench 24 and the plurality of fin structures 36.

[0117] The fourth step is Figure 6 As shown, the first oxide layer 25 is isotropically etched to form a first spacer 26 .

[0118] It can be understood that, through the isotropic process, only the first oxide layer 25 located on the sidewalls of the plurality of fin-shaped structures 36 is retained, thereby obtaining the first spacer 26 .

[0119] Step 5: Figure 7 As shown, the semiconductor substrate 20 is etched to form a second trench 27 .

[0120] It can be understood that after the semiconductor substrate 20 is exposed in the fourth step, the semiconductor substrate 20 can be etched downward to form the second trench 27. The second trench 27 includes the first trench 24.

[0121] Step 6: Figure 8 As shown, a dielectric material is deposited to form an initial isolation structure 28 .

[0122] It can be understood that the initial isolation structure 28 fills the second trench 27 and covers the plurality of fin structures 36 .

[0123] Step 7: Fig. 9 As shown, the initial isolation structure 28 is etched by an isotropic etching process to form an isolation structure 29 .

[0124] It can be understood that when the plurality of fin-shaped structures 36 are nanosheet structures, the isolation structure 29 can be a forksheet structure.

[0125] Step 8: Fig.10 As shown, the first spacer 26 , the hard mask layer 23 and the oxide layer 22 are removed to expose the fin structure 36 , thereby obtaining the first semiconductor structure 12 .

[0126] Step 9: Fig.11 As shown, in the gate region (see Fig.11 In (a)), a first dummy gate structure 30 is formed.

[0127] It is understandable that the first dummy gate spacer 111 and the dummy gate etching layer 31 may be formed while forming the first dummy gate structure 30 . The first dummy gate spacer 111 covers the sidewall of the first dummy gate structure 30 , and the dummy gate etching layer 31 covers the upper surface of the first dummy gate structure 30 .

[0128] Step 10: Fig.12 As shown, in the source and drain regions (see Fig.12 In (b)), the plurality of fin structures 36 are removed.

[0129] It can be understood that by removing the multiple fin structures 36 in the source and drain regions, the sidewalls of the multiple fin structures 36 in the gate region can be exposed.

[0130] Step 11: Fig.13 As shown, a plurality of inner spacers 32 of fin-shaped structures 36 are formed in the gate region.

[0131] It is understandable that the sacrificial layer 212 of the multiple fin-shaped structures 36 exposed in the tenth step can be etched to a certain depth, and an insulating material can be deposited at the position where the sacrificial layer 212 is etched to form the internal sidewalls 32 of the multiple fin-shaped structures 36. The internal sidewalls 32 are used to electrically isolate the internal structures of the transistor, such as the gate structure and the source and drain structure.

[0132] Step 12: Fig.14 As shown, a placeholder layer 33 and a first source / drain structure 112 are formed in the source / drain region.

[0133] It can be understood that after removing the multiple fin structures 36 in the source and drain regions, the semiconductor substrate 20 in the source and drain regions can be exposed. Subsequently, the exposed semiconductor substrate 20 can be etched to a preset depth to form a fourth trench. Then, a placeholder layer 33 material such as silicon dioxide and silicon nitride is deposited in the fourth trench to form a placeholder layer 33. After the placeholder layer 33 is formed, the first source and drain structure 112 can be epitaxially grown in the source and drain regions based on the fin structure 36 in the gate region.

[0134] In one embodiment, if Figures 14 to 21As shown, the plurality of fin structures 36 are respectively a first fin structure 36, a second fin structure 36, a third fin structure 36 and a fourth fin structure 36. Based on the first fin structure 36a, the second fin structure 36b, the third fin structure 36c and the fourth fin structure 36d, the first source-drain structure 112 in the first sub-transistor 11a, the second sub-transistor 11b, the third sub-transistor 11c and the fourth sub-transistor 11d can be formed respectively. Among them, the material forming the first sub-source-drain structure is the same as the material forming the second sub-source-drain structure, and the polarity of the first sub-transistor 11a and the second sub-transistor 11b is the same; the material forming the second sub-source-drain structure is different from the material forming the third sub-source-drain structure, and the polarity of the second sub-transistor 11b and the third sub-transistor 11c is different; the material forming the third sub-source-drain structure is the same as the material forming the fourth sub-source-drain structure, and the polarity of the third sub-transistor 11c and the fourth sub-transistor 11d is the same.

[0135] Step 13: Fig.15 As shown, after the first source-drain structure 112 is formed, a first interlayer dielectric layer 113 is formed on the first source-drain structure 112 .

[0136] It can be understood that the first interlayer dielectric layer 113 can be formed of an insulating material.

[0137] Step 14: Fig.16 As shown, the sacrificial layer 212 in the first dummy gate structure 30 and the fin structure 36 is removed.

[0138] It can be understood that removing the first dummy gate structure 30 can expose the multiple fin structures 36 in the gate region. Subsequently, the sacrificial layer 212 in the multiple fin structures 36 can be removed to complete the channel release.

[0139] Step 15: Fig.17 As shown, a gate dielectric material and a gate metal material are deposited to form a first gate structure 114 .

[0140] Step 16: Fig.18 As shown, a gate cutting process is performed to separate adjacent first gate structures 114 .

[0141] It can be understood that the gate cut process can form the gate gap 34 .

[0142] Step 17: Fig.19 As shown, a gate direct connection structure 115 is formed.

[0143] It can be understood that the gate direct connection structure 115 can be connected to the upper metal interconnection layer.

[0144] Step 18: Fig. 20 As shown, after flipping over and removing the semiconductor substrate 20 , a source-drain direct connection structure 116 is formed.

[0145] It can be understood that the source-drain direct connection structure 116 can be connected to the underlying metal interconnection layer.

[0146] Step 19: Fig.21 As shown, flip the film again and the preparation is completed.

[0147] In an embodiment of the present application, a first sidewall can be formed by first depositing a first oxide layer and performing isotropic etching, and then a substrate trench structure is formed, and a dielectric material is deposited in the trench, and isotropic etching is performed to form an isolation structure between every two transistors. In this process, the isolation structure can also serve as a shallow trench isolation structure and a gate isolation structure. Since an isolation structure is formed between every two transistors, the spacing between transistors can be effectively reduced, thereby further compressing the transistor distribution and improving space utilization. At the same time, the manufacturing process is optimized, that is, the isolation structure can also serve as a shallow trench isolation structure and a gate isolation structure, thereby eliminating the steps of shallow trench isolation material filling and gate isolation structure formation. Furthermore, the isolation structure can also reduce the possibility of device leakage and short circuit.

[0148] In a second aspect, an embodiment of the present application provides a transistor.

[0149] In the embodiments of the present application, the transistor can be applied to semiconductor devices such as memory and processor. Fig.21 As shown, the transistor includes a plurality of first transistors 11, for example, a first sub-transistor 11a, a second sub-transistor 11b, a third sub-transistor 11c and a fourth sub-transistor 11d. The first sub-transistor 11a, the second sub-transistor 11b, the third sub-transistor 11c and the fourth sub-transistor 11d are arranged in sequence along a first direction. The active structures in the first sub-transistor 11a, the second sub-transistor 11b, the third sub-transistor 11c and the fourth sub-transistor 11d are formed by the same process.

[0150] In some embodiments, the active structure in the first transistor 11 includes a first gate structure 114 and a first source-drain structure 112. Here, the preparation process of the first gate structure 114 and the first source-drain structure 112 can refer to the description in any embodiment of the first aspect, and for the sake of brevity of the specification, it will not be repeated here.

[0151] In some embodiments, an isolation structure 29 is disposed between active structures of any two adjacent first transistors 11 among the plurality of first transistors 11. The isolation structure 29 is used to electrically isolate any two adjacent transistors among the plurality of first transistors 11. The polarities of any two adjacent first transistors 11 are the same or different.

[0152] Understandably, Fig.21 Taking the structure shown as an example, the first sub-transistor 11a and the second sub-transistor 11b have the same polarity, both of which are N-type field effect transistors. The second sub-transistor 11b and the third sub-transistor 11c have different polarities, the second sub-transistor 11b is an N-type field effect transistor, and the third sub-transistor 11c is a P-type field effect transistor. The third sub-transistor 11c and the fourth sub-transistor 11d have the same polarity, both of which are P-type field effect transistors. An isolation structure 29 is provided between every two transistors in the first sub-transistor 11a, the second sub-transistor 11b, the third sub-transistor 11c and the fourth sub-transistor 11d, so that an isolation structure 29 exists between every two N-type field effect transistors or every two P-type field effect transistors, and an isolation structure 29 exists between the N-type field effect transistor and the P-type field effect transistor.

[0153] Fig. 22 This is a schematic diagram of the structure of the first transistor provided in the embodiment of the present application. Here, Fig. 22 (a) is along Figure 2 Schematic diagram of the structure of the AA' section; Fig. 22 (b) is along Figure 2 The structural diagram of the BB' section in FIG. Fig. 22 (c) is along Figure 2 Schematic diagram of the structure of the CC' section.

[0154] See also Fig. 22 As shown, the first sub-transistor 11a and the second sub-transistor 11b have the same polarity, both of which are N-type field effect transistors. The second sub-transistor 11b and the third sub-transistor 11c have different polarities, the second sub-transistor 11b is an N-type field effect transistor, and the third sub-transistor 11c is a P-type field effect transistor. The third sub-transistor 11c and the fourth sub-transistor 11d have the same polarity, both of which are P-type field effect transistors. There is a transistor structure in which an isolation structure 29 exists only between every two N-type field effect transistors or every two P-type field effect transistors. Then, there is no isolation structure 29 between the N-type field effect transistor and the P-type field effect transistor, so that a larger spacing has to be left between the N-type field effect transistor and the P-type field effect transistor to avoid short circuit.

[0155] For example, Fig.23 A schematic diagram of the structure of a second transistor provided in an embodiment of the present application. Fig.23 For along Figure 2 Schematic diagram of the structure of the AA' section in Fig.23 As shown, there is a large gap between the N-type field effect transistor and the P-type field effect transistor. Usually, an insulating gap structure 35 can be filled in the gap, and the gap structure 35 reduces the space utilization rate inside the unit.

[0156] Fig.24 This is a schematic diagram of the structure of the third transistor provided in the embodiment of the present application. Here, Fig.24 (a) is along Figure 2 Schematic diagram of the structure of the AA' section; Fig.24 (b) is along Figure 2 The structural diagram of the BB' section in FIG. Fig.24 (c) is along Figure 2 Schematic diagram of the structure of the CC' section.

[0157] See also Fig.24 As shown, the first sub-transistor 11a and the second sub-transistor 11b have the same polarity, both of which are N-type field effect transistors. The second sub-transistor 11b and the third sub-transistor 11c have different polarities, the second sub-transistor 11b is an N-type field effect transistor, and the third sub-transistor 11c is a P-type field effect transistor. The third sub-transistor 11c and the fourth sub-transistor 11d have the same polarity, both of which are P-type field effect transistors. There is a transistor structure in which an isolation structure 29 exists only between the N-type field effect transistor and the P-type field effect transistor.

[0158] Will Fig. 22 and Fig.24 and Fig.21 By comparison, Fig.21 In the transistor structure shown, there is an isolation structure 29 between every two transistors. Since the isolation structure 29 is formed between every two transistors, the spacing between the transistors can be effectively reduced, thereby further compressing the transistor distribution and improving space utilization.

[0159] In a third aspect, an embodiment of the present application provides a semiconductor device, including: a semiconductor structure as described in the above embodiment.

[0160] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0161] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0162] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a transistor, characterized in that: The method comprises: forming a stacked structure on a semiconductor substrate; Etching the stacked structure to form a plurality of fin-shaped structures, wherein the plurality of fin-shaped structures are arranged in sequence along a first direction, a first trench is formed between any two adjacent fin-shaped structures among the plurality of fin-shaped structures, and the first direction is perpendicular to a direction perpendicular to the semiconductor substrate; forming a first spacer in the first trench covering the sidewalls of the plurality of fin-shaped structures; Etching the semiconductor substrate below the first trench to obtain a second trench; depositing a dielectric material in the second trench to form an isolation structure; Removing the first spacer to separate the isolation structure and the plurality of fin structures to obtain a first semiconductor structure; Based on the multiple fin structures in the first semiconductor structure, multiple first transistors are formed, wherein one fin structure corresponds to one first transistor, and the isolation structure is used to electrically isolate any two adjacent first transistors among the multiple first transistors, and the polarities of the any two adjacent first transistors are the same or different.

2. The method according to claim 1, characterized in that: The forming of a plurality of first transistors based on the plurality of fin structures in the first semiconductor structure comprises: In the gate region, forming a first dummy gate structure covering the plurality of fin structures and the isolation structure; In the source and drain region, etching the fin structure not covered by the first dummy gate structure to retain the isolation structure; Based on the multiple fin structures in the gate region, multiple first source-drain structures are epitaxially formed in the source-drain region, wherein in a first direction, two adjacent first source-drain structures are isolated by the isolation structure; The first dummy gate structure is removed to expose the multiple fin structures and the isolation structure, and multiple first gate structures are formed on the exposed multiple fin structures, wherein one first source-drain structure and one first gate structure constitute a first transistor, and in a first direction, two adjacent first gate structures are isolated by the isolation structure.

3. The method according to claim 2, characterized in that The fin structure comprises: sacrificial layers and active layers stacked alternately; The step of forming a plurality of first gate structures on the exposed plurality of fin structures comprises: removing the sacrificial layer in the exposed plurality of fin-shaped structures to retain the active layer in the plurality of fin-shaped structures; For each of the plurality of fin structures, a first gate structure surrounding the active layer is formed.

4. The method according to claim 2, characterized in that: The plurality of fin structures include a first fin structure, a second fin structure, a third fin structure and a fourth fin structure arranged sequentially in a first direction; The step of epitaxially forming a plurality of first source-drain structures in the source-drain region based on the plurality of fin-shaped structures in the gate region comprises: Based on the first fin structure, the second fin structure, the third fin structure and the fourth fin structure in the gate region, epitaxially forming a first sub-source-drain structure, a second sub-source-drain structure, a third sub-source-drain structure and a fourth sub-source-drain structure in the source-drain region respectively; Among them, the first sub-source-drain structure, the second sub-source-drain structure, the third sub-source-drain structure and the fourth sub-source-drain structure are all the first source-drain structure; the material forming the first sub-source-drain structure is the same as the material forming the second sub-source-drain structure, the material forming the second sub-source-drain structure is different from the material forming the third sub-source-drain structure, and the material forming the third sub-source-drain structure is the same as the material forming the fourth sub-source-drain structure.

5. The method according to claim 2, characterized in that: After forming a plurality of first transistors based on the plurality of fin structures in the first semiconductor structure, the method further includes: After forming a gate direct connection structure connected to the first gate structure, flipping and removing the semiconductor substrate and forming a source-drain direct connection structure connected to the first source-drain structure; or, After forming a source-drain direct connection structure connected to the first source-drain structure, flipping the wafer and removing the semiconductor substrate and forming a gate direct connection structure connected to the first gate structure.

6. The method according to claim 1, characterized in that The step of forming a first spacer in the first trench and covering the sidewalls of the plurality of fin-shaped structures comprises: Depositing an oxide material over the first trench and the plurality of fin-shaped structures to form a first oxide layer, wherein the first oxide layer covers the upper surface of the semiconductor substrate and the sidewalls and upper surfaces of the plurality of fin-shaped structures; The first oxide layer is etched by an isotropic etching process until the semiconductor substrate and the plurality of fin structures are exposed to form the first sidewall spacer.

7. The method according to claim 1, characterized in that The step of depositing a dielectric material in the second trench to form an isolation structure comprises: Depositing a dielectric material until the second trench is filled to form an initial isolation structure; The initial isolation structure is etched by an isotropic etching process until the plurality of fin structures are exposed to form the isolation structure.

8. The preparation method according to claim 1, characterized in that: The first transistor is any one of the following: FinFETs, gate-all-around FETs, and planar FETs.

9. A transistor, prepared by the preparation method according to any one of claims 1 to 8, characterized in that: include: a plurality of first transistors; An isolation structure is arranged between the active structures of any two adjacent first transistors among the multiple first transistors, wherein the active structure includes a first gate structure and a first source-drain structure in the first transistor; the isolation structure is used to electrically isolate any two adjacent first transistors among the multiple first transistors, and the polarities of the any two adjacent first transistors are the same or different.

10. A semiconductor device, characterized in that: include: A transistor as claimed in claim 9.

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