Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductor manufacturing. The manufacturing method of the semiconductor structure comprises the steps of providing a substrate; wherein the base comprises a substrate and at least two gate structures arranged on the substrate at intervals; the gate structure protrudes out of the surface of the substrate; the spacing distance between the projections of two adjacent gate structures on the substrate is a first distance; forming a polymerization layer on the gate structure to obtain a transition gate structure; wherein the spacing distance between the projections of two adjacent transition gate structures on the substrate is a second distance; the second distance is smaller than the first distance; sigma trenches are formed within the substrate based on the second distance. According to the embodiment of the invention, the method achieves the adjustment of the size of the top of the sigma groove through the control of the thickness of the polymerization layer, reduces the adjustment difficulty of the critical size of the sigma groove, and improves the adjustment capability of the critical size of the sigma groove.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the semiconductor device manufacturing process, especially for the 28nm and below technology nodes, the preparation of sigma trenches is a key step in building high-performance devices. Specifically, since the special geometry of sigma trenches helps to optimize the movement of carriers, in the process of manufacturing complementary metal oxide semiconductor (CMOS) devices, sigma trenches are often used to introduce stress engineering to increase the driving current of P-type metal oxide semiconductor field effect transistors (MOSFETs), thereby improving the overall electrical performance of CMOS devices.

[0003] Sigma trenches are usually formed between N-type MOSFETs and P-type MOSFETs. Due to the special cross-sectional shape of sigma trenches, the process for preparing sigma trenches is relatively complex, and the dimensional accuracy requirements for trench dimensions are also high. Among the multiple dimensions of sigma trenches, the top dimension of the sigma trench has an important influence on the isolation effect between different components and the overall electrical performance, manufacturing yield, stability and reliability of the device, and is the key dimension for sigma trench preparation.

[0004] However, the existing sigma groove preparation method has a weak ability to adjust the top size of the sigma groove, and it is difficult to meet the preparation requirements of the sigma groove. Summary of the invention

[0005] In view of this, multiple embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure to enhance the ability to adjust the top size of a sigma trench.

[0006] In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; wherein the substrate comprises a substrate and at least two gate structures spaced apart on the substrate; the gate structure protrudes from the surface of the substrate; the spacing distance between projections of two adjacent gate structures on the substrate is a first distance; forming a polymer layer on the gate structure to obtain a transition gate structure; wherein the spacing distance between projections of two adjacent transition gate structures on the substrate is a second distance; the second distance is smaller than the first distance; and based on the second distance, forming a sigma groove in the substrate.

[0007] Optionally, the step of forming a polymer layer on the gate structure to obtain a transition gate structure includes: depositing a polymer film on the surface of the substrate and the surface of the gate structure; etching the polymer film to form the polymer layer to obtain the transition gate structure.

[0008] Optionally, the step of depositing a polymer film on the gate structure includes: depositing the polymer film on the surface of the substrate and the surface of the gate structure using chemical vapor deposition according to specified deposition parameters; wherein the thickness of the polymer film falls within the range of 1nm to 5nm.

[0009] Optionally, the specified deposition parameters include specified deposition bias power, specified deposition time and specified main reaction gas; wherein, the specified deposition bias power is not greater than 50W; the specified main reaction gas includes monofluoromethane and oxygen; and the polymer film formed based on the specified main reaction gas includes carbon, fluorine, hydrogen and silicon elements.

[0010] Optionally, the step of etching the polymer film to form the polymer layer to obtain the transition gate structure includes: performing physical dry etching on the polymer film according to specified etching parameters to form the polymer layer to obtain the transition gate structure.

[0011] Optionally, the specified etching parameters include specified etching bias power and specified etching gas; wherein the specified etching bias power falls within the range of 50W to 250W; and the specified etching gas includes oxygen and argon.

[0012] Optionally, the gate structure includes a gate portion and a sidewall portion; the polymer layer includes a sidewall protection layer formed on a surface of the sidewall portion and a gate protection layer formed on an exposed surface of the gate portion.

[0013] Optionally, along the normal direction of the substrate, the side wall protection layer has an upper edge away from the substrate and a lower edge close to the substrate; the distance between the projection of the lower edge on the substrate and the projection center of the gate structure on the substrate is a third distance; the distance between the projection of the upper edge on the substrate and the projection center of the gate structure on the substrate is a fourth distance; the fourth distance is smaller than the third distance; as the specified etching bias power increases, the difference between the third distance and the fourth distance decreases.

[0014] Optionally, the step of forming a sigma groove in the substrate based on the second distance includes: based on the second distance, dry etching the substrate to obtain a preliminary groove; wherein the width of the preliminary groove is equal to the second distance; and wet etching the preliminary groove to obtain the sigma groove.

[0015] In another aspect, an embodiment of the present application provides a semiconductor structure, wherein the semiconductor structure is manufactured according to the method for manufacturing a semiconductor structure as described in the above embodiment.

[0016] In multiple embodiments provided in the present application, at least two transition gate structures are obtained by forming a polymer layer on at least two gate structures spaced apart on a substrate, wherein the spacing distance between the projections of two adjacent gate structures on the substrate is a first distance; the spacing distance between the projections of two adjacent transition gate structures on the substrate is a second distance; the second distance is smaller than the first distance, and then a sigma groove is formed in the substrate based on the second distance; achieving unexpected effects includes: changing the spacing distance between the transition gate structures by changing the thickness of the polymer layer, thereby achieving the adjustment of the top size of the sigma groove by controlling the thickness of the polymer layer, reducing the difficulty of adjusting the critical size of the sigma groove, and improving the adjustment capability of the critical size of the sigma groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of forming a preliminary groove in a substrate is provided for related art.

[0019] Figure 2 A schematic diagram of obtaining a sigma groove based on a prepared groove is provided for related technology.

[0020] Figure 3 A schematic flow chart of a method for manufacturing a semiconductor structure provided for one embodiment of the present application.

[0021] Figure 4 A schematic structural diagram of a substrate provided for one embodiment of the present application.

[0022] Figure 5 A schematic flow chart of steps of forming a polymer layer on a gate structure to obtain a transition gate structure is provided for one embodiment of the present application.

[0023] Figure 6 A schematic diagram of depositing a polymer film on a surface of a substrate and a surface of a gate structure is provided for one embodiment of the present application.

[0024] Figure 7A schematic diagram of etching a polymer film to form a polymer layer to obtain a transition gate structure provided in one embodiment of the present application.

[0025] Figure 8 A schematic flow chart of steps for forming a sigma trench in a substrate based on a second distance is provided for one embodiment of the present application.

[0026] Fig. 9 A schematic diagram of dry etching a substrate to obtain a prepared groove based on a second distance is provided for one embodiment of the present application.

[0027] Fig.10 A schematic diagram of a sigma trench obtained by wet etching to prepare a trench provided in one embodiment of the present application.

[0028] Structure number description 100, base; 110, substrate; 111, substrate; 112, isolation layer; 120, gate structure; 121, gate portion; 122, sidewall portion; 130, transition gate structure; 131, polymer film; 132, polymer layer; 140, preliminary groove; 150, sigma groove. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0030] The drawings provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complicated.

[0031] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0032] Silicon germanium (SiGe) epitaxial technology is a semiconductor material preparation process mainly used in the manufacture of high-performance integrated circuit devices. Through chemical vapor deposition or molecular beam epitaxy, one or more layers of silicon germanium alloy material are epitaxially grown on a silicon substrate to utilize the physical properties of silicon germanium alloy to improve the electron mobility of PMOS components in CMOS devices, thereby improving the overall speed and performance of CMOS devices.

[0033] As the technology nodes of integrated circuits continue to shrink, in order to achieve performance improvements for small-size devices, researchers have further optimized silicon germanium epitaxial technology. For example, for technology nodes of 28nm and below, a technology for etching sigma trenches in silicon germanium epitaxial layers or silicon substrates has been developed to improve chip integration while maintaining good electrical performance of the device, thereby integrating more devices on a smaller chip area.

[0034] See also Figure 1 and Figure 2 Taking the preparation of sigma trenches in silicon substrates as an example, the preparation process of sigma trenches and the control of trench dimensions in related technologies are briefly introduced.

[0035] Since the cross-sectional shape of the sigma groove is rather special and difficult to prepare by one etching, in the related art, two etchings are usually used to prepare the sigma groove in the substrate. Specifically, a preliminary groove 140 can be formed between the gate structures 120 spaced apart on the substrate 110 by plasma dry etching. The cross-sectional shape of the preliminary groove 140 can be U-shaped or bowl-shaped. Subsequently, tetramethylammonium hydroxide can be used as a wet etching solution to perform crystal surface selective wet etching on the preliminary groove 140 to obtain a large bottom cut sigma groove 150 whose bottom width is significantly greater than the top opening width of the groove.

[0036] In order to control the cross-sectional shape of the sigma trench, it is necessary to precisely control the top dimension, bottom dimension, depth dimension and other dimensions of the sigma trench. Among them, the top dimension, i.e., the width CD2 of the top opening of the trench has a greater impact on device performance and is a key dimension for the preparation of the sigma trench. CD2 is determined based on the spacing distance CD1 between the projections of adjacent gate structures on the substrate, i.e., CD2 is equal to CD1. Figure 1 In the embodiment, the gate structure 120 includes a gate portion 121 and a sidewall portion 122. Figure 1 It can be seen that CD1 is determined based on the distance Pitch between the projections of the gate portion 121 on the substrate 110 , the width CD3 of the gate portion 121 and the thickness CD4 of the sidewall portion 122 , that is, CD1 is the difference between Pitch and twice CD3 and CD4.

[0037] Since Pitch and CD3 are key dimensions in the design process of CMOS devices, they are often determined before the preparation of the sigma groove and are difficult to change. Therefore, in the related art, the top size of the sigma groove is usually controlled by CD4, that is, the top size of the sigma groove can be adjusted by changing the thickness of the sidewall portion. However, the CD4 value has an important influence on the leakage performance of the CMOS device. Adjusting the top size of the sigma groove by changing the CD4 value may cause the leakage performance of the device to decrease. In addition, the sidewall portion is mainly formed by lateral etching of the nitride layer deposited on the surface of the gate portion using a dry etching process, and the nitride layer is deposited by a high-temperature furnace tube process, has a high density, and has a weaker ability to be etched laterally. Therefore, due to the difficulty in changing the CD4 value and the difficulty in controlling the lateral etching of the nitride layer, the sigma groove preparation method used in the related art has a weak ability to adjust the top size of the sigma groove, and it is difficult to meet the preparation requirements of sigma grooves with different top sizes.

[0038] Therefore, it is necessary to provide a method for manufacturing a semiconductor structure, by forming a polymer layer on at least two gate structures spaced apart on a substrate to obtain at least two transition gate structures, so that the spacing distance between the projections of two adjacent transition gate structures on the substrate is smaller than the spacing distance between the projections of two adjacent gate structures on the substrate, and changing the thickness of the polymer layer can change the spacing distance between the transition gate structures, so that the top size of the sigma trench can be adjusted by controlling the thickness of the polymer layer, so as to reduce the difficulty of adjusting the critical size of the sigma trench and improve the adjustment capability of the critical size of the sigma trench.

[0039] See also Figures 3 to 10 An embodiment of the present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure may include the following steps.

[0040] S110: providing a substrate.

[0041] See also Figure 4 The base 100 may include a substrate 110 and at least two gate structures 120 spaced apart from each other on the substrate 110 .

[0042] In this embodiment, the substrate 110 can be used as a support for transistors and other semiconductor elements. Specifically, the substrate 110 may include a base 111 and an isolation layer 112. The substrate 111 may be made of semiconductor materials, insulating materials, conductor materials, or any combination thereof. For example, the substrate 111 may be made of materials such as silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), and silicon carbide (SiC). The substrate 111 may be a single-layer structure or a multi-layer structure. In this embodiment, a silicon wafer is used as the substrate 111, taking into account factors such as dielectric loss requirements, manufacturing processes, and manufacturing costs. The isolation layer 112 can be used to isolate the electric field between the gate structure 120 in the MOSFET and the substrate 110 to reduce interference and leakage of carriers. Specifically, the material of the isolation layer 112 may be selected from insulating materials such as silicon nitride or silicon oxide, and the embodiments of this specification do not specifically limit the material of the isolation layer 112.

[0043] In this embodiment, the gate structure 120 may protrude from the surface of the substrate 110. Specifically, the gate structure 120 may include a gate portion 121 and a sidewall portion 122. The gate portion 121 may include a gate dielectric layer for reducing gate leakage current, a gate electrode for conducting electricity and adjusting the threshold voltage of the transistor, a contact layer for achieving electrical contact between the gate and an external circuit, and a gate cap for protecting the gate electrode. The top surface of the gate portion 121 may be an arc surface of the gate cap. The sidewall portion 122 may be used to define the position of a lightly doped (Lightly Doped Drain, LDD) region, control the short channel effect, and form isolation between multiple gate electrodes. The material of the sidewall portion 122 may be silicon nitride (SiN) or silicon oxide (SiO2).

[0044] Taking the side wall portion 122 as an example, the side wall portion 122 can be manufactured by the following process: after at least two gate portions 121 spaced apart are formed on the surface of the isolation layer 112 in the substrate 110, a SiN layer is deposited on the surface of the isolation layer 112 and the surface of the gate portion 121, and then the SiN layer is dry-etched in the etching main chamber to remove the SiN layer covering the surface of the isolation layer 112, thereby forming a side wall portion 122 covering part of the top surface and side surfaces of the gate portion 121.

[0045] In this embodiment, the spacing distance between the projections of two adjacent gate structures 120 on the substrate 110 is a first distance D1. Specifically, the sidewalls 122 of the two adjacent gate structures 120 have opposite surfaces, and accordingly, the spacing distance between the projections of the two adjacent gate structures 120 on the substrate 110 may be the distance between the projections of the opposite surfaces of the sidewalls 122 of the two adjacent gate structures 120 on the substrate 110.

[0046] S120: forming a polymer layer on the gate structure to obtain a transition gate structure.

[0047] Since the top dimension of the sigma trench 150 is equal to the spacing distance between the projections of two adjacent gate structures 120 on the substrate 110, in order to improve the ability to adjust the top dimension of the sigma trench 150, a polymer layer 132 with a variable thickness can be formed on the gate structure 120 to obtain a transition gate structure 130 including the polymer layer 132, so that the spacing distance between the projections of two adjacent transition gate structures 130 on the substrate 110 can be changed by changing the thickness of the polymer layer 132, thereby changing the top dimension of the sigma trench 150.

[0048] See also Figures 5 to 7 The step of forming the polymer layer 132 on the gate structure 120 to obtain the transition gate structure 130 may include the following steps.

[0049] S121: depositing a polymer film on the surface of the substrate and the surface of the gate structure.

[0050] See also Figure 6 To improve the ability to control the thickness of the polymer layer 132 and to provide protection to the gate portion 121 and the sidewall portion 122 during subsequent manufacturing processes, a polymer film 131 that wraps the entire gate structure 120 can be deposited on the surface of the substrate 110 and the surface of the gate structure 120 .

[0051] In this embodiment, the step of depositing the polymer film 131 on the surface of the substrate 110 and the surface of the gate structure 120 may include: depositing the polymer film 131 on the surface of the substrate 110 and the surface of the gate structure 120 by chemical vapor deposition according to specified deposition parameters. The surface of the gate structure 120 may include an exposed surface of the gate portion 121 and a surface of the sidewall portion 122. The exposed surface of the gate portion 121 may be a portion of the top surface of the gate portion 121 that is not covered by the sidewall portion 122.

[0052] To reduce the damage to the gate structure 120 during the subsequent etching of the polymer film 131 to form the polymer layer 132, in this embodiment, the thickness of the polymer film 131 may fall within the range of 1 nm to 5 nm. For example, the thickness of the polymer film 131 may be 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm.

[0053] To improve the control accuracy of polymer particle deposition, in this embodiment, the specified deposition parameters may include a specified deposition bias power, a specified deposition time, and a specified main reaction gas. Specifically, the specified deposition bias power can be used to control the deposition direction and deposition speed of the polymer particles, the specified deposition time can be used to control the thickness of the polymer film 131, and the specified main reaction gas can be used to control the composition of the polymer film 131.

[0054] In this embodiment, the specified deposition bias power may be no greater than 50W. Specifically, when the deposition bias power is large, the polymer particles may collide with the surface of the gate structure 120 and the surface of the substrate 110 at a high speed, bombarding the gate structure 120 and the substrate 110, and the polymer deposition may be directional, that is, the polymer particles may be concentrated and deposited at a specific position, which may cause damage to the gate structure 120 and the substrate 110 at the specific position. Therefore, in order to reduce the damage to the gate structure 120 and the substrate 110 during the deposition process of the polymer film 131, the specified deposition bias power can be set to a lower value. For example, the specified deposition bias power can be 40W, 42W, 45W, 47W, 50W.

[0055] In this embodiment, the specified deposition time can be determined according to the thickness of the polymer film 131. Specifically, in the process of depositing polymer particles to form the polymer film 131, the deposition bias power can be kept at the specified deposition bias power, and the thickness of the formed polymer film 131 can be controlled by controlling the deposition time, that is, the longer the deposition time, the thicker the formed polymer film 131.

[0056] In this embodiment, the designated main reaction gas may include fluoromethane (CH3F) and oxygen (O2). The main reaction gas reacts with the silicon element in the substrate 100, so that the polymer film 131 formed based on the designated main reaction gas may include carbon (C), fluorine (F), hydrogen (H), and silicon (Si) elements.

[0057] S122: Etching the polymer film to form a polymer layer to obtain a transition gate structure.

[0058] See also Figure 7 Since the top size of the sigma trench 150 is determined by the spacing distance between the projections of adjacent gate structures 120 on the substrate 110, in order to improve the ability to adjust the top size of the sigma trench 150, the polymer film 131 can be etched after the polymer film 131 is formed to form a polymer layer 132 to obtain a transition gate structure 130, so that the spacing distance between the projections of two adjacent transition gate structures 130 on the substrate 110 can be adjusted by using the polymer layer 132.

[0059] In this embodiment, the step of etching the polymer film 131 to form the polymer layer 132 to obtain the transition gate structure 130 may include: performing physical dry etching on the polymer film 131 according to specified etching parameters to form the polymer layer 132 to obtain the transition gate structure 130.

[0060] Since the polymer contains strong covalent bonds and has high bond energy, in order to improve the control accuracy of the etching of the polymer film 131 and enhance the etching effect of the polymer film 131 so that the shape of the polymer layer 132 formed by etching the polymer film 131 meets the process requirements, in this embodiment, the polymer film 131 can be etched by physical dry etching.

[0061] In this embodiment, the spacing distance between the projections of two adjacent transition gate structures 130 on the substrate 110 is a second distance D2. Specifically, the polymer layers 132 of the two adjacent transition gate structures 130 have opposite surfaces, and accordingly, the spacing distance between the projections of the two adjacent transition gate structures 130 on the substrate 110 may be the distance between the projections of the opposite surfaces of the polymer layers 132 of the two adjacent transition gate structures 130 on the substrate 110. The second distance D2 is smaller than the first distance D1.

[0062] To improve the control accuracy of etching the polymer film 131, in this embodiment, the specified etching parameters may include a specified etching bias power and a specified etching gas. Specifically, the specified etching bias power may be used to control the etching direction and etching speed of the polymer film 131, and the specified etching gas may be used to remove the polymer film 131 and improve the etching effect on the polymer film 131.

[0063] In this embodiment, the specified etching bias power may fall within the range of 50W to 250W. Specifically, the greater the etching bias power, the easier it is to control the direction of the etching plasma to be vertical, thereby improving the lateral etching capability of the polymer film 131. In order to improve the uniformity of the lateral etching of the polymer film 131, the specified etching bias power may be set to a higher value. For example, the specified deposition bias power may be 50W, 100W, 150W, 200W, or 250W.

[0064] To further improve the uniformity of the lateral etching of the polymer film 131, the designated etching gas may include oxygen (O2) and argon (Ar). Specifically, since the atomic mass of Ar is relatively large, during the physical dry etching process using argon, Ar atoms will bombard the polymer film 131, making the shape of the polymer layer 132 formed by etching the polymer film 131 more controllable.

[0065] In order to provide a certain degree of protection for the mask and the sidewall portion in the subsequent process steps of forming the sigma trench, in this embodiment, the polymer layer 132 may include a sidewall protection layer formed on the surface of the sidewall portion 122 and a gate protection layer formed on the exposed surface of the gate portion 121.

[0066] In an ideal state, the polymer film 131 can be etched uniformly in the side direction, that is, the angle between the surface of the sidewall protection layer and the surface of the substrate 110 is 90°. However, it is difficult to achieve the ideal state in the actual etching process. Therefore, in this embodiment, along the normal direction of the substrate 110, the sidewall protection layer has an upper edge away from the substrate 110 and a lower edge close to the substrate 110, wherein the distance between the projection of the lower edge on the substrate 110 and the projection center of the gate structure 120 on the substrate 110 is a third distance D3, and the distance between the projection of the upper edge on the substrate 110 and the projection center of the gate structure 120 on the substrate 110 is a fourth distance D4. Specifically, D4 is smaller than D3, that is, the angle between the surface of the sidewall protection layer and the surface of the substrate 110 is an acute angle. As the specified etching bias power increases, the surface of the sidewall protection layer gradually tends to be perpendicular to the surface of the substrate 110, that is, the angle between the surface of the sidewall protection layer and the surface of the substrate 110 gradually increases in the range of 0° to 90°, and the difference between D3 and D4 decreases. Therefore, the angle between the surface of the sidewall protection layer and the surface of the substrate 110 can be controlled by controlling the specified etching bias power to control the spacing distance between the projections of the transition gate structure 130 on the substrate 110, thereby controlling the top size of the sigma trench 150.

[0067] S130: Based on the second distance, forming a sigma trench in the substrate.

[0068] After the transition gate structure 130 is formed, a sigma trench 150 may be prepared based on the spacing distance between projections of two adjacent transition gate structures 130 on the substrate 110 .

[0069] See also Figures 8 to 10 Based on the second distance, forming the sigma trench 150 in the substrate 110 may include the following steps.

[0070] S131: Based on the second distance, dry-etching the substrate to obtain a preliminary groove.

[0071] See also Fig. 9. In this embodiment, a plasma dry etching method can be used to remove the isolation layer 112 located between adjacent transition gate structures 130, and the substrate 111 can be etched to obtain a preliminary groove 140. Specifically, perpendicular to the direction in which the preliminary groove 140 extends toward the substrate 111, the preliminary groove 140 has a width direction, and along the direction in which the preliminary groove 140 extends toward the substrate 111, the widths of the preliminary groove 140 in the width direction are equal, and the width can be equal to the second distance D2. The cross-sectional shape of the preliminary groove 140 can be U-shaped. The etching process parameters for obtaining the preliminary groove 140 are the same as the conventional etching process parameters used in the related art, and will not be repeated here.

[0072] S132: removing the polymerized layer.

[0073] In this embodiment, after the preliminary groove 140 is obtained, the transition semiconductor structure with the transition gate structure 130 formed on the surface of the substrate 110 can be cleaned to remove the polymer layer 132 and impurities. Specifically, the cleaning liquid used can be hydrofluoric acid or concentrated sulfuric acid.

[0074] S133: wet etching a preparatory groove to obtain a sigma groove.

[0075] See also Fig.10 In this embodiment, after removing the polymer layer 132, the preliminary groove 140 can be selectively wet-etched with tetramethylammonium hydroxide to obtain a sigma groove 150 with a top size of D2. Specifically, the etching process parameters for obtaining the sigma groove 150 are the same as the conventional etching process parameters used in the related art, and will not be repeated here.

[0076] In this embodiment, the process steps of depositing a polymer film, etching a polymer film to form a polymer layer, and dry etching a substrate to obtain a preparatory groove and the process step of etching a silicon nitride layer to form a side wall portion can be completed in the etching main chamber. Specifically, a chamber environment stabilization device, such as a dry pump, is provided in the etching main chamber. During the execution of the above process steps, the chamber environment stabilization device is always in operation to keep the environment in the etching main chamber clean and the pressure stable. At the same time, the temperature in the etching main chamber can fall within the range of 48°C to 52°C. For example, the temperature in the etching main chamber can be 48°C, 49°C, 50°C, 51°C, and 52°C. Compared with the process temperature of thousands of degrees Celsius in the process of preparing the side wall portion in the high-temperature furnace tube process, the process temperature for executing the above process steps is relatively low. Since multiple process steps are concentrated in the main etching chamber, impurity contamination that may be caused by executing different process steps in different environments is reduced, the process difficulty of adjusting the key dimensions of the sigma trench is reduced, and the preparation requirements of sigma trenches with different top dimensions can be met without adding additional machine configurations or changing the front-end process.

[0077] An embodiment of the present application provides a semiconductor structure, which can be manufactured by the semiconductor structure manufacturing method described in the above embodiment.

[0078] In an embodiment of the present application, at least two transition gate structures are obtained by forming a polymer layer on at least two gate structures spaced apart on a substrate, so that the spacing distance between the projections of two adjacent transition gate structures on the substrate is smaller than the spacing distance between the projections of two adjacent gate structures on the substrate. The unexpected effects achieved include: the spacing distance between the transition gate structures can be changed by changing the thickness of the polymer layer, so that the top size of the sigma trench can be adjusted by controlling the thickness of the polymer layer, thereby reducing the difficulty of adjusting the critical size of the sigma trench and improving the adjustment capability of the critical size of the sigma trench.

[0079] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of this application.

[0080] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0081] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0082] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are identical with the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments, and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above-mentioned" and "the" used in the embodiments of the present application are also intended to include majority forms, unless the context clearly indicates other meanings.

[0083] In the several embodiments provided in this application, it should be understood that the disclosed semiconductor structure can be implemented in other ways. For example, the embodiments of the semiconductor structure described above are merely illustrative.

[0084] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: A substrate is provided; wherein the substrate comprises a substrate and at least two gate structures spaced apart and arranged on the substrate; the gate structure protrudes from the surface of the substrate; and the spacing distance between projections of two adjacent gate structures on the substrate is a first distance; forming a polymer layer on the gate structure to obtain a transition gate structure; wherein the spacing distance between projections of two adjacent transition gate structures on the substrate is a second distance; and the second distance is smaller than the first distance; Based on the second distance, a sigma trench is formed in the substrate.

2. The method according to claim 1, characterized in that The step of forming a polymer layer on the gate structure to obtain a transition gate structure comprises: Depositing a polymer film on the surface of the substrate and the surface of the gate structure; The polymer film is etched to form the polymer layer to obtain the transition gate structure.

3. The method according to claim 2, characterized in that The step of depositing a polymer film on the surface of the substrate and the surface of the gate structure comprises: The polymer film is deposited on the surface of the substrate and the surface of the gate structure by chemical vapor deposition according to specified deposition parameters; wherein the thickness of the polymer film falls within the range of 1 nm to 5 nm.

4. The method according to claim 3, characterized in that: The specified deposition parameters include specified deposition bias power, specified deposition time and specified main reaction gas; wherein, the specified deposition bias power is not greater than 50W; the specified main reaction gas includes monofluoromethane and oxygen; the polymer film formed based on the specified main reaction gas includes carbon, fluorine, hydrogen and silicon elements.

5. The method according to claim 2, characterized in that: The step of etching the polymer film to form the polymer layer to obtain the transition gate structure comprises: According to the specified etching parameters, the polymer film is physically dry-etched to form the polymer layer, thereby obtaining the transition gate structure.

6. The method according to claim 5, characterized in that The specified etching parameters include specified etching bias power and specified etching gas; wherein the specified etching bias power falls within the range of 50W to 250W; and the specified etching gas includes oxygen and argon.

7. The method according to claim 6, characterized in that The gate structure includes a gate portion and a sidewall portion; the polymer layer includes a sidewall protection layer formed on a surface of the sidewall portion and a gate protection layer formed on an exposed surface of the gate portion.

8. The method according to claim 7, characterized in that Along the normal direction of the substrate, the sidewall protection layer has an upper edge away from the substrate and a lower edge close to the substrate; the distance between the projection of the lower edge on the substrate and the projection center of the gate structure on the substrate is a third distance; the distance between the projection of the upper edge on the substrate and the projection center of the gate structure on the substrate is a fourth distance; the fourth distance is smaller than the third distance; as the specified etching bias power increases, the difference between the third distance and the fourth distance decreases.

9. The method according to claim 1, characterized in that: Based on the second distance, the step of forming a sigma trench in the substrate comprises: Based on the second distance, dry-etching the substrate to obtain a preliminary groove; wherein the width of the preliminary groove is equal to the second distance; removing the polymeric layer; The preliminary groove is wet-etched to obtain the sigma groove.

10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured according to the method for manufacturing a semiconductor structure according to any one of claims 1 to 9.

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