Array substrate and display panel

Abstract

The embodiment of the invention provides an array substrate and a display panel. According to the array substrate, the first insulating layer is arranged, the first insulating layer comprises the first insulating part, the light transmittance of the first insulating layer is smaller than that of the buffer layer, the first insulating part and the channel part are correspondingly arranged, the projection of the first insulating layer on the substrate is located outside the light-transmitting area, and the part, located in the light-transmitting area, of the first insulating layer can be removed; therefore, the light transmittance of the light-transmitting area is improved, and the light transmittance of the array substrate is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] TFT-LCD (thin film transistor-liquid crystal display) is widely used due to its advantages such as long life, mature technology and low price. However, in actual use, it is found that the buffer layer in the liquid crystal display device generally adopts a stack of silicon nitride and silicon oxide. Since the transmittance of silicon nitride is low and the interface between silicon nitride and silicon oxide causes light to refract, the transmittance of the liquid crystal display device is low. Therefore, the existing liquid crystal display device has the technical problem of low transmittance. Summary of the invention

[0003] The embodiments of the present application provide an array substrate and a display panel to solve the technical problem of low light transmittance in existing liquid crystal display devices.

[0004] In order to achieve the above object, according to a first aspect of the present application, an array substrate is provided, the array substrate comprising a pixel area, the pixel area comprising a light-transmitting area and a non-light-transmitting area, the array substrate comprising:

[0005] substrate;

[0006] A first insulating layer, disposed on one side of the substrate, the first insulating layer comprising a first insulating portion;

[0007] A buffer layer, disposed on a side of the first insulating layer away from the substrate;

[0008] An active layer, disposed on a side of the buffer layer away from the first insulating layer, the active layer comprising an active portion, and the active portion comprising a channel portion;

[0009] The transmittance of the first insulating layer is lower than that of the buffer layer, the first insulating portion is arranged corresponding to the channel portion, and a projection of the first insulating layer on the substrate is located outside the light-transmitting area.

[0010] Optionally, the array substrate also includes a light-shielding layer, which is arranged between the first insulating layer and the buffer layer. The light-shielding layer includes a light-shielding portion, which is arranged corresponding to the channel portion, and a projection of the light-shielding portion on the substrate is located within a projection of the first insulating portion on the substrate.

[0011] Optionally, the array substrate also includes a light-shielding layer, which is arranged between the substrate and the first insulating layer. The light-shielding layer includes a light-shielding portion, which is arranged corresponding to the channel portion, and the projection of the first insulating portion on the substrate is located within the projection of the light-shielding portion on the substrate.

[0012] Optionally, the buffer layer is provided with a first step in a region corresponding to the first insulating portion, and the active portion is provided with a second step in a region corresponding to the first step.

[0013] Optionally, an angle between a side wall of the active portion and a plane where a top surface of the active portion is located is less than or equal to an angle between a side wall of the buffer layer and a plane where a top surface of the buffer layer is located.

[0014] Optionally, an angle between a side wall of the active portion and a plane where a top surface of the active portion is located ranges from 10 degrees to 55 degrees.

[0015] Optionally, a content of hydrogen per unit volume of a portion of the buffer layer close to the first insulating portion is greater than a content of hydrogen per unit volume of a portion of the buffer layer close to the active layer.

[0016] Optionally, the array substrate further includes a gate insulating layer, a gate layer and an interlayer insulating layer, the gate insulating layer is arranged on a side of the active layer away from the buffer layer, the gate layer is arranged on a side of the gate insulating layer away from the active layer, the interlayer insulating layer is arranged on a side of the gate layer away from the gate insulating layer, and the material of the interlayer insulating layer is silicon oxide.

[0017] Optionally, the array substrate also includes a second insulating layer, which is arranged between the gate layer and the gate insulating layer, the gate layer includes a gate, the second insulating layer includes a second insulating portion, the transmittance of the second insulating layer is less than the transmittance of the interlayer insulating layer, the gate and the second insulating portion are arranged correspondingly, and the projection of the second insulating layer on the substrate is located outside the light-transmitting area.

[0018] Optionally, the material of the second insulating layer is silicon nitride.

[0019] Optionally, a content of hydrogen per unit volume of a portion of the gate insulating layer close to the gate layer is greater than a content of hydrogen per unit volume of a portion of the gate insulating layer close to the active layer.

[0020] Optionally, the content of silicon-hydrogen bonds in the first insulating layer is in a range of 4% to 10%.

[0021] Optionally, the material of the first insulating layer is silicon nitride, and the material of the buffer layer is silicon oxide.

[0022] Optionally, the array substrate further includes a gate layer, the gate layer includes a gate, the active layer includes a plurality of active portions, each of the active portions includes a channel portion, each of the channel portions includes a first channel portion and a second channel portion, and the gate is arranged corresponding to the first channel portion and the second channel portion.

[0023] Optionally, each of the light shielding portions includes a first light shielding portion and a second light shielding portion, the first light shielding portion is arranged corresponding to the first channel portion, and the second light shielding portion is arranged corresponding to the second channel portion.

[0024] Optionally, each of the light shielding portions is arranged corresponding to the first channel portion, and the light shielding portions are arranged corresponding to the second channel portion.

[0025] Optionally, a projection of the active portion on the substrate is located within a projection of the first insulating portion on the substrate.

[0026] Optionally, the active portion further includes a doped portion, a projection of the channel portion on the substrate is located within a projection of the first insulating portion on the substrate, and a projection of at least part of the doped portion on the substrate is located outside a projection of the first insulating portion on the substrate.

[0027] Optionally, each of the first insulating parts is arranged corresponding to one of the active parts; or each of the first insulating parts is arranged corresponding to a plurality of the active parts.

[0028] According to a second aspect of the present application, a display panel is provided. The display panel includes an array substrate as described in any one of the above embodiments.

[0029] An embodiment of the present application provides an array substrate and a display panel; the array substrate is provided with a first insulating layer, the first insulating layer includes a first insulating portion, the transmittance of the first insulating layer is less than the transmittance of the buffer layer, the first insulating portion is provided corresponding to the channel portion, the projection of the first insulating layer on the substrate is located outside the light-transmitting area, the portion of the first insulating layer located in the light-transmitting area can be removed, thereby improving the transmittance of the light-transmitting area and improving the transmittance of the array substrate.

[0030] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0032] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0033] Figure 1 Schematic diagram of a comparative display device provided in an embodiment of the present application.

[0034] Figure 2 A plan view of an array substrate provided in an embodiment of the present application.

[0035] Figure 3 A first cross-sectional schematic diagram of an array substrate provided in an embodiment of the present application.

[0036] Figure 4 A second cross-sectional schematic diagram of an array substrate provided in an embodiment of the present application.

[0037] Figure 5 This is a third cross-sectional schematic diagram of the array substrate provided in an embodiment of the present application.

[0038] Figure 6 This is a fourth cross-sectional schematic diagram of the array substrate provided in an embodiment of the present application.

[0039] Figure 7 A first perspective schematic diagram and an exploded diagram of an array substrate provided in an embodiment of the present application.

[0040] Figure 8 A second perspective schematic diagram and an exploded diagram of the array substrate provided in an embodiment of the present application.

[0041] Fig. 9 A third perspective schematic diagram and an exploded diagram of the array substrate provided in an embodiment of the present application.

[0042] Fig.10 A fourth perspective schematic diagram and an exploded diagram of the array substrate provided in an embodiment of the present application.

[0043] Fig.11 A fifth perspective schematic diagram and an exploded diagram of the array substrate provided in an embodiment of the present application.

[0044] Fig.12 A comparison curve diagram of the hydrogen atom concentration in a comparative display device formed by using a rapid thermal annealing process and not using a rapid thermal annealing process provided in an embodiment of the present application.

[0045] Fig.13 This is a comparison diagram of the threshold voltage and mobility of the thin film transistor of the comparative display device provided in the embodiment of the present application and the threshold voltage and mobility of the array substrate in the embodiment of the present application.

[0046] Fig.14A schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0048] In view of the above technical problems, the embodiments of the present application provide an array substrate and a display panel to solve the above problems.

[0049] like Figures 2 to 11 As shown, an embodiment of the present application provides an array substrate, the array substrate 2 includes a pixel area 201, the pixel area 201 includes a light-transmitting area 201a and a non-light-transmitting area 201b, the array substrate 2 includes a substrate 211, a first insulating layer 212, a buffer layer 214 and an active layer 215, the first insulating layer 212 is arranged on one side of the substrate 211, the first insulating layer 212 includes a first insulating portion 212a, the buffer layer 214 is arranged on a side of the first insulating layer 212 away from the substrate 211, the active layer 215 is arranged on a side of the buffer layer 214 away from the first insulating layer 212, the active layer 215 includes an active portion 215a, the active portion 215a includes a channel portion 32, wherein the first insulating portion 212a is arranged corresponding to the channel portion 32, and the projection of the first insulating layer 212 on the substrate 211 is located outside the light-transmitting area 201a.

[0050] The embodiment of the present application provides an array substrate, which is provided with a first insulating layer, the first insulating layer includes a first insulating portion, the light transmittance of the first insulating layer is less than the light transmittance of the buffer layer, the first insulating portion is provided corresponding to the channel portion, the projection of the first insulating layer on the substrate is located outside the light transmission area, and the portion of the first insulating layer located in the light transmission area can be removed, thereby improving the light transmittance of the light transmission area and improving the light transmittance of the array substrate. Specifically, it can be understood that the pixel area corresponds to the display area in the display panel, and the non-pixel area corresponds to the non-display area in the display panel.

[0051] Specifically, Figure 2 As shown, the non-pixel area 202 is disposed around the pixel area 201 , but the embodiment of the present application is not limited thereto. The non-pixel area 202 can be disposed on one side, two sides, or three sides of the pixel area 201 .

[0052] Specifically, Figure 3 As shown, Figure 3As shown in the figure, the light-transmitting area 201a is located on both sides of the non-light-transmitting area 201b. In actual design, the non-light-transmitting area 201b may be arranged around the light-transmitting area 201a.

[0053] Specifically, the array substrate includes a thin film transistor.

[0054] In order to illustrate the principle of further technical problems in the embodiments of the present application, a comparative display device is provided. It is to be understood that the comparative display device cannot be used as the prior art of the present application. Figure 1 As shown, the comparative display device includes a substrate 111, a shading metal 112, a silicon nitride buffer film 113a, a silicon oxide buffer film 113b, a semiconductor film 114, a gate insulating film 115, a gate film 116, a silicon nitride interlayer insulating film 117, a silicon oxide interlayer insulating film 118, a source and drain film 119, a planarizing film 121, a first electrode film 122, a passivation film 123 and a second electrode film 124. The material of the silicon nitride buffer film 113a is silicon nitride, the material of the silicon oxide buffer film 113b is silicon oxide, the material of the silicon nitride interlayer insulating film 117 is silicon nitride, and the material of the silicon oxide interlayer insulating film 118 is silicon oxide. The comparative display device can be driven by a driving circuit using LTPS (Low Temperature Poly-silicon) technology. In order to prevent the ions in the substrate 111 from diffusing into the semiconductor film 114 and causing the performance of the thin film transistor to change, the comparative display device uses a stacked structure of a silicon nitride buffer film and a silicon oxide buffer film as the buffer film, and blocks the ions in the substrate 111 by silicon nitride, and in order to increase the hydrogen content in the semiconductor film 114, the interlayer insulating film uses a stacked structure of a silicon nitride interlayer insulating film 117 and a silicon oxide interlayer insulating film 118. However, since the light transmittance of silicon nitride is lower than that of silicon oxide, and the interface between silicon nitride and silicon oxide causes the light to refract, further reducing the refractive index of the light, resulting in a lower light transmittance of the comparative display device.

[0055] In order to solve the above problems, in some comparative display devices, the buffer film is changed from a stack of silicon nitride buffer film and silicon oxide buffer film to silicon oxide, thereby improving the transmittance of the comparative display device, but this will cause ions to enter the semiconductor film, resulting in poor device performance of the thin film transistor. Therefore, the existing liquid crystal display device has a technical problem that it cannot take into account both transmittance and performance stability. In some embodiments, the material of the first insulating layer 212 is silicon nitride, and the material of the buffer layer 214 is silicon oxide. By making the material of the buffer layer silicon oxide, the material of the first insulating layer is silicon nitride, the first insulating layer includes a first insulating portion, the first insulating portion is arranged corresponding to the channel portion, and the projection of the first insulating layer on the substrate is located outside the light-transmitting area, then the silicon nitride layer in the buffer layer and the portion of the first insulating layer located in the light-transmitting area can be removed, the silicon nitride in the light-transmitting area can be reduced, and the transmittance of the light-transmitting area can be improved. The first insulating portion is arranged corresponding to the channel portion, the first insulating portion can block the diffusion of metal ions into the channel, and the first insulating portion can replenish hydrogen to the channel portion, thereby improving the electrical stability of the thin film transistor, thereby taking into account both the transmittance and performance stability of the array substrate.

[0056] Specifically, compared with the comparative display device in which the buffer film is composed of a stack of silicon nitride and silicon oxide, the buffer layer in the embodiment of the present application has only silicon oxide, which can improve the transmittance of the array substrate, and the embodiment of the present application is provided with a first insulating layer, the material of the first insulating layer can be silicon nitride, so that the first insulating part and the channel part are arranged correspondingly, then the first insulating part can block the sodium ions, potassium ions and other ions in the substrate from diffusing into the channel, thereby improving the electrical stability of the thin film transistor.

[0057] In some embodiments, Figure 3 , Figure 4 As shown, the array substrate 2 further includes a light shielding layer 213, which is disposed between the first insulating layer 212 and the buffer layer 214. The light shielding layer 213 includes a light shielding portion 213a, which is disposed correspondingly to the channel portion 32, and the projection of the light shielding portion 213a on the substrate 211 is located within the projection of the first insulating portion 212a on the substrate 211. By disposing the light shielding layer, the light shielding portion is disposed correspondingly to the channel portion, so that the channel portion can be shielded from light, thereby preventing the performance of the active portion from changing due to light irradiating the channel portion, and improving the stability of the thin film transistor. Moreover, the projection of the light shielding portion on the substrate is located within the projection of the first insulating portion on the substrate, so that the edges of the first insulating portion and the light shielding portion form a step, reducing the risk of disconnection when the active portion climbs, and preventing the sodium ions and potassium ions in the substrate from diffusing to the channel portion along the edge of the light shielding portion, thereby improving the performance stability of the array substrate.

[0058] In some embodiments, Figure 5As shown, the array substrate 2 further includes a light shielding layer 213, the light shielding layer 213 is arranged between the substrate 211 and the first insulating layer 212, the light shielding layer 213 includes a light shielding portion 213a, the light shielding portion 213a is arranged corresponding to the channel portion 32, and the projection of the first insulating portion 212a on the substrate 211 is located within the projection of the light shielding portion 213a on the substrate 211. By arranging the light shielding layer, the light shielding portion is arranged corresponding to the channel portion, so that the channel portion can be shielded to prevent light from irradiating the channel portion and causing the performance of the active portion to change, thereby improving the stability of the thin film transistor, and the projection of the first insulating portion on the substrate is located within the projection of the light shielding portion on the substrate, so that the area of ​​the first insulating portion is smaller, further improving the light transmittance of the array substrate, and the first insulating portion is closer to the light shielding layer, and when hydrogen is contained in the first insulating layer, the hydrogen replenishment effect on the active layer can be further improved.

[0059] Specifically, the above-mentioned embodiment is described by taking the example that the light-shielding layer is arranged between the first insulating layer and the buffer layer, and the projection of the light-shielding portion on the substrate is located within the projection of the first insulating portion on the substrate; the light-shielding layer is arranged between the substrate and the first insulating layer, and the projection of the first insulating portion on the substrate is located within the projection of the light-shielding portion on the substrate, but the embodiments of the present application are not limited to this, and the light-shielding layer may be arranged between the first insulating layer and the buffer layer, and the projection of the first insulating portion on the substrate is located within the projection of the light-shielding portion on the substrate; or the light-shielding layer is arranged between the substrate and the first insulating layer, and the projection of the light-shielding portion on the substrate is located within the projection of the first insulating portion on the substrate.

[0060] In some embodiments, Figure 6 As shown, the buffer layer 214 is provided with a first step 214a in a region corresponding to the first insulating portion 212a, and the active portion 215a is provided with a second step 215b in a region corresponding to the first step 214a. When the first insulating portion is provided on the substrate, the first insulating layer is patterned so that some regions are provided with the first insulating layer and some regions are not provided with the first insulating layer. When the buffer layer is formed, the first step is formed in the region corresponding to the first insulating layer, and the film thickness of the buffer layer is relatively uniform. When the active layer is formed, the active layer can be provided with a second step in a region corresponding to the first step, so that the film thickness of the active layer is relatively uniform.

[0061] Specifically, Figure 6 As shown, it can be seen that the buffer layer forms a plurality of parts of different heights in the area corresponding to the first insulating part, so that a first step is formed between the parts, that is, a plurality of parts in the upper surface of the buffer layer are located at different horizontal planes, each part has a height difference and each part is interconnected to form the first step. At the same time, it can be seen that a plurality of parts in the upper surface of the active layer are located at different horizontal planes, so that the active layer forms a second step.

[0062] Specifically, Figure 6 As shown, since the light shielding layer 213 is disposed corresponding to the first insulating portion, the number of the first step of the buffer layer and the second step of the active layer will be increased accordingly.

[0063] Specifically, it can be understood that Figure 6 The step structures of the buffer layer and the active layer in the region corresponding to the first insulating portion are shown as an example for explanation, and other film layers may form step structures accordingly, such as the gate insulating layer, the interlayer insulating layer and other film layers. Figure 4 , Figure 5 In the array substrate shown and the array substrates in other embodiments, each film layer may also form a step structure accordingly, which will not be described in detail here.

[0064] Specifically, the active portion exceeding the first insulating portion is used as an example for explanation. Figures 7 to 9 It can be seen that in some array substrates, since the projection of the active portion completely falls within the projection of the first insulating layer, the number of steps of the active portion may be less than the number of steps of the buffer layer.

[0065] In some embodiments, Figure 6 As shown, the angle a1 between the side wall of the active portion 215a and the plane where the top surface of the active portion 215a is located is less than or equal to the angle a2 between the side wall of the buffer layer 214 and the plane where the top surface of the buffer layer 214 is located. When the buffer layer and the active layer are provided, since the active layer is formed after the buffer layer, due to the accumulation of the film layers, the angle between the side wall of the active layer and the plane where the top surface of the active layer is located will be relatively small, so that the slope of each film layer is relatively slow.

[0066] Specifically, it can be understood that the angle described in the above embodiment is described by taking an acute angle as an example.

[0067] Specifically, the above-mentioned embodiment is described by taking the angle between the side wall of the active part and the plane where the top surface of the active part is located, which is less than or equal to the angle between the side wall of the buffer layer and the plane where the top surface of the buffer layer is located, but the embodiments of the present application are not limited to this, and the angle between the side wall of the active part and the plane where the top surface of the active part is located can be greater than the angle between the side wall of the buffer layer and the plane where the top surface of the buffer layer is located.

[0068] Specifically, it can be understood that when the substrate to the second electrode layer are formed in sequence, due to the accumulation of film layers, when the film layers are patterned, due to the accumulation of each film layer, the climbing angle of each film layer can be gradually slowed down.

[0069] In some embodiments, the angle a1 between the sidewall of the active portion 215a and the plane where the top surface of the active portion 215a is located is in a range of 10 to 55 degrees. By making the angle a1 between the sidewall of the active portion 215a and the plane where the top surface of the active portion 215a is located in a range of 10 to 55 degrees, the slope of the active portion is relatively gentle, and the active portion is prevented from occupying too much space due to the slope angle being too small.

[0070] Specifically, it can be understood that the climbing angle of the active part ranges from 10 degrees to 55 degrees, and correspondingly, the climbing angles of the buffer layer, the first insulating part, and the light shielding part can range from 10 degrees to 55 degrees.

[0071] In some embodiments, Figure 5 As shown, the content of hydrogen per unit volume of the portion of the buffer layer 214 close to the first insulating portion 212a is greater than the content of hydrogen per unit volume of the portion of the buffer layer 214 close to the active layer 215. When forming the array substrate, hydrogen in the first insulating layer will diffuse to the active layer. Therefore, the content of hydrogen per unit volume of the portion of the buffer layer close to the first insulating portion is greater than the content of hydrogen per unit volume of the portion of the buffer layer close to the active layer, so that the first insulating layer can replenish hydrogen to the channel portion, thereby improving the electrical stability of the thin film transistor, thereby taking into account both the transmittance and performance stability of the array substrate.

[0072] In some embodiments, Figures 3 to 11 As shown, the array substrate 2 further includes a gate layer 217, the gate layer 217 includes a gate 217a, the active layer 215 includes a plurality of active portions 215a, each of the active portions 215a includes a channel portion 32, each of the channel portions 32 includes a first channel portion 321 and a second channel portion 322, and the gate 217a is disposed corresponding to the first channel portion 321 and the second channel portion 322. By making the channel portion include the first channel portion and the second channel portion, and the gate is disposed corresponding to the first channel portion and the second channel portion, the gate control capability of the thin film transistor can be improved, and the occupied space of the thin film transistor can be reduced, thereby improving the resolution.

[0073] Specifically, it can be understood that the portion of the gate layer 217 corresponding to the channel portion 32 serves as the gate 217 a , and the portion connected to the gate 217 a can serve as a scan line.

[0074] Specifically, by configuring the active portion 215 a to be U-shaped, the space occupied by the thin film transistor can be reduced and the gate control capability of the thin film transistor can be improved.

[0075] Specifically, the first channel portion and the second channel portion are two channel parts, and parameters of various aspects such as ion doping concentration, shape, length, width, etc. therein may be the same.

[0076] In some embodiments, Figure 7 , Fig.10 As shown, each of the light shielding portions 213a includes a first light shielding portion 311 and a second light shielding portion 312, the first light shielding portion 311 is arranged corresponding to the first channel portion 321, and the second light shielding portion 312 is arranged corresponding to the second channel portion 322. By making the first light shielding portion include the first light shielding portion and the second light shielding portion, the first light shielding portion is arranged corresponding to the first channel portion, so that the first channel portion can be shielded from light, and the second light shielding portion is arranged corresponding to the second channel portion, so that the second channel portion can be shielded from light, thereby preventing light from affecting the performance of the thin film transistor and improving the device stability of the array substrate.

[0077] In some embodiments, Figure 8 , Fig. 9 , Fig.11 As shown, each of the light-shielding portions 213a is arranged corresponding to the first channel portion 321, and the light-shielding portion 213a is arranged corresponding to the second channel portion 322. By arranging a light-shielding portion corresponding to the first channel portion, and the light-shielding portion corresponding to the second channel portion, the first channel portion and the second channel portion can be shielded by one light-shielding portion, thereby preventing light from affecting the performance of the thin film transistor and improving the device stability of the array substrate.

[0078] In some embodiments, Figures 7 to 9 As shown, the projection of the active portion 215a on the substrate 211 is located within the projection of the first insulating portion 212a on the substrate 211. By making the projection of the active portion on the substrate located within the projection of the first insulating portion on the substrate, the area of ​​the first insulating portion can be increased, so that when the first insulating layer contains hydrogen, the hydrogen replenishing effect of the first insulating portion on the active layer is improved, thereby improving the performance of the thin film transistor.

[0079] In some embodiments, Fig.10 , Fig.11 As shown, the active portion 215a further includes a doping portion 33, the projection of the channel portion 32 on the substrate 211 is located within the projection of the first insulating portion 212a on the substrate 211, and the projection of at least part of the doping portion 33 on the substrate 211 is located outside the projection of the first insulating portion 212a on the substrate 211. By making the projection of the channel portion on the substrate located within the projection of the first insulating portion on the substrate, and the projection of at least part of the doping portion on the substrate is located outside the projection of the first insulating portion on the substrate, the channel portion can be protected by the first insulating portion to prevent ions in the substrate from diffusing to the channel portion, which causes the performance of the thin film transistor to deteriorate. In addition, the area of ​​the first insulating portion is small, which further improves the light transmittance of the array substrate, thereby taking into account both the light transmittance and performance stability of the array substrate.

[0080] In some embodiments, Figure 7 , Figures 9 to 11 As shown, each of the first insulating portions 212a is disposed correspondingly to one of the active portions 215a; or as shown Figure 8 As shown, each of the first insulating parts 212a is arranged correspondingly to the plurality of active parts 215a. By arranging each first insulating part correspondingly to an active part, the region between the active parts can be free of the first insulating part, thereby further improving the light transmittance of the array substrate; by arranging a first insulating part correspondingly to the plurality of active parts, each active part can be protected by a first insulating part, and each active part can be supplemented with hydrogen by a first insulating part, thereby improving the performance stability of the array substrate.

[0081] In some embodiments, Figures 3 to 5 As shown, the array substrate 2 further includes a gate insulating layer 216, a gate layer 217 and an interlayer insulating layer 218, wherein the gate insulating layer 216 is disposed on a side of the active layer 215 away from the buffer layer 214, the gate layer 217 is disposed on a side of the gate insulating layer 216 away from the active layer 215, and the interlayer insulating layer 218 is disposed on a side of the gate layer 217 away from the gate insulating layer 216, and the material of the interlayer insulating layer 218 is silicon oxide. By making the material of the interlayer insulating layer silicon oxide, the light transmittance of the display panel can be further improved.

[0082] In some embodiments, Figure 4 , Figure 5 As shown, the array substrate 2 further includes a second insulating layer 225, the second insulating layer 225 is disposed between the gate layer 217 and the gate insulating layer 216, the gate layer 217 includes a gate 217a, the second insulating layer 225 includes a second insulating portion 225a, the light transmittance of the second insulating layer 225 is less than the light transmittance of the interlayer insulating layer 218, the gate 217a and the second insulating portion 225a are disposed correspondingly, and the projection of the second insulating layer 225 on the substrate 211 is located outside the light-transmitting area 201a. By disposing the second insulating layer, the second insulating portion is disposed correspondingly to the gate, and when hydrogen is contained in the second insulating layer, the hydrogen replenishing capacity can be increased through the second insulating layer, thereby improving the performance stability of the thin film transistor. When preparing the array substrate, the process error can be relatively large, thereby reducing the process difficulty and improving the yield.

[0083] Specifically, the gate layer and the second insulating layer may be formed by using the same mask.

[0084] In some embodiments, the material of the second insulating layer is silicon nitride. By making the material of the second insulating layer silicon nitride, the hydrogen replenishing capacity can be increased through the second insulating layer, the performance stability of the thin film transistor can be improved, and when preparing the array substrate, the process error can be relatively large, reducing the process difficulty and improving the yield.

[0085] In some embodiments, the content of hydrogen per unit volume of the portion of the gate insulating layer 216 close to the gate layer 217 is greater than the content of hydrogen per unit volume of the portion of the gate insulating layer 216 close to the active layer 215. When forming the array substrate, hydrogen in the second insulating layer will diffuse to the active layer, so that the content of hydrogen per unit volume of the portion of the gate insulating layer close to the gate layer is greater than the content of hydrogen per unit volume of the portion of the gate insulating layer close to the active layer, so that the hydrogen replenishing capacity can be increased through the second insulating layer, and the performance stability of the thin film transistor can be improved.

[0086] In some embodiments, the content of silicon-hydrogen bonds in the first insulating layer 212 is in the range of 4% to 10%. By making the content of silicon-hydrogen bonds in the first insulating layer in the range of 4% to 10%, the content of hydrogen elements diffused from the first insulating layer to the active layer can be sufficient, so that the electrical properties of the active layer are better, and the performance stability of the array substrate is improved.

[0087] Specifically, the non-display area includes a gate drive circuit setting area, and the first insulating layer includes a portion arranged in the gate drive circuit setting area. By arranging the first insulating layer in the gate drive circuit setting area, the ions in the substrate can be blocked by the first insulating layer to improve the stability of the active layer, and since the gate drive circuit setting area does not display, the first insulating layer will not affect the light transmittance.

[0088] Specifically, the material of the substrate includes a glass substrate.

[0089] Specifically, the material of the first insulating layer includes silicon nitride.

[0090] Specifically, the material of the buffer layer includes silicon oxide.

[0091] Specifically, the material of the gate insulating layer may be silicon oxide.

[0092] Specifically, the material of the active layer includes low temperature polysilicon.

[0093] Specifically, Figures 3 to 5 As shown, the array substrate 2 also includes a source and drain layer 219, a planarization layer 221, a first electrode layer 222, a passivation layer 223 and a second electrode layer 224. It can be understood that the embodiments of the present application are not limited to this, and the array substrate may have only the first electrode layer or the second electrode layer.

[0094] Specifically, the materials of the light shielding layer, the gate layer and the source and drain electrode layer may be metal, such as a stack of titanium, aluminum and titanium, or a titanium layer and an aluminum layer.

[0095] Specifically, the material of the first electrode layer and the second electrode layer may be indium tin oxide.

[0096] Specifically, the material of the passivation layer may be silicon nitride.

[0097] Specifically, it can be understood that the above-mentioned embodiments have described the array substrate in detail from the perspective of different film layers and the relative positions and connection relationships of each film layer. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the array substrate also includes a light-shielding layer, and the light-shielding layer is arranged between the first insulating layer and the buffer layer. The light-shielding layer includes a light-shielding portion, and the light-shielding portion is arranged corresponding to the channel portion, and the projection of the light-shielding portion on the substrate is located within the projection of the first insulating portion on the substrate; and the array substrate also includes a gate insulating layer, a gate layer and an interlayer insulating layer, the gate insulating layer is arranged on a side of the active layer away from the buffer layer, the gate layer is arranged on a side of the gate insulating layer away from the active layer, and the interlayer insulating layer is arranged on a side of the gate layer away from the gate insulating layer, and the material of the interlayer insulating layer is silicon oxide.

[0098] Specifically, Figure 3 As shown, the array substrate 2 includes a substrate 211, a first insulating layer 212, a shading layer 213, a buffer layer 214, an active layer 215, a gate insulating layer 216, a gate layer 217, an interlayer insulating layer 218, a source-drain layer 219, a planarizing layer 221, a first electrode layer 222, a passivation layer 223 and a second electrode layer 224, which are arranged in sequence. The material of the first insulating layer 212 is silicon nitride, the material of the buffer layer 214 is silicon oxide, and the material of the interlayer insulating layer is silicon oxide. The first insulating portion 212a, the shading portion 213a, the active portion 215a, and the gate 217 are arranged in the non-light-transmitting area 201b; by making the materials of the buffer layer and the interlayer insulating layer both silicon oxide, the transmittance of the array substrate can be improved, and the first insulating layer is arranged, and the first insulating portion is arranged corresponding to the channel portion, which can protect the channel portion, and the hydrogen in the first insulating portion can diffuse to the active layer to replenish the active layer with hydrogen.

[0099] Specifically, Figure 3 As shown, the content of silicon-hydrogen bonds in the first insulating layer 212 is in a range of 4% to 10%, so that the electrical properties of the array substrate meet the requirements.

[0100] Specifically, Figure 4 As shown, Figure 4 and Figure 3The difference between the array substrate shown in the figure is that the array substrate 2 further includes a second insulating layer 225, the second insulating layer 225 is arranged between the gate layer 217 and the gate insulating layer 216, and the second insulating layer 225 includes a second insulating portion 225a, and the second insulating portion 225a is arranged corresponding to the gate 217a, so that the active layer can be hydrogenated through the first insulating layer and the second insulating layer, further improving the hydrogenation capacity of the array substrate, improving the performance stability of the array substrate, and the transmittance can be comparable to Figure 3 The array substrates shown have the same light transmittance.

[0101] Specifically, Figure 5 As shown, Figure 5 and Figure 4 The difference between the array substrate shown is that Figure 4 In the array substrate shown, the first insulating layer is arranged between the light shielding layer and the substrate, and the projection of the light shielding portion on the substrate is located within the projection of the first insulating portion on the substrate; Figure 5 In the array substrate shown, the first insulating layer is arranged between the light-shielding layer and the buffer layer, and the projection of the first insulating part on the substrate is located within the projection of the light-shielding part on the substrate, so that the first insulating part is closer to the active part, thereby improving the hydrogen replenishment effect, and the area of ​​the first insulating replenishment is reduced, thereby further improving the transmittance of the array substrate.

[0102] Specifically, Figure 7 As shown, Figure 7 (a) is a first perspective schematic diagram of an array substrate; Figure 7 (b) in Figure 7 An exploded view of the first insulating layer of the array substrate in (a); Figure 7 (c) in Figure 7 An exploded view of the light shielding layer of the array substrate in (a); Figure 7 (d) in Figure 7 An exploded view of the active layer of the array substrate in (a); Figure 7 (e) in Figure 7 (a) is an exploded view of the gate layer of the array substrate. Figure 7 It can be seen that each of the shading portions 213a includes a first shading portion 311 and a second shading portion 312, the first shading portion 311 is arranged corresponding to the first channel portion 321, the second shading portion 312 is arranged corresponding to the second channel portion 322, the projection of the shading portion 213a on the substrate and the projection of the active portion 215a on the substrate are both located within the projection of the first insulating portion on the substrate, and each first insulating portion 212a is arranged corresponding to each active portion 215a.

[0103] Specifically, Figure 8 As shown, Figure 8 (a) is a second perspective schematic diagram of the array substrate; Figure 8 (b) in Figure 8 An exploded view of the first insulating layer of the array substrate in (a); Figure 8 (c) in Figure 8 An exploded view of the light shielding layer of the array substrate in (a); Figure 8 (d) in Figure 8 An exploded view of the active layer of the array substrate in (a); Figure 8 (e) in Figure 8 (a) is an exploded view of the gate layer of the array substrate. Figure 8 It can be seen that each of the shading portions 213a is arranged corresponding to the first channel portion 321, and the shading portion 213a is arranged corresponding to the second channel portion 322, the projection of the shading portion 213a on the substrate and the projection of the active portion 215a on the substrate are both located within the projection of the first insulating portion on the substrate, and the first insulating portion 212a is arranged corresponding to multiple active portions 215a.

[0104] Specifically, Fig. 9 As shown, Fig. 9 (a) is a third perspective schematic diagram of the array substrate; Fig. 9 (b) in Fig. 9 An exploded view of the first insulating layer of the array substrate in (a); Fig. 9 (c) in Fig. 9 An exploded view of the light shielding layer of the array substrate in (a); Fig. 9 (d) in Fig. 9 An exploded view of the active layer of the array substrate in (a); Fig. 9 (e) in Fig. 9 (a) is an exploded view of the gate layer of the array substrate. Fig. 9 It can be seen that each of the shading portions 213a is arranged corresponding to the first channel portion 321, and the shading portion 213a is arranged corresponding to the second channel portion 322, the projection of the shading portion 213a on the substrate and the projection of the active portion 215a on the substrate are both located within the projection of the first insulating portion on the substrate, and each first insulating portion 212a is arranged corresponding to each active portion 215a.

[0105] Specifically, Fig.10 As shown, Fig.10 (a) is a fourth perspective schematic diagram of the array substrate; Fig.10 (b) in Fig.10 An exploded view of the first insulating layer of the array substrate in (a); Fig.10 (c) in Fig.10 An exploded view of the light shielding layer of the array substrate in (a); Fig.10 (d) in Fig.10An exploded view of the active layer of the array substrate in (a); Fig.10 (e) in Fig.10 (a) is an exploded view of the gate layer of the array substrate. Fig.10 It can be seen that each of the shading portions 213a includes a first shading portion 311 and a second shading portion 312, the first shading portion 311 is arranged corresponding to the first channel portion 321, the second shading portion 312 is arranged corresponding to the second channel portion 322, the projection of the shading portion 213a on the substrate is located within the projection of the first insulating portion on the substrate, the projection of the channel portion 32 on the substrate 211 is located within the projection of the first insulating portion 212a on the substrate 211, and the projection of at least part of the doping portion 33 on the substrate 211 is located outside the projection of the first insulating portion 212a on the substrate 211; each first insulating portion 212a is arranged corresponding to each active portion 215a.

[0106] Specifically, Fig.11 As shown, Fig.11 (a) is a fifth perspective schematic diagram of the array substrate; Fig.11 (b) in Fig.11 An exploded view of the first insulating layer of the array substrate in (a); Fig.11 (c) in Fig.11 An exploded view of the light shielding layer of the array substrate in (a); Fig.11 (d) in Fig.11 An exploded view of the active layer of the array substrate in (a); Fig.11 (e) in Fig.10 (a) is an exploded view of the gate layer of the array substrate. Fig.11 It can be seen that each of the shading portions 213a is arranged corresponding to the first channel portion 321, and the shading portions 213a are arranged corresponding to the second channel portion 322, the projection of the shading portion 213a on the substrate is located within the projection of the first insulating portion on the substrate, the projection of the channel portion 32 on the substrate 211 is located within the projection of the first insulating portion 212a on the substrate 211, and the projection of at least part of the doping portion 33 on the substrate 211 is located outside the projection of the first insulating portion 212a on the substrate 211; each first insulating portion 212a is arranged corresponding to each active portion 215a.

[0107] It can be understood that the above-mentioned embodiments have obtained different array substrate structures by different combinations of some film layers and their structures. The above-mentioned embodiments are not the structures of all array substrates in the embodiments of the present application. When there is no conflict between the film layers and their structures, the film layers and their structures can be combined to obtain other array substrate structures.

[0108] Specifically, when the first insulating layer is disposed between the light shielding layer and the substrate, a separate mask can be used to pattern the first insulating layer when the first insulating layer is patterned. However, the embodiment of the present application is not limited thereto, and the mask of the light shielding layer can be designed as a halftone mask, so that the degree of residual photoresist after exposure in the region where the light shielding layer and the region where the first insulating layer are disposed are different, and the light shielding layer and the first insulating layer are patterned synchronously during etching, so that the projection of the light shielding portion on the substrate is located within the projection of the first insulating portion on the substrate.

[0109] Specifically, Figure 1 Taking the structure of the comparative display device shown in FIG. 1 as an example, when forming the comparative display device, in order to replenish hydrogen in the active film, a rapid thermal annealing process is performed after forming the interlayer insulating film. By comparing the hydrogen atom concentration in the comparative display device formed by the rapid thermal annealing process and the comparative display device formed without the rapid thermal annealing process, it is obtained that Fig.12 The curve graph shown, Fig.12 The horizontal axis in is the depth downward from the upper surface of the silicon oxide interlayer insulating film 118, and the unit is nanometers. For example, the position with a depth of 100 indicates that the distance from the upper surface of the silicon oxide interlayer insulating film is 100 nanometers, and the position with a depth of 0 indicates the position where the upper surface of the silicon oxide interlayer insulating film is located; Fig.12 The vertical axis in is the concentration of hydrogen atoms, and the unit is the number of hydrogen atoms per cubic centimeter. Curve 1 is the data obtained by testing the peripheral area of ​​the motherboard corresponding to the comparative display device when the comparative display device is formed by the rapid thermal annealing process, Curve 2 is the data obtained by testing the middle area of ​​the motherboard corresponding to the comparative display device when the comparative display device is formed by the rapid thermal annealing process, Curve 3 is the data obtained by testing the peripheral area of ​​the motherboard corresponding to the comparative display device when the comparative display device is formed without the rapid thermal annealing process, Curve 4 is the data obtained by testing the middle area of ​​the motherboard corresponding to the comparative display device when the comparative display device is formed without the rapid thermal annealing process; from Fig.12 It can be seen that when the rapid thermal annealing process is used, the hydrogen atom concentration of each film layer is relatively high, and the embodiment of the present application removes the silicon nitride layer in the interlayer insulating layer and uses the first insulating layer for hydrogen replenishment, so it is necessary to increase the hydrogen content in the first insulating layer, and specifically, the content of the silicon-hydrogen bond of the first insulating layer 212 can be made in the range of 4% to 10%, so that the electrical properties of the array substrate meet the requirements. A second insulating layer can also be provided to improve the hydrogen replenishment effect.

[0110] by Figure 1 The comparison shown shows the device and Figure 3 The array substrate shown in the figure was tested under the following test conditions: the temperature was 80 degrees Celsius, the voltage difference between the gate and the source was 1.5 volts, the voltage difference between the drain and the source was 20 volts, and the width-to-length ratio of the channel was 4.5 / 4.5. Fig.13 The curve graph shown, Fig.13 (a) is a curve diagram showing the change of the threshold voltage of the thin film transistor over time. Fig.13 The horizontal axis of (a) is time in seconds. For example, t10 can represent a duration of 10 seconds. Fig.13 The ordinate of (a) is the threshold voltage, in volts; Fig.13 (b) is a graph showing the mobility of the thin film transistor changing with time. Fig.13 The horizontal axis of (b) is time in seconds. Fig.13 The vertical coordinate of (b) is the mobility, and the unit is square centimeter / (volt*second). Fig.13 Curve 1 in (a) is a curve showing the change of the threshold voltage of the thin film transistor in the comparative display device over time. Fig.13 Curve 2 in (a) is a curve showing the change of the threshold voltage of the thin film transistor in the array substrate over time in the embodiment of the present application. Fig.13 Curve 1 in (b) is a curve showing the mobility of the thin film transistor in the comparative display device changing with time. Fig.13 Curve 2 in (b) is a curve showing the change of the mobility of the thin film transistor in the array substrate over time in the embodiment of the present application. Fig.13 It can be seen that the change trends of the threshold voltage and mobility of the thin film transistor of the array substrate in the embodiment of the present application are consistent with the change trends of the threshold voltage and mobility of the thin film transistor in the comparative display device, and the electrical stability of the array substrate in the embodiment of the present application is better.

[0111] At the same time, an embodiment of the present application provides a display panel, which includes the array substrate as described in any of the above embodiments.

[0112] Specifically, Fig.14 As shown, the display panel 4 includes an array substrate 2 , a color filter substrate 41 , and a liquid crystal layer 42 disposed between the array substrate 2 and the color filter substrate 41 .

[0113] Specifically, the display panel may be a liquid crystal display panel, which includes the array substrate and the color filter substrate described in any one of the above embodiments, and a liquid crystal layer disposed between the array substrate and the color filter substrate.

[0114] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0115] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0116] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0117] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes a pixel area, wherein the pixel area includes a light-transmitting area and a non-light-transmitting area. substrate; A first insulating layer, disposed on one side of the substrate, the first insulating layer comprising a first insulating portion; A buffer layer, disposed on a side of the first insulating layer away from the substrate; An active layer, disposed on a side of the buffer layer away from the first insulating layer, the active layer comprising an active portion, and the active portion comprising a channel portion; The transmittance of the first insulating layer is lower than that of the buffer layer, the first insulating portion is arranged corresponding to the channel portion, and a projection of the first insulating layer on the substrate is located outside the light-transmitting area.

2. The array substrate according to claim 1, characterized in that: The array substrate also includes a light-shielding layer, which is arranged between the first insulating layer and the buffer layer. The light-shielding layer includes a light-shielding portion, which is arranged corresponding to the channel portion, and a projection of the light-shielding portion on the substrate is located within a projection of the first insulating portion on the substrate.

3. The array substrate according to claim 1, characterized in that: The array substrate also includes a light-shielding layer, which is arranged between the substrate and the first insulating layer. The light-shielding layer includes a light-shielding portion, which is arranged corresponding to the channel portion, and a projection of the first insulating portion on the substrate is located within a projection of the light-shielding portion on the substrate.

4. The array substrate according to any one of claims 1 to 3, characterized in that: The buffer layer has a first step in a region corresponding to the first insulating portion, and the active portion has a second step in a region corresponding to the first step.

5. The array substrate according to claim 4, characterized in that: An angle between a side wall of the active portion and a plane where a top surface of the active portion is located is less than or equal to an angle between a side wall of the buffer layer and a plane where a top surface of the buffer layer is located.

6. The array substrate according to claim 5, characterized in that: The angle between the side wall of the active portion and the plane where the top surface of the active portion is located ranges from 10 degrees to 55 degrees.

7. The array substrate according to any one of claims 1 to 3, characterized in that: A content of hydrogen per unit volume of a portion of the buffer layer close to the first insulating portion is greater than a content of hydrogen per unit volume of a portion of the buffer layer close to the active layer.

8. The array substrate according to any one of claims 1 to 3, characterized in that: The array substrate also includes a gate insulating layer, a gate layer and an interlayer insulating layer. The gate insulating layer is arranged on a side of the active layer away from the buffer layer, the gate layer is arranged on a side of the gate insulating layer away from the active layer, and the interlayer insulating layer is arranged on a side of the gate layer away from the gate insulating layer. The material of the interlayer insulating layer is silicon oxide.

9. The array substrate according to claim 8, characterized in that: The array substrate also includes a second insulating layer, which is arranged between the gate layer and the gate insulating layer, the gate layer includes a gate, the second insulating layer includes a second insulating portion, the transmittance of the second insulating layer is less than the transmittance of the interlayer insulating layer, the gate and the second insulating portion are arranged correspondingly, and the projection of the second insulating layer on the substrate is located outside the light-transmitting area.

10. The array substrate according to claim 9, characterized in that: The material of the second insulating layer is silicon nitride.

11. The array substrate according to claim 9, characterized in that: The content of hydrogen per unit volume of a portion of the gate insulating layer close to the gate layer is greater than the content of hydrogen per unit volume of a portion of the gate insulating layer close to the active layer.

12. The array substrate according to claim 8, characterized in that: The content of Si-H bonds in the first insulating layer is in a range of 4% to 10%.

13. The array substrate according to any one of claims 1 to 3, characterized in that: The material of the first insulating layer is silicon nitride, and the material of the buffer layer is silicon oxide.

14. The array substrate according to any one of claims 1 to 3, characterized in that: The array substrate further includes a gate layer, the gate layer includes a gate, the active layer includes a plurality of active portions, each of the active portions includes a channel portion, each of the channel portions includes a first channel portion and a second channel portion, and the gate is arranged corresponding to the first channel portion and the second channel portion.

15. The array substrate according to claim 14, characterized in that: Each of the light shielding portions includes a first light shielding portion and a second light shielding portion, the first light shielding portion is arranged corresponding to the first channel portion, and the second light shielding portion is arranged corresponding to the second channel portion.

16. The array substrate according to claim 14, characterized in that: Each of the light shielding portions is disposed correspondingly to the first channel portion, and each of the light shielding portions is disposed correspondingly to the second channel portion.

17. The array substrate according to claim 14, characterized in that: A projection of the active portion on the substrate is located within a projection of the first insulating portion on the substrate.

18. The array substrate according to claim 14, characterized in that: The active portion further includes a doped portion, a projection of the channel portion on the substrate is located within a projection of the first insulating portion on the substrate, and a projection of at least part of the doped portion on the substrate is located outside a projection of the first insulating portion on the substrate.

19. The array substrate according to claim 14, characterized in that: Each of the first insulating parts is disposed correspondingly to one of the active parts; or each of the first insulating parts is disposed correspondingly to a plurality of the active parts.

20. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 19.

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