Array substrate and display panel

Abstract

According to the array substrate and the display panel provided by the embodiment of the invention, an interlayer insulating layer comprises a first insulating layer, the interlayer insulating layer is located in a light-transmitting region, and the content of a nitrogen element in the first insulating layer is smaller than that of an oxygen element, so that at least a silicon nitride material in the light-transmitting region in the interlayer insulating layer can be reduced; the content of hydrogen atoms per unit volume of the part, close to the grid electrode layer, of the first insulating layer is smaller than the content of hydrogen atoms per unit volume of the part, away from the grid electrode layer, of the first insulating layer, so that hydrogen can be supplemented to the active layer through diffusion when the array substrate is formed, the electrical performance of the active layer is good, and the light transmittance of the active layer is improved. Therefore, the light transmittance and the performance stability of the array substrate are both considered.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] TFT-LCD (thin film transistor-liquid crystal display) is widely used due to its advantages such as long life, mature technology and low price. Existing liquid crystal display devices drive the display panel based on the driving circuit of LTPS (Low Temperature Poly-silicon) technology, but in actual use, it is found that the transmittance of liquid crystal display devices is low. In order to improve the transmittance of liquid crystal display devices, existing liquid crystal display devices adjust the film layer structure, but adjusting the film layer structure will cause adverse effects.

[0003] Therefore, existing liquid crystal display devices have the technical problem of being unable to balance light transmittance and performance stability. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a display panel to solve the technical problem that the existing liquid crystal display devices cannot take into account both light transmittance and performance stability.

[0005] In order to achieve the above object, according to a first aspect of the present application, an array substrate is provided, the array substrate comprising a pixel area, the pixel area comprising a light-transmitting area and a non-light-transmitting area located on at least one side of the light-transmitting area, the array substrate comprising:

[0006] substrate;

[0007] An active layer, disposed on one side of the substrate;

[0008] A gate layer, disposed on a side of the active layer away from the substrate;

[0009] an interlayer insulating layer, arranged on a side of the gate layer away from the active layer, the interlayer insulating layer comprising a first insulating layer, wherein the content of nitrogen in the interlayer insulating layer and the first insulating layer located in the light-transmitting region is less than the content of oxygen;

[0010] The content of hydrogen per unit volume of a portion of the first insulating layer close to the gate layer is smaller than the content of hydrogen per unit volume of a portion of the first insulating layer far from the gate layer.

[0011] Optionally, the array substrate further includes a source-drain layer, which is disposed on a side of the interlayer insulating layer away from the gate layer, one side of the first insulating layer is in direct contact with the source-drain layer, and the other side of the first insulating layer is in direct contact with the gate layer.

[0012] Optionally, the interlayer insulating layer further includes a second insulating layer, the material of the second insulating layer is silicon nitride, the second insulating layer is arranged on a side of the first insulating layer away from the gate layer, and the second insulating layer is arranged in the non-light-transmitting area.

[0013] Optionally, the array substrate also includes a source-drain layer, the width of a surface of the source-drain layer on a side in contact with the second insulating layer is equal to the width of a surface of the second insulating layer on a side in contact with the source-drain layer, and the side walls of the source-drain layer and the corresponding side walls of the second insulating layer are on the same plane.

[0014] Optionally, the array substrate further includes a source-drain electrode layer, and a width of a surface of the source-drain electrode layer on a side in contact with the second insulating layer is smaller than a width of a surface of the second insulating layer on a side in contact with the source-drain electrode layer.

[0015] Optionally, an angle between a side wall of the source / drain layer and a bottom surface of the source / drain layer is less than or equal to an angle between a side wall of the second insulating layer and a bottom surface of the second insulating layer.

[0016] Optionally, a material of the first insulating layer includes silicon oxide.

[0017] Optionally, the array substrate further includes a buffer layer, wherein the buffer layer is disposed between the substrate and the active layer, and a material of a portion of the buffer layer located in the light-transmitting area is silicon oxide.

[0018] Optionally, the buffer layer includes a third insulating layer and a fourth insulating layer, the third insulating layer is made of silicon oxide, the fourth insulating layer is made of silicon nitride, and the fourth insulating layer is disposed in the non-light-transmitting area.

[0019] Optionally, the array substrate further includes a light shielding layer, wherein the light shielding layer is disposed between the fourth insulating layer and the substrate, the fourth insulating layer is disposed between the light shielding layer and the third insulating layer, and the fourth insulating layer covers the light shielding layer.

[0020] Optionally, the array substrate further includes a light shielding layer, the fourth insulating layer is arranged between the light shielding layer and the substrate, and the third insulating layer is arranged on a side of the light shielding layer away from the fourth insulating layer.

[0021] Optionally, a projection of a surface of the light-shielding layer close to the fourth insulating layer on the substrate coincides with a projection of a surface of the fourth insulating layer close to the light-shielding layer on the substrate, and a side wall of the light-shielding layer and a corresponding side wall in the fourth insulating layer are on the same plane.

[0022] Optionally, the buffer layer includes a third insulating layer, and the array substrate also includes a light-shielding layer, one side of the third insulating layer is in contact with the light-shielding layer, and the other side of the third insulating layer is in contact with the active layer, and the material of the portion of the buffer layer located in the non-light-transmitting area is silicon oxide.

[0023] Optionally, the array substrate further comprises a source-drain electrode layer, a planarization layer, a first electrode layer, a passivation layer, and a second electrode layer, the source-drain electrode layer is arranged on a side of the interlayer insulating layer away from the gate layer, the planarization layer is arranged on a side of the source-drain electrode layer away from the interlayer insulating layer, the first electrode layer is arranged on a side of the planarization layer away from the source-drain electrode layer, the passivation layer is arranged on a side of the first electrode layer away from the planarization layer, and the second electrode layer is arranged on a side of the passivation layer away from the first electrode layer;

[0024] Wherein, the material of the passivation layer is silicon oxide or silicon oxynitride.

[0025] According to a second aspect of the present application, a display panel is provided. The display panel includes an array substrate as described in any one of the above embodiments.

[0026] The embodiment of the present application provides an array substrate and a display panel. The interlayer insulating layer of the array substrate includes a first insulating layer. The nitrogen content in the interlayer insulating layer and the first insulating layer located in the light-transmitting area is less than the oxygen content. At least the silicon nitride material in the interlayer insulating layer located in the light-transmitting area can be reduced, thereby improving the transmittance of the light-transmitting area. The content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer is less than the content of hydrogen atoms per unit volume of the portion of the first insulating layer far from the gate layer. When forming the array substrate, the active layer can be supplemented with hydrogen by diffusion, so that the electrical performance of the active layer is better, thereby taking into account both the transmittance and performance stability of the array substrate.

[0027] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0029] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0030] Figure 1 Schematic diagram of a comparative display device provided in an embodiment of the present application.

[0031] Figure 2 A schematic plan view of an array substrate provided in an embodiment of the present application.

[0032] Figure 3 A first cross-sectional schematic diagram of an array substrate provided in an embodiment of the present application.

[0033] Figure 4 A second cross-sectional schematic diagram of an array substrate provided in an embodiment of the present application.

[0034] Figure 5 This is a third cross-sectional schematic diagram of the array substrate provided in an embodiment of the present application.

[0035] Figure 6 This is a fourth cross-sectional schematic diagram of the array substrate provided in an embodiment of the present application.

[0036] Figure 7 A fifth cross-sectional schematic diagram of the array substrate provided in an embodiment of the present application.

[0037] Figure 8 A schematic diagram of the structure of an array substrate corresponding to each step of the method for preparing an array substrate provided in an embodiment of the present application.

[0038] Fig. 9 A comparison curve diagram of the hydrogen atom concentration in a comparative display device formed by using a rapid thermal annealing process and not using a rapid thermal annealing process provided in an embodiment of the present application.

[0039] Fig.10 A schematic diagram of the diffusion of hydrogen elements in a comparative display device and an array substrate provided in an embodiment of the present application.

[0040] Fig.11 This is a comparison chart of the threshold voltage, mobility and on-state current of the comparative display device and the array substrate provided in the embodiments of the present application.

[0041] Fig.12 This is a comparison diagram of the subthreshold swing and leakage current of the comparative display device and the array substrate provided in the embodiment of the present application.

[0042] Fig.13 A schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0044] In order to explain the principle of the technical problem in the embodiment of the present application, a comparative display device is provided. It is understandable that the comparative display device cannot be used as the prior art of the present application. Figure 1 As shown, the comparative display device includes a substrate 111, a shading metal 112, a silicon nitride buffer film 113a, a silicon oxide buffer film 113b, a semiconductor film 114, a gate insulating film 115, a gate film 116, a silicon nitride interlayer insulating film 117a, a silicon oxide interlayer insulating film 117b, a source and drain film 118, a planarizing film 119, a first electrode film 121, a passivation film 122 and a second electrode film 123. The material of the silicon nitride buffer film 113a is silicon nitride, the material of the silicon oxide buffer film 113b is silicon oxide, the material of the silicon nitride interlayer insulating film 117a is silicon nitride, and the material of the silicon oxide interlayer insulating film 117b is silicon oxide. In order to prevent the ions in the substrate 111 from diffusing into the semiconductor film 114 and causing the performance of the thin film transistor to change, the comparative display device will use a stacked structure of a silicon nitride buffer film and a silicon oxide buffer film as the buffer film, and the ions in the substrate 111 will be blocked by silicon nitride, and in order to increase the content of hydrogen elements in the semiconductor film 114, the interlayer insulating film will use a stacked structure of a silicon nitride interlayer insulating film 117a and a silicon oxide interlayer insulating film 117b. However, since the light transmittance of silicon nitride is lower than that of silicon oxide, and the interface between silicon nitride and silicon oxide causes the light to refract, further reducing the refractive index of the light, resulting in a lower light transmittance of the comparative display device.

[0045] In order to solve the above problems, some comparative display devices change the film structure to improve the light transmittance of the comparative display devices, but this will cause the device performance of the thin film transistor to deteriorate. Therefore, the existing liquid crystal display devices have the technical problem of not being able to take into account both light transmittance and performance stability.

[0046] like Figures 2 to 7As shown, an embodiment of the present application provides an array substrate, the array substrate 2 includes a pixel area 201, the pixel area 201 includes a light-transmitting area 201a and a non-light-transmitting area 201b located at least on one side of the light-transmitting area 201a, the array substrate 2 includes a substrate 211, an active layer 214, a gate layer 216 and an interlayer insulating layer 217; the active layer 214 is arranged on one side of the substrate 211; the gate layer 216 is arranged on a side of the active layer 214 away from the substrate 211; the interlayer insulating layer 217 is arranged on a side of the gate layer 216 away from the active layer 214, the interlayer insulating layer 217 includes a first insulating layer 217a, and the content of nitrogen in the interlayer insulating layer and the first insulating layer located in the light-transmitting area 201a is less than the content of oxygen;

[0047] The content of hydrogen per unit volume of a portion of the first insulating layer 217 a close to the gate layer 216 is less than the content of hydrogen per unit volume of a portion of the first insulating layer 217 a far from the gate layer 216 .

[0048] An embodiment of the present application provides an array substrate, which can at least reduce the silicon nitride material in the light-transmitting area in the interlayer insulating layer by making the interlayer insulating layer include a first insulating layer, and the nitrogen content in the interlayer insulating layer and the first insulating layer located in the light-transmitting area is less than the oxygen content, thereby improving the transmittance of the light-transmitting area, and the content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer is less than the content of hydrogen atoms per unit volume of the portion of the first insulating layer far from the gate layer. When forming the array substrate, hydrogen can be supplemented to the active layer by diffusion, so that the electrical performance of the active layer is better, thereby taking into account both the transmittance and performance stability of the array substrate.

[0049] Specifically, the proportion of hydrogen per unit volume can be detected by mass spectrometry analysis to compare the content of hydrogen per unit volume in different parts.

[0050] Specifically, Figure 2 As shown, the array substrate 2 includes a pixel area 201 and a non-pixel area 202 arranged on at least one side of the pixel area 201. It can be understood that the pixel area corresponds to the display area in the display panel, and the non-pixel area corresponds to the non-display area in the display panel.

[0051] Specifically, Figure 2 As shown, the non-pixel area 202 is disposed around the pixel area 201 , but the embodiment of the present application is not limited thereto. The non-pixel area 202 can be disposed on one side, two sides, or three sides of the pixel area 201 .

[0052] Specifically, Figure 3 As shown, Figure 3As shown in the figure, the light-transmitting area 201a is located on one side of the non-light-transmitting area 201b. In actual design, the non-light-transmitting area 201b may be arranged around the light-transmitting area 201a.

[0053] Specifically, the array substrate includes a thin film transistor.

[0054] In some embodiments, the material of the first insulating layer includes silicon oxide, and the silicon nitride material in the light-transmitting region of the interlayer insulating layer can be reduced or removed, thereby improving the light transmittance of the light-transmitting region.

[0055] Specifically, the material of the portion of the interlayer insulating layer disposed in the light-transmitting area can be made of silicon oxide, and the silicon nitride material in the interlayer insulating layer located in the light-transmitting area can be removed to improve the transmittance of the light-transmitting area. Alternatively, the silicon nitride in the portion of the interlayer insulating layer disposed in the light-transmitting area can be made less than silicon oxide, for example, by reducing the thickness of the silicon nitride material, thereby improving the transmittance of the light-transmitting area.

[0056] In some embodiments, Figure 4 As shown, the array substrate 2 further includes a source-drain electrode layer 218, and the source-drain electrode layer 218 is arranged on the side of the interlayer insulating layer 217 away from the gate layer 216, and one side of the first insulating layer 217a is in direct contact with the source-drain electrode layer 218, and the other side of the first insulating layer 217a is in direct contact with the gate layer 216. By making one side of the first insulating layer in direct contact with the source-drain electrode layer and the other side of the first insulating layer in direct contact with the gate layer, the interlayer insulating layer can include only one first insulating layer, remove the silicon nitride layer, improve the light transmittance of the array substrate, and reduce the thickness of the array substrate. In addition, the content of hydrogen per unit volume of the portion of the first insulating layer close to the gate layer is less than the content of hydrogen per unit volume of the portion of the first insulating layer far from the gate layer, so that hydrogen atoms can diffuse into the active layer to replenish hydrogen for the active layer, so that the performance and electrical properties of the active layer are better, thereby taking into account both the light transmittance and performance stability of the array substrate.

[0057] Specifically, compared with the current display device, the silicon nitride interlayer insulating film is arranged between the silicon oxide interlayer insulating film and the gate layer. If the silicon nitride interlayer insulating film is removed and only the silicon oxide interlayer insulating film is formed, there will be no hydrogen element to replenish hydrogen to the active layer, which will lead to poor performance of the active layer. In the embodiment of the present application, the content of hydrogen elements per unit volume of the portion of the first insulating layer close to the gate layer is less than the content of hydrogen elements per unit volume of the portion of the first insulating layer far from the gate layer. When forming the array substrate, a hydrogen-containing film layer (such as a silicon nitride layer) can be arranged on the first insulating layer to allow hydrogen in the hydrogen-containing film layer to diffuse downward to the active layer to replenish hydrogen to the active layer, and then the hydrogen-containing film layer is removed or partially removed, so that when the normal hydrogen replenishment of the active layer is achieved, the transmittance of the array substrate is improved, thereby taking into account both the transmittance and performance stability of the array substrate.

[0058] In some embodiments, Figure 3 , Figure 5 As shown, the interlayer insulating layer 217 further includes a second insulating layer 217b, the material of the second insulating layer 217b is silicon nitride, the second insulating layer 217b is arranged on the side of the first insulating layer 217a away from the gate layer 216, and the second insulating layer 217b is arranged in the non-light-transmitting area 201b. By making the interlayer insulating layer further include a second insulating layer, the second insulating layer is arranged on the side of the first insulating layer away from the gate layer, and the second insulating layer is arranged in the non-light-transmitting area, the light transmittance of the array substrate can be improved by removing the portion of the second insulating layer located in the light-transmitting area, and the second insulating layer is arranged on the first insulating layer, when removing the portion of the second insulating layer located in the light-transmitting area, it is convenient to remove the portion of the second insulating layer, and the color deviation can be improved, thereby improving the display effect.

[0059] Specifically, compared with the second insulating layer being arranged between the first insulating layer and the gate layer, when the second insulating layer is patterned or removed, it is necessary to first pattern the second insulating layer or remove the second insulating layer before forming the first insulating layer, which will result in poor hydrogen replenishment effect and a more complicated process; whereas in the embodiment of the present application, the first insulating layer is arranged between the second insulating layer and the gate layer, then after the first insulating layer and the second insulating layer are formed, the active layer can be first hydrogen replenished, and then the second insulating layer can be patterned or removed. Since the hydrogen replenishment is completed, the performance of the active layer is better, the removal or patterning of the second insulating layer has less impact, and the second insulating layer can be etched and patterned or removed at the same time as other film layers, thereby simplifying the process.

[0060] Specifically, the second insulating layer may be disposed on the entire surface of the non-light-transmitting area.

[0061] In some embodiments, the source and drain electrode layer and the second insulating layer can be etched through the same mask plate; thus, no additional mask plate is required, thereby reducing process steps and costs.

[0062] In some embodiments, Figure 3 , Figure 5As shown, the array substrate 2 further includes a source-drain electrode layer 218, the width of the surface of the source-drain electrode layer 218 on the side in contact with the second insulating layer 217b is equal to the width of the surface of the second insulating layer 217b on the side in contact with the source-drain electrode layer 218, and the sidewall of the source-drain electrode layer 218 and the corresponding sidewall of the second insulating layer 217b are in the same plane. By making the width of the surface of the source-drain electrode layer on the side in contact with the second insulating layer equal to the width of the surface of the second insulating layer on the side in contact with the source-drain electrode layer, and the sidewall of the source-drain electrode layer and the corresponding sidewall of the second insulating layer are in the same plane, the source-drain electrode layer and the second insulating layer can be etched simultaneously without adding a mask, reducing the process steps, and improving the preparation efficiency of the array substrate.

[0063] In some embodiments, Figure 7 As shown, the array substrate 2 further includes a source-drain electrode layer 218, and the width of the surface of the source-drain electrode layer 218 on the side in contact with the second insulating layer 217b is smaller than the width of the surface of the second insulating layer 217b on the side in contact with the source-drain electrode layer 218. By making the width of the surface of the second insulating layer in contact with the source-drain electrode layer larger than the width of the surface of the source-drain electrode layer in contact with the second insulating layer, the second insulating layer and the source-drain electrode layer form a step structure, thereby avoiding the formation of a chamfer or undercut structure between the second insulating layer and the source-drain electrode layer, which results in the inability to fill the chamfer or undercut structure, resulting in poor display or reduced reliability.

[0064] In some embodiments, Figure 7 As shown, the angle a1 between the side wall of the source-drain electrode layer 218 and the bottom surface of the source-drain electrode layer 218 is less than or equal to the angle a2 between the side wall of the second insulating layer 217b and the bottom surface of the second insulating layer 217b. When preparing the source-drain electrode layer and the second insulating layer, the second insulating layer can be formed first, and then the source-drain electrode layer can be formed on the second insulating layer. Due to the stacking of the film layers, the climbing angle of the source-drain electrode layer can be less than or equal to the climbing angle of the second insulating layer, so that the climbing of each film layer is gentle.

[0065] Specifically, the above embodiment is described by taking the angle a1 between the side wall of the source-drain layer 218 and the bottom surface of the source-drain layer 218 as less than or equal to the angle a2 between the side wall of the second insulating layer 217b and the bottom surface of the second insulating layer 217b as an example, but the embodiments of the present application are not limited to this, and the angle between the side wall of the source-drain layer and the bottom surface of the source-drain layer can be greater than the angle between the side wall of the second insulating layer and the bottom surface of the second insulating layer.

[0066] Specifically, the angle between the sidewall of the source-drain electrode layer 218 and the bottom surface of the source-drain electrode layer 218 is in a range of 10 degrees to 55 degrees.

[0067] Specifically, when the source-drain electrode layer and the second insulating layer are formed using the same mask, the second insulating layer can be arranged beyond the source-drain electrode layer by controlling the etching rate, thereby avoiding the formation of a chamfer or undercut structure between the second insulating layer and the source-drain electrode layer, thereby improving the yield and reliability of the array substrate. When the source-drain electrode layer and the second insulating layer are formed using the same mask, the etching rate can be controlled so that the width of the surface of the source-drain electrode layer on the side in contact with the second insulating layer is equal to the width of the surface of the second insulating layer on the side in contact with the source-drain electrode layer, thereby improving the aperture ratio of the array substrate.

[0068] Specifically, when the same mask is used to form the source-drain layer and the second insulating layer, the etching rate can be controlled so that the angle between the side wall of the source-drain layer and the bottom surface of the source-drain layer is less than or equal to the angle between the side wall of the second insulating layer and the bottom surface of the second insulating layer; the etching rate can also be controlled so that the angle between the side wall of the source-drain layer and the bottom surface of the source-drain layer is greater than the angle between the side wall of the second insulating layer and the bottom surface of the second insulating layer.

[0069] Specifically, the present application embodiment takes the upper surface of a part of the film layer as a flat surface as an example for explanation. It can be understood that, due to the patterning of the part of the film layer, when the thickness of the film layer is made more uniform, the part of the film layer will form steps, for example, Figure 6 In the embodiment, the fourth insulating layer 213a and the light shielding layer 212 in the buffer layer are patterned so that when the third insulating layer 213b is formed, the third insulating layer will form a plurality of parts of different heights at the locations where the fourth insulating layer 213a and the light shielding layer 212 are set, so that steps are formed between the parts, that is, the plurality of parts on the upper surface of the buffer layer are located on different horizontal planes, and there are height differences between the parts and the parts are connected to each other to form steps, and accordingly, the active layer will form steps. Similarly, steps will also be formed for other film layers, which will not be described in detail here. It can be understood that for each embodiment, steps can be formed in the areas corresponding to other patterned film layers.

[0070] Specifically, it can be understood that when the substrate to the second electrode layer are formed in sequence, due to the accumulation of film layers, when the film layers are patterned, due to the accumulation of each film layer, the climbing angle of each film layer can be gradually slowed down.

[0071] Specifically, after forming the source-drain electrode layer and the second insulating layer, the source-drain electrode layer and the second insulating layer can be etched simultaneously through the same mask plate, without adding a new mask plate, and only the portion of the second insulating layer located under the source-drain electrode layer is retained, which can further improve the light transmittance of the array substrate. Figure 3As shown, it can be seen that the width of the bottom surface of the source and drain layer in contact with the second insulating layer is equal to the width of the top surface of the second insulating layer in contact with the source and drain layer, that is, the spacing from the left to the right side of the bottom surface of the source and drain layer is equal to the spacing from the left to the right side of the top surface of the second insulating layer. It can be understood that due to the difference in etching rates of different materials, there may be slight differences between the width of the bottom surface of the source and drain layer in contact with the second insulating layer and the width of the top surface of the second insulating layer in contact with the source and drain layer. At this time, it is still considered that the width of the bottom surface of the source and drain layer in contact with the second insulating layer is equal to the width of the top surface of the second insulating layer in contact with the source and drain layer.

[0072] Specifically, it can be understood that when the same mask plate is used to pattern the source and drain layer and the second insulating layer, due to process limitations, there may be certain differences in the edges of the various patterns of the source and drain layer and the second insulating layer. For example, during etching, the edges of each pattern will form a climbing area. Due to the difference in etching rates of different materials, the side walls of the pattern of the second insulating layer located in the lower layer and the side walls of the pattern of the source and drain layer may have certain differences in the climbing angle. The planes where the two are located may have a certain inclination and are not completely located in the same plane. At this time, the side walls of the source and drain layer are still defined as being on the same plane as the corresponding side walls in the second insulating layer.

[0073] Specifically, Figure 3 and Figure 5 Part of the structure of the source and drain layer, such as the source, drain and touch metal, is shown, and the second insulating layer located under the source, drain and touch metal is correspondingly shown. It can be understood that when the source and drain layer also includes other structures, part of the second insulating layer is correspondingly provided under the other structures.

[0074] In some embodiments, Figures 3 to 5 As shown, the array substrate 2 further includes a buffer layer 213, which is disposed between the substrate 211 and the active layer 214, and the material of the portion of the buffer layer 213 located in the light-transmitting region 201a is silicon oxide. By making the material of the portion of the buffer layer located in the light-transmitting region silicon oxide and removing the silicon nitride in the buffer layer located in the light-transmitting region, the light transmittance of the array substrate can be further improved.

[0075] Specifically, the buffer layer in the current display device is a stack of silicon nitride and silicon oxide. The embodiment of the present application makes the material of the portion of the buffer layer located in the light-transmitting area silicon oxide, removes the silicon nitride in the buffer layer located in the light-transmitting area, and improves the transmittance of the array substrate.

[0076] In some embodiments, Figure 3 to Figure 4 , Figure 6As shown, the buffer layer 213 includes a third insulating layer 213b and a fourth insulating layer 213a, the material of the third insulating layer 213b is silicon oxide, the material of the fourth insulating layer 213a is silicon nitride, and the fourth insulating layer 213a is arranged in the non-light-transmitting area 201b. By making the buffer layer include the third insulating layer and the fourth insulating layer, and making the fourth insulating layer arranged in the non-light-transmitting area, the portion of the fourth insulating layer located in the light-transmitting area can be removed, thereby improving the light transmittance of the array substrate, and the portion of the fourth insulating layer located in the non-light-transmitting area can block the ions in the substrate, thereby preventing the ions in the substrate from diffusing to the active layer to cause performance changes, thereby improving the performance stability of the array substrate, thereby taking into account both the light transmittance and performance stability of the array substrate.

[0077] Specifically, the fourth insulating layer may be entirely disposed in the non-light-transmitting area.

[0078] Specifically, compared with the buffer layer of the current display device which is a stack of silicon nitride and silicon oxide, directly removing the silicon nitride layer will cause the performance of the active layer to change. The fourth insulating layer can be set in the non-light-transmitting area to protect the active layer and improve the performance stability of the array substrate.

[0079] Specifically, the fourth insulating layer may be disposed corresponding to the active layer.

[0080] In some embodiments, Figure 3 , Figure 4 As shown, the array substrate 2 further includes a light shielding layer 212, the light shielding layer 212 is arranged between the fourth insulating layer 213a and the substrate 211, the fourth insulating layer 213a is arranged between the light shielding layer 212 and the third insulating layer 213b, and the fourth insulating layer 213a covers the light shielding layer 212. By arranging the light shielding layer between the fourth insulating layer and the substrate, the fourth insulating layer is arranged between the light shielding layer and the third insulating layer, and the fourth insulating layer covers the light shielding layer, the fourth insulating layer can block the diffusion of ions in the substrate to the active layer, block the path of ions diffusing from the light shielding layer to the active layer, and improve the performance stability of the array substrate.

[0081] Specifically, when forming the fourth insulating layer, a photomask may be used to pattern the fourth insulating layer, thereby removing the fourth insulating layer in the light-transmitting region and retaining the fourth insulating layer in other regions.

[0082] Specifically, only the portion of the fourth insulating layer corresponding to the active layer may be retained to further improve the light transmittance of the array substrate.

[0083] In some embodiments, Figure 6As shown, the array substrate 2 further includes a light shielding layer 212, the fourth insulating layer 213a is disposed between the light shielding layer 212 and the substrate 211, and the third insulating layer 213b is disposed on a side of the light shielding layer 212 away from the fourth insulating layer 213a. By disposing the fourth insulating layer between the light shielding layer and the substrate, and disposing the fourth insulating layer on a side of the light shielding layer away from the fourth insulating layer, the fourth insulating layer can block the diffusion of ions in the substrate to the active layer, thereby improving the performance stability of the array substrate.

[0084] In some embodiments, Figure 6 As shown, the projection of the surface of the light shielding layer 212 on the side close to the fourth insulating layer 213a on the substrate 211 coincides with the projection of the surface of the fourth insulating layer 213a on the side close to the light shielding layer 212 on the substrate 211, and the side wall of the light shielding layer 212 and the corresponding side wall in the fourth insulating layer 213a are in the same plane. By making the projection of the surface of the light shielding layer on the side close to the fourth insulating layer coincide with the projection of the surface of the fourth insulating layer on the side close to the light shielding layer on the substrate, the side wall of the light shielding layer and the corresponding side wall in the fourth insulating layer are in the same plane, the light shielding layer and the fourth insulating layer can be etched at the same time without adding a mask, reducing the process steps, and improving the preparation efficiency of the array substrate.

[0085] Specifically, after forming the fourth insulating layer and the light shielding layer, the same mask can be used to etch the fourth insulating layer and the light shielding layer without adding a new mask, and only the portion of the fourth insulating layer located under the light shielding layer is retained, which can further improve the transmittance of the array substrate.

[0086] Specifically, it can be understood that when the same mask is used to pattern the fourth insulating layer and the light-shielding layer, due to process limitations, there may be certain differences in the edges of the patterns of the fourth insulating layer and the light-shielding layer. For example, during etching, the edges of each pattern will form a climbing area. Due to the difference in etching rates of different materials, the climbing angles of the side walls of the pattern of the fourth insulating layer located in the lower layer and the side walls of the pattern of the light-shielding layer may be different. The planes where the two are located may be tilted to a certain extent and are not completely located in the same plane. At this time, the side walls of the light-shielding layer are still defined as being on the same plane as the corresponding side walls in the fourth insulating layer.

[0087] Specifically, the projection of the fourth insulating layer on the substrate can be made larger than the projection of the light-shielding layer on the substrate. The fourth insulating layer and the light-shielding layer can be etched through a semi-transparent mask to reduce the process steps. The projection of the fourth insulating layer on the substrate can be made larger than the projection of the light-shielding layer on the substrate, thereby further preventing ions in the substrate from diffusing into the active layer and improving the performance stability of the array substrate.

[0088] In some embodiments, Figure 5 As shown, the buffer layer 213 includes a third insulating layer 213b, the material of the third insulating layer 213b is silicon oxide, the array substrate 2 also includes a light shielding layer 212, one side of the third insulating layer 213b is in contact with the light shielding layer 212, and the other side of the third insulating layer 213b is in contact with the active layer 214, and the material of the portion of the buffer layer 213 located in the non-light-transmitting area 201b is silicon oxide. By making the buffer layer include only the third insulating layer, the light transmittance of the array substrate can be further improved, and since there is no need to etch the silicon nitride material in the buffer layer, a mask plate can be saved, the process steps can be reduced, and the preparation efficiency of the array substrate can be improved.

[0089] In some embodiments, Figures 3 to 6 As shown, the array substrate 2 further includes a source-drain electrode layer 218, a planarization layer 219, a first electrode layer 221, a passivation layer 222, and a second electrode layer 223. The source-drain electrode layer 218 is disposed on a side of the interlayer insulating layer 217 away from the gate layer 216, the planarization layer 219 is disposed on a side of the source-drain electrode layer 218 away from the interlayer insulating layer 217, the first electrode layer 221 is disposed on a side of the planarization layer 219 away from the source-drain electrode layer 218, the passivation layer 222 is disposed on a side of the first electrode layer 221 away from the planarization layer 219, and the second electrode layer 223 is disposed on a side of the passivation layer 222 away from the first electrode layer 221; wherein the material of the passivation layer 222 is silicon oxide or silicon oxynitride. By making the material of the passivation layer silicon oxide or silicon oxynitride, the light transmittance of the array substrate can be further improved.

[0090] Specifically, the above embodiment is described by taking the array substrate including the first electrode layer and the second electrode layer as an example, but the embodiment of the present application is not limited thereto, and the array substrate may have only the first electrode layer or the second electrode layer.

[0091] Specifically, by simulating the array substrate, compared with the comparative display device, the embodiment of the present application can improve the light transmittance of the array substrate by 3% by removing the silicon nitride material of the buffer layer located in the light-transmitting area and the silicon nitride material of the interlayer insulating layer located in the light-transmitting area. Further, by changing the material of the passivation layer from silicon nitride to silicon oxide or silicon oxynitride, the light transmittance of the array substrate can be improved by 5%, thereby improving the light transmittance of the array substrate and reducing power consumption.

[0092] Specifically, the array substrate 2 further includes a gate insulating layer 215 , and the gate insulating layer 215 is disposed between the active layer 214 and the gate layer 216 .

[0093] Specifically, the material of the substrate includes glass.

[0094] Specifically, the material of the gate insulating layer may be silicon oxide.

[0095] Specifically, the material of the active layer includes low temperature polysilicon. The active layer 214 includes a channel portion 214a, a lightly doped portion 214b and a heavily doped portion 214c, and the doping ion concentration of the heavily doped portion 214c is greater than that of the lightly doped portion.

[0096] Specifically, the materials of the light shielding layer, the gate layer and the source and drain electrode layer may be metal, such as a stack of titanium, aluminum and titanium, or a titanium layer and an aluminum layer.

[0097] Specifically, the material of the first electrode layer and the second electrode layer may be indium tin oxide.

[0098] Specifically, the content of hydrogen per unit volume from the portion of the first insulating layer away from the gate layer to the portion of the first insulating layer close to the gate layer is in the range of 1e 22 hydrogen atoms / cm3 to 1e 21 hydrogen atoms / cubic centimeter, and the hydrogen content per unit volume of the portion of the first insulating layer away from the gate layer may be greater than 1e 22 hydrogen atoms per cubic centimeter.

[0099] Specifically, the above embodiments describe the array substrate in detail from the perspective of different film layers and the relative positions and connection relationships of each film layer. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the array substrate also includes a source-drain layer, and the source-drain layer is arranged on the side of the interlayer insulating layer away from the gate layer, one side of the first insulating layer is in direct contact with the source-drain layer, and the other side of the first insulating layer is in direct contact with the gate layer. The array substrate also includes a buffer layer, and the buffer layer is arranged between the substrate and the active layer. The material of the portion of the buffer layer located in the light-transmitting area is silicon oxide.

[0100] Specifically, Figure 3As shown, the array substrate 2 includes a substrate 211, a light shielding layer 212, a fourth insulating layer 213a, a third insulating layer 213b, an active layer 214, a gate insulating layer 215, a gate layer 216, a first insulating layer 217a, a second insulating layer 217b, a source-drain electrode layer 218, a planarization layer 219, a first electrode layer 221, a passivation layer 222, and a second electrode layer 223, which are arranged in sequence. The content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer is less than the content of hydrogen atoms per unit volume of the portion of the first insulating layer far from the gate layer. By arranging the fourth insulating layer in the buffer layer in the non-light-transmitting area, the transmittance of the array substrate can be improved, and the fourth insulating layer can block ions in the substrate from entering the active layer, thereby improving the performance of the array substrate. The projection of the second insulating layer on the substrate coincides with the projection of the source-drain electrode layer on the substrate, thereby improving the transmittance of the array substrate without adding a mask plate and a process.

[0101] Specifically, Figure 4 As shown, the array substrate 2 includes a substrate 211, a light shielding layer 212, a fourth insulating layer 213a, a third insulating layer 213b, an active layer 214, a gate insulating layer 215, a gate layer 216, a first insulating layer 217a, a source-drain layer 218, a planarizing layer 219, a first electrode layer 221, a passivation layer 222 and a second electrode layer 223, which are arranged in sequence. The content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer is less than the content of hydrogen atoms per unit volume of the portion of the first insulating layer far from the gate layer. By setting the fourth insulating layer in the buffer layer in the non-light-transmitting area, the transmittance of the array substrate can be improved, and the fourth insulating layer can block ions in the substrate from entering the active layer, thereby improving the performance of the array substrate. The interlayer insulating layer includes only the first insulating layer, which can improve the transmittance of the array substrate.

[0102] Specifically, Figure 5 As shown, the array substrate 2 includes a substrate 211, a light shielding layer 212, a third insulating layer 213b, an active layer 214, a gate insulating layer 215, a gate layer 216, a first insulating layer 217a, a second insulating layer 217b, a source-drain layer 218, a planarization layer 219, a first electrode layer 221, a passivation layer 222 and a second electrode layer 223, which are arranged in sequence. The content of hydrogen atoms per unit volume of a portion of the first insulating layer close to the gate layer is less than the content of hydrogen atoms per unit volume of a portion of the first insulating layer far from the gate layer. By making the buffer layer only include the third insulating layer, the transmittance of the array substrate can be improved, and the projection of the second insulating layer on the substrate is made to coincide with the projection of the source-drain layer on the substrate, so that the transmittance of the array substrate can be improved without adding a mask plate and a process.

[0103] Specifically, Figure 6As shown, the array substrate 2 includes a substrate 211, a fourth insulating layer 213a, a light shielding layer 212, a third insulating layer 213b, an active layer 214, a gate insulating layer 215, a gate layer 216, a first insulating layer 217a, a second insulating layer 217b, a source-drain electrode layer 218, a planarization layer 219, a first electrode layer 221, a passivation layer 222, and a second electrode layer 223, wherein the content of hydrogen atoms per unit volume of a portion of the first insulating layer close to the gate layer is less than that of a portion of the first insulating layer far from the gate layer. The content of hydrogen atoms in the volume; by setting the fourth insulating layer in the buffer layer in the non-light-transmitting area, the transmittance of the array substrate can be improved, and the fourth insulating layer can block the ions in the substrate from entering the active layer, thereby improving the performance of the array substrate, and the projection of the fourth insulating layer on the substrate coincides with the projection of the light-shielding layer on the substrate, without adding a mask plate, simplifying the process steps, and improving the preparation efficiency of the array substrate, and making the projection of the second insulating layer on the substrate coincide with the projection of the source and drain layer on the substrate, which can improve the transmittance of the array substrate without adding a mask plate and process.

[0104] It can be understood that the above-mentioned embodiments have obtained different array substrate structures by different combinations of some film layers and their structures. The above-mentioned embodiments are not the structures of all array substrates in the embodiments of the present application. When there is no conflict between the film layers and their structures, the film layers and their structures can be combined to obtain other array substrate structures.

[0105] At the same time, an embodiment of the present application provides a method for preparing an array substrate, and the method for preparing an array substrate prepares the array substrate as described in any of the above embodiments.

[0106] Specifically, the method for preparing the array substrate includes:

[0107] A substrate is provided, and a light shielding layer and a fourth insulating layer are sequentially formed on the substrate; the structure of the array substrate corresponding to this step is as follows Figure 8 As shown in (a);

[0108] The fourth insulating layer is patterned; the structure of the array substrate corresponding to this step is as follows: Figure 8 As shown in (b);

[0109] A third insulating layer, an active layer, a gate insulating layer and a gate layer are formed on the fourth insulating layer; the structure of the array substrate corresponding to this step is as follows Figure 8 As shown in (c);

[0110] A first insulating layer and a second insulating layer are formed on the gate layer; the structure of the array substrate corresponding to this step is as follows Figure 8 As shown in (d);

[0111] The array substrate is subjected to rapid thermal annealing, and the second insulating layer is etched to form openings, and a source-drain electrode layer is formed on the second insulating layer; the structure of the array substrate corresponding to this step is as follows: Figure 8 As shown in (e);

[0112] The source and drain electrode layers and the second insulating layer are etched simultaneously; the structure of the array substrate corresponding to this step is as follows: Figure 8 As shown in (f);

[0113] A planarization layer, a first electrode layer, a passivation layer, and a second electrode layer are sequentially formed on the source and drain electrode layers; the structure of the array substrate corresponding to this step is as follows Figure 3 shown.

[0114] Specifically, when forming an array substrate, regardless of whether the second insulating layer is retained, the second insulating layer can be first formed on the first insulating layer, and then the array substrate is subjected to a rapid thermal annealing process to activate the hydrogen in the second insulating layer and diffuse it to the active layer to combine with the dangling bonds in the active layer, thereby reducing defects in the active layer. Then, the second insulating layer can be completely removed or a portion of the second insulating layer can be retained, for example, the second insulating layer and the source and drain layer can be etched at the same time. Both methods do not require the addition of a mask plate, thereby reducing costs and improving preparation efficiency.

[0115] Specifically, Fig. 9 As shown, Figure 1 Taking the structure of the comparative display device shown in FIG. 1 as an example, when forming the comparative display device, in order to replenish hydrogen in the active film, a rapid thermal annealing process is performed after forming the interlayer insulating film. By comparing the hydrogen atom concentration in the comparative display device formed by the rapid thermal annealing process and the comparative display device formed without the rapid thermal annealing process, it is obtained that Fig. 9 The curve graph shown, Fig. 9 The horizontal axis in the figure is the depth downward from the upper surface of the silicon oxide interlayer insulating film 117b, and the unit is nanometers. For example, the position with a depth of 100 indicates that the distance from the upper surface of the silicon oxide interlayer insulating film is 100 nanometers, and the position with a depth of 0 indicates the position where the upper surface of the silicon oxide interlayer insulating film is located; Fig. 9 The vertical axis in is the concentration of hydrogen atoms, and the unit is the number of hydrogen atoms per cubic centimeter. Curve 1 is the data obtained by testing the peripheral area of ​​the motherboard corresponding to the comparative display device when the comparative display device is formed by the rapid thermal annealing process, Curve 2 is the data obtained by testing the middle area of ​​the motherboard corresponding to the comparative display device when the comparative display device is formed by the rapid thermal annealing process, Curve 3 is the data obtained by testing the peripheral area of ​​the motherboard corresponding to the comparative display device when the comparative display device is formed without the rapid thermal annealing process, Curve 4 is the data obtained by testing the middle area of ​​the motherboard corresponding to the comparative display device when the comparative display device is formed without the rapid thermal annealing process; from Fig. 9 It can be seen that when the rapid thermal annealing process is used, the hydrogen atom concentration of each film layer is relatively high.

[0116] like Fig.10 As shown, Fig.10 (a) is a schematic diagram of the diffusion of hydrogen elements in a comparative display device provided in an embodiment of the present application, Fig.10 (b) is a schematic diagram of the diffusion of hydrogen elements in an array substrate provided in an embodiment of the present application. Fig.10 As can be seen in FIG. 1 , when the array substrate is subjected to rapid thermal annealing, the hydrogen atoms 31 in the silicon nitride layer diffuse into the channel portion of the active layer. Fig.10 In (a), the silicon nitride interlayer insulating film 117a is located between the silicon oxide interlayer insulating film 117b and the gate film 116. Therefore, the concentration of hydrogen atoms in the portion of the silicon oxide interlayer insulating film close to the silicon nitride interlayer insulating film is greater than the concentration of hydrogen atoms in the portion of the silicon oxide interlayer insulating film far from the silicon nitride interlayer insulating film. Specifically, the concentration of hydrogen atoms in the silicon oxide interlayer insulating film from far from the silicon nitride interlayer insulating film to close to the silicon nitride interlayer insulating film ranges from 0 to 1e 22 hydrogen atoms / cubic centimeter, and in the embodiment of the present application, Fig.10 As shown in (b), the second insulating layer is disposed on a side of the first insulating layer away from the gate layer. Therefore, the content of hydrogen atoms per unit volume of the portion of the first insulating layer away from the gate layer is greater than the content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer. The range of the content of hydrogen atoms per unit volume from the portion of the first insulating layer away from the gate layer to the portion of the first insulating layer close to the gate layer is 1e 22 hydrogen atoms / cm3 to 1e 21 hydrogen atoms per cubic centimeter.

[0117] Specifically, based on Figure 1 The comparison between the display device and Figure 3 The electrical properties of the thin film transistors are tested by the array substrate in Fig.11 , Fig.12 The data shown, Fig.11 (a) is a comparison diagram of the threshold voltage Vth of the thin film transistor in the display device and the threshold voltage Vth of the thin film transistor of the array substrate in the embodiment of the present application, Fig.11 (b) is a comparison diagram of the mobility Mob of the thin film transistor in the display device and the mobility Mob of the thin film transistor of the array substrate in the embodiment of the present application, Fig.11 (c) is a comparison diagram of the on-state current Ion of the thin film transistor in the display device and the on-state current Ion of the thin film transistor of the array substrate in the embodiment of the present application, Fig.12(a) is a comparison diagram of the subthreshold swing SS of the thin film transistor in the display device and the subthreshold swing SS of the thin film transistor of the array substrate in the embodiment of the present application, Fig.12 (b) is a comparison diagram of the leakage current loff of the thin film transistor in the display device and the leakage current loff of the thin film transistor of the array substrate in the embodiment of the present application. Fig.11 (a) to Fig.11 (c) Fig.12 (a) to Fig.12 STD1 in the horizontal axis of (b) represents the result obtained by the first test of the comparative display device, STD2 represents the result obtained by the second test of the comparative display device, ILD Reverse1 represents the result obtained by the first test of the array substrate in the embodiment of the present application, and ILD Reverse2 represents the result obtained by the second test of the array substrate in the embodiment of the present application. Fig.11 The vertical axis of (a) is the threshold voltage, the unit is V, that is, volts. Fig.11 The vertical axis of (b) is the mobility, in cm 2 / (V*s), that is, square centimeter / (volt*second), Fig.11 The vertical axis of (c) is the on-state current, with the unit of A, i.e. ampere. Fig.12 The vertical axis of (a) is the subthreshold swing, and the unit is mV / dec, that is, millivolt / decade. Fig.12 The vertical axis of (b) is the leakage current, and the unit is A, i.e. ampere.

[0118] from Fig.11 , Fig.12 It can be seen that the performance of the thin film transistor of the array substrate in the embodiment of the present application is similar to the performance of the thin film transistor in the comparative display device, that is, the electrical properties of the two are similar.

[0119] At the same time, an embodiment of the present application provides a display panel, which includes the array substrate as described in any of the above embodiments.

[0120] Specifically, Fig.13 As shown, the display panel 4 includes an array substrate 2 , a color filter substrate 41 , and a liquid crystal layer 42 disposed between the array substrate 2 and the color filter substrate 41 .

[0121] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0122] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0123] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0124] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes a pixel area, wherein the pixel area includes a light-transmitting area and a non-light-transmitting area located at at least one side of the light-transmitting area. The array substrate includes: substrate; An active layer, disposed on one side of the substrate; A gate layer, disposed on a side of the active layer away from the substrate; an interlayer insulating layer, arranged on a side of the gate layer away from the active layer, the interlayer insulating layer comprising a first insulating layer, wherein the content of nitrogen in the interlayer insulating layer and the first insulating layer located in the light-transmitting region is less than the content of oxygen; The content of hydrogen per unit volume of a portion of the first insulating layer close to the gate layer is smaller than the content of hydrogen per unit volume of a portion of the first insulating layer far from the gate layer.

2. The array substrate according to claim 1, characterized in that: The array substrate further includes a source-drain layer, which is disposed on a side of the interlayer insulating layer away from the gate layer, one side of the first insulating layer is in direct contact with the source-drain layer, and the other side of the first insulating layer is in direct contact with the gate layer.

3. The array substrate according to claim 1, characterized in that: The interlayer insulating layer further includes a second insulating layer. The material of the second insulating layer is silicon nitride. The second insulating layer is arranged on a side of the first insulating layer away from the gate layer. The second insulating layer is arranged in the non-light-transmitting area.

4. The array substrate according to claim 3, characterized in that: The array substrate also includes a source-drain layer, the width of the surface of the source-drain layer on the side in contact with the second insulating layer is equal to the width of the surface of the second insulating layer on the side in contact with the source-drain layer, and the side wall of the source-drain layer and the corresponding side wall of the second insulating layer are on the same plane.

5. The array substrate according to claim 3, characterized in that: The array substrate further includes a source-drain electrode layer, and a width of a surface of the source-drain electrode layer on a side in contact with the second insulating layer is smaller than a width of a surface of the second insulating layer on a side in contact with the source-drain electrode layer.

6. The array substrate according to claim 5, characterized in that: An included angle between a side wall of the source / drain electrode layer and a bottom surface of the source / drain electrode layer is smaller than or equal to an included angle between a side wall of the second insulating layer and a bottom surface of the second insulating layer.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The material of the first insulating layer includes silicon oxide.

8. The array substrate according to any one of claims 1 to 6, characterized in that: The array substrate further includes a buffer layer, which is disposed between the substrate and the active layer, and a portion of the buffer layer located in the light-transmitting region is made of silicon oxide.

9. The array substrate according to claim 8, characterized in that: The buffer layer includes a third insulating layer and a fourth insulating layer. The material of the third insulating layer is silicon oxide, the material of the fourth insulating layer is silicon nitride, and the fourth insulating layer is arranged in the non-light-transmitting area.

10. The array substrate according to claim 9, characterized in that: The array substrate further includes a light shielding layer, which is disposed between the fourth insulating layer and the substrate, the fourth insulating layer is disposed between the light shielding layer and the third insulating layer, and the fourth insulating layer covers the light shielding layer.

11. The array substrate according to claim 9, characterized in that: The array substrate further includes a light shielding layer, the fourth insulating layer is arranged between the light shielding layer and the substrate, and the third insulating layer is arranged on a side of the light shielding layer away from the fourth insulating layer.

12. The array substrate according to claim 11, characterized in that: The projection of the surface of the light-shielding layer close to the fourth insulating layer on the substrate coincides with the projection of the surface of the fourth insulating layer close to the light-shielding layer on the substrate, and the side wall of the light-shielding layer and the corresponding side wall in the fourth insulating layer are on the same plane.

13. The array substrate according to claim 8, characterized in that: The buffer layer includes a third insulating layer, and the array substrate also includes a light shielding layer. One side of the third insulating layer contacts the light shielding layer, and the other side of the third insulating layer contacts the active layer. The material of the portion of the buffer layer located in the non-light-transmitting area is silicon oxide.

14. The array substrate according to any one of claims 1 to 6, characterized in that: The array substrate further comprises a source-drain electrode layer, a planarization layer, a first electrode layer, a passivation layer, and a second electrode layer, wherein the source-drain electrode layer is arranged on a side of the interlayer insulating layer away from the gate layer, the planarization layer is arranged on a side of the source-drain electrode layer away from the interlayer insulating layer, the first electrode layer is arranged on a side of the planarization layer away from the source-drain electrode layer, the passivation layer is arranged on a side of the first electrode layer away from the planarization layer, and the second electrode layer is arranged on a side of the passivation layer away from the first electrode layer; Wherein, the material of the passivation layer is silicon oxide or silicon oxynitride.

15. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 14.

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