Quantum dot-vertical linear avalanche photodiode single photon detector and preparation method thereof

Abstract

The application relates to an avalanche diode single-photon detector and a preparation method thereof, in particular to a quantum dot-vertical linear avalanche diode single-photon detector and a preparation method thereof, and solves the problems of low detection efficiency of the existing single-photon detector and high preparation difficulty, high cost and limited effect of the existing method. + The detector comprises a detector N + substrate, a back electrode grown on the lower surface thereof, a plurality of quantum dot-vertical linear units arranged at intervals on the upper surface thereof, a passivation layer and a front electrode; the quantum dot-vertical linear unit comprises a semiconductor vertical linear structure, a porous nanomaterial layer and a quantum dot material layer; the semiconductor vertical linear structure is grown on the upper surface of the detector N + substrate; the porous nanomaterial layer covers the semiconductor vertical linear structure; the quantum dot material layer covers the porous nanomaterial layer; the passivation layer is filled between the quantum dot-vertical linear units; and the front electrode is grown on the part of the quantum dot-vertical linear unit extending out of the passivation layer.

Description

Technical Field

[0001] This invention relates to an avalanche diode single-photon detector and its fabrication method, and particularly to a quantum dot-vertical linear avalanche diode single-photon detector and its fabrication method. Background Technology

[0002] Single-photon detectors possess extremely high sensitivity at the photon scale, playing a crucial role in advancing cutting-edge fields such as quantum communication, biomedicine, and remote sensing. Avalanche diode single-photon detector arrays are an important type of single-photon detector, offering advantages over other single-photon detectors such as photomultiplier tubes and superconducting single-photon detectors, including high integration, low power consumption, and versatility in applications. However, the photon detection efficiency of single-photon avalanche diodes is limited by the photon absorption efficiency of the photon-absorbing material. Existing Si, SiGe, and III-V group single-photon avalanche diodes have limited response bands and relatively low photon absorption efficiencies, restricting further improvements in the performance of avalanche diode single-photon detectors.

[0003] Existing methods to improve photon absorption efficiency include integrating a microlens structure into the light-gathering surface of an avalanche diode single-photon detector or introducing a distributed Bragg mirror structure within it. These two methods are detailed below:

[0004] (1) Integrating a microlens structure on the light-receiving surface of the detector. The principle of this method is to utilize the deflection and converging effect of the microlens structure integrated on the light-receiving surface of the detector to focus light onto the active region of the detector, thereby improving the absorption rate of incident light. The disadvantage of this method is that the deflection and converging effect of the microlens structure on light not only depends on the size and structural design, but also the final appearance of the microlens structure morphology is affected by the photolithography mask preparation and etching process, making it difficult to strictly control the morphology of the microlens structure. This results in high fabrication costs and a lower-than-expected focusing effect. In addition, because the microlens units are isolated from each other, their fill factor in the entire detector chip is low, which has a limited effect on improving photon absorption efficiency, and thus the effect on improving the photon detection efficiency of the detector is not obvious.

[0005] (2) Introducing a distributed Bragg mirror structure inside the detector. The principle of this method is to improve the peak value of photon absorption and the in-band flatness of broadband light absorption by using a distributed Bragg mirror structure introduced inside the detector. The disadvantage of this method is that the specific composition of the distributed Bragg mirror structure involves the stacking of multiple thin film materials with different refractive indices, making it difficult to find the optimal solution for material thickness design, thus limiting its effect on improving photon absorption efficiency; in addition, introducing a distributed Bragg mirror structure increases the number of detector fabrication steps, increasing the difficulty and complexity of the process, and resulting in higher fabrication costs.

[0006] In summary, developing an avalanche diode single-photon detector that is easy to fabricate, has low fabrication cost, and high photon detection efficiency is an urgent problem to be solved. Summary of the Invention

[0007] The purpose of this invention is to address the technical problems of low photon detection efficiency in existing avalanche diode single-photon detectors, and the increased difficulty and cost of fabrication, as well as the limited effect on improving photon detection efficiency when using existing methods to enhance their photon detection efficiency. The invention provides a quantum dot-vertical linear avalanche diode single-photon detector and its fabrication method.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0009] A quantum dot-vertical-line avalanche diode single-photon detector, which is special in that:

[0010] Including detector N + Substrate, grown on the detector N + The back electrode on the lower surface of the substrate and the array spacing are arranged on the detector N. + Multiple quantum dot-vertical line units on the upper surface of the substrate, as well as a passivation layer and a front electrode;

[0011] Each of the quantum dot-vertical-line units includes a semiconductor vertical-line structure, a porous nanomaterial layer, and a quantum dot material layer;

[0012] The semiconductor vertical line structure is grown on detector N. + On the upper surface of the substrate, there are heavily doped N atoms epitaxially grown sequentially from bottom to top. + Layer, undoped type I layer, lightly doped P - Layers and heavily doped P + The semiconductor vertical line structure consists of a porous nanomaterial layer grown on the outer surface of the semiconductor vertical line structure, covering the semiconductor vertical line structure; a quantum dot material layer coated on the outer surface of the porous nanomaterial layer, covering the porous nanomaterial layer; the quantum dot material layer is used to absorb photons; the porous nanomaterial layer is used to absorb photogenerated excitons and achieve electron-hole separation; and the semiconductor vertical line structure is used to achieve photogenerated carrier multiplication.

[0013] The passivation layer fills the gaps between each quantum dot-vertical line unit and the outer ring surrounding all the quantum dot-vertical line units; the upper surface of the passivation layer is parallel to the detector N. + On the upper surface of the substrate, and above the heavily doped P + The bottom surface of the layer, the top of the quantum dot-vertical line unit extends out of the top surface of the passivation layer;

[0014] The front electrode is grown on the outer surface of the protruding portion of each quantum dot-vertical line unit that extends beyond the upper surface of the passivation layer. Its lower surface is coplanar with the upper surface of the passivation layer, covering the upper surface of the passivation layer and the outer surface of the protruding portion of each quantum dot-vertical line unit that extends beyond the upper surface of the passivation layer.

[0015] Furthermore, the detector N + The substrate refers to a doping concentration in the range of 5×10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer;

[0016] The heavily doped N + A layer refers to a doping concentration range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 The N-type semiconductor layer; the lightly doped P - A layer refers to a doping concentration range of 1×10⁻⁶. 15 cm -3 Up to 5×10 16 cm -3 The P-type semiconductor layer; the heavily doped P + A layer refers to a doping concentration range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 P-type semiconductor layer;

[0017] The radial dimension of the horizontal cross-section of the semiconductor vertical line structure is greater than or equal to 10 nm and less than or equal to 10 μm.

[0018] Furthermore, the height of the top of the quantum dot-vertical line unit extending beyond the upper surface of the passivation layer is greater than or equal to 10 nm and less than or equal to 1 μm.

[0019] Furthermore, the detector N + The substrate and the semiconductor vertical line structure are made of silicon, germanium, or group III-V semiconductor materials;

[0020] The porous nanomaterial layer is made of a two-dimensional material;

[0021] The quantum dot material layer is made of lead sulfide, indium phosphide, cadmium selenide, or indium arsenide.

[0022] The passivation layer is made of benzocyclobutene, SU-8 resin, or spin-coated glass.

[0023] Furthermore, the front electrode is made of a transparent conductive film;

[0024] The material of the back electrode is a metallic material or a multilayer material of multiple metals.

[0025] Meanwhile, the present invention also provides a method for fabricating the above-mentioned quantum dot-vertical linear avalanche diode single-photon detector, which is characterized by including the following steps:

[0026] Step 1: Based on the size and material requirements of the quantum dot-vertical linear avalanche diode single-photon detector to be fabricated, prepare detector N. + Substrate;

[0027] Step 2: The detector N prepared in step 1 + On the upper surface of the substrate, heavily doped N₂ is epitaxially grown sequentially from bottom to top. + Layer, undoped type I layer, lightly doped P - Layers and heavily doped P + layer;

[0028] Step 3: After the heavy doped P has been grown on the upper surface in step 2 + Layer detector N + A back electrode is grown on the lower surface of the substrate;

[0029] Step 4: After the back electrode is grown in step 2, the heavily doped P electrode is grown in step 3. + On the upper surface of the layer, the semiconductor vertical line structure region is defined by photolithography and etched. During etching, the heavily doped P grown in step 2 is etched. + Starting from the top surface of the layer, it passes through heavily doped P layers from top to bottom. + Layer, lightly doped P - Layer, undoped type I layer, heavily doped N + Layer, until detector N is reached. + On the upper surface of the substrate, an array of spaced cells is etched to grow on the detector N. + Multiple semiconductor vertical line structures on the upper surface of the substrate;

[0030] Step 5: On the outer surface of each of the semiconductor vertical line structures etched in step 4, a porous nanomaterial layer is grown to cover each of the semiconductor vertical line structures.

[0031] Step 6: After the porous nanomaterial layers corresponding to the vertical line structures of the semiconductors grown on the outer surface in Step 5 are completed, a quantum dot material layer is coated on the outer surface to cover the porous nanomaterial layers, resulting in an array spaced arrangement on detector N. + Multiple quantum dot-vertical line units on the surface of the substrate;

[0032] Step 7: The gap positions between each quantum dot-vertical line unit obtained in Step 6 and the outer ring positions surrounding all the quantum dot-vertical line units are coated with passivation material and heat-treated to form a thermosetting polymer, i.e., a passivation layer is formed.

[0033] Step 8: Use an etching process to remove excess passivation material on the passivation layer formed in Step 7 to expose the top of each quantum dot-vertical line unit obtained in Step 6; then grow a front electrode on the outer surface of the protruding portion of the top of each quantum dot-vertical line unit that extends beyond the upper surface of the passivation layer; complete the fabrication of the quantum dot-vertical line avalanche diode single-photon detector.

[0034] Furthermore, in step 2, the detector N prepared in step 1... + On the upper surface of the substrate, heavily doped N₂ is epitaxially grown sequentially from bottom to top. + Layer, undoped type I layer, lightly doped P - Layers and heavily doped P + When growing layers, the growth method can be either chemical vapor deposition or molecular beam epitaxy.

[0035] Furthermore, in step 5, when growing the porous nanomaterial layer, the growth method can be pulsed laser deposition, chemical vapor deposition, or electrolytic etching.

[0036] Furthermore, in step 6, when coating the quantum dot material layer, the coating is performed by spin coating or spray coating.

[0037] Furthermore, in step 3, when growing the back electrode, the growth method is either magnetron sputtering or electron beam evaporation;

[0038] In step 8, the front electrode is grown using magnetron sputtering.

[0039] The beneficial effects of this invention are:

[0040] (1) The quantum dot-vertical avalanche diode single-photon detector of the present invention integrates a semiconductor vertical structure with a quantum dot material layer. The quantum dot material layer is coated on the outer surface of a porous nanomaterial layer grown on the outer surface of the semiconductor vertical structure. The quantum dot material is designed as a photon absorbing material to cover the vertical PIN avalanche diode in three dimensions. The quantum dot material layer is used as a photosensitive layer to efficiently capture incident photons and generate photogenerated carriers. The vertical avalanche diode operates in Geiger mode, and the carriers undergo collisional ionization under high electric field conditions to form a detectable current. The present invention overcomes the limitation that the quantum dot material layer in conventional single-photon detectors can only cover a certain plane of the device, greatly increasing the effective area of ​​the photon absorbing layer and expanding the effective incident light. The increased field of view of the detector enhances photon absorption efficiency, thereby significantly improving the photon detection efficiency of the single-photon detector. In the fabrication process of the quantum dot-vertical avalanche diode single-photon detector of this invention, a simple liquid-phase processing technique is used to uniformly coat quantum dot material over a large area onto the outer surface of a porous nanomaterial layer grown on the outer surface of a semiconductor vertical-line structure. This process is not limited by lattice mismatch, exhibiting excellent material compatibility, ease of fabrication, easy control of process parameters, and low fabrication cost. Therefore, this invention solves the technical problems of low photon detection efficiency in existing avalanche diode single-photon detectors and the increased fabrication difficulty, higher fabrication cost, and limited effect on improving photon detection efficiency when using existing methods to enhance their photon detection efficiency.

[0041] (2) In the quantum dot-vertical-line avalanche diode single-photon detector of the present invention, quantum dot material is used as photon absorption material. By utilizing the quantum confinement effect of quantum dots, the material band gap can be precisely controlled by adjusting the size and material of quantum dots, and flexible spectral response can be achieved. Simple liquid phase processing technology such as spin coating and spraying is used to replace epitaxial material growth. Quantum dot material is uniformly coated on the outer surface of the porous nanomaterial layer grown on the outer surface of the semiconductor vertical line structure, so that the quantum dots and the carrier avalanche multiplication structure are integrated, which improves the flexibility of device structure design. The vertical semiconductor vertical line structure is used to realize photogenerated carrier multiplication. Since each semiconductor vertical line structure can undergo avalanche multiplication independently, the dark count and after-pulse effect of the single-photon detector can be effectively suppressed.

[0042] (3) The quantum dot-vertical avalanche diode single-photon detector of the present invention effectively reduces the area per unit number of pixels while improving photon detection efficiency. This is beneficial to reducing the pixel center distance and the total area of ​​a single chip. Compared with existing single-photon detectors, in order to improve the sensitivity of a single pixel, the diameter of a single pixel of the single-photon avalanche diode reaches tens of micrometers, which limits the spatial resolution and array size of the detector and increases the cost of fabrication. The present invention improves the upper limit of the array size of the single-photon detector. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of an embodiment of the quantum dot-vertical-line avalanche diode single-photon detector of the present invention;

[0044] Figure 2 This is a flowchart of an embodiment of the fabrication method of the quantum dot-vertical linear avalanche diode single-photon detector of the present invention.

[0045] The labels in the diagram are explained as follows:

[0046] 1-Detector N + Substrate, 2-back electrode, 3-semiconductor vertical line structure, 31-heavily doped N + Layer 32 - Undoped Type I layer, Layer 33 - Lightly doped P - Layer, 34-heavily doped P + 4-Porous nanomaterial layer, 5-Quantum dot material layer, 6-Passivation layer, 7-Front electrode. Detailed Implementation

[0047] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0048] See Figure 1 This invention discloses a quantum dot-vertical-line avalanche diode single-photon detector, comprising detector N. + Substrate 1, grown on detector N + The back electrode 2 on the lower surface of substrate 1 is arranged in an array at intervals on detector N. + The substrate 1 has multiple quantum dot-vertical line units on its upper surface, and also includes a passivation layer 6 and a front electrode 7. The aforementioned detector N... + Substrate 1 typically refers to a doping concentration in the range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 The N-type semiconductor layer.

[0049] Each of the aforementioned quantum dot-vertical-line units comprises a semiconductor vertical-line structure 3, a porous nanomaterial layer 4, and a quantum dot material layer 5. The aforementioned semiconductor vertical-line structure 3 is grown on the detector N. + On the upper surface of substrate 1, there are heavily doped N atoms epitaxially grown sequentially from bottom to top. + Layer 31, undoped type I layer; Layer 32, lightly doped P. - Layer 33 and heavily doped P + Layer 34; the above heavily doped N + Layer 31 typically refers to a doping concentration range of 5 × 10⁻⁶. 17 cm -3 Up to 1×1020 cm -3 The N-type semiconductor layer; the above lightly doped P - Layer 33 typically refers to a doping concentration range of 1×10⁻⁶. 15 cm -3 Up to 5×10 16 cm -3 The P-type semiconductor layer; the above-mentioned heavily doped P + Layer 34 typically refers to a doping concentration range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 The P-type semiconductor layer; the radial dimension of the horizontal cross-section of the above semiconductor vertical line structure 3 is greater than or equal to 10 nm and less than or equal to 10 μm; the above detector N + The materials of substrate 1 and the aforementioned semiconductor vertical line structure 3 include, but are not limited to, silicon, germanium, or group III-V semiconductor materials; in this embodiment, detector N + The substrate 1 is made of indium phosphide (InP), and the semiconductor vertical line structure 3 is also made of indium phosphide (InP). The porous nanomaterial layer 4 is grown on the outer surface of the semiconductor vertical line structure 3, covering it. The material of the porous nanomaterial layer 4 includes, but is not limited to, surface defect materials and loosely structured two-dimensional materials; in this embodiment, the porous nanomaterial layer 4 is made of porous graphene. The quantum dot material layer 5 is coated on the outer surface of the porous nanomaterial layer 4, covering it. The material of the quantum dot material layer 5 includes, but is not limited to, lead sulfide, indium phosphide, cadmium selenide, or indium arsenide; in this embodiment, the quantum dot material layer 5 is made of indium arsenide (InAs). The quantum dot material layer 5 is used to absorb photons, the porous nanomaterial layer 4 is used to absorb photoexcitons and achieve electron-hole separation, and the semiconductor vertical line structure 3 is used to achieve photogenerated carrier multiplication.

[0050] The aforementioned passivation layer 6 fills the gaps between each quantum dot-vertical line unit and the outer ring surrounding all the quantum dot-vertical line units; the upper surface of the passivation layer 6 is parallel to the detector N. + On the upper surface of substrate 1, and above the heavily doped P + On the lower surface of layer 34, the top of the quantum dot-vertical line unit extends beyond the upper surface of passivation layer 6. Preferably, the height of the top of the quantum dot-vertical line unit extending beyond the upper surface of passivation layer 6 is typically greater than or equal to 10 nm and less than or equal to 1 μm. The material of passivation layer 6 includes, but is not limited to, benzocyclobutene (BCB), SU-8 resin, or spin-coated glass. In this embodiment, spin-coated glass material is used for passivation layer 6.

[0051] The aforementioned front electrode 7 is grown on the outer surface of the protruding portion extending from the top of each quantum dot-vertical line unit beyond the upper surface of the passivation layer 6. Its lower surface is coplanar with the upper surface of the passivation layer 6, covering both the upper surface of the passivation layer 6 and the outer surface of the protruding portion extending from the top of each quantum dot-vertical line unit beyond the upper surface of the passivation layer 6. The material of the aforementioned back electrode 2 includes, but is not limited to, metals such as gold, aluminum, titanium, and nickel, or multilayer materials of various metals; in this embodiment, the back electrode 2 uses a titanium / gold multilayer (Ti / Au multilayer) material. The material of the aforementioned front electrode 7 includes, but is not limited to, transparent conductive films such as ITO; in this embodiment, the front electrode 7 uses a transparent conductive film of ITO material.

[0052] In addition, the present invention also provides a method for fabricating the above-mentioned quantum dot-vertical-line avalanche diode single-photon detector, see [link to documentation]. Figure 2 This includes the following steps:

[0053] Step 1: Based on the size and material requirements of the quantum dot-vertical linear avalanche diode single-photon detector to be fabricated, prepare detector N. + Substrate 1;

[0054] Step 2: The detector N prepared in step 1 + On the upper surface of substrate 1, heavily doped N₂ is epitaxially grown sequentially from bottom to top. + Layer 31, undoped type I layer; Layer 32, lightly doped P. - Layer 33 and heavily doped P + Layer 34; its growth methods include, but are not limited to, chemical vapor deposition, molecular beam epitaxy, etc.

[0055] Step 3: After the heavy doped P has been grown on the upper surface in step 2 + Detector N of layer 34 + On the lower surface of substrate 1, a back electrode 2 is grown; the growth method includes, but is not limited to, magnetron sputtering, electron beam evaporation, etc.

[0056] Step 4: After growing the back electrode 2 in step 3, the heavily doped P grown in step 2 is... + On the upper surface of layer 34, the semiconductor vertical line structure 3 region is defined by photolithography and etched. During etching, the heavily doped P grown in step 2 is etched. + Starting from the top surface of layer 34, the layers pass through heavily doped P layers from top to bottom. + Layer 34, lightly doped P - Layer 33, undoped type I layer 32, heavily doped N + Layer 31, until detector N is reached. + On the upper surface of substrate 1, an array of spaced-out arrangements is etched to grow on detector N. + Multiple semiconductor vertical line structures 3 on the upper surface of substrate 1;

[0057] Step 5: On the outer surface of each of the semiconductor vertical line structures 3 etched in step 4, a porous nanomaterial layer 4 is grown to cover each of the semiconductor vertical line structures 3; the growth method includes, but is not limited to, pulsed laser deposition, chemical vapor deposition, electrolytic etching, etc.

[0058] Step 6: On the outer surface of the porous nanomaterial layer 4 corresponding to each of the aforementioned semiconductor vertical line structures 3 after the porous nanomaterial layer 4 has been grown on the outer surface in step 5, a quantum dot material layer 5 is coated to cover the aforementioned porous nanomaterial layer 4, resulting in an array spaced arrangement on the detector N. + Multiple quantum dot-vertical line units on the upper surface of substrate 1; when coating quantum dot material layer 5, the coating method includes, but is not limited to, spin coating, spray coating, etc.

[0059] Step 7: The gap positions between each of the quantum dot-vertical line units obtained in step 6 and the outer ring positions surrounding all the quantum dot-vertical line units are coated with passivation material and heat-treated to form a thermosetting polymer, i.e., passivation layer 6 is formed.

[0060] Step 8: Use an etching process to remove excess passivation material from the passivation layer 6 formed in step 7 to expose the top of each quantum dot-vertical line unit obtained in step 6; then, grow a front electrode 7 on the outer surface of the protruding portion of the top of each quantum dot-vertical line unit extending from the upper surface of the passivation layer 6; the growth method of the front electrode 7 includes, but is not limited to, magnetron sputtering; thus completing the fabrication of the quantum dot-vertical line avalanche diode single-photon detector.

[0061] In summary, the quantum dot-vertical-line avalanche diode single-photon detector of the present invention effectively reduces the area per unit pixel while improving photon detection efficiency. This is beneficial for reducing pixel center-to-center distance and the total area of ​​a single chip, thereby increasing the upper limit of the single-photon detector array size. Furthermore, the fabrication method of the quantum dot-vertical-line avalanche diode single-photon detector of the present invention is simple, the process parameters are easy to control, and the fabrication cost is low.

Claims

1. A quantum dot-vertical-line avalanche diode single-photon detector, characterized in that: Including detector N + Substrate (1), grown on detector N + The back electrode (2) on the lower surface of the substrate (1) and the array spacing are arranged on the detector N. + Multiple quantum dot-vertical line units on the upper surface of the substrate (1) also include a passivation layer (6) and a front electrode (7); Each of the quantum dot-vertical-line units comprises a semiconductor vertical-line structure (3), a porous nanomaterial layer (4), and a quantum dot material layer (5); The semiconductor vertical line structure (3) is grown on the detector N. + On the upper surface of the substrate (1), there are heavily doped N atoms epitaxially grown sequentially from bottom to top. + Layer (31), undoped type I layer (32), lightly doped P - Layer (33) and heavily doped P + Layer (34); the porous nanomaterial layer (4) is grown on the outer surface of the semiconductor vertical line structure (3) and covers the semiconductor vertical line structure (3); the quantum dot material layer (5) is coated on the outer surface of the porous nanomaterial layer (4) and covers the porous nanomaterial layer (4); the quantum dot material layer (5) is used to absorb photons; the porous nanomaterial layer (4) is made of porous graphene material; the semiconductor vertical line structure (3) is used to realize photogenerated carrier multiplication; The passivation layer (6) fills the gaps between each quantum dot-vertical line unit and the outer ring surrounding all the quantum dot-vertical line units. The upper surface of the passivation layer (6) is parallel to the detector N. + The upper surface of substrate (1), and above the heavily doped P + The lower surface of layer (34) and the top of quantum dot-vertical line unit extend out of the upper surface of passivation layer (6); The front electrode (7) is grown on the outer surface of the protruding portion of the top of each quantum dot-vertical line unit extending out of the upper surface of the passivation layer (6), and its lower surface is coplanar with the upper surface of the passivation layer (6), covering the upper surface of the passivation layer (6) and the outer surface of the protruding portion of the top of each quantum dot-vertical line unit extending out of the upper surface of the passivation layer (6).

2. The quantum dot-vertical avalanche diode single-photon detector according to claim 1, characterized in that: The detector N + Substrate (1) refers to a doping concentration range of 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer; The heavily doped N + Layer (31) refers to a doping concentration range of 5×10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 The N-type semiconductor layer; the lightly doped P - Layer (33) refers to a doping concentration range of 1×10 15 cm -3 Up to 5×10 16 cm -3 The P-type semiconductor layer; the heavily doped P + Layer (34) refers to a doping concentration range of 5 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 P-type semiconductor layer; The radial dimension of the horizontal cross-section of the semiconductor vertical line structure (3) is greater than or equal to 10 nm and less than or equal to 10 μm.

3. The quantum dot-vertical avalanche diode single-photon detector according to claim 1, characterized in that: The height of the passivation layer (6) extending from the top of the quantum dot-vertical line unit is greater than or equal to 10 nm and less than or equal to 1 μm.

4. The quantum dot-vertical-line avalanche diode single-photon detector according to any one of claims 1 to 3, characterized in that: The detector N + The substrate (1) and the semiconductor vertical line structure (3) are made of silicon, germanium, or group III-V semiconductor materials; The quantum dot material layer (5) is made of lead sulfide, indium phosphide, cadmium selenide or indium arsenide; The passivation layer (6) is made of benzocyclobutene, SU-8 resin or spin-coated glass.

5. The quantum dot-vertical avalanche diode single-photon detector according to claim 4, characterized in that: The front electrode (7) is made of a transparent conductive film; The material of the back electrode (2) is a metallic material.

6. A method for fabricating a quantum dot-vertical-line avalanche diode single-photon detector, characterized in that, Includes the following steps: Step 1: Based on the size and material requirements of the quantum dot-vertical linear avalanche diode single-photon detector to be fabricated, prepare detector N. + Substrate (1); Step 2: The detector N prepared in step 1 + On the upper surface of substrate (1), heavily doped N₂ is epitaxially grown sequentially from bottom to top. + Layer (31), undoped type I layer (32), lightly doped P - Layer (33) and heavily doped P + Layer (34); Step 3: After the heavy doped P has been grown on the upper surface in step 2 + Detector N of layer (34) + On the lower surface of the substrate (1), a back electrode (2) is grown; Step 4: The heavily doped P grown in step 2 of step 3 after the back electrode (2) has been grown. + On the upper surface of layer (34), the semiconductor vertical line structure (3) region is defined by photolithography and etched. During etching, the heavily doped P grown in step 2 is etched. + Starting from the upper surface of layer (34), it passes through heavily doped P layers from top to bottom. + Layer (34), lightly doped P - Layer (33), undoped type I layer (32), heavily doped N + Layer (31), until it reaches detector N. + On the upper surface of substrate (1), an array of spaced cells is etched to grow on detector N. + Multiple semiconductor vertical line structures (3) on the upper surface of substrate (1); Step 5: On the outer surface of each of the semiconductor vertical line structures (3) obtained by etching in step 4, a porous nanomaterial layer (4) is grown to cover each of the semiconductor vertical line structures (3); the porous nanomaterial layer (4) is made of porous graphene material; Step 6: On the outer surface of the porous nanomaterial layer (4) corresponding to each semiconductor vertical line structure (3) after the porous nanomaterial layer (4) has been grown on the outer surface in step 5, a quantum dot material layer (5) is coated to cover the porous nanomaterial layer (4), resulting in an array spaced arrangement on the detector N. + Multiple quantum dot-vertical line units on the upper surface of substrate (1); Step 7: The gap positions between each quantum dot-vertical line unit obtained in step 6 and the outer ring positions surrounding all quantum dot-vertical line units are coated with passivation material and heat-treated to form a thermosetting polymer, i.e., a passivation layer (6). Step 8: Use an etching process to remove excess passivation material on the passivation layer (6) formed in step 7 to expose the top of each quantum dot-vertical line unit obtained in step 6; then grow a front electrode (7) on the outer surface of the protruding portion of the top of each quantum dot-vertical line unit extending from the upper surface of the passivation layer (6); complete the fabrication of the quantum dot-vertical line avalanche diode single-photon detector.

7. The method for fabricating a quantum dot-vertical-line avalanche diode single-photon detector according to claim 6, characterized in that: In step 2, the detector N prepared in step 1... + On the upper surface of substrate (1), heavily doped N₂ is epitaxially grown sequentially from bottom to top. + Layer (31), undoped type I layer (32), lightly doped P - Layer (33) and heavily doped P + When growing layer (34), the growth method is either chemical vapor deposition or molecular beam epitaxy.

8. The method for fabricating a quantum dot-vertical-line avalanche diode single-photon detector according to claim 7, characterized in that: In step 5, when growing the porous nanomaterial layer (4), the growth method is pulsed laser deposition, chemical vapor deposition or electrolytic corrosion.

9. The method for fabricating a quantum dot-vertical-line avalanche diode single-photon detector according to claim 8, characterized in that: In step 6, when coating the quantum dot material layer (5), the coating is carried out by spin coating or spray coating.

10. The method for fabricating a quantum dot-vertical-line avalanche diode single-photon detector according to claim 9, characterized in that: In step 3, when growing the back electrode (2), the growth method is either magnetron sputtering or electron beam evaporation; In step 8, when growing the front electrode (7), the growth method is magnetron sputtering.

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