Display panel

Abstract

A display panel is provided. The display panel includes: a base layer including a light emitting region and a non-light emitting region adjacent to the light emitting region; a light emitting element including a first electrode disposed in the light emitting region, a second electrode disposed on the first electrode, and a light emitting pattern disposed between the first electrode and the second electrode; and a partition wall including a lower layer disposed in the non-light emitting region and an upper layer disposed on the lower layer. The second electrode contacts a side surface of the lower layer, and the lower layer includes a plurality of layers including different metals.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0123854, filed on September 18, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a display panel, and more particularly, to a display panel having improved reliability and enhanced visibility. Background Art

[0003] The display device is activated according to an electrical signal. The display device may include a display panel that displays an image. Among display panels, an organic light emitting display panel has low power consumption, high brightness, and fast response speed.

[0004] Among display panels, an organic light emitting display panel includes an anode, a cathode, and a light emitting layer. The light emitting layer is separated for each of the light emitting regions, and the cathode provides a common voltage for each of the light emitting regions. Summary of the invention

[0005] An aspect of the present disclosure provides a display panel that forms a light emitting element without using a metal mask while having improved display efficiency and improved electrical reliability.

[0006] According to an embodiment, a display panel includes: a base layer including a light-emitting area and a non-light-emitting area adjacent to the light-emitting area; a light-emitting element including a first electrode arranged in the light-emitting area, a second electrode arranged on the first electrode, and a light-emitting pattern arranged between the first electrode and the second electrode; and a partition wall including a lower layer arranged in the non-light-emitting area and an upper layer arranged on the lower layer, wherein the second electrode contacts a side surface of the lower layer, and the lower layer includes a plurality of layers including different metals.

[0007] The lower layer may include a first layer, a second layer, a third layer, a fourth layer, and a fifth layer sequentially stacked, and a contact resistance of the second layer and the fourth layer with the upper layer may be lower than a contact resistance of the first layer, the third layer, and the fifth layer with the upper layer.

[0008] The first layer, the third layer, and the fifth layer may each include aluminum, and the second layer and the fourth layer may each include any one of molybdenum and a molybdenum alloy.

[0009] The molybdenum alloy may include molybdenum, nickel, and titanium.

[0010] The content of nickel and titanium may be no greater than 50% of the total weight of the molybdenum alloy.

[0011] The thickness of the lower layer can be 5000 angstroms to And the thickness of the upper layer can be to

[0012] The thickness of the first layer, the third layer and the fifth layer may be to And the thickness of the second layer and the fourth layer can be to

[0013] The upper layer may include titanium.

[0014] Side surfaces of the first to fifth layers may be aligned with each other.

[0015] Side surfaces of the second layer and the fourth layer may each protrude further than the first layer, the third layer, and the fifth layer in a direction facing the light emitting region.

[0016] The second electrode may contact the second layer and may expose the fourth layer.

[0017] The second electrode may be spaced apart from the second layer and may contact the fourth layer.

[0018] The second electrode may contact the second layer and the fourth layer.

[0019] A side surface of the upper layer may protrude further than a side surface of the lower layer in a direction facing the light emitting region.

[0020] The display panel may further include a pixel defining layer disposed on the base layer and defined by the pixel defining layer with an opening exposing at least a portion of the first electrode, the pixel defining layer may include an inorganic material, and the lower layer may be disposed on the pixel defining layer.

[0021] The partition wall may define a partition wall opening overlapping the opening.

[0022] The display panel may further include an encapsulation layer including a lower inorganic layer covering the light emitting element and the partition wall, an upper inorganic layer disposed on the lower inorganic layer, and an organic layer disposed between the lower and upper inorganic layers and in the partition wall opening.

[0023] The display panel may further include a dummy pattern disposed on the upper layer and including the same material as that of at least one of the light emitting pattern and the second electrode, and the dummy pattern may be covered by the lower inorganic layer.

[0024] A dummy groove exposing an upper surface of the upper layer may be defined by the dummy pattern, and the organic layer may contact the upper surface of the upper layer.

[0025] The display panel may also include a transistor, a connecting electrode, an auxiliary electrode, an interlayer insulating layer, a pixel defining layer and an auxiliary connecting electrode, the transistor is arranged on the base layer, the connecting electrode connects the transistor and the first electrode, the auxiliary electrode is arranged on the same layer as the connecting electrode, the interlayer insulating layer covers the connecting electrode and the auxiliary electrode and the first electrode is arranged thereon, an opening exposing at least a portion of the first electrode is defined by the pixel defining layer, the auxiliary connecting electrode is arranged on the interlayer insulating layer and is connected to the auxiliary electrode through a contact hole defined in the interlayer insulating layer, and the lower layer may be arranged on the auxiliary connecting electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0027] Figure 1A is a perspective view of a display device according to an embodiment of the present disclosure.

[0028] Figure 1B is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0030] Figure 3A is a plan view of a display panel according to an embodiment of the present disclosure.

[0031] Figure 3B is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0032] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to an embodiment of the present disclosure.

[0033] Figure 5 is along Figure 4 A cross-sectional view taken along line II'.

[0034] Figure 6 is a cross-sectional view showing a portion of a partition wall according to an embodiment of the present disclosure.

[0035] Figure 7 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0036] Fig. 8A is a cross-sectional view showing a portion of a partition wall according to another embodiment of the present disclosure.

[0037] Figure 8B is a cross-sectional view showing a portion of a partition wall according to still another embodiment of the present disclosure.

[0038] Figure 8C is a cross-sectional view showing a portion of a partition wall according to still another embodiment of the present disclosure.

[0039] 9A to 9E is a cross-sectional view illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In the specification, when it is mentioned that a component (or a region, layer, portion or the like) is "arranged on", "connected to" or "coupled to" another component, it means that the former component may be directly arranged on, directly connected to or directly coupled to the latter component, or a third component may be arranged between the components.

[0041] The same reference numerals represent the same components. In addition, in the drawings, the thickness, proportion, and size of the components are exaggerated for the effective description of the technical content. The term "and / or" includes one or more combinations that can be defined by the associated components.

[0042] When describing various components, terms such as "first" and "second" may be used, but the present disclosure is not limited by these terms. These terms are only used to distinguish components. For example, a first component may be named a second component, and similarly, a second component may be named a first component without departing from the scope of the present disclosure. Unless the context clearly indicates an exception, a singular expression includes a plural expression.

[0043] In addition, terms such as "lower", "below", "upper", and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described with respect to the directions indicated in the drawings.

[0044] When terms such as “include” and / or “comprising” are used in the specification, it should be understood that they specify the presence of the above-mentioned features, numbers, steps, operations, components, parts and / or their combinations, and do not exclude the presence or addition of one or more other features, numbers, steps, operations, components, parts and / or their combinations.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant technology, and should not be interpreted as an idealized or overly formal meaning unless explicitly defined as such in this article.

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0047] Figure 1A is a perspective view of a display device according to an embodiment of the present disclosure. Figure 1B is an exploded perspective view of a display device according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0048] In the embodiment, the display device DD may be a component included in a large electronic device such as a television, a monitor, or an outdoor advertising panel. In addition, the display device DD may be a component included in a medium / small electronic device such as a personal computer (such as a notebook computer and a tablet computer), a personal digital terminal, a vehicle navigation unit, a game console, a smart phone, and a camera. They are only proposed as embodiments, and may also be adopted as other display devices as long as they do not deviate from the concept of the present disclosure. In the embodiment, it is exemplarily shown that the display device DD is a smart phone.

[0049] Reference Figure 1A , Figure 1B and Figure 2 , the display device DD may display an image IM toward a third direction DR3 on a display surface FS parallel to the first direction DR1 and the second direction DR2. The image IM may include a still image and a dynamic image. Figure 1A A watch window and an icon are shown as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0050] In an embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of the member are defined with reference to the direction in which the image IM is displayed. The front surface and the rear surface may face each other in the third direction DR3, and the normal directions of the front surface and the rear surface may be parallel to the third direction DR3. On the other hand, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be converted to other directions. In the specification, the expression "on a plane" may mean when observed in the third direction DR3.

[0051] like Figure 1B As shown in FIG. 1 , the display device DD according to the embodiment may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to constitute the appearance of the display device DD.

[0052] The window WP may include an optically transparent insulating material. In an embodiment, for example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. In an embodiment, for example, the transmission area TA may have a visible light transmittance of about 90% or more.

[0053] The frame area BZA may be a region whose light transmittance is lower than the light transmittance of the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and may surround the transmission area TA. On the other hand, this is shown exemplarily, and in the window WP according to an embodiment of the present disclosure, the frame area BZA may be omitted. The window WP according to the embodiment may include at least one functional layer of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to any one embodiment.

[0054] The display module DM may be arranged under the window WP. The display module DM may be a configuration that substantially generates an image IM. The image IM generated by the display module DM is displayed on the display surface IS of the display module DM and is observed by a user from the outside through the transmission area TA.

[0055] The display module DM includes a display area DA and a non-display area NDA. The display area DA may be an area activated according to an electrical signal. The non-display area NDA is adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA is an area covered by the frame area BZA and cannot be observed from the outside.

[0056] like Figure 2 As shown in , the display module DM according to the embodiment may include a display panel DP and an input sensor INS. Although not shown separately, the display device DD according to the embodiment of the present disclosure may further include a protection member arranged on the lower surface of the display panel DP or an anti-reflection member and / or a window member arranged on the upper surface of the input sensor INS.

[0057] The display panel DP may be a light-emitting display panel, and is not particularly limited thereto. In an embodiment, for example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel includes an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel includes quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0058] The display panel DP may include a base layer BL, a circuit element layer DP-CL arranged on the base layer BL, a display element layer DP-OLED, and an encapsulation layer TFE. The input sensor INS may be directly arranged on the encapsulation layer TFE. In the specification, the statement "configuration "A" is directly arranged on configuration "B"" means that no adhesive layer is arranged between configuration "A" and configuration "B".

[0059] The base layer BL may include at least one plastic film. The base layer BL is a flexible plate or a rigid plate, and may include a plastic plate, a glass plate, a metal plate, or an organic / inorganic composite material plate. In the specification, it may be considered that the display area DA and the non-display area NDA are defined in the base layer BL, and then, it may also be considered that the configuration arranged on the base layer BL is arranged to overlap with the display area DA or the non-display area NDA.

[0060] The circuit element layer DP-CL includes at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines and driving circuits for pixels.

[0061] The circuit element layer DP-CL may be formed by common processes for manufacturing circuit elements by forming insulating layers, semiconductor layers and conductive layers through schemes such as coating or deposition, selectively patterning the insulating layers, semiconductor layers and conductive layers through photolithography and etching processes, and forming semiconductor patterns, conductive patterns and signal lines.

[0062] The display element layer DP-OLED includes a conductive partition wall and a light emitting element. The light emitting element may include an anode (first electrode), a light emitting pattern and a cathode (second electrode), and the light emitting pattern may include at least a functional layer.

[0063] The encapsulation layer TFE includes a plurality of thin films. Some of the thin films may be arranged on corresponding pixels and have a specific thickness to improve optical efficiency. In addition, some of the thin films are arranged to protect the light-emitting elements.

[0064] The input sensor INS acquires coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single layer or multiple layers of conductive layers. The input sensor INS may include a single layer or multiple layers of insulating layers. For example, the input sensor INS may sense the external input through a capacitive scheme.

[0065] In the present disclosure, the scheme of operating the input sensor INS is not particularly limited, and in an embodiment of the present disclosure, the input sensor INS may sense external input in an electromagnetic induction scheme or a pressure sensitive scheme. On the other hand, in another embodiment of the present disclosure, the input sensor INS may be omitted.

[0066] like Figure 1B As shown in , the housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a specific inner space. The display module DM may be accommodated in the inner space.

[0067] The housing HAU may include a material having relatively high rigidity. In an embodiment, for example, the housing HAU may include a plurality of frames and / or plates including glass, plastic, or metal or a combination thereof. The housing HAU may stably protect the configuration of the display device DD housed in the internal space from external impact.

[0068] Figure 3A is a plan view of a display panel according to an embodiment of the present disclosure. Figure 3B is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure. As used herein, a "plan view" is a diagram of a base layer BL (see Figure 2 ) in the thickness direction (i.e., the third direction DR3).

[0069] Reference Figure 3A In the display panel DP, a display area DA and a non-display area NDA around the display area DA may be defined. The display area DA and the non-display area NDA may be classified according to whether the pixels PX are arranged. The pixels PX may be arranged in the display area DA. The scanning driving part SDV, the data driving part, and the light emitting driving part EDV may be arranged in the non-display area NDA. The data driving part may be a partial circuit arranged in the driver IC DIC.

[0070] The display panel DP may include pixels PX, initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, data lines DL1 to DLn, first and second control lines CSL1 and CSL2, driving voltage lines PL, and a plurality of pads PD. Here, "m" and "n" are natural numbers of 2 or more.

[0071] The pixels PX may be connected to initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, and data lines DL1 to DLn.

[0072] The initialization scan lines GIL1 to GILm, the compensation scan lines GCL1 to GCLm, the write scan lines GWL1 to GWLm, and the black scan lines GBL1 to GBLm may extend in the first direction DR1 and may be electrically connected to the scan driving part SDV. The data lines DL1 to DLn may extend in the second direction DR2 and may be electrically connected to the driver IC DIC. The light emission control lines ECL1 to ECLm may extend in the first direction DR1 and may be electrically connected to the light emission driving part EDV.

[0073] The driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be arranged at different layers. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0074] The first control line CSL1 may be connected to the scan driving part SDV, and the second control line CSL2 may be connected to the light emitting driving part EDV.

[0075] The driver IC DIC, the driving voltage line PL, the first control line CSL1 and the second control line CSL2 may be electrically connected to the pad PD. The flexible circuit film FCB may be electrically connected to the pad PD through an anisotropic conductive adhesive layer. The pad PD may be a pad for connecting the flexible circuit film FCB to the display panel DP. The pad PD may be connected to the corresponding pixel PX through the driving voltage line PL, the first control line CSL1 and the second control line CSL2.

[0076] In addition, the pads PD may also include input pads. The input pads may be used to connect the flexible circuit film FCB to the input sensor INS (see Figure 2 However, the present disclosure is not limited thereto, and in another embodiment, the input pad may be arranged on the input sensor INS (see Figure 2 ) and can be connected to pads PD and a separate circuit board. Alternatively, the input sensor INS (see Figure 2 ) may be omitted and the input pad may not be further included.

[0077] Figure 3B It is shown as an example Figure 3A 1 is an equivalent circuit diagram of one pixel PXij among the plurality of pixels PX. Since the plurality of pixels PX have the same circuit structure, the detailed description of the remaining pixels PX will be replaced by the description of the circuit structure of the pixel PXij.

[0078] Reference Figure 3A and Figure 3B, the pixel PXij is connected to the i-th data line DLi among the data lines DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th light emission control line ECLj among the light emission control lines ECL1 to ECLm, the first driving voltage line VL1 and the second driving voltage line VL2, and the first initialization voltage line VL3 and the second initialization voltage line VL4. "i" is an integer not less than 1 and not greater than "n", and "j" is an integer not less than 1 and not greater than "m".

[0079] The pixel PXij includes a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. As an example of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, and the present disclosure is not particularly limited thereto. The pixel circuit PDC may control the amount of current flowing through the light emitting element ED corresponding to the data signal Di. The light emitting element ED may emit light having a specific brightness corresponding to the amount of current provided from the pixel circuit PDC.

[0080] The pixel circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a first capacitor Cst, a second capacitor Cbst, and a third capacitor Nbst. According to the present disclosure, the configuration of the pixel circuit PDC is not limited to Figure 3B The embodiment shown in . Figure 3B The pixel circuit PDC shown in FIG. 1 is merely an example, and the configuration of the pixel circuit PDC may be modified to perform.

[0081] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having a low temperature polycrystalline silicon ("LTPS") semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having an oxide semiconductor layer. In an embodiment, for example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be LTPS transistors.

[0082] Since the first transistor T1 can directly affect the brightness of the light emitting element ED, when the first transistor T1 includes a semiconductor layer including polysilicon with high reliability, a high-resolution display device can be implemented. In addition, when at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 includes an oxide semiconductor, the amount of leakage current that may flow to the gate electrode of the first transistor T1 can be reduced, and power consumption can be reduced.

[0083] Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the rest may be N-type transistors. In an embodiment, for example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0084] The configuration of the pixel circuit PDC according to the present disclosure is not limited to Figure 3B The embodiment shown in . Figure 3B The pixel circuit PDC shown in is only an example, and the configuration of the pixel circuit PDC may be modified to perform. In an embodiment, for example, all of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors or N-type transistors. In addition, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be P-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be N-type transistors.

[0085] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj can transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a signal similar to that input to the display device DD (see Figure 1A )’s image signal corresponding to the voltage level.

[0086] The first and second driving voltage lines VL1 and VL2 may transmit the first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 may transmit the first and second initialization voltages VINT and VAINT to the pixels PXij, respectively.

[0087] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or referred to as an anode) of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the first capacitor Cst. The first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DLi according to the switching operation of the second transistor T2, and supply the driving current to the light emitting element ED.

[0088] The second transistor T2 may be connected to the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 may be turned on according to the j-th write scan signal GWj received through the j-th write scan line GWLj, and may transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst may be connected to the third electrode of the second transistor T2, and the opposite end of the second capacitor Cbst may be connected to the first node N1.

[0089] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the jth compensation scan line GCLj. The third transistor T3 may be turned on according to the jth compensation scan signal GCj transmitted through the jth compensation scan line GCLj, and may connect the third electrode of the first transistor T1 and the second electrode of the first transistor T1 to connect the first transistor T1 in a diode manner. One end of the third capacitor Nbst may be connected to the third electrode of the third transistor T3, and the opposite end of the third capacitor Nbst may be connected to the first node N1.

[0090] The fourth transistor T4 is connected between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 transmitting the first initialization voltage VINT, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line GILj. The fourth transistor T4 is turned on according to the j-th initialization scan signal GIj received through the j-th initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1, and initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0091] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th light emitting control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode (e.g., the second node N2) of the light emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th light emitting control line ECLj.

[0092] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the jth emission control signal EMj received through the jth emission control line ECLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 can be transmitted to the light emitting element ED through the sixth transistor T6 after being compensated by the diode-connected first transistor T1.

[0093] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 transmitting a second initialization voltage VAINT, a second electrode connected to a second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to a j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level lower than that of the first initialization voltage VINT.

[0094] One end of the first capacitor Cst may be connected to the third electrode of the first transistor T1, and the opposite end of the first capacitor Cst may be connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than that of the first driving voltage ELVDD.

[0095] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to an embodiment of the present disclosure. Figure 4 The display module DM (see Figure 2 ) of the display surface IS (see Figure 1B ) is a plane of the display module DM observed from the top, and the arrangement of the light emitting areas PXA-R, PXA-G and PXA-B is shown.

[0096] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may correspond in a one-to-one relationship to the Figure 5 The first light emitting opening OP1 -E, the second light emitting opening OP2 -E, and the third light emitting opening OP3 -E defined in the pixel defining layer PDL described in FIG.

[0097] Reference Figure 4 , the display area DA may include a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B, and a non-light emitting area NPXA surrounding the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B. The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may correspond to the light emitting elements ED1, ED2, and ED3 (see Figure 5 ) provided by the light. The first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B may be arranged according to the direction toward the display module DM (see Figure 2 )’s external emitted light color classification.

[0098] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may respectively provide first to third color lights having different colors. In an embodiment, for example, the first color light may have red, the second color light may have green, and the third color light may have blue. However, examples of the first to third color lights are not limited to this example.

[0099] The non-luminescent area NPXA can set the boundaries of the first luminescent area PXA-R, the second luminescent area PXA-G and the third luminescent area PXA-B, and since a structure including a light-shielding material is arranged at the portion overlapping with the non-luminescent area NPXA, the color mixing of the first luminescent area PXA-R, the second luminescent area PXA-G and the third luminescent area PXA-B can be prevented.

[0100] The number of each of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be plural, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be repeatedly arranged while having a specific arrangement form. In an embodiment, for example, the first light emitting region PXA-R and the third light emitting region PXA-B may be alternately arranged along the first direction DR1 to constitute a "first group". The second light emitting region PXA-G may be arranged along the first direction DR1 to constitute a "second group". The number of each of the "first group" and the "second group" may be plural, and the first group and the second group may be alternately arranged along the second direction DR2. One second light emitting region PXA-G may be arranged to be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0101] on the other hand, Figure 4 The arrangement form of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B is exemplarily shown, and the present disclosure is not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be arranged in various forms. Figure 4 As shown in FIG. 1 , the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have Alternatively, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have a stripe arrangement form or a diamond arrangement form. Layout form.

[0102] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have various shapes on a plane. In an embodiment, for example, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have a shape such as a polygonal shape, a circular shape, or an elliptical shape. Figure 4 It is exemplarily shown that the first and third light emitting regions PXA-R and PXA-B have a rectangular shape (or a diamond shape) and the second light emitting region PXA-G has an octagonal shape in a plan view.

[0103] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same shape in a plan view, or at least some of them may have different shapes. Figure 4The first and third light emitting regions PXA-R and PXA-B having the same shape in a plan view and the second light emitting region PXA-G having a shape different from those of the first and third light emitting regions PXA-R and PXA-B are exemplarily shown.

[0104] At least some of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have different areas in a plan view. In an embodiment, the area of ​​the first light emitting region PXA-R emitting red light may be larger than the area of ​​the second light emitting region PXA-G emitting green light, and may be smaller than the area of ​​the third light emitting region PXA-B emitting blue light.

[0105] However, the size relationship between the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B depending on the light emitting color is not limited thereto, and may be different depending on the display module DM (see Figure 2 ). In addition, the present disclosure is not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same area in a plan view.

[0106] Because the first light-emitting region PXA-R, the second light-emitting region PXA-G and the third light-emitting region PXA-B form light of different wavelength bands, the first light-emitting region PXA-R, the second light-emitting region PXA-G and the third light-emitting region PXA-B require a separate inorganic layer that can optimize the light-emitting efficiency to match the corresponding wavelength to improve the efficiency of the light-emitting element.

[0107] On the other hand, the display module DM (see Figure 2 The shapes, areas, arrangements, etc. of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be determined according to the color of the emitted light or the display module DM (see Figure 2 ) size and configuration for various designs, and are not limited to Figure 4 The embodiment shown in .

[0108] Figure 5 is along Figure 4 A cross-sectional view taken along line II'. Figure 6 is a cross-sectional view showing a portion of a partition wall according to an embodiment of the present disclosure.

[0109] Reference Figure 5 According to an embodiment, the display module DM may include a display panel DP and an input sensor INS directly disposed on the display panel DP. The input sensor INS may correspond to Figure 2 The input sensor INS described in.

[0110] The display panel DP according to the embodiment may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and an encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2 and ED3, sacrificial patterns SP1, SP2 and SP3, a pixel defining layer PDL, a partition wall PW and a dummy pattern DMP.

[0111] The base layer BL may provide a base surface on which the circuit element layer DP-CL, the display element layer DP-OLED and the encapsulation layer TFE may be arranged. The base layer BL may be flexible or rigid. In an embodiment, for example, the base layer BL may include a synthetic resin film or any one of glass and metal. Figure 5 A single-layered base layer BL is illustrated, but the present disclosure is not limited thereto, and in another embodiment, the base layer BL may be provided as a multi-layer in which a plurality of organic layers and a plurality of inorganic layers are alternately arranged.

[0112] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a plurality of insulating layers and conductive patterns disposed between the plurality of insulating layers.

[0113] The circuit element layer DP-CL may include at least one transistor connected to each of the light emitting elements ED1, ED2, and ED3 included in the display element layer DP-OLED, and an insulating layer. The structure of the at least one transistor is not limited to any one as long as it is used to drive the pixel PX (see Figure 3A The insulating layer may be provided with a single layer including any one of an inorganic layer and an organic layer, or may be provided with a multilayer in which different inorganic layers are stacked, but the present disclosure is not limited thereto.

[0114] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. In the circuit element layer DP-CL, the light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3.

[0115] The first light emitting element ED1 may include a first anode AE1, a first light emitting pattern EP1, and a first cathode CE1, the second light emitting element ED2 may include a second anode AE2, a second light emitting pattern EP2, and a second cathode CE2, and the third light emitting element ED3 may include a third anode AE3, a third light emitting pattern EP3, and a third cathode CE3. In an embodiment, the first light emitting pattern EP1 may provide red light, the second light emitting pattern EP2 may provide green light, and the third light emitting pattern EP3 may provide blue light.

[0116] The first anode AE1, the second anode AE2, and the third anode AE3 may be individually patterned and may be spaced apart from each other. The first anode AE1, the second anode AE2, and the third anode AE3 may be conductive. In an embodiment, for example, the first anode AE1, the second anode AE2, and the third anode AE3 may be formed of various materials as long as the material is a conductive material such as a metal, a transparent conductive oxide ("TCO"), or a conductive polymer material.

[0117] Although it is shown that each of the first anode AE1, the second anode AE2, and the third anode AE3 has a single layer, this is exemplary, and each of the first anode AE1, the second anode AE2, and the third anode AE3 may have a multi-layer structure, and one of the first anode AE1, the second anode AE2, and the third anode AE3 may have a single-layer structure and the other may have a multi-layer structure, and the present disclosure is not limited to any one embodiment.

[0118] The first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may be arranged on the corresponding first anode AE1, the second anode AE2, and the third anode AE3, respectively. The first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may be patterned by a tip portion TIP defined in the partition wall PW. A hole control layer may also be arranged between each of the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 and the corresponding first anode AE1, the second anode AE2, and the third anode AE3. In addition, an electron control layer may also be arranged between each of the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 and the corresponding first cathode CE1, the second cathode CE2, and the third cathode CE3. An electron blocking layer may also be arranged between each of the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 and the corresponding first anode AE1, the second anode AE2, and the third anode AE3.

[0119] The first cathode CE1, the second cathode CE2, and the third cathode CE3 may provide a plurality of patterns spaced apart from each other. The first cathode CE1, the second cathode CE2, and the third cathode CE3 may be conductive. In an embodiment, for example, the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be formed of various materials as long as the material is a conductive material such as a metal, a transparent conductive oxide (TCO), or a conductive polymer material. The first cathode CE1, the second cathode CE2, and the third cathode CE3 may be patterned by a tip portion TIP defined by a partition wall PW.

[0120] The pixel defining layer PDL may be arranged on the circuit element layer DP-CL. In an embodiment, the pixel defining layer PDL may be an insulating film including an inorganic material. In an embodiment, for example, the pixel defining layer PDL may include silicon oxide, silicon nitride, or a combination thereof. According to an embodiment, the pixel defining layer PDL may have a two-layer structure in which a silicon oxide layer and a silicon nitride layer are sequentially stacked. However, this is an illustrative description, and when the pixel defining layer PDL may be an insulating film including an inorganic material, various changes may be made to the material and whether it is a single layer or a multilayer, and the present disclosure is not limited to any one embodiment.

[0121] In an embodiment, the pixel defining layer PDL may define a first light emitting opening OP1-E, a second light emitting opening OP2-E, and a third light emitting opening OP3-E therein. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The first light emitting region PXA-R may be defined as a region of the upper surface of the first anode AE1 exposed by the first light emitting opening OP1-E. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The second light emitting region PXA-G may be defined as a region of the upper surface of the second anode AE2 exposed by the second light emitting opening OP2-E. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3. The third light emitting region PXA-B may be defined as a region of the upper surface of the third anode AE3 exposed by the third light emitting opening OP3-E.

[0122] The display panel DP according to the embodiment may further include sacrificial patterns SP1, SP2, and SP3. The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3 may be arranged on edges of the corresponding first anode AE1, the second anode AE2, and the third anode AE3, respectively. The first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3 may be covered by the corresponding light emitting patterns EP1, EP2, and EP3 and the pixel defining layer PDL. The sacrificial patterns SP1, SP2, and SP3 may include an amorphous transparent conductive oxide.

[0123] The sacrificial patterns SP1, SP2, and SP3 may be formed by a wet etching process. The sacrificial patterns SP1, SP2, and SP3 may have an etching rate higher than that of the first anode AE1, the second anode AE2, and the third anode AE3. Thus, in an etching process of forming the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E in the pixel defining layer PDL, the sacrificial patterns SP1, SP2, and SP3 may prevent the first anode AE1, the second anode AE2, and the third anode AE3 from being etched together with the pixel defining layer PDL.

[0124] In an embodiment, the sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial opening OP1-S, a second sacrificial opening OP2-S, and a third sacrificial opening OP3-S, respectively. The first sacrificial opening OP1-S, the second sacrificial opening OP2-S, and the third sacrificial opening OP3-S may overlap with the corresponding first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, respectively, in a plan view. Each of the first sacrificial opening OP1-S, the second sacrificial opening OP2-S, and the third sacrificial opening OP3-S may expose at least a portion of a corresponding one of the first anode AE1, the second anode AE2, and the third anode AE3.

[0125] Each of the first sacrificial pattern SP1, the second sacrificial pattern SP2 and the third sacrificial pattern SP3 may be covered by a side surface of the pixel defining layer PDL that defines a corresponding one of the first light emitting opening OP1-E, the second light emitting opening OP2-E and the third light emitting opening OP3-E, a corresponding one of the first anode AE1, the second anode AE2 and the third anode AE3 and a corresponding one of the first light emitting pattern EP1, the second light emitting pattern EP2 and the third light emitting pattern EP3.

[0126] Each of the first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3 may include a transparent conductive oxide. The transparent conductive oxide may include indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide ("IGZO"), or aluminum zinc oxide.

[0127] In an embodiment, the partition wall PW may be disposed on the pixel defining layer PDL. The partition wall PW may overlap the non-light emitting area NPXA. The partition wall PW may include a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P.

[0128] The first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P may overlap with the corresponding first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B in a one-to-one relationship, respectively. Each of the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P may define an opening space that is integrated with the corresponding light emitting opening. Accordingly, the corresponding light emitting elements ED1, ED2, and ED3 may be arranged in the integrated partition wall openings OP1-P, OP2-P, and OP3-P and the light emitting openings OP1-E, OP2-E, and OP3-E. In addition, the integrated partition wall openings OP1-P, OP2-P, and OP3-P and the light emitting openings OP1-E, OP2-E, and OP3-E may expose portions of the corresponding anodes AE1, AE2, and AE3.

[0129] The partition wall PW according to the embodiment may include a lower layer L1 and an upper layer L2 disposed on the lower layer L1. The lower layer L1 may be disposed on the pixel defining layer PDL.

[0130] The lower layer L1 may include a conductive material. The lower layer L1 according to the present disclosure may be a multilayer in which different metal layers are stacked. In an embodiment, for example, the lower layer L1 may include a first layer AL1, a second layer MO1, a third layer AL2, a fourth layer MO2, and a fifth layer AL3 sequentially stacked on the pixel defining layer PDL. According to the present disclosure, the contact resistance between the second layer MO1 and the fourth layer MO2 and the upper layer L2 may be lower than the contact resistance between the first layer AL1, the third layer AL2, and the fifth layer AL3 and the upper layer L2.

[0131] The first layer AL1, the third layer AL2, and the fifth layer AL3 may include the same first material, and the second layer MO1 and the fourth layer MO2 may include the same second material, which is different from the first material. In an embodiment, for example, the first layer AL1, the third layer AL2, and the fifth layer AL3 may each include aluminum (Al), and the second layer MO1 and the fourth layer MO2 may each include any one of molybdenum (Mo) and a molybdenum alloy.

[0132] In the present disclosure, the molybdenum alloy may be molybdenum (Mo)-nickel (Ni)-titanium (Ti). According to an embodiment, the content of nickel (Ni)-titanium (Ti) in the total weight of the molybdenum (Mo)-nickel (Ni)-titanium (Ti) alloy may be 50% or less. When the content of nickel (Ni)-titanium (Ti) in the total weight of the molybdenum (Mo)-nickel (Ni)-titanium (Ti) alloy is greater than 50%, the contact resistance with the upper layer L2 may increase.

[0133] Reference Figure 6 , the total thickness of the lower layer L1 may not be less than and not greater than The total thickness of the upper layer L2 may not be less than and not greater than

[0134] The thickness of the first layer AL1, the third layer AL2 and the fifth layer AL3 in the lower layer L1 may be not less than and not greater than The thickness of the second layer MO1 and the fourth layer MO2 in the lower layer L1 may be not less than and not greater than

[0135] According to an embodiment, the thicknesses of the first layer AL1, the third layer AL2, and the fifth layer AL3 may be different from each other. In an embodiment, for example, the thickness A-T1 of the first layer AL1 may be The thickness A-T2 of the third layer AL2 may be And the thickness A-T3 of the fifth layer AL3 may be The thickness M-T1 of the second layer MO1 and the thickness M-T2 of the fourth layer MO2 may be respectively And the thickness of the upper layer L2 can be

[0136] In an embodiment, the upper layer L2 may include a metal or a non-metal. In an embodiment, for example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The non-metal may include silicon, silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, or a combination thereof, and the metal oxide may include a transparent conductive oxide (TCO).

[0137] According to the present disclosure, when the lower layer L1 includes only aluminum, the lower layer L1 may be oxidized, and thus the contact resistance with the upper layer L2 may be increased.

[0138] According to an embodiment, a side surface of the upper layer L2 further protrudes than a side surface of the lower layer L1 in a direction facing the light emitting regions PXA-R, PXA-G, and PXA-B. The side surface of the upper layer L2 further protruding than the side surface of the lower layer L1 may be defined as a tip portion TIP. Due to the difference between the etching rates of the lower layer L1 and the upper layer L2, the tip portion TIP defined by the partition wall PW may be formed in an undercut shape.

[0139] According to the present disclosure, anodes AE1, AE2 and AE3, light emitting patterns EP1, EP2 and EP3, and cathodes CE1, CE2 and CE3 included in the light emitting elements ED1, ED2 and ED3 may be individually patterned in corresponding partition wall openings OP1-P, OP2-P and OP3-P by tip portions TIP defined by the partition wall PW.

[0140] The first light emitting pattern EP1 and the first cathode CE1 may be arranged in the first partition wall opening OP1-P, the second light emitting pattern EP2 and the second cathode CE2 may be arranged in the second partition wall opening OP2-P, and the third light emitting pattern EP3 and the third cathode CE3 may be arranged in the third partition wall opening OP3-P. Each of the first cathode CE1, the second cathode CE2, and the third cathode CE3 may contact the side surface of the lower layer L1 defining the corresponding first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P.

[0141] like Figure 6 As shown in FIG. 1 , each of the first cathode CE1, the second cathode CE2, and the third cathode CE3 may contact the side surface of the first layer AL1 and the side surface of the second layer MO1 in the partition wall PW. The first cathode CE1, the second cathode CE2, and the third cathode CE3 may expose the side surfaces of the third layer AL2, the fourth layer MO2, and the fifth layer AL3.

[0142] In an embodiment, the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be physically separated from each other by the upper layer L2 forming the tip portion TIP and may be arranged in the corresponding first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P. Accordingly, the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be spaced apart from each other with the partition wall PW interposed therebetween. According to the present disclosure, the first cathode CE1, the second cathode CE2, and the third cathode CE3 may contact the lower layer L1 including the conductive material in the partition wall PW to be electrically connected to each other, thereby being provided with a common voltage.

[0143] The lower layer L1 may have a thickness greater than that of the upper layer L2. In an embodiment, the lower layer L1 has a conductivity and a thickness greater than those of the upper layer L2, respectively, and thus, reduces contact resistance with the first cathode CE1, the second cathode CE2, and the third cathode CE3. Accordingly, a common cathode voltage may be uniformly supplied to the light emitting regions PXA-R, PXA-G, and PXA-B.

[0144] According to the present disclosure, the light emitting patterns EP1, EP2, and EP3 can be sequentially patterned and deposited in units of pixels through the tip portion TIP defined by the partition wall PW. That is, the light emitting patterns EP1, EP2, and EP3 can be commonly formed on the entire surface of the base layer BL by using an open mask, and can be easily patterned and deposited in units of pixels through the partition wall PW.

[0145] On the other hand, when the light emitting pattern is patterned by using a fine metal mask ("FMM"), a separate supporting spacer protruding from the conductive partition wall must be provided to support the fine metal mask. In addition, the height of the partition wall and the spacer is separated from the base surface on which the fine metal mask is patterned, and there is a limitation in achieving high resolution. In addition, since the fine metal mask is in contact with the spacer, foreign matter may remain in the spacer after the process of patterning the light emitting pattern, or the spacer may be imprinted and damaged by the fine metal mask. Accordingly, a defective display panel may be formed.

[0146] According to the present embodiment, since it includes a partition wall PW containing a conductive material, the light emitting elements ED1, ED2, and ED3 can be easily physically separated from each other. Accordingly, current leakage or driving errors between adjacent light emitting regions PXA-R, PXA-G, and PXA-B can be prevented, and the light emitting elements ED1, ED2, and ED3 can be driven independently.

[0147] Specifically, since the display area DA (see Figure 2 ), the light emitting patterns EP1, EP2, and EP3 are sequentially patterned in the case of a mask with internal configuration contacts in the display panel DP, thereby providing a display panel DP with reduced defect rate and improved process reliability. In addition, since patterning can be performed even without providing a separate supporting spacer protruding from the partition wall PW, the areas of the light emitting regions PXA-R, PXA-G, and PXA-B can be minimized, and thus a display panel DP that can easily achieve high resolution can be provided.

[0148] Furthermore, when manufacturing a large-area display panel DP, process costs may be reduced by omitting production of a large-area mask, and the process may not be affected by defects that may occur in the large-area mask, and thus a display panel DP having improved reliability may be provided.

[0149] Refer again Figure 5 , the display panel DP according to the embodiment may further include cover patterns CP1, CP2, and CP3. The cover patterns CP1, CP2, and CP3 may include a first cover pattern CP1, a second cover pattern CP2, and a third cover pattern CP3.

[0150] The first, second, and third cover patterns CP1, CP2, and CP3 are disposed on corresponding first, second, and third cathodes CE1, CE2, and CE3, and may be disposed in the first, second, and third partition wall openings OP1-P, OP2-P, and OP3-P.

[0151] The first, second and third covering patterns CP1, CP2 and CP3 may be directly disposed on the corresponding cathodes CE1, CE2 and CE3 to protect the first, second and third cathodes CE1, CE2 and CE3 in subsequent processes. Each of the first, second and third covering patterns CP1, CP2 and CP3 may include an organic material.

[0152] The display panel DP according to the embodiment may further include a dummy pattern DMP. The dummy pattern DMP may include a first dummy pattern DMP1 and a second dummy pattern DMP2.

[0153] The first dummy pattern DMP1 may be disposed on the partition wall PW adjacent to the first light emitting element ED1, and the second dummy pattern DMP2 may be disposed on the partition wall PW adjacent to the second light emitting element ED2 and the third light emitting element ED3. According to one embodiment, a dummy groove RC may be defined by the dummy pattern DMP. The dummy groove RC may expose the upper surface LU of the partition wall PW overlapping the non-light emitting area NPXA.

[0154] In an embodiment, for example, an upper surface LU of a partition wall PW arranged between the first light emitting element ED1 and the second light emitting element ED2 may be exposed by a dummy groove RC defined between the first dummy pattern DMP1 and the second dummy pattern DMP2, and an upper surface LU of a partition wall PW arranged between the second light emitting element ED2 and the third light emitting element ED3 may be exposed by a dummy groove RC defined between adjacent second dummy patterns DMP2.

[0155] According to embodiments, the thickness of the second dummy pattern DMP2 may be greater than the thickness of the first dummy pattern DMP1 .

[0156] Each of the first dummy pattern DMP1 and the second dummy pattern DMP2 may include a first layer D-ED, a second layer D-CE, and a third layer D-CP. The second dummy pattern DMP2 may further include an additional layer D-CL disposed between the partition wall PW and the first layer D-ED. The first layer D-ED may include the same material as the material of the light emitting pattern included in the adjacent light emitting element. The second layer D-CE may include the same material as the material of the first cathode CE1, the second cathode CE2, and the third cathode CE3. The third layer D-CP may include the same material as the material of the first covering pattern CP1, the second covering pattern CP2, and the third covering pattern CP3. The additional layer D-CL may include an inorganic material.

[0157] The first dummy pattern DMP1 and the second dummy pattern DMP2 may define therein a first dummy opening OP1-D, a second dummy opening OP2-D, and a third dummy opening OP3-D corresponding to the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E. The first dummy opening OP1-D may be defined by an inner surface of the first dummy pattern DMP1 adjacent to the first light emitting element ED1, the second dummy opening OP2-D may be defined by an inner surface of the second dummy pattern DMP2 adjacent to the second light emitting element ED2, and the third dummy opening OP3-D may be defined by the second dummy pattern DMP2 adjacent to the third light emitting element ED3.

[0158] The encapsulation layer TFE according to an embodiment may include a lower inorganic layer LIL, an organic layer OL, and an upper inorganic layer UIL.

[0159] The lower inorganic layer LIL is arranged on the display element layer DP-OLED and may cover the light emitting elements ED1, ED2, and ED3. The lower inorganic layer LIL may include any one of silicon oxynitride and silicon nitride. The lower inorganic layer LIL may protect the light emitting elements ED1, ED2, and ED3 from moisture and / or oxygen. The lower inorganic layer LIL may be penetrated at a portion that overlaps with the dummy groove RC in a plan view by an etching process. Accordingly, the lower inorganic layer LIL may expose an upper surface LU of the partition wall PW that overlaps with the dummy groove RC in a plan view.

[0160] The organic layer OL may be disposed on the lower inorganic layer LIL. The organic layer OL may protect the light emitting elements ED1, ED2, and ED3 from foreign matter such as dust particles. The organic layer OL may include an acrylic-based organic layer, but the present disclosure is not limited thereto. The organic layer OL may contact the upper surface LU of the partition wall PW exposed from the dummy groove RC.

[0161] The upper inorganic layer UIL is disposed on the organic layer OL. The upper inorganic layer UIL may include any one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0162] The display module DM according to the embodiment may include an input sensor INS. The input sensor INS may be arranged on the display panel DP. The input sensor INS may include at least one conductive layer and at least one insulating layer. In the embodiment, the input sensor INS may include a first sensing insulating layer TIL1, a first conductive layer TML1, a second sensing insulating layer TIL2, a second conductive layer TML2, and a third sensing insulating layer TIL3.

[0163] The first sensing insulating layer TIL1 may be directly disposed on the upper inorganic layer UIL. The first conductive layer TML1 is disposed on the first sensing insulating layer TIL1. The second sensing insulating layer TIL2 covers the first conductive layer TML1 and is disposed on the first sensing insulating layer TIL1. The second conductive layer TML2 is disposed on the second sensing insulating layer TIL2. The third sensing insulating layer TIL3 covers the second conductive layer TML2 and is disposed on the second sensing insulating layer TIL2. The first conductive layer TML1 and the second conductive layer TML2 may overlap with the non-light emitting area NPXA. Accordingly, the first conductive layer TML1 and the second conductive layer TML2 may overlap with the partition wall PW in a plan view.

[0164] The first, second, and third sensing insulating layers TIL1, TIL2, and TIL3 may be inorganic layers including at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0165] Each of the first conductive layer TML1 and the second conductive layer TML2 may have a single layer structure or a multilayer structure stacked along the third direction DR3. The second conductive layer TML2 may include a conductive line defining a mesh electrode. At least one of the conductive patterns of the first conductive layer TML1 and the conductive patterns of the second conductive layer TML2 may be connected to each other through a contact hole passing through the second sensing insulating layer TIL2.

[0166] The first conductive layer TML1 and the second conductive layer TML2 of the single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper or aluminum or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide, indium zinc oxide, zinc oxide or indium zinc tin oxide. In addition, the transparent conductive layer may include a conductive polymer (such as PEDOT), a metal nanowire and graphene.

[0167] The first conductive layer TML1 and the second conductive layer TML2 of the multilayer structure may include a plurality of metal layers. The plurality of metal layers may have, for example, a three-layer structure of titanium / aluminum / titanium. The first conductive layer TML1 and the second conductive layer TML2 of the multilayer structure may include at least one metal layer and at least one transparent conductive layer. The second sensing insulating layer TIL2 may be arranged between the first conductive layer TML1 and the second conductive layer TML2.

[0168] The display module DM according to the embodiment may further include an anti-reflection layer arranged on the input sensor INS. The anti-reflection layer may further include a light shielding layer overlapping the non-luminous area NPXA and containing a light absorbing material and a color filter corresponding to the luminous areas PXA-R, PXA-G and PXA-B. The light shielding layer is a layer having a black color, and in an embodiment, the light shielding layer may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black or a metal such as chromium or an oxide thereof.

[0169] Figure 7 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0170] The display panel DP-a according to the embodiment may include a base layer BL, insulating layers 10, 20, 30, 40, 50 arranged on the base layer BL, a transistor TR, a shielding electrode BML, connection electrodes CNP1 and CNP2, an auxiliary electrode SP, an auxiliary connection electrode SS, a partition wall PW-a, a pixel defining layer PDL and a light emitting element ED.

[0171] The base layer BL may be flexible or rigid. In an embodiment, for example, the base layer BL may include a synthetic resin film or any one of glass and metal. Figure 7 A single-layered base layer BL is illustrated, but the present disclosure is not limited thereto, and in another embodiment, the base layer BL may be provided as a multi-layer in which a plurality of organic layers and a plurality of inorganic layers are alternately arranged.

[0172] The first insulating layer 10 (i.e., barrier layer) may be disposed on the base layer BL. The first insulating layer 10 prevents the introduction of foreign matter from the outside. The first insulating layer 10 may include at least one inorganic layer. The first insulating layer 10 may include a silicon oxide layer and a silicon nitride layer. Each of these layers may be provided in plural, and a plurality of silicon oxide layers and a plurality of silicon nitride layers may be alternately stacked.

[0173] The shielding electrode BML may be arranged on the first insulating layer 10. The shielding electrode BML may be arranged to overlap the semiconductor pattern SC of the transistor TR in a plan view. The shielding electrode BML may include a metal. In an embodiment, for example, the shielding electrode BML may include a first layer arranged on the base layer BL and a second layer arranged on the first layer. The first layer may include aluminum and the second layer may include titanium.

[0174] The shielding electrode BML may block external light from reaching the transistor TR. In an embodiment of the present disclosure, the shielding electrode BML may be a floating electrode isolated from other electrodes or wirings.

[0175] According to an embodiment, the shielding electrode BML may receive a bias voltage. The shielding electrode BML may receive a first power supply voltage. The shielding electrode BML may block a potential generated by polarization from affecting the transistor TR. In an embodiment of the present disclosure, the shielding electrode BML may be connected to a portion of the semiconductor pattern SC through the first connection electrode CNP1.

[0176] The second insulating layer 20 covers the shielding electrode BML and may be disposed on the first insulating layer 10. The second insulating layer 20 may prevent metal atoms or impurities from diffusing from the base layer BL to the semiconductor pattern SC located on the upper side. The second insulating layer 20 may include at least one inorganic layer. The second insulating layer 20 may include a silicon oxide layer and a silicon nitride layer.

[0177] The semiconductor pattern SC may be arranged on the second insulating layer 20. The semiconductor pattern SC may include a metal oxide semiconductor. The metal oxide semiconductor may include a crystalline or amorphous oxide semiconductor. In an embodiment, for example, the oxide semiconductor may include an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) or a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and its oxide. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO) or zinc tin oxide (ZTO).

[0178] However, the present disclosure is not limited thereto, and the semiconductor pattern SC may include a silicon semiconductor. In an embodiment, for example, the silicon semiconductor may include amorphous silicon and / or polycrystalline silicon. In an embodiment, for example, the semiconductor pattern SC may include low temperature polycrystalline silicon.

[0179] The semiconductor pattern SC may have different electrical properties depending on whether it is doped or not. The semiconductor pattern SC may include a first region of high conductivity and a second region of low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region or a region doped at a lower concentration than the first region.

[0180] The conductivity of the first region is greater than that of the second region, and the first region may be substantially used as an electrode or a signal line. The second region may substantially correspond to a channel region (or an active region) of a transistor. That is, a portion of the semiconductor pattern SC may be a channel region of a transistor, another portion of the semiconductor pattern SC may be a source or a drain of the transistor, and another portion of the semiconductor pattern SC may be a connection electrode or a connection signal line.

[0181] The semiconductor pattern SC may include a plurality of regions SE, AC, and DE classified according to whether the semiconductor pattern SC is reduced or not. The region in which the semiconductor pattern SC is reduced (hereinafter referred to as the reduction region) has a higher conductivity than the region in which the semiconductor pattern SC is not reduced (hereinafter referred to as the non-reduction region). The reduction region substantially serves as a source / drain or a signal line of a transistor. The non-reduction region substantially corresponds to a semiconductor region (or channel region) of a transistor. That is, some regions of the semiconductor pattern SC may be a channel region AC of a transistor, other regions of the semiconductor pattern SC may be a source region SE / drain region DE of a transistor, and other portions may be used as a signal transmission region.

[0182] The third insulating layer 30 may overlap the channel region AC in a plan view. The gate GT disposed on the third insulating layer 30 may be patterned using a mask. The third insulating layer 30 may include at least one of a silicon oxide layer and a silicon nitride layer.

[0183] The gate GT may be disposed on the third insulating layer 30. The gate GT overlaps the channel region AC in a plan view. The gate GT may be a portion of a metal pattern. The gate GT may be a mask in a process of doping the semiconductor pattern SC.

[0184] The fourth insulating layer 40 may cover the gate electrode GT and may be disposed on the second insulating layer 20 and the third insulating layer 30. The fourth insulating layer 40 may include a silicon oxide layer and a silicon nitride layer. According to an embodiment, in the fourth insulating layer 40, the silicon oxide layer and the silicon nitride layer may be alternately stacked. However, the present disclosure is not limited thereto, and the fourth insulating layer 40 may include an organic material.

[0185] The first connection electrode CNP1 and the second connection electrode CNP2 may be disposed on the fourth insulating layer 40. A portion of the first connection electrode CNP1 may be connected to the shielding electrode BML through a contact hole passing through the second insulating layer 20 and the fourth insulating layer 40, and the other portion of the first connection electrode CNP1 may be connected to the drain region DE through a contact hole passing through the fourth insulating layer 40. A portion of the second connection electrode CNP2 may be connected to the source region SE through a contact hole passing through the fourth insulating layer 40.

[0186] The display panel DP-a according to the embodiment may further include an auxiliary electrode SP disposed on the fourth insulating layer 40. The auxiliary electrode SP is patterned by the same process as that of the first and second connection electrodes CNP1 and CNP2 and may thus include the same material as that of the first and second connection electrodes CNP1 and CNP2.

[0187] The auxiliary electrode SP, the first connection electrode CNP1, and the second connection electrode CNP2 may include a metal layer including first to third layers sequentially stacked on the fourth insulating layer 40. The first and third layers may include titanium, and the second layer may include aluminum.

[0188] The fifth insulating layer 50 (interlayer insulating layer) may cover the auxiliary electrode SP, the first connection electrode CNP1, and the second connection electrode CNP2, and may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may include polyimide.

[0189] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP and a cathode CE (or a second electrode). The anode AE ​​of the light emitting element ED may be arranged on the fifth insulating layer 50. The anode AE ​​can be a (semi) transmissive electrode or a reflective electrode. The anode AE ​​may include a stacked structure of ITO / Ag / ITO stacked sequentially. The positions of the anode AE ​​and the cathode CE may be replaced with each other.

[0190] The pixel defining layer PDL may be arranged on the fifth insulating layer 50. The pixel defining layer PDL may be an organic layer including polyimide. The pixel defining layer PDL may have a property of absorbing light, and for example, the pixel defining layer PDL may have a black color. The pixel defining layer PDL may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black or a metal such as chromium or an oxide thereof. The pixel defining layer PDL may correspond to a light shielding pattern having a light shielding property. An opening exposing a portion of the anode AE ​​may be defined in the pixel defining layer PDL.

[0191] The auxiliary connection electrode SS may be disposed on the fifth insulating layer 50. Since the auxiliary connection electrode SS is patterned by the same process as the patterning process of the anode AE, the auxiliary connection electrode SS may include the same material as that of the anode AE. The auxiliary connection electrode SS may be connected to the auxiliary electrode SP through a contact hole CNT defined by the fifth insulating layer 50.

[0192] The display panel DP-a according to the embodiment may include a partition wall PW-a. The partition wall PW-a according to the embodiment may include a lower layer L1 and an upper layer L2 disposed on the lower layer L1. The lower layer L1 may be directly disposed on the auxiliary connection electrode SS.

[0193] The lower layer L1 may include a conductive material. The lower layer L1 according to the present disclosure may be provided as a multilayer in which different metal layers are stacked. In an embodiment, for example, the lower layer L1 may include a first layer AL1, a second layer MO1, a third layer AL2, a fourth layer MO2, and a fifth layer AL3 sequentially stacked on the pixel defining layer PDL. According to the present disclosure, the contact resistance between the second layer MO1 and the fourth layer MO2 and the upper layer L2 may be lower than the contact resistance between the first layer AL1, the third layer AL2, and the fifth layer AL3 and the upper layer L2.

[0194] The first layer AL1, the third layer AL2, and the fifth layer AL3 may include the same first material, and the second layer MO1 and the fourth layer MO2 may include the same second material, which is different from the first material. In an embodiment, for example, the first layer AL1, the third layer AL2, and the fifth layer AL3 may each include aluminum (Al), and the second layer MO1 and the fourth layer MO2 may each include any one of molybdenum (Mo) and a molybdenum alloy. The description of the lower layer L1 may correspond to Figure 5 and Figure 6 The partition wall PW described in .

[0195] The upper layer L2 may include a metal or a non-metal. In an embodiment, for example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The non-metal may include silicon, silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or metal nitride, or a combination thereof, and the metal oxide may include a transparent conductive oxide (TCO).

[0196] According to an embodiment, the cathode CE may contact a side surface of the partition wall PW-a. Accordingly, the cathode CE may be connected to the auxiliary electrode SP through the partition wall PW-a including a conductive material and the auxiliary connection electrode SS.

[0197] The electrode pattern CE-P may be arranged on the upper layer L2. The electrode pattern CE-P may be a portion disconnected from the cathode CE due to the tip portion TIP of the partition wall PW-a. Accordingly, the electrode pattern CE-P may be arranged on the upper layer L2 and may include the same material as that of the cathode CE. The portions of the cathode CE disconnected due to the tip portion TIP of the partition wall PW-a may be electrically connected to each other while contacting the side surface of the partition wall PW-a.

[0198] A light control layer including quantum dots may be disposed on the display panel DP-a according to the embodiment. The light control layer may change the property of source light provided by the display panel DP-a.

[0199] According to an embodiment, in order to prevent a voltage drop (IR drop) phenomenon of the cathode CE, it may be connected to a low-resistance auxiliary electrode SP through a partition wall PW-a. The auxiliary electrode SP may provide Figure 3BSince the second driving voltage ELVSS is provided within 0.2V, a voltage drop (IR drop) phenomenon of the cathode CE can be prevented. Accordingly, a display panel DP-a having improved brightness uniformity can be provided.

[0200] Fig. 8A is a cross-sectional view showing a portion of a partition wall according to another embodiment of the present disclosure. Figure 8B is a cross-sectional view showing a portion of a partition wall according to still another embodiment of the present disclosure. Figure 8C is a cross-sectional view showing a portion of a partition wall according to yet another embodiment of the present disclosure. Figure 5 and Figure 6 The same / similar parts as those described in the drawings will be described herein, and repeated description will be omitted. FIG. 8A to FIG. 8C The embodiments of the partition wall described in the following can be applied to Figure 5 and Figure 6 The dividing wall described in .

[0201] Reference Fig. 8A , which may include a partition wall PW-1 disposed on the circuit element layer DP-CL. The partition wall PW-1 according to the embodiment may include a lower layer L1 and an upper layer L2 disposed on the lower layer L1.

[0202] The lower layer L1 may include a conductive material. The lower layer L1 according to the present disclosure may be provided as a multilayer in which different metal layers are stacked. In an embodiment, for example, the lower layer L1 may include a first layer AL1, a second layer MO1, a third layer AL2, a fourth layer MO2, and a fifth layer AL3 sequentially stacked on the circuit element layer DP-CL. According to the present disclosure, the contact resistance of the second layer MO1 and the fourth layer MO2 with the upper layer L2 may be lower than the contact resistance of the first layer AL1, the third layer AL2, and the fifth layer AL3 with the upper layer L2.

[0203] According to an embodiment, the first layer AL1, the third layer AL2, and the fifth layer AL3 may each include aluminum (Al), and the second layer MO1 and the fourth layer MO2 may each include any one of molybdenum (Mo) and a molybdenum alloy. The description of the lower layer L1 may correspond to Figure 5 and Figure 6 The partition wall PW described in . The upper layer L2 may include titanium (Ti).

[0204] According to the present embodiment, cathodes CE1 and CE2 included in each of the light emitting elements ED1 and ED2 may contact side surfaces of the first layer AL1, the second layer MO1, the third layer AL2, and the fourth layer MO2. Specifically, cathodes CE1 and CE2 may contact side surfaces M-E1 of the second layer MO1 and M-E2 of the fourth layer MO2 having relatively low contact resistance. The cathodes CE1 and CE2 may expose side surfaces of the fifth layer AL3.

[0205] Reference Figure 8B , which may include a partition wall PW-2 disposed on the circuit element layer DP-CL. The partition wall PW-2 according to the embodiment may include a lower layer L1 and an upper layer L2 disposed on the lower layer L1.

[0206] The lower layer L1 may include a conductive material. The lower layer L1 according to the present disclosure may be provided as a multilayer in which different metal layers are stacked. In an embodiment, for example, the lower layer L1 may include a first layer AL1, a second layer MO1, a third layer AL2, a fourth layer MO2, and a fifth layer AL3 sequentially stacked on the circuit element layer DP-CL. According to the present disclosure, the contact resistance of the second layer MO1 and the fourth layer MO2 with the upper layer L2 may be lower than the contact resistance of the first layer AL1, the third layer AL2, and the fifth layer AL3 with the upper layer L2.

[0207] According to an embodiment, the first layer AL1, the third layer AL2, and the fifth layer AL3 may each include aluminum (Al), and the second layer MO1 and the fourth layer MO2 may each include any one of molybdenum (Mo) and a molybdenum alloy. The description of the lower layer L1 may correspond to Figure 5 and Figure 6 The partition wall PW described in . The upper layer L2 may include titanium (Ti).

[0208] According to an embodiment, the light emitting patterns EP1 and EP2 included in each of the light emitting elements ED1 and ED2 may contact a side surface of the first layer AL1, a side surface M-E1 of the second layer MO1, and a portion of a side surface of the third layer AL2. The cathodes CE1 and CE2 may contact the remaining portion of the side surface of the third layer AL2 and the side surface M-E2 of the fourth layer MO2. Accordingly, the cathodes CE1 and CE2 do not contact the side surface M-E1 of the second layer MO1, and may contact only the side surface M-E2 of the fourth layer MO2.

[0209] Reference Figure 8C , which may include a partition wall PW-3 disposed on the circuit element layer DP-CL. The partition wall PW-3 according to the embodiment may include a lower layer L1 and an upper layer L2 disposed on the lower layer L1.

[0210] The lower layer L1 may include a conductive material. The lower layer L1 according to the present disclosure may be provided as a multilayer in which different metal layers are stacked. In an embodiment, for example, the lower layer L1 may include a first layer AL1, a second layer MO1, a third layer AL2, a fourth layer MO2, and a fifth layer AL3 sequentially stacked on the circuit element layer DP-CL. According to the present disclosure, the contact resistance of the second layer MO1 and the fourth layer MO2 with the upper layer L2 may be lower than the contact resistance of the first layer AL1, the third layer AL2, and the fifth layer AL3 with the upper layer L2.

[0211] According to an embodiment, the first layer AL1, the third layer AL2, and the fifth layer AL3 may each include aluminum (Al), and the second layer MO1 and the fourth layer MO2 may each include any one of molybdenum (Mo) and a molybdenum alloy. The description of the lower layer L1 may correspond to Figure 5 and Figure 6 The partition wall PW described in . The upper layer L2 may include titanium (Ti).

[0212] According to the embodiment, the side surface M-E1 of the second layer MO1 and the side surface M-E2 of the fourth layer MO2 may protrude in a direction facing the light emitting patterns EP1 and EP2 compared to the side surface A-E1 of the first layer AL1, the side surface A-E2 of the third layer AL2, and the side surface A-E3 of the fifth layer AL3. This may be formed into an undercut shape due to the difference in etching rate. Since the partition wall PW-3 according to the embodiment has an undercut shape for each adjacent layer, the light emitting patterns EP1 and EP2 and the cathodes CE1 and CE2 may be more easily patterned separately.

[0213] 9A to 9E is a cross-sectional view showing a method for manufacturing a display panel according to an embodiment of the present disclosure. Figure 5 and Figure 6 The same / similar parts as those described in the drawings will be described herein, and repeated description will be omitted.

[0214] Reference Fig.9A According to an embodiment, the method for manufacturing a display panel may include an operation of forming a circuit element layer DP-CL on a base layer BL, an operation of forming a pixel defining layer PDL on the circuit element layer DP-CL, an operation of forming a lower layer L1 on the pixel defining layer PDL, an operation of forming an upper layer L2 on the lower layer L1, and an operation of forming a photoresist layer PR on the upper layer L2.

[0215] The circuit element layer DP-CL may be formed by a common process of manufacturing circuit elements by forming an insulating layer, a semiconductor layer and a conductive layer through a scheme such as coating or deposition, selectively patterning the insulating layer, the semiconductor layer and the conductive layer through photolithography and etching processes, and forming a semiconductor pattern, a conductive pattern and a signal line. The pixel defining layer PDL may include polyimide.

[0216] The lower layer L1 may be formed as a multilayer in which different metal layers are stacked. In an embodiment, for example, in the lower layer L1, a first layer AL1, a second layer MO1, a third layer AL2, a fourth layer MO2, and a fifth layer AL3 may be sequentially formed on the pixel defining layer PDL. According to the present disclosure, the contact resistance between the second layer MO1 and the fourth layer MO2 and the upper layer L2 may be lower than the contact resistance between the first layer AL1, the third layer AL2, and the fifth layer AL3 and the upper layer L2.

[0217] In the lower layer L1, the first layer AL1, the third layer AL2, and the fifth layer AL3 may each be formed to have a thickness not less than and not greater than In the lower layer L1, the second layer MO1 and the fourth layer MO2 may each be formed to have a thickness not less than and not greater than

[0218] According to an embodiment, the thicknesses of the first layer AL1, the third layer AL2, and the fifth layer AL3 may be different from each other. In an embodiment, for example, the thickness of the first layer AL1 may be The thickness of the third layer AL2 can be And the thickness of the fifth layer AL3 can be Then, the thickness of the second layer MO1 and the fourth layer MO2 can be respectively And the thickness of the upper layer L2 can be The upper layer L2 may be formed on the fifth layer AL3. The upper layer L2 may include titanium (Ti). A method for forming the layers included in the lower layer L1 and the upper layer L2 is not limited to any one method as long as it is a process for forming a metal layer.

[0219] A photoresist layer PR may be formed on the upper layer L2. The photoresist layer PR is not limited to any one as long as it is used in a photoresist process.

[0220] Afterwards, refer to Fig. 9B The method for manufacturing a display panel according to an embodiment may include a first etching operation. In the first etching operation, at least a portion of the upper layer L2 and the fifth layer AL3 may be removed by a dry etching process while using the photoresist layer PR as a mask.

[0221] Afterwards, refer to Fig. 9C , the method for manufacturing a display panel according to an embodiment may include a second etching operation. In the second etching operation, at least a portion of the first layer AL1, the second layer MO1, the third layer AL2, the fourth layer MO2, and the fifth layer AL3 may be removed by a wet etching process. The etchant used in the wet etching process may be a phosphorus nitrogen-based FAN-based etchant.

[0222] Afterwards, refer to Fig.9D , the method for manufacturing a display panel according to an embodiment may further include an operation of etching a pixel defining layer PDL.

[0223] Afterwards, refer to Fig.9E The method for manufacturing a display panel according to an embodiment may further include an operation of forming a light emitting element ED. The anode AE, the emission pattern EP, and the cathode CE included in the light emitting element ED may be individually patterned to be shifted in the partition wall opening PW-OP defined by the partition wall PW.

[0224] According to the embodiment, due to the difference between the etching rates of the lower layer L1 and the upper layer L2, the components included in the light emitting element ED can be separated by the tip portion TIP of the undercut shape and can be easily patterned in the partition wall opening PW-OP. In addition, since the lower layer L1 includes a layer including a molybdenum alloy having a low contact resistance with the upper layer L2, a display panel having an enhanced coupling force between the lower layer L1 and the upper layer L2 can be provided.

[0225] According to the present disclosure, since the light emitting layer can be patterned without using a mask, process reliability can be improved and high resolution can be easily achieved. In addition, since the lower layer of the partition wall includes a molybdenum alloy layer, the contact resistance between the lower layer and the upper layer can be reduced.

[0226] Although the present disclosure has been described with reference to the embodiments, those skilled in the art to which the present disclosure pertains will appreciate that modifications and variations may be made to the present disclosure within the scope of the appended claims without departing from the spirit and technical field of the present disclosure.

[0227] Therefore, the technical scope of the present disclosure should not be limited to the detailed description of the specification but should be determined by the claims.

Claims

1. A display panel, comprising: A base layer, the base layer comprising a light-emitting area and a non-light-emitting area adjacent to the light-emitting area; a light emitting element, the light emitting element comprising a first electrode arranged in the light emitting region, a second electrode arranged on the first electrode, and a light emitting pattern arranged between the first electrode and the second electrode; as well as a partition wall including a lower layer arranged in the non-light emitting region and an upper layer arranged on the lower layer, wherein the second electrode contacts the side surface of the lower layer, and Wherein, the lower layer includes a plurality of layers containing different metals.

2. The display panel according to claim 1, wherein: The lower layer comprises: The first layer, the second layer, the third layer, the fourth layer and the fifth layer are sequentially stacked, The contact resistance between the second layer and the fourth layer and the upper layer is lower than the contact resistance between the first layer, the third layer and the fifth layer and the upper layer.

3. The display panel according to claim 2, wherein: The first layer, the third layer, and the fifth layer each include aluminum, and The second layer and the fourth layer each include any one of molybdenum and a molybdenum alloy.

4. The display panel according to claim 3, wherein: The molybdenum alloy includes molybdenum, nickel and titanium.

5. The display panel according to claim 4, wherein: The content of nickel and titanium is not more than 50% of the total weight of the molybdenum alloy.

6. The display panel according to claim 3, wherein: The thickness of the lower layer is to as well as Wherein, the thickness of the upper layer is to 7. The display panel according to claim 3, wherein: The thickness of the first layer, the third layer and the fifth layer are respectively to as well as Wherein, the thickness of the second layer and the fourth layer are respectively to 8. The display panel according to claim 3, wherein: The upper layer includes titanium.

9. The display panel according to claim 2, wherein: Side surfaces of the first to fifth layers are aligned with each other.

10. The display panel according to claim 2, wherein: Each of the side surfaces of the second layer and the fourth layer protrudes further than the first layer, the third layer, and the fifth layer in a direction facing the light emitting region.

11. The display panel according to claim 2, wherein: The second electrode contacts the second layer and exposes the fourth layer.

12. The display panel according to claim 2, wherein: The second electrode is spaced apart from the second layer and contacts the fourth layer.

13. The display panel according to claim 2, wherein: The second electrode contacts the second layer and the fourth layer.

14. The display panel according to claim 1, wherein: A side surface of the upper layer protrudes further than the side surface of the lower layer in a direction facing the light emitting region.

15. The display panel according to claim 1, further comprising: a pixel defining layer, the pixel defining layer being arranged on the base layer and having an opening through which at least a portion of the first electrode is exposed, Wherein, the pixel defining layer comprises an inorganic material, and Wherein, the lower layer is arranged on the pixel defining layer.

16. The display panel according to claim 15, wherein: A partition wall opening overlapping the opening is defined by the partition wall.

17. The display panel according to claim 16, further comprising: An encapsulation layer includes a lower inorganic layer covering the light emitting element and the partition wall, an upper inorganic layer disposed on the lower inorganic layer, and an organic layer disposed between the lower inorganic layer and the upper inorganic layer and in the partition wall opening.

18. The display panel according to claim 17, further comprising: a dummy pattern disposed on the upper layer and including a same material as that of at least one of the light emitting pattern and the second electrode, Wherein, the dummy pattern is covered by the lower inorganic layer.

19. The display panel according to claim 18, wherein: A dummy groove exposing an upper surface of the upper layer is defined by the dummy pattern, and Wherein, the organic layer contacts the upper surface of the upper layer.

20. The display panel according to claim 1, further comprising: a transistor, the transistor being arranged on the base layer; a connecting electrode, the connecting electrode connecting the transistor and the first electrode; an auxiliary electrode, the auxiliary electrode being arranged at the same layer as the connecting electrode; an interlayer insulating layer, the interlayer insulating layer covering the connecting electrode and the auxiliary electrode and the first electrode being arranged on the interlayer insulating layer; a pixel defining layer, wherein an opening exposing at least a portion of the first electrode is defined by the pixel defining layer; as well as an auxiliary connection electrode disposed on the interlayer insulating layer and connected to the auxiliary electrode through a contact hole defined in the interlayer insulating layer, Wherein, the lower layer is arranged on the auxiliary connection electrode.

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