Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a base layer including a display area and a non-display area adjacent to the display area; a plurality of insulating layers disposed on the base layer; a plurality of pixels disposed in the display area; a plurality of pads connected to the plurality of pixels, arranged in the first direction and arranged in the non-display area; and a driving chip connected to the plurality of pads. Each of a plurality of side pads arranged at opposite ends in a first direction among the plurality of pads includes: a first conductive pattern; a first insulating pattern including a plurality of protruding patterns protruding in a direction toward the driving chip; and a second insulating pattern disposed on the first insulating pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0123042, filed on September 15, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device and a method of manufacturing the display device, and more particularly, to a display device including a pad having improved bonding reliability and a method of manufacturing the display device. Background Art

[0004] The display device includes a display area activated according to an electrical signal and a non-display area adjacent to the display area. The display device can display various images through the display area to provide information to a user and simultaneously detect input from the outside. The driver chip can be mounted on the display panel. The driver chip can be connected to the display panel through a pad arranged in the non-display area of ​​the display panel. Summary of the invention

[0005] Embodiments of the present disclosure provide a display device having improved bonding reliability between a pad and a driving chip and a method of manufacturing the display device.

[0006] According to an embodiment, a display device includes: a base layer, which includes a display area and a non-display area adjacent to the display area; a plurality of insulating layers, which are arranged on the base layer; a plurality of pixels, which are arranged in the display area; a plurality of pads, which are connected to the plurality of pixels, arranged in a first direction and arranged in the non-display area; and a driving chip, which is connected to the plurality of pads, wherein each of a plurality of side pads arranged at opposite ends in the first direction among the plurality of pads includes: a first conductive pattern; a first insulating pattern, which includes a plurality of protruding patterns protruding in a direction toward the driving chip; and a second insulating pattern, which is arranged on the first insulating pattern.

[0007] The plurality of protruding patterns have an integrated shape, the plurality of lower portions of the plurality of protruding patterns are connected in the integrated shape, a valley recessed in a direction toward the base layer may be defined between the plurality of protruding patterns, and the second insulating pattern may overlap the valley in a plan view.

[0008] Two valleys recessed in a direction toward the base layer may be defined between the plurality of protruding patterns, the second insulating pattern may further include a plurality of sub-protruding patterns, the plurality of sub-protruding patterns protruding in a direction toward the driving chip and respectively overlapping with the two valleys in a plan view, a sub-valley recessed in a direction toward the base layer may be defined between the plurality of sub-protruding patterns, and each of the plurality of side pads may further include a third insulating pattern arranged on the second insulating pattern and overlapping with the sub-valley in a plan view.

[0009] Each of the plurality of side pads may further include a second conductive pattern covering the second insulating pattern and a portion of the first insulating pattern exposed from the second insulating pattern.

[0010] The second conductive pattern may include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially laminated, and the first conductive layer and the third conductive layer may include titanium, and the second conductive layer may include aluminum.

[0011] The first conductive pattern may cover the second insulating pattern and a portion of the first insulating pattern exposed from the second insulating pattern.

[0012] The first conductive pattern may cover the second insulating pattern and a portion of the first insulating pattern exposed from the second insulating pattern, and each of the plurality of side pads may further include a second conductive pattern covering the first conductive pattern.

[0013] The first insulating pattern may include a positive photoresist, and the second insulating pattern may include one of a positive photoresist and a negative photoresist.

[0014] The first insulating pattern may include a negative photoresist, and the second insulating pattern may include a negative photoresist.

[0015] The first and second insulating patterns may include a polymer.

[0016] Each of the plurality of center pads arranged between the plurality of side pads among the plurality of pads may include: a third conductive pattern; an insulating pattern having a convex shape protruding in a direction toward the driving chip; and a fourth conductive pattern covering the insulating pattern.

[0017] The multiple insulating layers may include a barrier layer disposed on the base layer, a buffer layer disposed on the barrier layer, and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer arranged on the buffer layer, and each of the third to fifth insulating layers may expose the second insulating layer in the non-display area, and the first conductive pattern may be disposed on the second insulating layer.

[0018] The display device may further include: a plurality of data lines connecting a plurality of pixels and a plurality of pads, disposed on the first insulating layer and covered by a second insulating layer, wherein the first conductive pattern may be arranged in a plurality of contact holes passing through the second insulating layer and connected to the plurality of data lines.

[0019] The display device may further include: a first connection electrode, which is arranged on the second insulating layer, arranged in a contact hole passing through the first insulating layer and the second insulating layer, and is electrically connected to a semiconductor pattern included in each of the plurality of pixels; and a second connection electrode, which is arranged on the fourth insulating layer, arranged in a contact hole passing through the third insulating layer and the fourth insulating layer, and is connected to the first connection electrode, wherein each of the plurality of pixels may include: a transistor, which includes a semiconductor pattern arranged on the buffer layer and a gate region arranged on the first insulating layer; and a light emitting element, which is electrically connected to the semiconductor pattern through the first connection electrode and the second connection electrode.

[0020] The first connection electrode and the first conductive pattern may include the same material.

[0021] A non-conductive film (NCF) may be disposed between the driving chip and the pad.

[0022] The driving chip may include a base film and a plurality of bumps protruding from the base film and connected to the plurality of pads.

[0023] The plurality of pads and the driving chip may be bent with a predetermined curvature with respect to the first direction.

[0024] In the first direction, a width of the first insulating pattern may be in a range of about 5 micrometers (μm) to about 8 μm, and a width of the second insulating pattern may be in a range of about 1 μm to about 4 μm.

[0025] A thickness of the second insulation pattern measured from an uppermost end of the first insulation pattern may be 30% or less of a maximum thickness of the first insulation pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0027] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0028] Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0029] Figure 3 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0030] Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0031] Figure 5 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0032] Fig. 6A is a cross-sectional view of a portion of a display device according to an embodiment of the present disclosure.

[0033] Figure 6B is a plan view of an input sensing unit according to an embodiment of the present disclosure.

[0034] Figure 7 is an enlarged perspective view of a partial area of ​​a display device according to an embodiment of the present disclosure.

[0035] Figure 8 It is along Figure 7 A cross-sectional view taken along line II' in FIG.

[0036] Fig. 9 It is along Figure 7 A cross-sectional view taken along line II-II'.

[0037] Fig.10 It is along Figure 7 A cross-sectional view taken along line III-III'.

[0038] Fig.11 is a cross-sectional view of a side pad according to an embodiment of the present disclosure.

[0039] Fig.12 is a cross-sectional view of a side pad according to an embodiment of the present disclosure.

[0040] Fig.13 is a cross-sectional view of a side pad according to an embodiment of the present disclosure.

[0041] FIG. 14A to FIG. 14G is a cross-sectional view illustrating a method of manufacturing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In this specification, the statement that a first component (or region, layer, part, portion, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is interposed therebetween.

[0043] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated in order to effectively describe the technical content. The expression "and / or" includes one or more combinations that the relevant components can define.

[0044] Although the terms "first", "second", etc. can be used to describe various components, the components should not be limited by the terms. The terms are only used to distinguish one component from another component. For example, without departing from the scope of the present disclosure, the first component can be referred to as the second component, and similarly, the second component can also be referred to as the first component. Unless otherwise clearly indicated in the context, a singular expression includes a plural expression.

[0045] In addition, the terms "lower", "below", "upper", "above" and the like are used to describe the relationship between components illustrated in the drawings. Conceptually relative terms are described based on directions illustrated in the drawings.

[0046] It will be understood that the terms “include,” “comprise,” “have,” etc. specify the presence of features, numbers, steps, operations, elements or components, or a combination thereof, described in the specification, and do not preclude the presence or possibility of adding one or more other features, numbers, steps, operations, elements or components, or a combination thereof.

[0047] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an overly idealized or overly formal sense, unless clearly defined herein.

[0048] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±10%, 5%, or 2% of the stated value. Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0049] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure. Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0050] The electronic device ED may be a device activated according to an electrical signal. In the embodiment, the electronic device ED is exemplarily illustrated as a smart phone. However, the present disclosure is not limited thereto, and in the embodiment, the electronic device ED according to the present disclosure may be provided. For example, the electronic device ED may be applied to a personal computer (PC), a laptop computer, a television, a personal digital assistant, a vehicle navigation unit, a game console, a tablet computer, a camera, etc.

[0051] The electronic device ED can display an image IM via the display surface ED-IS. Figure 1 , an icon image is illustrated as an example of the image IM. The display surface ED-IS may be parallel to a plane defined by the first direction DR1 and the second direction DR2.

[0052] At the same time, Figure 1 In the following drawings, first to third directions DR1 to DR3 are illustrated, and directions indicated by the first, second, and third directions DR1, DR2, and DR3 described in the specification are relative concepts and may be changed to different directions.

[0053] In the specification, for convenience of description, the third direction DR3 is defined as a direction in which an image is provided to a user. In addition, the first direction DR1 and the second direction DR2 may be perpendicular to each other, and the third direction DR3 may be a normal direction of a plane defined by the first direction DR1 and the second direction DR2.

[0054] The display surface ED-IS may include a display area ED-DA displaying an image IM and a non-display area ED-NDA adjacent to the display area ED-DA. The non-display area ED-NDA may be an area where the image IM is not displayed. However, the present disclosure is not limited thereto, and the non-display area ED-NDA may be adjacent to one side of the display area ED-DA or may be omitted.

[0055] refer to Figure 2 , the electronic device ED according to the embodiment may include a window WM, a display device DD, and a storage member BC.

[0056] The window WM may be disposed on the display device DD and transmit an image IM provided from the display device DD to the outside. The window WM may include a transmission area TA and a non-transmission area NTA.

[0057] The window WM may include a base layer and a functional layer arranged on the base layer. The functional layer may include a protective layer, an anti-fingerprint layer, etc. The base layer of the window WM may be made of glass, sapphire or plastic. The base layer of the window WM may include an optically transparent insulating material. For example, the base layer of the window WM may include glass or a plastic film, or may include a glass substrate and a plastic film bonded by an adhesive.

[0058] The transmission area TA can be Figure 1 The transmissive area TA may overlap the display area ED-DA illustrated in FIG. 1 and have a shape corresponding to the display area ED-DA. The transmissive area TA may be an image IM (see FIG. 1 ) provided from the display device DD. Figure 1 ) is transmitted to the outside area.

[0059] The non-transmissive area NTA may be Figure 1 The non-display area ED-NDA illustrated in FIG. 1 overlaps with the non-display area ED-NDA illustrated in FIG. 1 and has a shape corresponding to the non-display area ED-NDA. The non-transmission area NTA may be an area having a relatively low light transmittance compared to the transmission area TA. The non-transmission area NTA may be defined by a frame pattern in a local area of ​​the base layer of the window WM, and an area in which the frame pattern is not set may be defined as the transmission area TA. However, the present disclosure is not limited thereto, and the non-transmission area NTA may be omitted.

[0060] According to an embodiment, an anti-reflection layer may be provided between the window WM and the display device DD. The anti-reflection layer may reduce the reflection of an external light beam input from the outside of the display device DD. The anti-reflection layer may include a color filter. The color filter may have a predetermined arrangement. For example, the color filter may be arranged in consideration of the luminous color of the pixel included in the display panel DP to be described below. In addition, the anti-reflection layer may further include a black matrix adjacent to the color filter.

[0061] The display device DD according to the embodiment may include a display panel DP and an input sensing unit ISU.

[0062] The display panel DP may be a liquid crystal display panel or a light-emitting display panel. For example, the display panel DP may be a liquid crystal display panel including a liquid crystal element, an organic electroluminescent display panel including an organic electroluminescent element, or a quantum dot light-emitting display panel including a quantum dot light-emitting element. However, the embodiment is not limited thereto. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0063] The input sensing unit ISU may be provided on the display panel DP. The input sensing unit ISU may include any one of a capacitive sensor, an optical sensor, an ultrasonic sensor, and an electromagnetic induction sensor. The input sensing unit ISU may be formed on the display panel DP through a continuous process, or may be manufactured separately and then attached to the upper portion of the display panel DP through an adhesive layer.

[0064] The display device DD may further include a driving chip DC and a circuit board PB disposed on the display panel DP.

[0065] In an embodiment, the circuit board PB may be a flexible circuit board. Hereinafter, the circuit board PB is described as a flexible circuit board and relates to the same reference numerals, but the present disclosure is not limited thereto. For example, the circuit board PB may be rigid. The circuit board PB may electrically connect the display panel DP and the main circuit board.

[0066] The driving chip DC may be mounted on the display panel DP. The driving chip DC may be an integrated circuit coupled to a pad exposed by the display panel DP and provided in the form of a chip. The driving chip DC may be connected to at least some of a plurality of signal lines connected to pixels. The driving chip DC provides electrical signals to pixels arranged in the display panel DP through the signal lines. The driving chip DC may be connected to a data line DL (see Figure 4 ) and provides the data signal to the data driving circuit D-IC of the data line DL (see Figure 7 ).

[0067] The driving chip DC may be connected to the circuit board PB. The driving chip DC may include a driving element, for example, a data driving circuit D-IC for driving the pixels of the display panel DP. In an embodiment, the driving chip DC and the circuit board PB directly mounted on the display panel DP may be collectively referred to as an electronic component. The coupling structure between the display panel DP and the circuit board PB described below may also be applied to other electronic components such as the driving chip DC in addition to the circuit board PB.

[0068] According to an embodiment, a portion of the circuit board PB may be bent to face the rear surface of the display panel DP. However, the present disclosure is not limited thereto, and a portion of the display panel DP may be bent so that the driving chip DC faces the rear surface of the display device DD.

[0069] The storage member BC may accommodate the display device DD. The storage member BC may be coupled to the window WM to define the appearance of the electronic device ED. The storage member BC according to the embodiment may include a material having relatively high rigidity, and the storage member BC may absorb an impact applied from the outside. The storage member BC may be provided in a form in which a plurality of storage members BC are coupled.

[0070] The display device DD according to the embodiment may further include a main board accommodated in the storage member BC, an electronic module mounted on the main board, a camera module, a power module, and the like.

[0071] Figure 3 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0072] The display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and an encapsulation layer TFL disposed on the display element layer DP-OLED.

[0073] The display panel DP includes a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP may be Figure 1 The display area ED-DA of the electronic device ED described and the reference Figure 2 The non-display area DP-NDA of the display panel DP may correspond to the transmissive area TA described above. Figure 1 The non-display area ED-NDA of the electronic device ED described and the reference Figure 2 The components or layers of the display panel DP (eg, the base layer BL) may include a display area and a non-display area corresponding to the display area DP-DA and the non-display area DP-NDA of the display panel DP, respectively.

[0074] The base layer BL may be disposed at the lowermost side of the display panel DP and provide a base surface on which the components of the display panel DP are arranged. The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited thereto. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, and the like.

[0075] The base layer BL may be provided in a form in which an organic layer and an inorganic layer are alternately laminated. For example, the base layer BL may be provided in a structure in which a first organic layer including polyimide, a first inorganic layer disposed on the first organic layer, a second organic layer including polyimide and disposed on the first inorganic layer, and a second inorganic layer disposed on the second organic layer are alternately laminated, and the present disclosure is not limited to the embodiments.

[0076] The circuit element layer DP-CL may include a plurality of insulating layers and circuit elements. The insulating layer may include at least one inorganic layer and at least one organic layer. The circuit element may include a signal line, a driving circuit, etc. The insulating layer, the semiconductor layer, and the conductive layer are formed by processes such as coating and deposition, and then the insulating layer, the semiconductor layer, and the conductive layer are selectively patterned by photolithography and etching processes, so that the insulating layer and the circuit element can be formed. Therefore, a semiconductor pattern, a conductive pattern, a signal line, etc. can be formed in the circuit element layer DP-CL.

[0077] Meanwhile, patterns arranged on the same layer are formed by the same process. In the specification, the fact that patterns are formed by the same process means that the patterns contain the same material and have the same laminated structure.

[0078] The display element layer DP-OLED may include a pixel definition layer PDL (see Figure 5 ) and light-emitting element OLED (see Figure 5 ).

[0079] The encapsulation layer TFL may be disposed on and cover the display element layer DP-OLED. The encapsulation layer TFL may prevent moisture / oxygen from penetrating into the display element layer DP-OLED. The encapsulation layer TFL may include a laminated structure of an inorganic layer / organic layer / inorganic layer.

[0080] The input sensing unit ISU may be directly disposed on the display panel DP. In the specification, the wording “component A is directly disposed on component B” is defined as a state in which no other component is disposed between component A and component B.

[0081] Figure 4 2 is a plan view of a display panel according to an embodiment of the present disclosure. As used herein, a “plan view” is a view in the thickness direction of the base layer BL (ie, the third direction DR3 ).

[0082] refer to Figure 4 , the display panel DP according to the embodiment may include pixels PX, a gate driving circuit GDC, signal lines SGL, and signal pads DP-PD.

[0083] The pixels PX may be arranged in the display area DP-DA. Each of the plurality of pixels PX may include a light emitting element OLED and a pixel driving circuit connected to the light emitting element OLED. In an embodiment, the light emitting element OLED may be an organic light emitting element.

[0084] The gate drive circuit GDC may be disposed in the non-display area DP-NDA of the display panel DP. The gate drive circuit GDC may sequentially output gate signals to the gate lines GL. The transistors of the gate drive circuit GDC may be formed by the same process as the manufacturing process of the transistors of the pixels PX (e.g., a low temperature polycrystalline silicon (LTPS) process, a low temperature polycrystalline oxide (LTPO) process, or a mixed oxide and polycrystalline silicon (HOP) process).

[0085] However, the driving circuit included in the display panel DP is not limited to the gate driving circuit GDC, and the display panel DP may further include another driving circuit that provides a light emitting control signal to the pixel PX. For example, the display panel DP may include a scan driving circuit.

[0086] The signal line SGL may be arranged in the display area DP-DA and the non-display area DP-NDA. The signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. The gate line GL may be connected to a corresponding pixel PX among a plurality of pixels PX, and the data line DL may be connected to a corresponding pixel PX among a plurality of pixels PX. The power line PL may be connected to the pixel PX. The control signal line CSL may provide a control signal to the scan drive circuit.

[0087] The signal pads DP-PD may be arranged in the display area DP-DA. The signal pads DP-PD may include a first pad PD1, a second pad PD2, and a third pad PD3.

[0088] The non-display area DP-NDA may include a first pad area PA1 and a second pad area PA2. The first pad area PA1 may be a region in which the first pad PD1 and the second pad PD2 are arranged and a driving chip DC is provided (see FIG. Figure 2 The second pad area PA2 may be an area in which the third pads PD3 are arranged and the circuit board PB is provided.

[0089] The first pad area PA1 and the second pad area PA2 may be spaced apart from each other in the second direction DR2.

[0090] The first pad area PA1 may include a first area B1 in which the first pad PD1 is arranged and a second area B2 in which the second pad PD2 is arranged. The first pad PD1 may be arranged in the first direction DR1 in the first area B1, and the second pad PD2 may be arranged in the first direction DR1 in the second area B2. Hereinafter, the area in which the first pad PD1 and the second pad PD2 are arranged may be defined as the first pad area PA1, and the area in which the third pad PD3 is arranged may be defined as the second pad area PA2.

[0091] The first pad PD1, the second pad PD2, and the third pad PD3 may be exposed to the outside in the non-display area DP-NDA among the insulating layer included in the display panel DP. A description related thereto will be made below.

[0092] In an embodiment, a plurality of first pads PD1 may be arranged in a row in the first region B1. A plurality of second pads PD2 may be arranged in a row in the second region B2. However, the number of arranged rows is not limited thereto. For example, the pads may be arranged in two or more rows in the corresponding region.

[0093] refer to Figure 4 , the second region B2 may be spaced apart from the first region B1 in the second direction DR2. The second pads PD2 arranged in the second region B2 may be connected to the third pads PD3 arranged in the second pad region PA2 through the connection signal lines S-CL in a one-to-one correspondence.

[0094] The circuit board PB may include a plate-shaped bump electrode PB-BP. The plate-shaped bump electrode PB-BP may be arranged in the first direction DR1. The plate-shaped bump electrode PB-BP of the circuit board PB may contact and be connected to the third pad PD3 of the second pad area PA2.

[0095] Figure 5 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. Figure 5 A cross section corresponding to one light emitting region PXA and a portion of the non-light emitting region NPXA is illustrated. Definition of the light emitting region PXA and the non-light emitting region NPXA will be described below.

[0096] The display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and an encapsulation layer TFL disposed on the display element layer DP-OLED.

[0097] For ease of description, Figure 5 Only one transistor TR is illustrated as an embodiment of the driving circuit of the pixel PX, but the embodiments of the present disclosure are not limited thereto, and the pixel PX may include a plurality of transistors TR.

[0098] In an embodiment, the circuit element layer DP-CL may include a barrier layer BRL, a buffer layer BFL, first to fifth insulating layers 10 to 50, a transistor TR, a connection signal line SSL, a first connection electrode CNE1 and a second connection electrode CNE2. However, the embodiments of the present disclosure are not limited thereto, and the barrier layer BRL or the buffer layer BFL may be omitted, one or more layers of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be omitted, or another insulating layer may be further included.

[0099] The barrier layer BRL is disposed on the base layer BL. The barrier layer BRL prevents the inflow of foreign matter from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plural, and the silicon oxide layer and the silicon nitride layer may be alternately laminated.

[0100] The buffer layer BFL is disposed on the barrier layer BRL. The buffer layer BFL may improve the coupling force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately laminated.

[0101] The semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the present disclosure is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide.

[0102] Figure 5 A portion of the semiconductor pattern is illustrated, and in a plan view, additional semiconductor patterns may be provided in other regions of the display panel DP. The semiconductor pattern may include a first region and a second region. The first region may be doped with an N-type dopant or a P-type dopant and may have a higher conductivity than that of the second region. The first region substantially corresponds to an electrode or a signal line. The second region has a low doping concentration or may be a non-doped region and substantially corresponds to an active (or channel) region "A" of the transistor TR.

[0103] The drain region "D", the active region "A", and the source region "S" may be arranged on the buffer layer BFL. The drain region "D", the active region "A", and the source region "S" may define the transistor TR together with the gate region "G". When the display panel DP includes another transistor in addition to the transistor TR, the other transistor may include a material different from that of the transistor TR and may be disposed on a different layer. The source region "S", the active region "A", and the drain region "D" of the transistor TR may be formed of a semiconductor pattern.

[0104] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the semiconductor pattern. The first insulating layer 10 may overlap with a plurality of pixels PX in common. A gate region "G" is disposed on the first insulating layer 10. The gate region "G" may be a part of the metal pattern. The gate region "G" may overlap with the active region "A" in a plan view. The gate region "G" may be used as a mask in the process of doping the semiconductor pattern.

[0105] The gate region "G" may include titanium (Ti), silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AIN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but the present disclosure is not particularly limited thereto.

[0106] The second insulating layer 20 covering the gate region "G" may be disposed on the first insulating layer 10. The second insulating layer 20 may overlap the plurality of pixels PX in common. The transistor TR according to an embodiment may further include an upper electrode (not shown) disposed on the second insulating layer 20 and overlapping the gate region "G" in a plan view. The first connection electrode CNE1 may be connected to the connection signal line SSL through a contact hole CNT-1 passing through the first insulating layer 10 and the second insulating layer 20. Even in Figure 5 Not shown in the figure, a connection signal line SSL may also be electrically connected to the semiconductor pattern.

[0107] The third insulating layer 30 covering the first connection electrode CNE1 may be disposed on the second insulating layer 20. The first to third insulating layers 10 to 30 may be inorganic layers and / or organic layers and may have a single-layer or multi-layer structure.

[0108] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be an organic layer. The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the third insulating layer 30 and the fourth insulating layer 40.

[0109] A fifth insulating layer 50 covering the second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. The first electrode AE ​​may be disposed on the fifth insulating layer 50. The first electrode AE ​​may be connected to the second connection electrode CNE2 through a contact hole CNT-3 passing through the fifth insulating layer 50.

[0110] The display element layer DP-OLED may include a pixel defining film PDL and a light emitting element OLED. In the pixel defining film PDL, a pixel opening OPN may be defined. The pixel opening OPN of the pixel defining film PDL may expose at least a portion of the first electrode AE. In an embodiment, the light emitting area PXA may be defined to correspond to a local area of ​​the first electrode AE ​​exposed by the pixel opening OPN.

[0111] The hole control layer HCL may be commonly disposed in the light emitting region PXA and the non-light emitting region NPXA. The hole control layer HCL may include a hole transport layer, and may further include a hole injection layer.

[0112] The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in a region corresponding to the pixel opening OPN. That is, the light emitting layer EML may be formed separately in each pixel PX. However, the present disclosure is not limited thereto, and the light emitting layer EML may be formed in common in a plurality of pixels PX using an opening mask.

[0113] The electronic control layer ECL may be disposed on the light emitting layer EML. The light emitting layer EML according to the embodiment is patterned for each pixel PX so that the light emitting layer EML is disposed on one pixel opening OPN, but the present disclosure is not limited thereto, and the light emitting layer EML may be commonly disposed throughout a plurality of pixels PX, but the embodiment is not limited thereto.

[0114] According to an embodiment, the electron control layer ECL may include an electron transport layer, and may further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be commonly formed in a plurality of pixels PX using an open mask.

[0115] The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may have an integral shape and may be commonly disposed in a plurality of pixels PX.

[0116] The encapsulation layer TFL may be disposed on the second electrode CE. The encapsulation layer TFL may include a plurality of thin films. For example, the encapsulation layer TFL may include an inorganic layer and an organic layer covered by the inorganic layer.

[0117] The inorganic layer can protect the light emitting element OLED from moisture and / or oxygen. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the material of the inorganic layer is not limited to the above examples.

[0118] The organic layer can protect the light emitting element OLED from foreign matter such as dust particles. For example, the organic layer may include acrylic resin. However, the material of the organic layer is not limited to the above examples.

[0119] Fig. 6A is a cross-sectional view of a portion of a display device according to an embodiment of the present disclosure. Figure 6B is a plan view of an input sensing unit according to an embodiment of the present disclosure.

[0120] refer to Fig. 6AThe input sensing unit ISU may include a first sensing insulating layer IS-IL1, a first sensing conductive layer IS-CL1 disposed on the first sensing insulating layer IS-IL1, a second sensing insulating layer IS-IL2 disposed on the first sensing conductive layer IS-CL1, a second sensing conductive layer IS-CL2 disposed on the second sensing insulating layer IS-IL2, and a third sensing insulating layer IS-IL3 disposed on the second sensing conductive layer IS-CL2. The first sensing insulating layer IS-IL1 may be directly disposed on the encapsulation layer TFL.

[0121] However, the present disclosure is not limited thereto, and the first sensing insulating layer IS-IL1 and / or the third sensing insulating layer IS-IL3 may be omitted. When the first sensing insulating layer IS-IL1 is omitted, the first sensing conductive layer IS-CL1 may be directly disposed on the encapsulation layer TFL. The third sensing insulating layer IS-IL3 may be replaced with an adhesive layer or an insulating layer of an anti-reflection member of the input sensing unit ISU.

[0122] The first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may each include an inorganic layer or an organic layer. The inorganic layer may include silicon oxide, silicon nitride, or silicon oxynitride, and the organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0123] In an embodiment, at least one of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may be an organic layer. For example, the third sensing insulating layer IS-IL3 may include an organic layer.

[0124] exist Fig. 6A In order to schematically illustrate the laminated structure, each of the first sensing conductive layer IS-CL1 and the second sensing conductive layer IS-CL2 is illustrated as one layer overlapping the entire display panel DP. However, the embodiment is not limited thereto, and each of the first sensing conductive layer IS-CL1 and the second sensing conductive layer IS-CL2 may be patterned.

[0125] refer to Figure 6B , the input sensing unit ISU may include a sensing area IS-DA and a non-sensing area IS-NDA adjacent to the sensing area IS-DA. The sensing area IS-DA and the non-sensing area IS-NDA may be respectively adjacent to the display area DP-DA (see Figure 3 ) and non-display area DP-NDA (see Figure 3 ) corresponding to.

[0126] The input sensing unit ISU may include first electrodes E1 - 1 to E1 - 5 , second electrodes E2 - 1 to E2 - 4 , a first track SL1 , and a second track SL2 .

[0127] The first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may be arranged in the sensing area IS-DA. The first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may be insulated from and intersect each other.

[0128] The first and second traces SL1 and SL2 may be arranged in the non-sensing area IS-NDA. The plurality of first traces SL1 may be electrically connected to the first electrodes E1-1 to E1-5, respectively, and the plurality of second traces SL2 may be electrically connected to the second electrodes E2-1 to E2-4, respectively.

[0129] The first electrodes E1 - 1 to E1 - 5 , the second electrodes E2 - 1 to E2 - 4 , the first trace SL1 , and the second trace SL2 may be part of the first sensing conductive layer IS- CL1 or the second sensing conductive layer IS- CL2 .

[0130] The first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may include a plurality of conductive lines intersecting each other. The plurality of conductive lines may have a mesh shape defining a plurality of openings. In a plan view, the conductive lines may be Figure 5 The conductive line may overlap the pixel defining film PDL described in the embodiment of the present invention, and the opening defined by the conductive line may overlap the pixel opening OPN defined in the pixel defining film PDL.

[0131] Each of the first electrodes E1-1 to E1-5 may include a sensing portion SP1 and a middle portion CP1 extending from the sensing portion SP1 and having a shape integrated with the sensing portion SP1. That is, the sensing portion SP1 and the middle portion CP1 are integrated patterns patterned by the same process, but are described separately for convenience of description.

[0132] Each of the second electrodes E2-1 to E2-4 may include a sensing pattern SP2 and a bridge pattern CP2 (or a connection pattern). The sensing patterns SP2 may be arranged in the second direction DR2. At least one bridge pattern CP2 may be provided between adjacent sensing patterns SP2. The bridge pattern CP2 may be arranged on the first sensing insulating layer IS-IL1, and the sensing pattern SP2 may be arranged on the second sensing insulating layer IS-IL2. Two adjacent sensing patterns SP2 may be connected to the bridge pattern CP2 through a contact hole CH-1 passing through the second sensing insulating layer IS-IL2.

[0133] The first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may include a plurality of conductive lines intersecting each other. The plurality of conductive lines may define a plurality of openings, and each of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have a mesh shape. Each of the plurality of openings may be defined as Figure 5 It corresponds to the pixel opening OPN of the pixel definition film PDL shown in the figure.

[0134] The input sensing unit ISU according to the embodiment can detect the external input in a capacitive manner. For example, one of the first trace SL1 and the second trace SL2 transmits a transmission signal for detecting the external input from the external circuit, and the other of the first trace SL1 and the second trace SL2 transmits the change of the capacitance between the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 as a reception signal to the external circuit.

[0135] Figure 7 is an enlarged perspective view of a partial area of ​​a display device according to an embodiment of the present disclosure. Figure 8 It is along Figure 7 A cross-sectional view taken along line II' in FIG. Fig. 9 It is along Figure 7 A cross-sectional view taken along line II-II'. Fig.10 It is along Figure 7 A cross-sectional view taken along line III-III'.

[0136] Figure 7 is an enlarged exploded perspective view of the first pad area PA1 and the second pad area PA2 of the display device DD according to an embodiment of the present disclosure. Figure 7 The figure shows the driver chip DC and the circuit board PB removed from the display panel DP. Figure 4 The arrangement relationship and the connection relationship between the first pad area PA1 and the second pad area PA2 are described, and thus repeated descriptions thereof will be omitted.

[0137] refer to Figure 7 and Figure 8 The driving chip DC may include a base film DC-BS and a driving bump electrode DC-BP protruding from the base film DC-BS. The driving bump electrode DC-BP may include a first bump BP1 connected to the first pad PD1 in one-to-one correspondence and a second bump BP2 connected to the second pad PD2 in one-to-one correspondence.

[0138] The first film CF1 may be disposed between the driving chip DC and the first pad area PA1. According to the present disclosure, the first film CF1 may include a non-conductive film (NCF). Thus, the first film CF1 may include a synthetic resin having an adhesive property and may not include a conductive ball included in an anisotropic conductive film (ACF). The driving chip DC may include a rear surface DC-DS facing the display panel DP and an upper surface DC-US opposite to the rear surface DC-DS.

[0139] In a state in which the first film CF1 is provided, the driving chip DC may electrically connect the driving bump electrode DC-BP and the first and second pads PD1 and PD2 arranged in the first pad area PA1 through a compression process.

[0140] According to an embodiment, when a compression process is performed, a lower film PSA may be disposed on the rear surface of the display panel DP. During the compression process, the lower film PSA may protect the display panel DP from external impact applied to the display panel DP. The lower film PSA according to an embodiment may include a pressure-sensitive adhesive.

[0141] The circuit board PB may include a base layer P-BS and a plate-shaped bump electrode PB-BP mounted on the circuit board PB. The circuit board PB may include an upper surface PB-US and a lower surface PB-DS, and the lower surface PB-DS of the circuit board PB may be a surface facing the third pad PD3. The circuit board PB may provide image signals, driving voltages, and other control signals to the driving chip DC.

[0142] The plate-shaped bump electrode PB-BP may be disposed on the lower surface PB-DS of the circuit board PB. The plate-shaped bump electrode PB-BP may be connected to the third pad PD3 in a one-to-one correspondence. The second film CF2 may be disposed between the circuit board PB and the second pad area PA2. The plate-shaped bump electrode PB-BP may be connected to the third pad PD3 arranged in the second direction DR2 through a connection wiring SCLn.

[0143] According to an embodiment, the second film CF2 may include any one of an anisotropic conductive film and a non-conductive film. When the anisotropic conductive film is disposed between the circuit board PB and the second pad area PA2, the plate-shaped bump electrode PB-BP and the third pad PD3 may be electrically connected during compression through the conductive ball included in the anisotropic conductive film.

[0144] When the non-conductive film is disposed between the circuit board PB and the second pad area PA2, the shape associated with the third pad PD3 may be the same as the shape of the first pad PD1 and the shape of the second pad PD2, which will be described below.

[0145] The driving chip DC may receive the first signal through the second pad PD2 and the second bump BP2. The driving chip DC may provide the second signal generated based on the first signal to the first pad PD1 through the first bump BP1. For example, the driving chip DC may include a data driving circuit D-IC, and generate the second signal based on the first signal through the data driving circuit D-IC.

[0146] The first signal may be an image signal which is a digital signal applied from an external unit, and the second signal may be a data signal which is an analog signal. The driving chip DC may generate an analog voltage corresponding to the grayscale value of the image signal. The data signal may be provided to the pixel PX through the data line DL (see Figure 4 ).

[0147] Figure 8 The diagram shows a state in which the driving bump electrode DC-BP of the driving chip DC is in contact with the first pad PD1. The description of the first pad PD1 to be made below can also be applied to the second pad PD2 and the third pad PD3. Figure 8 For ease of description, Figure 5 The buffer layer BFL, the barrier layer BRL, the first insulating layer 10, and the second insulating layer 20 described in FIG. 1 are illustrated as an insulating layer IL.

[0148] The first pads PD1 may be arranged in the first direction DR1. In the specification, pads arranged at opposite ends in the first direction DR1 among the first pads PD1 may be defined as side pads L-PD and side pads R-PD. A pad arranged between the side pads L-PD and the side pads R-PD may be defined as a center pad C-PD. The side pads L-PD and the side pads R-PD may have a laminated structure different from that of the center pad C-PD.

[0149] In the process of compressing the driving bump electrode DC-BP and the first pad PD1, the thickness of the lower film PSA may be different in each area due to the pressure applied to the lower film PSA. For example, the following phenomenon may occur: in the process of compressing the driving bump electrode DC-BP and the first pad PD1, the lower film PSA overlapping the central portion of the first pad PD1 in the plan view is pushed toward the portion overlapping the side pad L-PD and the side pad R-PD due to the pressure. After the compression process, the display panel DP and the driving chip DC mounted on the display panel DP may be bent with a predetermined curvature relative to the first direction DR1, such as Figure 8 as shown in .

[0150] After performing the compression process, the thickness TC of the lower film PSA overlapping the central portion of the first pad PD1 in the plan view may be smaller than the thickness TS of the portion overlapping the side pads L-PD and the side pads R-PD in the plan view. In this case, when the side pads L-PD and the side pads R-PD have the same thickness as the center pad C-PD in the third direction DR3, that is, when the first pad PD1 has a constant size, the degree to which the first pad PD1 is pressed against the driving bump electrode DC-BP may be different depending on the position of the first pad PD1. Therefore, a poor connection between the driving chip DC and the first pad PD1 may result.

[0151] According to the present disclosure, the side pad L-PD and the side pad R-PD having a relatively large compression amount have greater strength and / or density than the center pad C-PD having a relatively small compression amount due to the step of the lower film PSA, and thereby the compression amount of the side pad L-PD and the side pad R-PD can be effectively reduced.

[0152] Therefore, even after the compression process, the distance DS between the side pad L-PD and the side pad R-PD and the driving bump electrode DC-BP and the distance DC between the center pad C-PD and the driving bump electrode DC-BP can also remain the same or similar (including errors in the process). Therefore, during the compression process, the compression amount for each position remains constant, and thus a display panel DP with improved bonding properties can be provided. Thus, a display device DD with improved reliability can be provided.

[0153] Fig. 9 A center pad C-PD is shown, and Fig.10 One side pad R-PD is shown.

[0154] refer to Fig. 9 , the center pad C-PD may include a first conductive pattern CL1-C, an insulating pattern PR, and a second conductive pattern CL2-C.

[0155] The first conductive pattern CL1-C may be disposed on the second insulating layer 20. According to an embodiment, the first conductive pattern CL1-C may be connected to the data line DL-E through the contact hole CT defined in the second insulating layer 20. The data line DL-E may be connected to the second insulating layer 20. Figure 4 The first conductive pattern CL1-C may include any one of the plurality of data lines DL in the Figure 5 The first conductive pattern CL1-C may include the same material as the material of the first connection electrode CNE1 described in . For example, the first conductive pattern CL1-C may include first to third conductive layers that are sequentially laminated. The first conductive layer and the third conductive layer may include titanium, and the second conductive layer may include aluminum.

[0156] The insulating pattern PR may be disposed on the first conductive pattern CL1-C. Before being compressed together with the driving bump electrode DC-BP, the insulating pattern PR may have a convex shape PP1 protruding in the third direction DR3 (see Figure 8 ). The insulating pattern PR may include a polymer. The insulating pattern PR according to an embodiment may include any one of a negative photoresist and a positive photoresist.

[0157] The second conductive pattern CL2-C may cover the insulating pattern PR and the lateral sides of the upper surfaces of the first conductive pattern CL1-C exposed from the insulating pattern PR. Figure 5 The second conductive pattern CL2-C may be made of the same material as the material of the second connection electrode CNE2 described in . For example, the second conductive pattern CL2-C may include first to third conductive layers laminated in sequence. The first conductive layer and the third conductive layer may include titanium, and the second conductive layer may include aluminum. When the compression process is performed, the second conductive pattern CL2-C may contact the driving bump electrode DC-BP.

[0158] refer to Fig.10 , the side pad R-PD may include a first conductive pattern CL1-S, a first insulating pattern PR1, a second insulating pattern PR2, and a second conductive pattern CL2-S.

[0159] The first conductive pattern CL1-S may be disposed on the second insulating layer 20. According to an embodiment, the first conductive pattern CL1-S may be connected to the data line DL-E through a contact hole CT defined in the second insulating layer 20. The data line DL-E may be connected to the second insulating layer 20. Figure 4 The first conductive pattern CL1-S may include any one of the plurality of data lines DL in the Figure 5 The first conductive pattern CL1-S may include the same material as the material of the first connection electrode CNE1 described in . For example, the first conductive pattern CL1-S may include first to third conductive layers that are sequentially laminated. The first and third conductive layers may include titanium, and the second conductive layer may include aluminum.

[0160] The first insulating pattern PR1 may be disposed on the first conductive pattern CL1-S. Before being compressed together with the driving bump electrode DC-BP, the first insulating pattern PR1 may include a protrusion pattern PP2 protruding in the third direction DR3 (see Figure 8). The plurality of lower portions of the plurality of protruding patterns PP2 may have an integrated shape in which the plurality of lower portions are connected to each other. A valley VA recessed in a direction toward the base layer BL may be defined between the plurality of protruding patterns PP2. The valley VA may be formed by patterning the first insulating pattern PR1 using a halftone mask. The first insulating pattern PR1 may include a polymer. The first insulating pattern PR1 according to an embodiment may include any one of a negative photoresist and a positive photoresist.

[0161] The second insulating pattern PR2 may be disposed on the first insulating pattern PR1. The second insulating pattern PR2 may overlap the valley VA defined in the first insulating pattern PR1 in a plan view. The second insulating pattern PR2 may include a polymer. When the first insulating pattern PR1 includes a positive photoresist, the second insulating pattern PR2 according to an embodiment may include any one of a negative photoresist and a positive photoresist. The present disclosure is not limited thereto, and when the first insulating pattern PR1 includes a negative photoresist, the second insulating pattern PR2 may include a negative photoresist.

[0162] The second conductive pattern CL2-S may cover the second insulating pattern PR2, a portion of the first insulating pattern PR1 exposed from the second insulating pattern PR2, and a lateral side of an upper surface of the first conductive pattern CL1-S exposed from the first insulating pattern PR1. Figure 5 The second conductive pattern CL2-S may be made of the same material as the material of the second connection electrode CNE2 described in . For example, the second conductive pattern CL2-S may include first to third conductive layers laminated in sequence. The first conductive layer and the third conductive layer may include titanium, and the second conductive layer may include aluminum. When the compression process is performed, the second conductive pattern CL2-S may contact the driving bump electrode DC-BP.

[0163] The first thickness TH1 of the first insulating pattern PR1 in the third direction DR3 may be greater than the second thickness TH2 of the second insulating pattern PR2 in the third direction DR3. In an embodiment, the first thickness TH1 may be the maximum thickness of the first insulating pattern PR1, and the second thickness TH2 of the second insulating pattern PR2 may be measured from the uppermost end of the first insulating pattern PR1 and may be 30% or less of the first thickness TH1 of the first insulating pattern PR1. The second thickness TH2 may be 5% or more of the first thickness TH1.

[0164] The first width CD1 of the first insulating pattern PR1 in the first direction DR1 may be in the range of about 5 μm to about 8 μm. The second width CD2 of the second insulating pattern PR2 in the first direction DR1 may be in the range of about 1 μm to about 4 μm. The first width CD1 may be greater than the second width CD2.

[0165] According to an embodiment, the side pads R-PD and the side pads L-PD arranged at opposite ends in the first direction DR1 among the first pads PD1 include the first insulating pattern PR1 and the second insulating pattern PR2 laminated in sequence, and thus may have a strength and / or density greater than that of the center pad C-PD arranged between the side pads R-PD and the side pads L-PD. Therefore, the compression amount of the side pads R-PD and the compression amount of the side pads L-PD caused by the step of the lower film PSA during compression can be effectively reduced.

[0166] Fig.11 is a cross-sectional view of a side pad according to an embodiment of the present disclosure. Fig.12 is a cross-sectional view of a side pad according to an embodiment of the present disclosure. Fig.13 is a cross-sectional view of a side pad according to an embodiment of the present disclosure. Figures 7 to 10 The same / similar components described in the drawings will be described herein and their repeated description will be omitted.

[0167] refer to Fig.11 , the side pad R-PD1 may include a first conductive pattern CL1-S, a first insulating pattern PR1, a second insulating pattern PR2, a third insulating pattern PR3, and a second conductive pattern CL2-S.

[0168] The first conductive pattern CL1-S may be disposed on the second insulating layer 20. According to an embodiment, the first conductive pattern CL1-S may be connected to the data line DL-E through a contact hole CT defined in the second insulating layer 20.

[0169] The first insulating pattern PR1 may be disposed on the first conductive pattern CL1-S. Before being compressed together with the driving bump electrode DC-BP, the first insulating pattern PR1 may include a protrusion pattern PP2 protruding in the third direction DR3 (see Figure 8 ). The plurality of lower portions of the plurality of protruding patterns PP2 may have an integrated shape in which the plurality of lower portions are connected to each other. At least one valley VA1 recessed in a direction toward the base layer BL may be defined between the plurality of protruding patterns PP2. According to an embodiment, the first insulating pattern PR1 may include three protruding patterns PP2, and two valleys VA1 may be defined between the three protruding patterns PP2.

[0170] The valley VA1 may be formed by patterning the first insulating pattern PR1 using a half-tone mask. The first insulating pattern PR1 may include a polymer.

[0171] The second insulating pattern PR2 may be disposed on the first insulating pattern PR1. The second insulating pattern PR2 may include a sub-protruding pattern PP-S overlapping the valley VA1 defined in the first insulating pattern PR1 in a plan view. The plurality of lower portions of the plurality of sub-protruding patterns PP-S may have an integrated shape in which the plurality of lower portions are connected to each other. At least one sub-valley VA2 recessed in a direction toward the base layer BL may be defined between the plurality of sub-protruding patterns PP-S. According to an embodiment, the second insulating pattern PR2 may include two sub-protruding patterns PP-S, and one sub-valley VA2 may be defined between the two sub-protruding patterns PP-S.

[0172] The third insulating pattern PR3 may be disposed on the second insulating pattern PR2. The third insulating pattern PR3 may overlap the sub-valley VA2 defined in the second insulating pattern PR2 in a plan view. The third insulating pattern PR3 may have a polymer.

[0173] The second conductive pattern CL2-S may cover the third insulating pattern PR3, a portion of the second insulating pattern PR2 exposed from the third insulating pattern PR3, a portion of the first insulating pattern PR1 exposed from the second insulating pattern PR2, and a lateral side of an upper surface of the first conductive pattern CL1-S exposed from the first insulating pattern PR1. Figure 5 The material of the second connection electrode CNE2 described in .

[0174] refer to Fig.12 , the side pad R-PD2 may include a first conductive pattern CL1-S, a first insulating pattern PR1, and a second insulating pattern PR2.

[0175] The first insulating pattern PR1 may be disposed on the second insulating layer 20. Before being compressed together with the driving bump electrode DC-BP, the first insulating pattern PR1 may include a protrusion pattern PP2 protruding in the third direction DR3 (see Figure 8 ). The plurality of lower portions of the plurality of protruding patterns PP2 may have an integrated shape in which the plurality of lower portions are connected to each other. A valley VA recessed in a direction toward the base layer BL may be defined between the plurality of protruding patterns PP2. The valley VA may be formed by patterning the first insulating pattern PR1 using a half-tone mask. The first insulating pattern PR1 may include a polymer.

[0176] The second insulating pattern PR2 may be disposed on the first insulating pattern PR1. The second insulating pattern PR2 may overlap the valley VA defined in the first insulating pattern PR1 in a plan view. The second insulating pattern PR2 may include a polymer.

[0177] The first conductive pattern CL1-S may cover the second insulating pattern PR2, a portion of the first insulating pattern PR1 exposed from the second insulating pattern PR2, and a portion of the second insulating layer 20. Figure 5 The material of the first connection electrode CNE1 described in the above is the same as the material of the first connection electrode CNE1 described in the above. Fig.10 The second conductive pattern CL2-S described in .

[0178] Fig.13 The main focus will be on describing Fig.12 Reference Fig.13 , the side pad R-PD3 may include a first insulating pattern PR1, a second insulating pattern PR2, a first conductive pattern CL1-S, and a second conductive pattern CL2-S.

[0179] The first insulating pattern PR1 may be disposed on the second insulating layer 20. The second insulating pattern PR2 may be disposed on the first insulating pattern PR1. The first conductive pattern CL1-S may cover the second insulating pattern PR2, a portion of the first insulating pattern PR1 exposed from the second insulating pattern PR2, and a portion of the second insulating layer 20. According to an embodiment, the second conductive pattern CL2-S may cover the first conductive pattern CL1-S.

[0180] FIG. 14A to FIG. 14G is a cross-sectional view illustrating a method of manufacturing a display panel according to an embodiment of the present disclosure.

[0181] refer to Fig.14A The method may include an operation of forming a first polymer PR1-A on a preliminary substrate. The preliminary substrate may be arranged in a state where a first polymer PR1-A is formed. Figure 5 The state of the buffer layer BFL, the barrier layer BRL, the first insulating layer 10 and the second insulating layer 20, and the first central conductive pattern CL1-C and the first side conductive pattern CL1-S on the base layer BL described in the above description. The first central conductive pattern CL1-C and the first side conductive pattern CL1-S may be formed on the second insulating layer 20 and spaced apart from each other. The first polymer PR1-A may be formed on the second insulating layer 20 and cover the first central conductive pattern CL1-C and the first side conductive pattern CL1-S. The first polymer PR1-A may include any one of a negative photoresist and a positive photoresist.

[0182] Afterwards, refer to Fig. 14B The method may include an operation of patterning the first polymer PR1-A. The operation of patterning the first polymer PR1-A may be performed using a first mask MS1 in a photoresist process.

[0183] The half-tone mask MS-H may be disposed on the first side conductive pattern CL1-S disposed at opposite ends among the first center conductive pattern CL1-C and the first side conductive pattern CL1-S, and the normal mask MS-N may be disposed on the first center conductive pattern CL1-C disposed between the plurality of first side conductive patterns CL1-S. The half-tone mask MS-H may include a plurality of slits SL spaced apart from each other. A mask opening M-OP may be defined between the plurality of slits SL.

[0184] When a photoresist process is performed on the first polymer PR1-A through the first mask MS1, the first insulating pattern PR1 may be formed on the first side conductive pattern CL1-S, and the insulating pattern PR may be formed on the first center conductive pattern CL1-C. The insulating pattern PR may have a convex shape protruding in the thickness direction (i.e., the third direction DR3). A protruding pattern protruding in the third direction DR3 may be formed in the first insulating pattern PR1. A plurality of lower portions of the plurality of protruding patterns may have an integrated shape in which the plurality of lower portions are connected to each other. A valley VA recessed in a direction toward the base layer BL may be defined between the plurality of protruding patterns.

[0185] Afterwards, refer to Fig. 14C , the method may include an operation of forming a second polymer PR2-A on the second insulating layer 20. The second polymer PR2-A may cover the first insulating pattern PR1 and the insulating pattern PR. When the first polymer PR1-A includes a positive photoresist, the second polymer PR2-A may include a positive photoresist.

[0186] Afterwards, refer to Fig.14D The method may include an operation of patterning the second polymer PR2-A. The operation of patterning the second polymer PR2-A may be performed using a second mask MS2 in a photoresist process.

[0187] The second mask MS2 may be disposed only on the first insulating pattern PR1. Therefore, the second insulating pattern PR2 overlapping the valley VA in a plan view may be formed on the first insulating pattern PR1. The second polymer PR2-A disposed on the insulating pattern PR may be removed.

[0188] Afterwards, refer to Fig.14E , the method may include an operation of forming a second center conductive pattern CL2-C and a second side conductive pattern CL2-S. Figure 5The second central conductive pattern CL2-C and the second side conductive pattern CL2-S are formed in the same process as the manufacturing process of the second connection electrode CNE2 described in . Each of the plurality of second central conductive patterns CL2-C may cover the insulating pattern PR. A portion of the second central conductive pattern CL2-C may contact the first central conductive pattern CL1-C. Each of the plurality of second side conductive patterns CL2-S may cover the second insulating pattern PR2 and a portion of the first insulating pattern PR1 exposed from the second insulating pattern PR2. A portion of the second side conductive pattern CL2-S may contact the first side conductive pattern CL1-S.

[0189] Each of the side pads L-PD and the side pads R-PD may include a first side conductive pattern CL1-S, a first insulating pattern PR1, a second insulating pattern PR2, and a second side conductive pattern CL2-S, and each of the multiple center pads C-PD may include a first center conductive pattern CL1-C, an insulating pattern PR, and a second center conductive pattern CL2-C.

[0190] Afterwards, refer to Fig.14F , the method may include the operation of arranging the driving bump electrode DC-BP and the side pad L-PD, the side pad R-PD and the center pad C-PD of the driving chip DC. The driving chip DC may include a driving bump electrode DC-BP protruding from the lower surface of the driving chip DC. The driving bump electrode DC-BP may correspond to the pad side L-PD, the side pad R-PD and the center pad C-PD in a one-to-one correspondence. That is, the driving bump electrode DC-BP may overlap with the side pad L-PD, the side pad R-PD and the center pad C-PD in a one-to-one correspondence in a plan view. The non-conductive film CF may be disposed between the driving bump electrode DC-BP and the side pad L-PD, the side pad R-PD and the center pad C-PD.

[0191] Afterwards, refer to Figure 14G , the method may include an operation of compressing the driving bump electrode DC-BP and the side pads L-PD, the side pads R-PD, and the center pad C-PD. Before the compression process, the lower film PSA may be attached to the lower surface of the base layer BL. The lower film PSA may protect the components arranged on the base layer BL from external impact. The lower film PSA according to an embodiment may include a pressure-sensitive adhesive.

[0192] During the compression process, in the process of compressing the driving bump electrode DC-BP and the side pads L-PD, the side pads R-PD and the center pad C-PD, the thickness of the lower film PSA may be different in each area due to the pressure applied to the lower film PSA. For example, the following phenomenon may occur: in the process of compressing the driving bump electrode DC-BP and the side pads L-PD, the side pads R-PD and the center pad C-PD, the lower film PSA overlapping the central part of the center pad C-PD in the plan view is pushed to the part overlapping the side pads L-PD and the side pads R-PD due to the pressure. After the compression process, the section from the base layer BL to the driving chip DC can be bent with a predetermined curvature relative to the first direction DR1.

[0193] After performing the compression process, a thickness TC of the lower film PSA overlapping the central portion of the center pad C-PD in a plan view may be smaller than a thickness TS of a portion overlapping the side pads L-PD and R-PD in a plan view.

[0194] In the method for manufacturing a display device according to the present disclosure, the side pad L-PD and the side pad R-PD may include a laminated first insulating pattern PR1 and a laminated second insulating pattern PR2, and thus have a strength and / or density greater than that of the center pad C-PD. Therefore, the compression amount of the side pad L-PD and the compression amount of the side pad R-PD can be reduced, and the reliability of the process of compressing the driving bump electrode DC-BP and the side pad L-PD, the side pad R-PD and the center pad C-PD can be effectively increased.

[0195] According to an embodiment of the present disclosure, a display panel having improved bonding properties can be provided by maintaining a constant compression amount at each position during a compression process. Therefore, a display device having improved reliability can be provided.

[0196] Although the above has been described with reference to the embodiments of the present disclosure, it will be appreciated that the present disclosure may be modified and altered in various ways by those skilled in the art or those of ordinary skill in the art without departing from the spirit and technical scope of the present disclosure described in the appended claims.

[0197] Therefore, the technical scope of the present disclosure is not limited to the detailed description of the specification but should be defined by the accompanying claims.

Claims

1. A display device, comprising: a base layer, the base layer comprising a display area and a non-display area adjacent to the display area; a plurality of insulating layers, the plurality of insulating layers being disposed on the base layer; A plurality of pixels, wherein the plurality of pixels are arranged in the display area; a plurality of pads connected to the plurality of pixels, arranged in a first direction and disposed in the non-display area; as well as a driving chip connected to the plurality of pads, Wherein, each of the plurality of side pads arranged at opposite ends in the first direction among the plurality of pads comprises: a first conductive pattern; a first insulating pattern including a plurality of protrusion patterns protruding in a direction toward the driving chip; and A second insulating pattern is disposed on the first insulating pattern.

2. The display device according to claim 1, wherein: The plurality of protruding patterns have an integrated shape, and the plurality of lower portions of the plurality of protruding patterns are connected in the integrated shape, A valley recessed in a direction toward the base layer is defined between the plurality of protruding patterns, and The second insulating pattern overlaps the valley in a plan view.

3. The display device according to claim 1, wherein: defining two valleys recessed in a direction toward the base layer between the plurality of protruding patterns, The second insulating pattern further includes: a plurality of sub-protruding patterns that protrude in the direction toward the driving chip and overlap the two valleys, respectively, in a plan view. A sub-valley recessed in the direction toward the base layer is defined between the plurality of sub-protrusion patterns, and Each of the plurality of side pads further includes a third insulation pattern disposed on the second insulation pattern and overlapping the one sub-valley in the plan view.

4. The display device according to claim 1, wherein: Each of the plurality of side pads further includes a second conductive pattern covering the second insulating pattern and a portion of the first insulating pattern exposed from the second insulating pattern.

5. The display device according to claim 4, wherein: The second conductive pattern includes: a first conductive layer, a second conductive layer, and a third conductive layer, the first conductive layer, the second conductive layer, and the third conductive layer are sequentially laminated, and The first conductive layer and the third conductive layer include titanium, and the second conductive layer includes aluminum.

6. The display device according to claim 1, wherein: The first conductive pattern covers the second insulating pattern and a portion of the first insulating pattern exposed from the second insulating pattern.

7. The display device according to claim 1, wherein: The first conductive pattern covers the second insulating pattern and a portion of the first insulating pattern exposed from the second insulating pattern, and Each of the plurality of side pads further includes a second conductive pattern covering the first conductive pattern.

8. The display device according to claim 1, wherein: The first insulating pattern includes a positive photoresist, and the second insulating pattern includes one of the positive photoresist and a negative photoresist.

9. The display device according to claim 1, wherein: The first insulating pattern includes a negative photoresist, and the second insulating pattern includes the negative photoresist.

10. The display device according to claim 1, wherein: The first insulating pattern and the second insulating pattern include a polymer.

11. The display device according to claim 1, wherein: Each of a plurality of center pads arranged between the plurality of side pads among the plurality of pads includes: a third conductive pattern; an insulating pattern having a convex shape protruding in the direction toward the driving chip; and A fourth conductive pattern covers the insulating pattern.

12. The display device according to claim 1, wherein: The plurality of insulating layers include: a barrier layer, the barrier layer being disposed on the base layer; a buffer layer disposed on the barrier layer; and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer are arranged on the buffer layer, and Each of the third to fifth insulating layers exposes the second insulating layer in the non-display area, and the first conductive pattern is disposed on the second insulating layer.

13. The display device according to claim 12, further comprising: a plurality of data lines, the plurality of data lines being configured to connect the plurality of pixels and the plurality of pads, being disposed on the first insulating layer and being covered by the second insulating layer, The first conductive patterns are arranged in a plurality of contact holes passing through the second insulating layer and connected to the plurality of data lines.

14. The display device according to claim 12, further comprising: a first connection electrode disposed on the second insulating layer, disposed in a contact hole passing through the first insulating layer and the second insulating layer, and electrically connected to a semiconductor pattern included in each of the plurality of pixels; as well as a second connection electrode, the second connection electrode being disposed on the fourth insulating layer, disposed in a contact hole passing through the third insulating layer and the fourth insulating layer and connected to the first connection electrode, Wherein, each of the plurality of pixels comprises: a transistor including the semiconductor pattern disposed on the buffer layer and a gate region disposed on the first insulating layer; and A light emitting element is electrically connected to the semiconductor pattern through the first connection electrode and the second connection electrode.

15. The display device according to claim 14, wherein: The first connection electrode and the first conductive pattern include the same material.

16. The display device according to claim 1, wherein: A non-conductive film is disposed between the driving chip and the plurality of pads.

17. The display device according to claim 16, wherein: The driver chip comprises: basement membrane; and A plurality of bumps protrude from the base film and are connected to the plurality of pads.

18. The display device according to claim 1, wherein: The plurality of pads and the driving chip are bent with a predetermined curvature with respect to the first direction.

19. The display device according to claim 1, wherein: In the first direction, a width of the first insulating pattern is in a range of 5 μm to 8 μm, and a width of the second insulating pattern is in a range of 1 μm to 4 μm.

20. The display device according to claim 1, wherein: A thickness of the second insulation pattern measured from an uppermost end of the first insulation pattern is 30% or less of a maximum thickness of the first insulation pattern.

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