Display substrate and display device

Abstract

The invention relates to a display substrate and a display device. The display substrate comprises a first display area and a second display area, the first display area is adjacent to the second display area, and the light transmittance of the first display area is larger than that of the second display area. The plurality of first sub-pixels are located in the first display area and are divided into a plurality of sub-pixel groups, each sub-pixel group comprises at least two adjacent first sub-pixels in the row direction, and each first sub-pixel in the plurality of first sub-pixels comprises a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. The plurality of power lines are connected to the plurality of first sub-pixels, including first power lines extending in the row direction and connected to the pixel circuits of the first sub-pixels located in the row direction, and second power lines extending in the column direction and connected to the pixel circuits of the first sub-pixels located in the column direction, the row direction and the column direction crossing each other. According to the technical scheme, the number of power lines can be reduced, and the light transmittance of the first display area can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In the related art, organic light emitting diode (OLED) display substrates are widely used in the fields of smart phones, televisions, VR (Virtual Reality) devices, and wearable devices due to their excellent display effects, thinness, flexibility, excellent shock resistance, and suitability for wearable products. With the increasing screen-to-body ratio of display substrates on mobile phones and other terminal devices that require cameras, setting a camera under the display substrate is one of the best solutions to meet this demand. Setting a camera under the display substrate puts higher requirements on the performance of the display substrate, especially the transmittance. The high transmittance of the area on the display substrate used to enable the camera to take pictures is a basic condition for the application of this solution. Therefore, how to improve the transmittance of the display substrate is a technical problem that needs to be solved. Summary of the invention

[0003] The present invention provides a display substrate and a display device to solve the deficiencies in the related art.

[0004] According to a first aspect of an embodiment of the present invention, there is provided a display substrate, comprising a display area, wherein the display area comprises a first display area and a second display area, the first display area and the second display area are adjacent to each other, and the transmittance of the first display area is greater than the transmittance of the second display area;

[0005] A plurality of first sub-pixels, located in the first display area, the plurality of first sub-pixels are divided into a plurality of sub-pixel groups, each of the sub-pixel groups includes at least two first sub-pixels adjacent to each other in a row direction, and each of the plurality of first sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light;

[0006] A plurality of power lines are connected to the plurality of first sub-pixels, the plurality of power lines include a first power line and a second power line, the first power line extends along a row direction and is connected to the pixel circuit of the first sub-pixel located in the row direction, the second power line extends along a column direction and is connected to the pixel circuit of the first sub-pixel located in the column direction, and the row direction and the column direction intersect.

[0007] In one embodiment, in the same row of sub-pixel groups, a distance between two adjacent sub-pixel groups is greater than or equal to a width of one of the sub-pixel groups in the same row in the row direction;

[0008] In the same column of sub-pixel groups, a distance between two adjacent sub-pixel groups is greater than or equal to a length of one of the sub-pixel groups in the same column in a column direction.

[0009] In one embodiment, the orthogonal projection of the i+2th row of subpixel groups in the plurality of subpixel groups on the i-th row of subpixel groups is outside the orthogonal projection of the i+1th row of subpixel groups on the i-th row of subpixel groups, the orthogonal projection of the i+3th row of subpixel groups on the i-th row of subpixel groups coincides with the orthogonal projection of the i+1th row of subpixel groups on the i-th row of subpixel groups, and the orthogonal projection of the i+3th row of subpixel groups on the i-th row of subpixel groups is outside the orthogonal projection of the i+2th row of subpixel groups on the i-th row of subpixel groups, where i is a positive integer;

[0010] The orthogonal projection of the j+2th column sub-pixel group on the jth column sub-pixel group is outside the orthogonal projection of the j+1th column sub-pixel group on the jth column sub-pixel group, the orthogonal projection of the j+3th column sub-pixel group on the jth column sub-pixel group coincides with the orthogonal projection of the j+1th column sub-pixel group on the jth column sub-pixel group, and the orthogonal projection of the j+3th column sub-pixel group on the jth column sub-pixel group is outside the orthogonal projection of the j+2th column sub-pixel group on the jth column sub-pixel group, where j is a positive integer.

[0011] In one embodiment, the pixel circuits of the first sub-pixels in the same sub-pixel group are connected to the same first power line, and the same first power line is connected to the pixel circuits of the first sub-pixels in two adjacent rows of sub-pixel groups.

[0012] In one embodiment, the number of the second power lines connected to a sub-pixel group is less than the number of columns of the first sub-pixels in the same sub-pixel group.

[0013] In one embodiment, the number of the second power lines is equal to the number of columns of the sub-pixel groups;

[0014] The pixel circuits of the first sub-pixels in the sub-pixel group in the same column are connected to the same second power line.

[0015] In one embodiment, each of the sub-pixel groups includes three first sub-pixels arranged sequentially along the row direction, the first power line is connected to the three first sub-pixels at the same time, and the second power line is connected to the first sub-pixel located in the middle of the three first sub-pixels.

[0016] In one embodiment, a plurality of the first power lines and a plurality of the second power lines form a mesh structure.

[0017] In one embodiment, the three first sub-pixels include a red sub-pixel, a blue sub-pixel, and a green sub-pixel.

[0018] In one embodiment, the plurality of power lines further include a third power line, the third power line being connected to at least one of the first power line and the second power line;

[0019] The number of the third power lines is the same as the number of the sub-pixel groups, and the pixel circuit of the first sub-pixel in each sub-pixel group is connected to the same third power line.

[0020] In one embodiment, when the third power line is connected to the first power line and the second power line, the third power line includes a first conductive portion and a second conductive portion, the first conductive portion is connected to the second conductive portion, the first conductive portion extends in a row direction, and the second conductive portion extends in a column direction; the first power line includes a third conductive portion, the third conductive portion extends in a row direction; the second power line extends in a column direction; the first conductive portion is connected to the third conductive portion, and the second power line is connected to the first conductive portion or the second conductive portion;

[0021] When the third power line is connected to the first power line, the third power line includes a first conductive portion extending in a row direction, the first power line includes a third conductive portion extending in a row direction; the first conductive portion is connected to the third conductive portion.

[0022] In one embodiment, the sum of the number of the first power lines and the number of the second power lines is less than the sum of the number of rows and the number of columns of the array formed by the plurality of first sub-pixels.

[0023] In one embodiment, the sum of the number of the first power lines connected to each of the sub-pixel groups and the number of the second power lines is less than the sum of the number of rows and the number of columns corresponding to each of the sub-pixel groups.

[0024] In one embodiment, the number of the first power lines is equal to the number of rows of the array formed by the plurality of first sub-pixels;

[0025] The pixel circuits of the first sub-pixels in the sub-pixel group in the same row are only connected to the same first power line, and the same first power line is only connected to the pixel circuits of the first sub-pixels in the sub-pixel group in the same row.

[0026] In one embodiment, the number of the second power lines is less than the number of columns of the array.

[0027] In one embodiment, the number of the second power lines is equal to 1 / 3 times the number of columns of the array, and the number of the second power lines is equal to the number of columns of the sub-pixel groups;

[0028] The pixel circuits of the first sub-pixels in the sub-pixel group in the same column are connected to the same second power line, and the same second power line is connected to the pixel circuits of the first sub-pixels in the sub-pixel group in the same column.

[0029] In one embodiment, the second display area includes a plurality of second sub-pixels, and the plurality of second sub-pixels are arranged in an array along a row direction and a column direction;

[0030] The density of the first sub-pixels in the first display area is smaller than the density of the second sub-pixels in the second display area.

[0031] In one embodiment, the plurality of power lines further include a fourth power line and a fifth power line, the fourth power line is configured to be connected to the pixel circuits of the second sub-pixels arranged along the row direction, and the fifth power line is configured to be connected to the pixel circuits of the second sub-pixels arranged along the column direction;

[0032] The density of the power lines in the first display area is less than the density of the power lines in the second display area.

[0033] The present application also provides a display device, which includes a photosensitive element and the above-mentioned display substrate, wherein the projection of the photosensitive element on the display substrate is located in the first display area.

[0034] In one embodiment, the photosensitive element is an image sensor, an ambient light sensor or a distance sensor.

[0035] According to the above embodiment, since the multiple power lines in the first display area include at least one of the first power line and the second power line, and the sum of the number of the first power lines and the number of the second power lines is less than the sum of the number of rows and the number of columns of the array formed by the first sub-pixels, wherein the first power line is configured to be connected to the pixel circuit of the first sub-pixels arranged along the row direction, and the second power line is configured to be connected to the pixel circuit of the first sub-pixels arranged along the column direction, therefore, there is at least one row of first sub-pixels in which the first power line is not arranged near or at least one column of first sub-pixels in which the second power line is not arranged near, thereby reducing the number of power lines and the area occupied, which is beneficial to improving the light transmittance of the first display area.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0038] Figure 1is a schematic structural diagram of a display substrate according to an embodiment of the present invention;

[0039] Figure 2 is a schematic structural diagram of another display substrate according to an embodiment of the present invention;

[0040] Figure 3 is a schematic structural diagram of another display substrate according to an embodiment of the present invention;

[0041] Figure 4 is a schematic structural diagram of another display substrate according to an embodiment of the present invention;

[0042] Figure 5 is a structural schematic diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present invention;

[0043] Figures 6 to 14 is a schematic structural diagram of each layer of a pixel circuit according to an embodiment of the present invention;

[0044] Fig.15 is a schematic diagram of the structure of a power line according to an embodiment of the present invention;

[0045] Fig.16 is a schematic structural diagram of another display substrate according to an embodiment of the present invention;

[0046] Fig.17 is a schematic structural diagram of another display substrate according to an embodiment of the present invention;

[0047] Fig.18 is a schematic structural diagram of another display substrate according to an embodiment of the present invention;

[0048] Fig.19 is a schematic structural diagram of another display substrate according to an embodiment of the present invention;

[0049] Fig. 20 FIG. 4 is a schematic structural diagram of another display substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0051] An embodiment of the present invention provides a display substrate. The display substrate 1, such as Figure 1As shown, the display area 11 includes a first display area 111 and a second display area 112 . The light transmittance of the first display area 111 is greater than that of the second display area 112 .

[0052] In this embodiment, if Figures 2 to 12 As shown, the display substrate 1 includes: a plurality of first sub-pixels 21 and a plurality of power lines VDD.

[0053] In this embodiment, a plurality of first sub-pixels 21 and a plurality of power lines VDD are located in the first display area 111. The plurality of first sub-pixels 21 are arranged in an array along the row direction X and the column direction Y. The first sub-pixels 21 include a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. A plurality of power lines 22 are connected. The plurality of power lines 22 include at least one of a first power line 221 and a second power line 222. The first power line 221 is configured to be connected to the pixel circuit of the first sub-pixels 21 arranged along the row direction X, and the second power line 222 is configured to be connected to the pixel circuit of the first sub-pixels 21 arranged along the column direction Y. The sum of the number of the first power lines 221 and the number of the second power lines 222 is less than the sum of the number of rows and the number of columns of the above-mentioned array.

[0054] In the present embodiment, since the plurality of power lines in the first display area 111 include at least one of the first power line 221 and the second power line 222, and the sum of the number of the first power lines 221 and the number of the second power lines 222 is less than the sum of the number of rows and the number of columns of the array formed by the first sub-pixels 21, wherein the first power line 221 is configured to be connected to the pixel circuit of the first sub-pixels 21 arranged along the row direction X, and the second power line 222 is configured to be connected to the pixel circuit of the first sub-pixels 21 arranged along the column direction Y, there is at least one row of first sub-pixels 21 near which the first power line 221 is not arranged or at least one column of first sub-pixels 21 near which the second power line 222 is not arranged, thereby reducing the number of power lines and the area occupied, which is beneficial to improving the light transmittance of the first display area 111.

[0055] The display substrate provided by the embodiment of the present invention is briefly introduced above. The display substrate provided by the embodiment of the present invention is introduced in detail below.

[0056] The embodiment of the present invention further provides a display substrate. Figure 1 As shown, the display substrate includes a display area, and the display area includes a first display area 111 and a second display area 112 . The light transmittance of the first display area 111 is greater than the light transmittance of the second display area 112 .

[0057] In this embodiment, if Figure 2 to Figure 4As shown, the display substrate includes a plurality of first sub-pixels 21 and a plurality of power lines 22. The plurality of first sub-pixels 21 and the plurality of power lines 22 are located in the first display area 111.

[0058] In this embodiment, if Figure 2 and Figure 4 As shown, a plurality of first sub-pixels 21 are arranged in an array along the row direction X and the column direction Y. Each first sub-pixel 21 includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light. The pixel circuit may include a transistor and may also include a capacitor. The pixel circuit may be a 1T pixel circuit, a 2T1C pixel circuit, a 3T1C pixel circuit, a 4T1C pixel circuit, a 5T1C pixel circuit or a 7T1C pixel circuit. In this embodiment, the pixel circuit is a 7T1C pixel circuit as an example for illustration.

[0059] In this embodiment, if Figure 2 and Figure 4 As shown, the plurality of first sub-pixels 21 are divided into a plurality of sub-pixel groups 31 , each sub-pixel group 31 includes two first sub-pixels 21 adjacent to each other in the row direction X and two first sub-pixels 21 adjacent to each other in the column direction Y. That is, each sub-pixel group 31 includes four first sub-pixels 21 .

[0060] In this embodiment, if Figure 2 As shown, each subpixel group 31 includes a red subpixel 211, two green subpixels 212 and a blue subpixel 213. In each subpixel group 31, the red subpixel 211 and the blue subpixel 213 may be located in the same column, and the two green subpixels 212 may be located in the same column, but not limited thereto.

[0061] In the present embodiment, the second display area 112 includes a plurality of second sub-pixels, and the plurality of second sub-pixels are arranged in an array along the row direction X and the column direction Y. The density of the first sub-pixels 21 in the first display area 111 is less than the density of the second sub-pixels in the second display area 112. For example, the density of the first sub-pixels 21 in the first display area 111 may be 1 / 2 of the density of the second sub-pixels in the second display area 112.

[0062] In this embodiment, if Figure 2 As shown, in the same row of sub-pixel groups 31, the spacing S1 between two adjacent sub-pixel groups 31 is greater than the width W of the sub-pixel group 31 in the row direction X. Of course, in other embodiments, in the same row of sub-pixel groups 31, the spacing S1 between two adjacent sub-pixel groups 31 may also be equal to the width W of the sub-pixel group 31 in the row direction X. In this way, the light transmittance of the first display area 111 can be improved.

[0063] In this embodiment, if Figure 2As shown, in the same column of sub-pixel groups 31, the spacing S2 between two adjacent sub-pixel groups 31 is equal to the length L of the sub-pixel group 31 in the column direction Y. In other embodiments, in the same column of sub-pixel groups 31, the spacing S2 between two adjacent sub-pixel groups 31 may also be greater than the length L of the sub-pixel group 31 in the column direction Y. In this way, the light transmittance of the first display area 111 can be improved.

[0064] In this embodiment, if Figure 2 and Figure 4 As shown, the orthogonal projection of the i+2th row sub-pixel group 31 on the i-row sub-pixel group 31 is outside the orthogonal projection of the i+1th row sub-pixel group 31 on the i-row sub-pixel group 31, the orthogonal projection of the i+3th row sub-pixel group 31 on the i-row sub-pixel group 31 coincides with the orthogonal projection of the i+1th row sub-pixel group 31 on the i-row sub-pixel group 31, and the orthogonal projection of the i+3th row sub-pixel group 31 on the i-row sub-pixel group 31 is outside the orthogonal projection of the i+2th row sub-pixel group 31 on the i-row sub-pixel group 31, and i is a positive integer.

[0065] For example, when i is 1, the orthogonal projection of the 3rd row sub-pixel group 31 on the 1st row sub-pixel group 31 is outside the orthogonal projection of the 2nd row sub-pixel group 31 on the 1st row sub-pixel group 31, the orthogonal projection of the 4th row sub-pixel group 31 on the 1st row sub-pixel group 31 coincides with the orthogonal projection of the 2nd row sub-pixel group 31 on the 1st row sub-pixel group 31, and the orthogonal projection of the 4th row sub-pixel group 31 on the 1st row sub-pixel group 31 is outside the orthogonal projection of the 3rd row sub-pixel group 31 on the 1st row sub-pixel group 31.

[0066] In this embodiment, if Figure 2 and Figure 4 As shown, the orthogonal projection of the j+2th column sub-pixel group 31 on the jth column sub-pixel group 31 is outside the orthogonal projection of the j+1th column sub-pixel group 31 on the jth column sub-pixel group 31, the orthogonal projection of the j+3th column sub-pixel group 31 on the jth column sub-pixel group 31 coincides with the orthogonal projection of the j+1th column sub-pixel group 31 on the jth column sub-pixel group 31, and the orthogonal projection of the j+3th column sub-pixel group 31 on the jth column sub-pixel group 31 is outside the orthogonal projection of the j+2th column sub-pixel group 31 on the jth column sub-pixel group 31, and j is a positive integer.

[0067] For example, when j is 1, the orthogonal projection of the 3rd column sub-pixel group 31 on the 1st column sub-pixel group 31 is outside the orthogonal projection of the 2nd column sub-pixel group 31 on the 1st column sub-pixel group 31, the orthogonal projection of the 4th column sub-pixel group 31 on the 1st column sub-pixel group 31 coincides with the orthogonal projection of the 2nd column sub-pixel group 31 on the 1st column sub-pixel group 31, and the orthogonal projection of the 4th column sub-pixel group 31 on the 1st column sub-pixel group 31 is outside the orthogonal projection of the 3rd column sub-pixel group 31 on the 1st column sub-pixel group 31.

[0068] In this embodiment, if Figure 3 and Figure 4 As shown, a plurality of power lines 22 are connected. In this way, the resistance of the power lines can be reduced, and thus the voltage drop of the power voltage in the column direction Y can be reduced.

[0069] In this embodiment, if Figure 3 and Figure 4 As shown, the plurality of power lines 22 include a first power line 221 , a second power line 222 and a third power line 223 . The first power line 221 , the second power line 222 and the third power line 223 are located in the first display area 111 .

[0070] In this embodiment, if Figure 3 and Figure 4 As shown, the first power lines 221 are configured to be connected to the pixel circuits of the first sub-pixels 21 arranged along the row direction X. In this embodiment, the number of the first power lines 221 is less than the number of rows of the array, and the number of the first power lines 221 is equal to 0.25 times the number of rows of the array, and the number of the first power lines 221 is equal to 0.5 times the number of sub-pixel groups 31. For example, Figure 2 , 8 rows of first sub-pixels 21 , 4 rows of sub-pixel groups 31 , and 2 first power lines 221 are shown.

[0071] In this embodiment, if Figure 4 As shown, the pixel circuits of the four first sub-pixels 21 in the same sub-pixel group 31 are only connected to the same first power line 221, and the same first power line 221 is connected to the pixel circuits of the first sub-pixels 21 in two adjacent rows of sub-pixel groups 31, that is, the same first power line 221 is connected to the pixel circuits of the first sub-pixels 21 in four adjacent rows.

[0072] In this embodiment, if Figure 4 As shown, the second power lines 222 are configured to be connected to the pixel circuits of the first sub-pixels 21 arranged along the column direction Y. In this embodiment, the number of the second power lines 222 is less than the number of columns of the array, and the number of the second power lines 222 is equal to 0.5 times the number of columns of the array, and the number of the second power lines 222 is equal to the number of columns of the sub-pixel group 31. For example, Figure 4 , 8 columns of first sub-pixels 21 , 4 columns of sub-pixel groups 31 , and 4 second power lines 222 are shown.

[0073] In this embodiment, if Figure 3 and Figure 4 As shown, the pixel circuits of the four first sub-pixels 21 in the same column of the sub-pixel group 31 are connected to the same second power line 222. The same second power line 222 is connected to the pixel circuits of the four first sub-pixels 21 in the same column of the sub-pixel group 31.

[0074] In this embodiment, if Figure 3 and Figure 4 As shown, the third power line 223 is connected to the first power line 221 and the second power line 222, the number of the third power lines 223 is the same as the number of the sub-pixel groups 31, and the pixel circuits of the four first sub-pixels 21 in each sub-pixel group 31 are connected to the same third power line 223. The third power line 223 may be in a ring shape, for example, a rectangular ring shape, but is not limited thereto.

[0075] In this embodiment, if Figure 3 As shown, the third power line 223 includes a first conductive portion E1 and a second conductive portion E2. The first conductive portion E1 is connected to the second conductive portion E2, the first conductive portion E1 extends along the row direction X, and the second conductive portion E2 extends along the column direction Y.

[0076] In this embodiment, if Figure 3 As shown, the first power line 221 includes a third conductive portion E3, the third conductive portion E3 extends along the row direction X, and the second power line 222 extends along the column direction Y. For some third power lines 223, for example, Figure 3 For the second third power line 223 from the left, the first conductive portion E1 is connected to the third conductive portion E3, and the second power line 222 is connected to the second conductive portion E2. For other third power lines 223, for example, Figure 3 In the third power line 223 on the rightmost side, the first conductive portion E1 is connected to the second power line 222 .

[0077] In this embodiment, the sum of the number of first power lines 221 and the number of second power lines 222 is less than the sum of the number of rows and the number of columns of the array. Therefore, there is at least one row of first sub-pixels 21 where the first power line 221 is not arranged near or at least one column of first sub-pixels 21 where the second power line 222 is not arranged near, which reduces the number of power lines and the area occupied, and is conducive to improving the light transmittance of the first display area 111.

[0078] In this embodiment, the plurality of power lines 22 further include a fourth power line and a fifth power line. The fourth power line and the fifth power line may be located in the second display area 112, and the first power line 221, the second power line 222, the third power line 223, the fourth power line, and the fifth power line are connected.

[0079] In this embodiment, the fourth power line is configured to be connected to the pixel circuits of the second sub-pixels arranged along the row direction X, and the fifth power line is configured to be connected to the pixel circuits of the second sub-pixels arranged along the column direction Y.

[0080] In this embodiment, in the second display area, the number of fourth power lines is the same as the number of rows of the array. The pixel circuits of the second sub-pixels in the same row are connected to the same fourth power line, and the same fourth power line is connected to the pixel circuits of the second sub-pixels in the same row.

[0081] In this embodiment, in the second display area, the number of fifth source lines is the same as the number of columns of the array. The pixel circuits of the second sub-pixels in the same column are connected to the same fifth power line, and the same fifth power line is connected to the pixel circuits of the second sub-pixels in the same column.

[0082] In this embodiment, the density of the power lines in the first display area 111 is less than that in the second display area 112. Since the density of the power lines in the first display area 111 is less than that in the second display area 112, the light transmittance of the first display area 111 can be improved.

[0083] In the above text, Figures 2 to 4 The structure of the display substrate in this embodiment is briefly shown, and the structure of the display substrate in this embodiment is further introduced below.

[0084] First, let's introduce the structure of the pixel circuit. Figure 5 As shown, the pixel circuit 51 is connected to the light emitting element D, and is used to drive the light emitting element D to emit light. The pixel circuit 51 is connected to the power line VDD, and the cathode of the light emitting element D is connected to the power line VSS.

[0085] like Figure 5 As shown, the pixel circuit 51 may include a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a second light emission control transistor T4, a first light emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C. The threshold compensation transistor T3 and the first reset transistor T6 may be dual-gate transistors.

[0086] In this embodiment, the driving transistor T1 is used to provide a driving current for the light-emitting element D, the gate of the driving transistor T1 is connected to the first electrode of the capacitor C, the first electrode of the threshold compensation transistor T3, and the second electrode of the first reset transistor T6, the first electrode of the driving transistor T1 is connected to the second electrode of the threshold compensation transistor T3 and the second electrode of the first light-emitting control transistor T5, and the second electrode of the driving transistor T1 is connected to the first electrode of the second light-emitting control transistor T4 and the second electrode of the data writing transistor T2. The first electrode of the data writing transistor T2 is configured to be electrically connected to the data line Vd to receive a data signal, the gate of the data writing transistor T2 is electrically connected to the first scanning signal line Ga1 to receive a scanning signal, and the first electrode of the data writing transistor T2 is electrically connected to the data line Vd to receive a data signal. The gate of the threshold compensation transistor T3 is electrically connected to the second scanning signal line Ga2 to receive a compensation control signal. The gate of the second light-emitting control transistor T4 is electrically connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal, and the second electrode of the second light-emitting control transistor T4 is connected to the second electrode of the capacitor and the power line VDD. The gate of the first light-emitting control transistor T5 is electrically connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal, and the first electrode of the first light-emitting control transistor T5 is connected to the first electrode of the second reset transistor T7 and the positive electrode of the light-emitting element D. The gate of the first reset transistor T6 is electrically connected to the first reset control signal line Rst1 to receive the first sub-reset control signal, and the first electrode of the first reset transistor T6 is electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal. The gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2 to receive the second sub-reset control signal, and the second electrode of the second reset transistor T7 is electrically connected to the second reset power supply terminal Vinit2 to receive the second reset signal.

[0087] In this embodiment, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the second light emission control transistor T4, the first light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7 are P-type transistors, the first pole is the source, and the second pole is the drain. In other embodiments, one or more of the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the second light emission control transistor T4, the first light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7 may also be N-type transistors.

[0088] In this embodiment, the voltage of the power signal provided by the power line VDD is greater than the voltage of the power signal provided by the power line VSS. The voltage of the power signal provided by the power line VDD is a positive voltage, and the voltage of the power signal provided by the power line VSS may be 0 or a negative voltage. For example, when the power line VSS is grounded, the voltage of the power signal provided is 0. Of course, in other embodiments, the voltage of the power signal provided by the power line VDD may be less than the voltage of the power signal provided by the power line VSS.

[0089] In this embodiment, the first light-emitting control signal and the second light-emitting control signal may be the same, and the gate of the second light-emitting control transistor T4 and the gate of the first light-emitting control transistor T5 may be connected to the same light-emitting control signal line EM, which is the first light-emitting control signal line EM1 or the second light-emitting control signal line EM2. Similarly, the first sub-reset control signal and the second sub-reset control signal may be the same, and the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may be connected to the same reset control signal line Rst, which may be the first reset control signal line Rst1 or the second reset control signal line Rst2. When the first reset signal and the second reset signal are the same, the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 are connected to the same reset signal line VINIT.

[0090] The above introduces the structure of the pixel circuit. Figure 6 to Figure 14 Introduce the structure of each layer of the pixel circuit. Figure 6 to Figure 14 The structure of each layer of the pixel circuit of the first sub-pixel 21 with 4 rows and 6 columns is shown, or in other words, the structure of each layer of the pixel circuit of the first sub-pixel 21 in the sub-pixel group 31 with 2 rows and 3 columns is shown.

[0091] Figures 6 to 11 The structure of the active semiconductor layer 61 in the pixel circuit is shown. The active semiconductor layer 61 can be formed by patterning semiconductor materials. The active semiconductor layer 61 can be used to make the active layers of the above-mentioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, second light-emitting control transistor T4, first light-emitting control transistor T5, first reset transistor T6 and second reset transistor T7. The active semiconductor layer 61 includes an active layer pattern and a doping region pattern of each transistor of each sub-pixel, and the doping region pattern includes a source region and a drain region. And the active layer pattern and the doping region pattern of each transistor in the same pixel circuit are arranged in one piece.

[0092] like Figures 8 to 11As shown, the driving transistor T1 includes an active layer T1C, a source region T1S and a drain region T1D, the data writing transistor T2 includes an active layer T2C, a source region T2S and a drain region T2D, the threshold compensation transistor T3 includes an active layer T3C, a source region T3S and a drain region T3D, the second light-emitting control transistor T4 includes an active layer T4C, a source region T4S and a drain region T4D, the first light-emitting control transistor T5 includes an active layer T5C, a source region T5S and a drain region T5D, the first reset transistor T6 includes an active layer T6C, a source region T6S and a drain region T6D, and the second reset transistor T7 includes an active layer T7C, a source region T7S and a drain region T7D.

[0093] It should be noted that the active layer may include an integrally formed low-temperature polysilicon layer, wherein the source region and the drain region may be conductively connected by doping, etc. to achieve electrical connection of various structures. That is, the active semiconductor layer of each transistor of each first sub-pixel 21 is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doping region pattern (i.e., a source region and a drain region) and an active layer pattern, and the active layers of different transistors are separated by doping structures.

[0094] In this embodiment, the active semiconductor layer 61 may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region may be regions doped with N-type impurities or P-type impurities.

[0095] like Figure 6-7 As shown, in each sub-pixel group 31, the active semiconductor layer 61 is symmetrical about the symmetry axis 71, and the symmetry axis 71 extends along the column direction Y, that is, the active semiconductor layer 61 of the pixel circuits of the red sub-pixel 211 and the green sub-pixel 212 located in the same row is symmetrical about the symmetry axis 71, and the active semiconductor layer 61 of the pixel circuits of the blue sub-pixel 213 and the green sub-pixel 212 located in the same row is symmetrical about the symmetry axis 71. It should be noted that each sub-pixel group 31 is also symmetrical about the symmetry axis 71.

[0096] like Figure 7 As shown, in each sub-pixel group 31, the active semiconductor layers 61 of the pixel circuits of the first sub-pixels 21 located in the same column are connected. In each sub-pixel group 31, the structures of the active semiconductor layers 61 of the pixel circuits of the two first sub-pixels 21 located in the same column are roughly the same, and there are also different parts. For details, please refer to Figures 8 to 11 .in, Figure 8 and Fig. 9 The structure of the active semiconductor layer 61 of the pixel circuit of the red sub-pixel 211 is shown. Fig.10 and Fig.11The structure of the active semiconductor layer 61 of the pixel circuit of the blue sub-pixel 213 is shown.

[0097] In this embodiment, Fig.12 FIG. 1 shows the structure of the first conductive layer 121 in the pixel circuit. The first conductive layer 121 is located on the gate insulating layer, and the first conductive layer 121 is located on the gate insulating layer and is insulated from the active semiconductor layer 61. Fig.12 As shown, the first conductive layer 121 may include the first electrode CC1 of the storage capacitor C, the first scan signal line Ga1, the reset control signal line Rst, the light emitting control signal line EM, the first longitudinal conductive portion 2221, and the first conductive layer 121 may include the gates of the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the second light emitting control transistor T4, the first light emitting control transistor T5, the first reset transistor T6, and the second reset transistor T7. The first electrode CC1 of the storage capacitor C is also the gate of the driving transistor T1.

[0098] like Fig.12 As shown, the gate of the data writing transistor T2 may be the portion where the first scanning signal line Ga1 overlaps with the active semiconductor layer 61; the gate of the second light-emitting control transistor T4 may be the first portion where the light-emitting control signal line EM overlaps with the active semiconductor layer 61, and the gate of the first light-emitting control transistor T5 may be the second portion where the light-emitting control signal line EM overlaps with the active semiconductor layer 61; the gate of the first reset transistor T6 may be the first portion where the reset control signal line Rst overlaps with the active semiconductor layer 61, and the gate of the second reset transistor T7 may be the second portion where the reset control signal line Rst overlaps with the active semiconductor layer 61; the threshold compensation transistor T3 may be a thin film transistor with a dual-gate structure, the first gate of the threshold compensation transistor T3 may be the portion where the first scanning signal line Ga1 overlaps with the active semiconductor layer 61, and the second gate of the threshold compensation transistor T3 may be the portion where the protrusion P protruding from the first scanning signal line Ga1 overlaps with the active semiconductor layer 61.

[0099] like Fig.12 As shown, the first longitudinal conductive portion 2221 extends along the column direction Y and constitutes a part of the second power line 222. The first longitudinal conductive portion 2221 includes a connecting portion 122, which is used to connect with other parts of the power line through a via hole.

[0100] In this embodiment, Fig.13 FIG. 1 shows the structure of the second conductive layer 131 in the pixel circuit. Fig.13As shown, the second conductive layer 131 includes a reset signal line VINIT, a second electrode CC2 of the storage capacitor C, a second longitudinal conductive portion 2222, a first transverse conductive portion 2211, a second transverse conductive portion 2212, and a light shielding portion SHL. The reset signal lines VINIT of the pixel circuits of all first sub-pixels 21 are connected together. The second electrode CC2 is connected to the power line. For example, the second electrode CC2 in the red sub-pixel 211 may be a part of a first conductive portion E1 of the third power line 223, the second electrode CC2 in the blue sub-pixel 213 is a part of another first conductive portion E1 of the third power line 223, and the second electrode CC2 in the blue sub-pixel 213 is also connected to the second transverse conductive portion 2212. The second transverse conductive portion 2212 and the first transverse conductive portion 2211 are a part of the first power line 221, and the second longitudinal conductive portion 2222 is a part of the second power line 222. The light shielding portion SHL is used for light shielding to prevent the above-mentioned double-gate transistor from being optically interfered. The light shielding portion SHL may be connected to a DC power supply, so that the light shielding portion SHL may play an electrical shielding role to prevent the above-mentioned dual-gate transistor from being electrically interfered.

[0101] It should be noted that the transverse conductive portion does not refer to the conductive portion extending along the row direction X, but refers to the portion used to connect with the pixel circuit of the first sub-pixel 21 arranged along the row direction X. The longitudinal conductive portion may refer to the conductive portion extending along the column direction Y.

[0102] like Fig.13 As shown, the second longitudinal conductive portion 2222 includes a connecting portion 132 for connecting to other parts of the power line through a via hole. The first transverse conductive portion 2211 includes a connecting portion 133 for connecting to the second transverse conductive portion 2212 through a via hole, and the second transverse conductive portion 2212 includes a connecting portion 134 for connecting to the first transverse conductive portion 2211 through a via hole.

[0103] In this embodiment, Fig.14 FIG. 1 shows the structure of the third conductive layer 141 in the pixel circuit. Fig.13 As shown, the third conductive layer 141 includes a data line Vd, a third longitudinal conductive portion 2231, a fourth longitudinal conductive portion 2232 and a connecting portion 142. The third longitudinal conductive portion 2231 and the fourth longitudinal conductive portion 2232 extend along the column direction Y. The third longitudinal conductive portion 2231 and the fourth longitudinal conductive portion 2232 are the second conductive portion E2 described above.

[0104] In this embodiment, if Fig.15 As shown, the third longitudinal conductive portion 2231 and the fourth longitudinal conductive portion 2232 are respectively connected to the second electrode CC2 through via holes to realize the ring structure of the third power line 223223.

[0105] In this embodiment, if Figures 14 to 15 As shown, the third longitudinal conductive part 2231 includes a connecting part 143, which is connected to the connecting part 132 of the second longitudinal conductive part 2222 through a via hole, and the fourth longitudinal conductive part 2232 includes a connecting part 144, which is connected to the connecting part 122 of the first longitudinal conductive part 2221 through a via hole to realize the connection between the third power line 223 and the second power line 222.

[0106] In this embodiment, if Figures 14 to 15 As shown, the connection portion 142 is respectively connected to the connection portion 133 of the first transverse conductive portion 2211 and the connection portion 134 of the second transverse conductive portion 2212 through via holes to form the first power line 221 .

[0107] The embodiment of the present invention further provides a display substrate. Figure 16 to Figure 17 As shown, different from the above embodiment, in this embodiment, the plurality of power lines 22 only include the first power line 221 and the third power line 223, and do not include the second power line 222, that is, the number of the second power lines 222 is 0. Moreover, the density of the first power lines 221 is greater than the density of the first power lines 221 in the above embodiment.

[0108] In this embodiment, if Fig.16 and Fig.17 As shown, there is a first power line 221 between the pixel circuits of the first sub-pixels 21 in two adjacent rows of sub-pixel groups 31, and the pixel circuits of the first sub-pixels 21 in two adjacent rows of sub-pixel groups 31 are connected to the same first power line 221, that is, the pixel circuits of the first sub-pixels 21 in four adjacent rows are connected to the same first power line 221. Moreover, the pixel circuits of the first sub-pixels 21 in the same sub-pixel group 31 are connected to two adjacent first power lines 221.

[0109] In this embodiment, if Fig.16 and Fig.17 As shown, the third power line 223 includes two first conductive portions E1, and the first conductive portion E1 extends along the row direction X. The first power line 221 includes a third conductive portion E3, and the third conductive portion E3 extends along the row direction X. The first conductive portion of the third power line 223 is connected to the third conductive portion of the first power line 221. The third power line 223 is connected to the two first power lines 221 through the two first conductive portions.

[0110] In this embodiment, the density of the power lines in the first display area 111 is less than that in the second display area 112. Since the density of the power lines in the first display area 111 is less than that in the second display area 112, the light transmittance of the first display area 111 can be improved.

[0111] The embodiment of the present invention further provides a display substrate. Figures 18 to 20 As shown, different from the above embodiment, each sub-pixel group 31 includes three first sub-pixels 21 adjacent to each other in the row direction X.

[0112] In this embodiment, if Fig.18 As shown, each sub-pixel group 31 includes a red sub-pixel 211 , a green sub-pixel 212 , and a blue sub-pixel 213 that are adjacent to each other in the row direction X.

[0113] In this embodiment, the density of the first sub-pixels 21 in the first display area 111 is smaller than the density of the second sub-pixels in the second display area 112. In this way, the light transmittance of the first display area 111 can be improved.

[0114] In this embodiment, if Fig.19 and Fig. 20 As shown, the number of first power lines 221 is equal to the number of rows of the array. The pixel circuits of the first sub-pixels 21 in the same row of sub-pixel groups 31 are only connected to the same first power line 221, and the same first power line 221 is only connected to the pixel circuits of the first sub-pixels 21 in the same row of sub-pixel groups 31.

[0115] In this embodiment, the number of the second power lines 222 is less than the number of columns of the array, so that the number of the second power lines 222 can be reduced and the light transmittance of the first display area 111 can be improved.

[0116] In this embodiment, if Fig.19 and Fig. 20 As shown, the number of the second power lines 222 is equal to 1 / 3 of the number of columns of the array, and the number of the second power lines 222 is equal to the number of columns of the sub-pixel group 31. For example, Fig. 20 9 columns of first sub-pixels 21 , 3 columns of sub-pixel groups 31 , and the number of second power lines 222 equals 3 are shown.

[0117] In this embodiment, if Fig.19 and Fig. 20 As shown, the pixel circuits of the first sub-pixels 21 in the same column of sub-pixel groups 31 are connected to the same second power line 222 , and the same second power line 222 is connected to the pixel circuits of the first sub-pixels 21 in the same column of sub-pixel groups 31 .

[0118] An embodiment of the present invention further provides a display device, comprising a photosensitive element and a display substrate according to any of the above embodiments. The projection of the photosensitive element on the display substrate is located in the first display area 111 .

[0119] In this embodiment, the photosensitive element may be an image sensor, an ambient light sensor or a distance sensor, but is not limited thereto.

[0120] It should be noted that the display device in this embodiment can be: electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, or any other product or component with a display function.

[0121] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0122] In the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0123] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the disclosure disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The description and examples are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0124] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A display substrate, characterized in that: comprising a display area, the display area comprising a first display area and a second display area, the first display area and the second display area are adjacent to each other, and the light transmittance of the first display area is greater than the light transmittance of the second display area; A plurality of first sub-pixels, located in the first display area, the plurality of first sub-pixels are divided into a plurality of sub-pixel groups, each of the sub-pixel groups includes at least two first sub-pixels adjacent to each other in a row direction, and each of the plurality of first sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light; A plurality of power lines are connected to the plurality of first sub-pixels, the plurality of power lines include a first power line and a second power line, the first power line extends along a row direction and is connected to the pixel circuit of the first sub-pixel located in the row direction, the second power line extends along a column direction and is connected to the pixel circuit of the first sub-pixel located in the column direction, and the row direction and the column direction intersect.

2. The display substrate according to claim 1, characterized in that: In the same row of sub-pixel groups, a distance between two adjacent sub-pixel groups is greater than or equal to a width of one of the sub-pixel groups in the same row in the row direction; In the same column of sub-pixel groups, a distance between two adjacent sub-pixel groups is greater than or equal to a length of one of the sub-pixel groups in the same column in a column direction.

3. The display substrate according to claim 1, characterized in that: The orthographic projection of the i+2th row of subpixel groups in the plurality of subpixel groups on the i-row subpixel group is outside the orthographic projection of the i+1th row of subpixel groups on the i-row subpixel group, the orthographic projection of the i+3th row of subpixel groups on the i-row subpixel group coincides with the orthographic projection of the i+1th row of subpixel groups on the i-row subpixel group, and the orthographic projection of the i+3th row of subpixel groups on the i-row subpixel group is outside the orthographic projection of the i+2th row of subpixel groups on the i-row subpixel group, where i is a positive integer; The orthogonal projection of the j+2th column sub-pixel group on the jth column sub-pixel group is outside the orthogonal projection of the j+1th column sub-pixel group on the jth column sub-pixel group, the orthogonal projection of the j+3th column sub-pixel group on the jth column sub-pixel group coincides with the orthogonal projection of the j+1th column sub-pixel group on the jth column sub-pixel group, and the orthogonal projection of the j+3th column sub-pixel group on the jth column sub-pixel group is outside the orthogonal projection of the j+2th column sub-pixel group on the jth column sub-pixel group, where j is a positive integer.

4. The display substrate according to claim 3, characterized in that: The pixel circuits of the first sub-pixels in the same sub-pixel group are connected to the same first power line, and the same first power line is connected to the pixel circuits of the first sub-pixels in two adjacent rows of sub-pixel groups.

5. The display substrate according to claim 4, characterized in that: The number of the second power lines connected to a sub-pixel group is less than the number of columns of the first sub-pixels in the same sub-pixel group.

6. The display substrate according to claim 1, characterized in that: The number of the second power lines is equal to the number of columns of the sub-pixel groups; The pixel circuits of the first sub-pixels in the sub-pixel group in the same column are connected to the same second power line.

7. The display substrate according to claim 1, characterized in that: Each of the sub-pixel groups includes three first sub-pixels arranged in sequence along the row direction, the first power line is connected to the three first sub-pixels simultaneously, and the second power line is connected to a first sub-pixel located in the middle of the three first sub-pixels.

8. The display substrate according to claim 7, characterized in that: The plurality of first power lines and the plurality of second power lines form a mesh structure.

9. The display substrate according to claim 7, characterized in that: The three first sub-pixels include a red sub-pixel, a blue sub-pixel and a green sub-pixel.

10. The display substrate according to any one of claims 1 to 9, characterized in that: The plurality of power lines further include a third power line, the third power line being connected to at least one of the first power line and the second power line; The number of the third power lines is the same as the number of the sub-pixel groups, and the pixel circuit of the first sub-pixel in each sub-pixel group is connected to the same third power line.

11. The display substrate according to claim 10, characterized in that: When the third power line is connected to the first power line and the second power line, the third power line includes a first conductive portion and a second conductive portion, the first conductive portion is connected to the second conductive portion, the first conductive portion extends in a row direction, and the second conductive portion extends in a column direction; the first power line includes a third conductive portion, the third conductive portion extends in a row direction; the second power line extends in a column direction; the first conductive portion is connected to the third conductive portion, and the second power line is connected to the first conductive portion or the second conductive portion; When the third power line is connected to the first power line, the third power line includes a first conductive portion extending in a row direction, the first power line includes a third conductive portion extending in a row direction; the first conductive portion is connected to the third conductive portion.

12. The display substrate according to claim 1, characterized in that: The sum of the number of the first power lines and the number of the second power lines is smaller than the sum of the number of rows and the number of columns of the array formed by the plurality of first sub-pixels.

13. The display substrate according to claim 1, characterized in that: The sum of the number of the first power lines connected to each of the sub-pixel groups and the number of the second power lines is less than the sum of the number of rows and the number of columns corresponding to each of the sub-pixel groups.

14. The display substrate according to claim 13, characterized in that: The number of the first power lines is equal to the number of rows of the array formed by the plurality of first sub-pixels; The pixel circuits of the first sub-pixels in the sub-pixel group in the same row are only connected to the same first power line, and the same first power line is only connected to the pixel circuits of the first sub-pixels in the sub-pixel group in the same row.

15. The display substrate according to claim 14, characterized in that: The number of the second power lines is less than the number of columns of the array.

16. The display substrate according to claim 15, characterized in that: The number of the second power lines is equal to 1 / 3 of the number of columns of the array, and the number of the second power lines is equal to the number of columns of the sub-pixel groups; The pixel circuits of the first sub-pixels in the sub-pixel group in the same column are connected to the same second power line, and the same second power line is connected to the pixel circuits of the first sub-pixels in the sub-pixel group in the same column.

17. The display substrate according to claim 1, characterized in that: The second display area includes a plurality of second sub-pixels, and the plurality of second sub-pixels are arranged in an array along a row direction and a column direction; The density of the first sub-pixels in the first display area is smaller than the density of the second sub-pixels in the second display area.

18. The display substrate according to claim 17, characterized in that: The plurality of power lines further include a fourth power line and a fifth power line, the fourth power line is configured to be connected to the pixel circuits of the second sub-pixels arranged along the row direction, and the fifth power line is configured to be connected to the pixel circuits of the second sub-pixels arranged along the column direction; The density of the power lines in the first display area is less than the density of the power lines in the second display area.

19. A display device, characterized in that: It comprises a photosensitive element and a display substrate as claimed in any one of claims 1 to 18, wherein the projection of the photosensitive element on the display substrate is located in the first display area.

20. The display device according to claim 19, characterized in that The photosensitive element is an image sensor, an ambient light sensor or a distance sensor.

Images