Semiconductor storage structure and method for forming the same

Abstract

The present application provides a semiconductor storage structure and a method for forming the same, relating to the field of semiconductor technology, and used to improve the performance of semiconductor storage structures. The structure includes: a spin-orbit moment layer, and a storage magnetic tunnel junction, a dummy magnetic tunnel junction, and a dielectric layer disposed on the spin-orbit moment layer; the dummy magnetic tunnel junction is located next to the storage magnetic tunnel junction; the dielectric layer at least fills the gap between the storage magnetic tunnel junction and the dummy magnetic tunnel junction; the spin-orbit moment layer is formed by etching using the storage magnetic tunnel junction, the dummy magnetic tunnel junction, and the dielectric layer as a mask. The semiconductor storage structure and method for forming the same provided by the present application do not require a mask for the spin-orbit moment layer, which can simplify the formation process. At the same time, it can also avoid overlay offset between the storage magnetic tunnel junction and the spin-orbit moment layer, ensuring that the storage magnetic tunnel junction and the spin-orbit moment layer are aligned, thereby improving the write current efficiency and improving the performance of the semiconductor storage structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor storage structure and a method for forming the same. Background Art

[0002] With the continuous advancement of semiconductor technology, magnetic random access memory (MRAM) has been widely used in fields such as the Internet of Things (IoT), edge AI devices, high-performance computing, and automobiles. Among them, spin-orbit torque magnetic random access memory (SOT-MRAM) uses current to flip the free layer for data storage. It offers the advantages of high read and write speeds and low power consumption, and holds broad application prospects.

[0003] The cell structure in a SOT-MRAM device is a three-terminal device consisting of two electrical channels. One channel, with current flowing through a magnetic tunnel junction (MTJ), serves as the data "read" channel; the other channel, with current flowing through the SOT layer (i.e., the bottom electrode), serves as the data "write" channel. For the "write" channel, the write current must flow through the SOT layer, where spin-orbit coupling creates a spin current that diffuses into the MTJ's free layer, exerting a spin-orbit torque effect on the free layer. This influences the magnetization direction of the free layer, thereby distinguishing between "0" and "1" in binary, and enabling the write process.

[0004] However, the lithography of the SOT layer in the SOT-MRAM device is independent of the MTJ, and a separate mask needs to be provided for the SOT layer. Moreover, as the size of the SOT-MRAM device continues to shrink, the lithography of the SOT layer and the MTJ is prone to misalignment, causing the device to fail. Summary of the Invention

[0005] In view of the above problems, an embodiment of the present application provides a semiconductor storage structure and a method for forming the same, which can simplify the formation process of the semiconductor storage structure, and at the same time avoid the overlay offset of the storage magnetic tunnel junction and the spin-orbit moment layer, so as to improve the performance of the semiconductor storage structure.

[0006] According to some embodiments, the present application provides a semiconductor storage structure, comprising: a spin-orbit moment layer, and a storage magnetic tunnel junction, a dummy magnetic tunnel junction and a dielectric layer arranged on the spin-orbit moment layer; the dummy magnetic tunnel junction is located next to the storage magnetic tunnel junction; the dielectric layer at least fills the gap between the storage magnetic tunnel junction and the dummy magnetic tunnel junction; the spin-orbit moment layer is formed by etching using the storage magnetic tunnel junction, the dummy magnetic tunnel junction and the dielectric layer as a mask.

[0007] In some possible implementations, the method further includes: a substrate having at least two conductive through-holes disposed therein, the conductive through-holes being located on both sides of the storage magnetic tunnel junction; and the orthographic projections of the storage magnetic tunnel junction, the dummy magnetic tunnel junction, and the dielectric layer on the substrate covering at least two of the conductive through-holes on both sides of the storage magnetic tunnel junction.

[0008] In some possible embodiments, one dummy magnetic tunnel junction is provided, and the dummy magnetic tunnel junction covers one of the conductive through holes; the dielectric layer also covers the side wall of the storage magnetic tunnel junction away from one end of the dummy magnetic tunnel junction, and covers one of the conductive through holes.

[0009] In some possible implementations, two dummy magnetic tunnel junctions are provided; and the two dummy magnetic tunnel junctions respectively cover one conductive through hole.

[0010] In some possible implementations, the storage magnetic tunnel junction and the dummy magnetic tunnel junction are formed by synchronous etching.

[0011] In some possible implementations, the distances between the sidewalls of the dummy magnetic tunnel junction and the storage magnetic tunnel junction that are opposite to each other are equal.

[0012] The semiconductor storage structure in the embodiments of the present application includes a spin-orbit moment layer, a storage magnetic tunnel junction, a dummy magnetic tunnel junction, and a dielectric layer. The storage magnetic tunnel junction, the dummy magnetic tunnel junction, and the dielectric layer are all disposed on the spin-orbit moment layer, with the dummy magnetic tunnel junction located adjacent to the storage magnetic tunnel junction. The dielectric layer at least fills the gap between the storage magnetic tunnel junction and the dummy magnetic tunnel junction to connect the storage magnetic tunnel junction and the dummy magnetic tunnel junction. The spin-orbit moment layer is formed by etching using the storage magnetic tunnel junction, the dummy magnetic tunnel junction, and the dielectric layer as masks. This eliminates the need for a photomask for the spin-orbit moment layer, simplifying the formation process. Overlay offset between the storage magnetic tunnel junction and the spin-orbit moment layer is also avoided, ensuring alignment between the storage magnetic tunnel junction and the spin-orbit moment layer, thereby improving write current efficiency and enhancing the performance of the semiconductor storage structure.

[0013] According to some embodiments, the present application also provides a method for forming a semiconductor storage structure, which includes: forming a spin-orbit moment initial layer and a magnetic tunnel junction stacking layer, wherein the magnetic tunnel junction stacking layer is located on the spin-orbit moment initial layer; etching the magnetic tunnel junction stacking layer to form a storage magnetic tunnel junction and a dummy magnetic tunnel junction, wherein the dummy magnetic tunnel junction is located next to the storage magnetic tunnel junction; forming a dielectric layer, wherein the dielectric layer at least fills the gap between the storage magnetic tunnel junction and the dummy magnetic tunnel junction; using the storage magnetic tunnel junction, the dummy magnetic tunnel junction and the dielectric layer as a mask, etching the spin-orbit moment initial layer to form a spin-orbit moment layer.

[0014] In some possible embodiments, forming the dielectric layer includes: depositing an initial dielectric layer, wherein the initial dielectric layer at least covers the spin-orbit moment initial layer, the storage magnetic tunnel junction, and the dummy magnetic tunnel junction, and fills the gap between the storage magnetic tunnel junction and the dummy magnetic tunnel junction; etching the initial dielectric layer, removing a portion of the initial dielectric layer, and the remaining initial dielectric layer forms the dielectric layer.

[0015] In some possible implementations, removing part of the initial dielectric layer includes: removing the entire initial dielectric layer on the top surface of the storage magnetic tunnel junction, the dummy magnetic tunnel junction, and the spin-orbit moment initial layer to expose the storage magnetic tunnel junction and the dummy magnetic tunnel junction.

[0016] In some possible implementations, the thickness of the initial dielectric layer on the sidewalls of the storage magnetic tunnel junction and the dummy magnetic tunnel junction is not less than half of the distance between the storage magnetic tunnel junction and the dummy magnetic tunnel junction.

[0017] The method for forming a semiconductor storage structure in an embodiment of the present application includes: forming a spin-orbit moment initialization layer and a magnetic tunnel junction stacking layer, wherein the magnetic tunnel junction stacking layer is located on the spin-orbit moment initialization layer; etching the magnetic tunnel junction stacking layer to form a storage magnetic tunnel junction and a dummy magnetic tunnel junction, wherein the dummy magnetic tunnel junction is located next to the storage magnetic tunnel junction; forming a dielectric layer, wherein the dielectric layer at least fills the gap between the storage magnetic tunnel junction and the dummy magnetic tunnel junction; and etching the spin-orbit moment initialization layer using the storage magnetic tunnel junction, the dummy magnetic tunnel junction, and the dielectric layer as a mask to form a spin-orbit moment layer. The spin-orbit moment initialization layer is patterned using the storage magnetic tunnel junction, the dummy magnetic tunnel junction, and the dielectric layer, and the spin-orbit moment layer can be formed without separate photolithography. There is no need to set a mask for the spin-orbit moment layer, which simplifies the formation process. At the same time, it can also avoid overlay offset between the storage magnetic tunnel junction and the spin-orbit moment layer, ensuring that the storage magnetic tunnel junction and the spin-orbit moment layer are aligned, thereby improving the write current efficiency and improving the performance of the semiconductor storage structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a three-dimensional diagram after forming a magnetic tunnel junction in the related art;

[0019] Figure 2 It is a cross-sectional view after forming a magnetic tunnel junction in the related art;

[0020] Figure 3 It is a top view after forming a magnetic tunnel junction in the related art;

[0021] Figure 4 It is a three-dimensional image after forming the photoresist in the related art;

[0022] Figure 5 It is a cross-sectional view after photoresist is formed in the related art;

[0023] Figure 6 It is a top view after forming the photoresist in the related art;

[0024] Figure 7 A cross-sectional view of a dielectric hard mask after patterning in the related art;

[0025] Figure 8 A top view of a dielectric hard mask after patterning in the related art;

[0026] Figure 9 A cross-sectional view of a spin-orbit moment layer after patterning in the related art;

[0027] Figure 10 A top view of the spin-orbit moment layer after patterning in the related art;

[0028] Figure 11 A three-dimensional diagram of a first semiconductor storage structure according to an embodiment of the present application;

[0029] Figure 12 is a cross-sectional view of a first semiconductor storage structure in an embodiment of the present application;

[0030] Figure 13 A top view of a first semiconductor storage structure according to an embodiment of the present application;

[0031] Figure 14 is a cross-sectional view of a second semiconductor storage structure according to an embodiment of the present application;

[0032] Figure 15 is a cross-sectional view of a third semiconductor storage structure according to an embodiment of the present application;

[0033] Figure 16 is a cross-sectional view of a fourth semiconductor storage structure according to an embodiment of the present application;

[0034] Figure 17 is a cross-sectional view of a fifth semiconductor storage structure in an embodiment of the present application;

[0035] Figure 18 is a top view of a fifth semiconductor storage structure in an embodiment of the present application;

[0036] Figure 19 is a flow chart of a method for forming a semiconductor memory structure in an embodiment of the present application;

[0037] Figure 20 is a three-dimensional diagram of a substrate in an embodiment of the present application;

[0038] Figure 21 This is a three-dimensional diagram after forming a mask layer in an embodiment of the present application;

[0039] Figure 22 This is a three-dimensional diagram after forming a photoresist layer in an embodiment of the present application;

[0040] Figure 23 This is a three-dimensional diagram after etching the mask layer in an embodiment of the present application;

[0041] Figure 24 This is a three-dimensional diagram after forming a dummy magnetic tunnel junction and a storage magnetic tunnel junction in an embodiment of the present application;

[0042] Figure 25 This is a cross-sectional view after forming a dummy magnetic tunnel junction and a storage magnetic tunnel junction in an embodiment of the present application;

[0043] Figure 26 This is a top view after forming a dummy magnetic tunnel junction and a storage magnetic tunnel junction in an embodiment of the present application;

[0044] Figure 27 This is a three-dimensional diagram after the dielectric layer is formed in the embodiment of the present application;

[0045] Figure 28 This is a cross-sectional view after the dielectric layer is formed in the embodiment of the present application;

[0046] Figure 29 This is a top view after the dielectric layer is formed in the embodiment of the present application;

[0047] Figure 30 This is a three-dimensional diagram after the initial dielectric layer is formed in an embodiment of the present application;

[0048] Figure 31 This is a cross-sectional view after the initial dielectric layer is formed in an embodiment of the present application;

[0049] Figure 32 This is a top view after the initial dielectric layer is formed in an embodiment of the present application.

[0050] Description of reference numerals:

[0051] 10-substrate; 11-conductive via; 20-magnetic tunnel junction; 21-dummy magnetic tunnel junction; 22-storage magnetic tunnel junction; 23-magnetic tunnel junction stack layer; 30-spin-orbit moment layer; 31-spin-orbit moment initial layer; 41-dielectric hard mask; 42-photoresist; 50-dielectric layer; 51-initial dielectric layer; 52-step; 60-mask layer; 70-photoresist layer; 80-isolation layer; 90-top electrode. DETAILED DESCRIPTION

[0052] In related art, see Figures 1 to 10 The patterns of the spin-orbit moment layer 30 and the magnetic tunnel junction 20 are usually independent and need to be photolithographically processed separately. The process is as follows: First, Figure 1 、 Figure 2 and Figure 3 As shown, the magnetic tunnel junction 20 is photolithographically and etched; thereafter, as shown Figure 4 、 Figure 5 and Figure 6 As shown, after depositing a non-conductive dielectric hard mask 41 (usually SiN) and a photoresist 42, the photoresist 42 is photoetched to cover the dielectric hard mask 41 with the patterned photoresist 42; Figure 7 and Figure 8 As shown, the dielectric hard mask 41 is then etched to transfer the pattern of the photoresist 42 to the dielectric hard mask 41; Figure 9 and Figure 10 As shown, the etched dielectric hard mask 41 is used as a mask to etch the spin-orbit moment layer 30. This process requires a separate mask for the spin-orbit moment layer 30, and the corresponding pattern is transferred in the order of photoresist 42, dielectric hard mask 41, and spin-orbit moment layer 30.

[0053] Furthermore, as device dimensions shrink to tens of nanometers or even lower, critical dimensions must continue to shrink, making the alignment of the spin-orbit moment layer 30 and the magnetic tunnel junction 20 increasingly critical. Significant misalignment between the two directly reduces write current efficiency, leading to write failures in the magnetic tunnel junction 20 and, consequently, memory failure.

[0054] To this end, an embodiment of the present application provides a semiconductor storage structure, in which a dielectric layer connects a virtual magnetic tunnel junction and a storage magnetic tunnel junction, so that the three are integrated. The spin-orbit moment layer is formed by etching using the virtual magnetic tunnel junction, the storage magnetic tunnel junction and the dielectric layer as masks. There is no need to set a mask for the spin-orbit moment layer, which simplifies the formation process. At the same time, it can also avoid overlay offset between the storage magnetic tunnel junction and the spin-orbit moment layer, ensure that the storage magnetic tunnel junction and the spin-orbit moment layer are aligned, thereby improving the write current efficiency and improving the performance of the semiconductor storage structure.

[0055] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0056] The present invention provides a semiconductor memory structure according to an embodiment of the present invention. The semiconductor memory structure is, for example, a magnetic memory. Figures 11 to 13The semiconductor storage structure includes a spin-orbit moment layer 30, a storage magnetic tunnel junction 22, a dummy magnetic tunnel junction 21 (Dummy MTJ), and a dielectric layer 50 disposed on the spin-orbit moment layer 30. The dummy magnetic tunnel junction 21 is located next to the storage magnetic tunnel junction 22; the dielectric layer 50 at least fills the gap between the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21; the spin-orbit moment layer 30 is formed by etching using the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, and the dielectric layer 50 as a mask.

[0057] The spin-orbit moment layer 30 is used to generate corresponding polarization currents with different directions of write currents, thereby generating different torques. The spin-orbit moment layer 30 can be in the shape of a long strip or an L shape. The embodiment of the present application does not limit the shape of the spin-orbit moment layer 30. For example, the spin-orbit moment layer 30 extends along a first direction, and the first direction is as follows: Figure 11 X direction shown.

[0058] The spin-orbit moment layer 30 is a single layer or a stacked layer, and the material of the spin-orbit moment layer 30 includes a conductive material with a strong spin-orbit coupling effect. Exemplarily, the material of the spin-orbit moment layer 30 includes one or more of Pt, Pd, Hf, Au, AuPt, PtHf, PtCr, PtMn, FeMn, NiMn, Ta, W, Ir, IrMn, WOx, WN, WON, TaN, TaB, and topological insulators. Topological insulators include Bi x Se 1-x ,Bi x Sb 1-x , (Bi,Sb)2Te3, where x independently satisfies the value of 0.1-0.9.

[0059] The storage magnetic tunnel junction 22 is used to store data. It is located on and in contact with the spin-orbit moment layer 30. When a write current in different directions flows through the spin-orbit moment layer 30, the storage magnetic tunnel junction 22 switches to a high-resistance state or a low-resistance state, respectively, to store data "1" or "0," thereby enabling rapid data writing.

[0060] The dummy magnetic tunnel junction 21 is not used to store data. On the one hand, in the embodiment of the present application, since the film layer height of the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 is the same, it can support the storage magnetic tunnel junction 22 during etching and chemical mechanical polishing, thereby improving the uniformity of etching and chemical mechanical polishing of the storage magnetic tunnel junction 22; on the other hand, in the embodiment of the present application, a dielectric layer is filled in the gap between the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22, so that the dummy magnetic tunnel junction 21, the storage magnetic tunnel junction 22 and the dielectric layer 50 are used as a template to form a patterned hard mask of the spin-orbit moment layer 30.

[0061] The dummy magnetic tunnel junction 21 is disposed on the spin-orbit moment layer 30 and is in contact with the spin-orbit moment layer 30. The dummy magnetic tunnel junction 21 is located next to the storage magnetic tunnel junction 22 and is spaced apart from the storage magnetic tunnel junction. The dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 are arranged along the extension direction of the spin-orbit moment layer 30.

[0062] The number of each of the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 can be at least one, and these dummy magnetic tunnel junctions 21 and the storage magnetic tunnel junction 22 are sequentially arranged and spaced apart from each other along the extension direction of the spin-orbit moment layer 30. At least one dummy magnetic tunnel junction 21 is located outside the storage magnetic tunnel junction 22, and along the extension direction of the spin-orbit moment layer 30, a dummy magnetic tunnel junction 21 is correspondingly provided at at least one end of the spin-orbit moment layer 30, that is, at least one dummy magnetic tunnel junction 21 is adjacent to an end of the spin-orbit moment layer 30.

[0063] For example, one dummy magnetic tunnel junction 21 is provided, and at least one storage magnetic tunnel junction 22 is provided, and these storage magnetic tunnel junctions 22 are located on the same side of the dummy magnetic tunnel junction 21. For another example, two dummy magnetic tunnel junctions 21 are provided, and one storage magnetic tunnel junction 22 is provided, and these two dummy magnetic tunnel junctions 21 can be provided on both sides of the storage magnetic tunnel junction 22 or on the same side.

[0064] For another example, there are two dummy magnetic tunnel junctions 21 and at least two storage magnetic tunnel junctions 22. The two dummy magnetic tunnel junctions 21 can be located on both sides of these storage magnetic tunnel junctions 22, respectively, or one of the dummy magnetic tunnel junctions 21 is located on one side of these storage magnetic tunnel junctions 22, and the other dummy magnetic tunnel junction 21 is located between the two storage magnetic tunnel junctions 22.

[0065] In some possible embodiments, the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 have the same height, that is, the top surfaces of the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 are flush, so as to facilitate their formation and use as a mask. The dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 may be made of the same material and structure. Exemplarily, the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 are formed by simultaneous etching, that is, by etching the deposited film layer to simultaneously form the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22. In this way, the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 do not need to be patterned separately, simplifying the formation process.

[0066] Exemplarily, the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 each include a free layer, a barrier layer, and a reference layer stacked in sequence, with the free layer disposed on the spin-orbit moment layer 30. The magnetization direction of the free layer can be changed, while the magnetization direction of the reference layer is fixed. The barrier layer isolates the free layer and the reference layer. The free layer and the reference layer are both made of ferromagnetic materials, such as at least one of Co, Fe, B, Ni, Ru, Ir, and Pt. The free layer and the reference layer may be made of the same or different materials. The barrier layer may be made of an insulating material, such as at least one of MgO, Al2O3, and SiO2. The shape of the storage magnetic tunnel junction 22 may be cylindrical, elliptical, rectangular, or curved, without limitation. The dummy magnetic tunnel junction 21 may be designed into a specific shape according to actual needs, and the specific shape may be the same as or different from the shape of the storage magnetic tunnel junction 22.

[0067] Continue reading Figures 11 to 13 In some possible implementations, the distances between the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 are equal. In this way, the gaps between the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 are substantially equal in width, which facilitates the formation of the dielectric layer 50 and ensures the quality of the dielectric layer 50. In some possible implementations, such as Figure 13 As shown, the sidewalls of the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 at one end adjacent to each other have the same shape, for example, both are arc-shaped. In this way, along the outer circumference of the storage magnetic tunnel junction 22, the spacing d between the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 remains the same.

[0068] For example, Figure 13 As shown, the storage magnetic tunnel junction 22 can be in the shape of an ellipse, i.e., the orthographic projection of the storage magnetic tunnel junction 22 on the substrate 10 is an ellipse, with the minor axis of the ellipse aligning with the direction of extension of the spin-orbit moment layer 30. The dummy magnetic tunnel junction 21 can be in the shape of a rectangular column, with the surface of the dummy magnetic tunnel junction 21 being recessed inward toward the storage magnetic tunnel junction 22, forming a curved surface. The orthographic projection of the dummy magnetic tunnel junction 21 on the substrate 10 comprises three sequentially connected straight lines and an arc. Along the circumference of the ellipse, the arc and the ellipse are spaced evenly apart.

[0069] In other examples, the storage magnetic tunnel junction 22 can be in the shape of an ellipse, i.e., the orthographic projection of the storage magnetic tunnel junction 22 on the substrate 10 is an ellipse, with the minor axis of the ellipse aligning with the extension direction of the spin-orbit moment layer 30. The dummy magnetic tunnel junction 21 can also be in the shape of an arcuate column, with both the surface of the dummy magnetic tunnel junction 21 facing the storage magnetic tunnel junction 22 and the surface facing away from the storage magnetic tunnel junction 22 concave in a direction away from the storage magnetic tunnel junction 22, forming an arc surface. Alternatively, the dummy magnetic tunnel junction 21 can be in the shape of a meniscus and concave in a direction away from the storage magnetic tunnel junction 22.

[0070] In other possible implementations, the spacing between the oppositely disposed sidewalls of the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 may also be unequal, to increase flexibility in the arrangement of the dummy magnetic tunnel junction 21. Exemplarily, the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 have the same shape, for example, the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 are both elliptical, i.e., the orthographic projections of the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 on the substrate 10 are both ellipses, and the sizes of the two ellipses may be equal or unequal.

[0071] The dielectric layer 50 at least fills the gap between the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 to connect the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21. In this way, the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, and the dielectric layer 50 form a single integral structure. Using the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, and the dielectric layer 50 as a mask to form the spin-orbit moment layer 30 ensures the continuity of the spin-orbit moment layer 30. Furthermore, there is no need to set a photomask for the spin-orbit moment layer 30, simplifying the formation process. Furthermore, overlay offset between the storage magnetic tunnel junction 22 and the spin-orbit moment layer 30 is avoided, ensuring alignment between the storage magnetic tunnel junction 22 and the spin-orbit moment layer 30. This improves write current efficiency and enhances the performance of the semiconductor storage structure.

[0072] The dielectric layer 50, the storage magnetic tunnel junction 22, and the top surface of the storage magnetic tunnel junction 22 are flush, and the above-mentioned top surface refers to the surface away from the spin-orbit moment layer 30. The dielectric layer 50 at least covers the sidewalls of the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 that face each other. The material of the dielectric layer 50 includes an insulating material, such as at least one of SiO2, SiN, and SiON, to ensure insulation isolation of the storage magnetic tunnel junction 22.

[0073] In other possible examples, the top surface of the dielectric layer 50 may be higher than the top surfaces of the storage magnetic tunnel junction 22 and the storage magnetic tunnel junction 22. In this way, the dielectric layer 50 also covers the storage magnetic tunnel junction 22 and the storage magnetic tunnel junction 22, thereby protecting the storage magnetic tunnel junction 22 and the storage magnetic tunnel junction 22, reducing the loss of the storage magnetic tunnel junction 22 and the storage magnetic tunnel junction 22 when etching downwards as a mask, thereby ensuring storage performance.

[0074] In some possible implementations, such as Figure 14 As shown, dummy magnetic tunnel junctions 21 are provided on both sides of the storage magnetic tunnel junction 22, and a dielectric layer 50 is located between the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22, that is, the dielectric layer 50 covers the sidewalls of the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 adjacent to each other, and the sidewalls of the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 away from each other are exposed. Alternatively, as Figure 12As shown, the dielectric layer 50 covers the entire side wall of the dummy magnetic tunnel junction 21 and the entire side wall of the storage magnetic tunnel junction 22, that is, the dielectric layer 50 surrounds the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22, and the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 are located in the dielectric layer 50.

[0075] In some other possible implementations, such as Figure 15 As shown, a dummy magnetic tunnel junction 21 is provided on one side of the storage magnetic tunnel junction 22, and a dielectric layer 50 is located between the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22, and covers the sidewall of the storage magnetic tunnel junction 22 away from the dummy magnetic tunnel junction 21. Exemplarily, the dielectric layer 50 covers the entire sidewall of the storage magnetic tunnel junction 22, and covers a portion of the sidewall of the dummy magnetic tunnel junction 21 adjacent to the storage magnetic tunnel junction 22, leaving a portion of the sidewall of the dummy magnetic tunnel junction 21 away from the storage magnetic tunnel junction 22 exposed. Alternatively, as Figure 16 As shown, the dielectric layer 50 also covers a portion of the sidewall of the dummy magnetic tunnel junction 21 away from the storage magnetic tunnel junction 22, that is, the dielectric layer 50 covers the entire sidewall of the dummy magnetic tunnel junction 21. The dummy magnetic tunnel junction 21 and the storage magnetic tunnel are located within the dielectric layer 50.

[0076] To implement data writing, in some possible implementations, the semiconductor storage structure further includes a substrate 10 having at least two conductive vias 11 disposed therein, the conductive vias 11 being located on either side of a storage magnetic tunnel junction 22. The orthographic projections of the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, and the dielectric layer 50 on the substrate 10 cover the at least two conductive vias on either side of the storage magnetic tunnel junction 22. Thus, the entirety formed by the dummy magnetic tunnel junction 21, the storage magnetic tunnel junction 22, and the dielectric layer 50 can meet the pattern requirements of the spin-orbit moment layer 30, such that the two ends of the spin-orbit moment layer 30 formed using this entirety as a mask are respectively connected to the conductive vias 11 on the substrate 10 and pass beneath the storage magnetic tunnel junction 22.

[0077] The substrate 10 supports the structures thereon and is made of semiconductor materials such as silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), or germanium-on-insulator (SOG). A conductive via 11 extends through the substrate 10, with both ends of the conductive via 11 exposed on either side of the substrate 10, connecting the spin-orbit moment layer 30 with external circuitry. At least two conductive vias 11 are provided to allow write currents of different directions to be passed into the spin-orbit moment layer 30. At least two conductive vias 11 are located on either side of the storage magnetic tunnel junction 22, with the orthographic projection of the storage magnetic tunnel junction 22 on the substrate 10 spaced from each conductive via 11. Exemplarily, there are multiple storage magnetic tunnel junctions 22, with a conductive via 11 provided on each side of the multiple storage magnetic tunnel junctions 22 facing away from each other.

[0078] In some possible implementations, such as Figure 15 and Figure 16 As shown, a dummy magnetic tunnel junction 21 is provided, and the dummy magnetic tunnel junction 21 covers a corresponding conductive via 11. The dielectric layer 50 also covers the sidewall of the storage magnetic tunnel junction 22 away from the dummy magnetic tunnel junction 21 and covers a corresponding conductive via 11. The dummy magnetic tunnel junction 21 is located on one side of the storage magnetic tunnel junction 22 and covers a corresponding conductive via 11 on that side. The dummy magnetic tunnel junction 21 covers a corresponding conductive via 11 means that the orthographic projection of the dummy magnetic tunnel junction 21 on the substrate 10 covers the corresponding conductive via 11.

[0079] In the above implementation, a dielectric layer 50 is required on the sidewall of the storage magnetic tunnel junction 22 away from the dummy magnetic tunnel junction 21, and this portion of the dielectric layer 50 covers a corresponding conductive via 11 to ensure that the formed spin-orbit moment layer 30 covers the conductive via 11, allowing the semiconductor storage structure to operate normally. The dielectric layer 50 covers a corresponding conductive via 11, which means that the orthographic projection of the dielectric layer 50 on the substrate 10 covers the corresponding conductive via 11. Thus, the two conductive vias 11 are located above the dummy magnetic tunnel junction 21 and the dielectric layer 50, respectively.

[0080] In some other possible implementations, such as Figure 12 and Figure 14 As shown, two dummy magnetic tunnel junctions 21 are provided; the two dummy magnetic tunnel junctions 21 respectively cover a corresponding conductive through hole 11. The two dummy magnetic tunnel junctions 21 are located on both sides of the storage magnetic tunnel junction 22, and respectively cover a conductive through hole 11 on that side, that is, two dummy magnetic tunnel junctions 21 correspond to two conductive through holes 11. Among them, the dummy magnetic tunnel junction 21 correspondingly covers a conductive through hole 11 means that the orthographic projection of the dummy magnetic tunnel junction 21 on the substrate 10 covers the corresponding conductive through hole 11. In this way, two dummy magnetic tunnel junctions 21 correspond to each other above the two conductive through holes 11.

[0081] In other possible implementations, one dummy magnetic tunnel junction 21 is provided, and the dummy magnetic tunnel junction 21 and the adjacent portion of the dielectric layer 50 correspondingly cover one conductive through-hole 11, and the portion of the dielectric layer 50 at one end of the storage magnetic tunnel junction 22 away from the dummy magnetic tunnel junction 21 correspondingly covers one conductive through-hole 11. Alternatively, two dummy magnetic tunnel junctions 21 are provided, wherein at least one dummy magnetic tunnel junction 21 and the adjacent portion of the dielectric layer 50 correspondingly cover one conductive through-hole 11. In this implementation, the dummy magnetic tunnel junction 21 is not located directly above the conductive through-hole 11, the orthographic projection of the dummy magnetic tunnel junction 21 on the substrate 10 partially overlaps with the conductive through-hole 11, and the dummy magnetic tunnel junction 21 and the dielectric layer 50 correspond to two conductive through-holes 11.

[0082] In some possible implementations, see Figure 17 and Figure 18 The semiconductor storage structure further includes an isolation layer 80 and a top electrode 90. The isolation layer 80 covers the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, the dielectric layer 50, the spin-orbit moment layer 30, and the substrate 10. The top electrode 90 is connected to the storage magnetic tunnel junction 22 and extends above the isolation layer 80. The material of the isolation layer 80 can be the same as that of the dielectric layer 50. For example, the material of the isolation layer 80 and the dielectric layer 50 are both silicon nitride, so that the isolation layer 80 and the dielectric layer 50 form an integral structure. The top electrode 90 penetrates the isolation layer 80 to contact and conduct with the storage magnetic tunnel junction 22. It can be formed by opening a hole in the isolation layer 80 and then filling it with a conductive material. The material of the top electrode 90 includes metal, such as copper. The top electrode 90 is also connected to an external circuit, for example, it is connected to the read circuit in the substrate 10 through a plug or conductive through-hole 11 in the isolation layer 80.

[0083] In some possible embodiments, the semiconductor storage structure further includes a mask layer (not shown in the figure). The mask layer is disposed above the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21. The mask layer is a conductive mask and can be a single-layer mask layer or a multi-layer mask layer. The material of the mask layer includes at least one of Ta, TaN, TiN, Ru, Co, and C. The mask layer can be used to connect to the top electrode 90 or an external circuit to enable the read circuit to be conductive, and can also protect the area above the storage magnetic tunnel junction 22 to prevent etching damage caused by the process.

[0084] The semiconductor storage structure in the embodiment of the present application includes a spin-orbit moment layer 30, a storage magnetic tunnel junction 22, a dummy magnetic tunnel junction 21, and a dielectric layer 50. The storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, and the dielectric layer 50 are all disposed on the spin-orbit moment layer 30, with the dummy magnetic tunnel junction 21 located adjacent to the storage magnetic tunnel junction 22. The dielectric layer 50 at least fills the gap between the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21, thereby connecting the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21. The spin-orbit moment layer 30 is formed by etching using the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, and the dielectric layer 50 as a mask. This eliminates the need for a photomask for the spin-orbit moment layer 30, simplifying the formation process. It also prevents overlay offset between the storage magnetic tunnel junction 22 and the spin-orbit moment layer 30, ensuring alignment between the storage magnetic tunnel junction 22 and the spin-orbit moment layer 30, thereby improving write current efficiency and enhancing the performance of the semiconductor storage structure.

[0085] The present application also provides a method for forming a semiconductor storage structure. Figure 19 , the forming method may specifically include the following steps:

[0086] Step S100: forming a spin-orbit moment initial layer and a magnetic tunnel junction stacking layer, wherein the magnetic tunnel junction stacking layer is located on the spin-orbit moment initial layer.

[0087] See Figure 20 and Figure 21 The spin-orbit moment initialization layer 31 and the magnetic tunnel junction stacking layer 23 can be formed by a deposition process. The spin-orbit moment initialization layer 31 is used to form the spin-orbit moment layer 30 (see Figure 11 ), which can be a single layer or a stacked layer. The material of the spin-orbit moment initial layer 31 includes a conductive material with a strong spin-orbit coupling effect, which will not be described here.

[0088] The spin-orbit moment initialization layer 31 can be formed on a substrate 10, which is typically placed on a stage. The substrate 10 supports the structures thereon and is made of a semiconductor material. At least two conductive vias 11 are also provided within the substrate 10. These vias 11 extend through the substrate 10, with their ends exposed on either side of the substrate 10, allowing write currents in different directions to be passed through the spin-orbit moment layer 30.

[0089] The magnetic tunnel junction stacking layer 23 is located on the spin-orbit moment initialization layer 31 and is used for the subsequent formation of the virtual magnetic tunnel junction 21 and the storage magnetic tunnel junction 22. The magnetic tunnel junction stacking layer 23 includes a free initialization layer, a barrier initialization layer and a reference initialization layer stacked in sequence, and the free initialization layer is arranged on the spin-orbit moment initialization layer 31. Among them, the free initialization layer is used to form a free layer, and its magnetization direction can be changed. The reference initialization layer is used to form a reference layer, and its magnetization direction is fixed. The barrier initialization layer is used to form a barrier layer to isolate the free layer and the reference layer. The material of the free initialization layer and the reference initialization layer both includes ferromagnetic material, and the material of the free initialization layer and the reference initialization layer can be the same or different. The material of the barrier initialization layer includes an insulating material.

[0090] Step S200: etching the magnetic tunnel junction stack layer to form a storage magnetic tunnel junction and a dummy magnetic tunnel junction, wherein the dummy magnetic tunnel junction is located beside the storage magnetic tunnel junction.

[0091] See Figures 22 to 26 , part of the magnetic tunnel junction stacking layer 23 is removed, and the remaining magnetic tunnel junction stacking layer 23 forms a storage magnetic tunnel junction 22 and a dummy magnetic tunnel junction 21. The storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 can be formed at the same time, simplifying the formation process. The dummy magnetic tunnel junction 21 is located next to the storage magnetic tunnel junction 22 and is spaced apart from the storage magnetic tunnel junction 22. One or more dummy magnetic tunnel junctions 21 and storage magnetic tunnel junctions 22 can be provided. Exemplarily, dummy magnetic tunnel junctions 21 are provided on both sides of the storage magnetic tunnel junction 22, or a dummy magnetic tunnel junction 21 is provided on one side of the storage magnetic tunnel junction 22.

[0092] The distances between the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 are equal. In this way, the gaps between the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 are substantially equal in width. Figure 13 ), when the deposition thickness is half of the gap between the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 can be connected, and the dielectric layer 50 can be formed as quickly as possible without the deposition thickness being too high, so as to facilitate the formation of the dielectric layer 50 and ensure the quality of the dielectric layer 50.

[0093] In some possible implementations, the sidewalls of the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 at one end adjacent to each other have the same shape, for example, both are arc surfaces. Exemplarily, the storage magnetic tunnel junction 22 can be in the shape of an elliptical cylinder, that is, the orthographic projection of the storage magnetic tunnel junction 22 on the substrate 10 is an ellipse, and the short axis of the ellipse is in the same direction as the extension of the spin-orbit moment layer 30. The dummy magnetic tunnel junction 21 can be in the shape of a rectangular cylinder, and the dummy magnetic tunnel junction 21 is concave inward toward the surface of the storage magnetic tunnel junction 22 to form an arc surface. The orthographic projection of the dummy magnetic tunnel junction 21 on the substrate 10 includes three straight lines and an arc line connected in sequence, and along the circumference of the ellipse, the spacing between the arc line and the ellipse is equal.

[0094] In some possible implementations, etching the magnetic tunnel junction stack layer 23 may specifically include: Figure 21 , forming a mask layer 60 on the magnetic tunnel junction stack layer 23, and forming a photoresist layer 70 on the mask layer 60; Figure 22 and Figure 23 , exposing and developing the photoresist layer 70, and using the developed photoresist layer 70 as a mask, etching the mask layer 60 to transfer the pattern to the mask layer 60; Figures 23 to 26 The magnetic tunnel junction stack layer 23 is etched downward using the etched mask layer 60 as a mask to form a storage magnetic tunnel junction 22 and a dummy magnetic tunnel junction 21 ; and the remaining mask layer 60 is removed.

[0095] The mask layer 60 may be a single layer or a stacked layer. For example, the mask layer 60 includes a first layer disposed on the magnetic tunnel junction stack layer 23 and a second layer disposed on the first layer. The first layer is made of at least one of Ta, TaN, TiN, Ru, Co, and C, and the second layer is made of at least one of SiO2 and SiN. The second layer may be completely consumed as a sacrificial layer during the etching process of the first layer.

[0096] In the example where at least two conductive through-holes 11 are provided in the substrate 10, the storage magnetic tunnel junction 22 and the conductive through-holes 11 are staggered, and the dummy magnetic tunnel junction 21 covers the corresponding conductive through-hole 11, that is, the orthographic projection of the storage magnetic tunnel junction 22 on the substrate 10 does not coincide with the conductive through-hole 11, and the orthographic projection of the dummy magnetic tunnel junction 21 on the substrate 10 covers the corresponding conductive through-hole 11, or partially overlaps with the corresponding conductive through-hole 11.

[0097] Step S300: forming a dielectric layer, wherein the dielectric layer at least fills the gap between the storage magnetic tunnel junction and the dummy magnetic tunnel junction.

[0098] See Figures 27 to 29 The dielectric layer 50 is located in the gap between the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21, and connects the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21. The dielectric layer 50 is made of an insulating material, such as at least one of SiO2, SiN, and SiON. The top surfaces of the dielectric layer 50, the storage magnetic tunnel junction 22, and the dummy magnetic tunnel junction 21 can be flush. The orthographic projection of the overall structure formed by the dielectric layer 50, the storage magnetic tunnel junction 22, and the dummy magnetic tunnel junction 21 on the substrate 10 covers at least one conductive via 11 on each side of the storage magnetic tunnel junction 22, thereby ensuring that the semiconductor storage structure can operate normally.

[0099] In some possible examples, the dielectric layer 50 also covers the ends of the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 that are away from each other. For example, the dielectric layer 50 covers the entire side wall of the dummy magnetic tunnel junction 21 and the entire side wall of the storage magnetic tunnel junction 22, that is, the dielectric layer 50 surrounds the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22, and the dummy magnetic tunnel junction 21 and the storage magnetic tunnel junction 22 are located within the dielectric layer 50.

[0100] Step S400: using the storage magnetic tunnel junction, the dummy magnetic tunnel junction and the dielectric layer as masks, etching the spin-orbit moment initial layer to form a spin-orbit moment layer.

[0101] See Figure 28 and Figure 12 Using the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, and the dielectric layer 50 as masks, the spin-orbit moment initiation layer 31 is etched, partially removing the spin-orbit moment initiation layer 31. The remaining spin-orbit moment initiation layer 31 forms the spin-orbit moment layer 30, which serves as the bottom electrode. At this point, a portion of the top surface of the substrate 10 is exposed. This eliminates the need for a mask for the spin-orbit moment layer 30, simplifying the formation process. It also prevents overlay offset between the storage magnetic tunnel junction 22 and the spin-orbit moment layer 30, ensuring alignment between the storage magnetic tunnel junction 22 and the spin-orbit moment layer 30, thereby improving write current efficiency and enhancing the performance of the semiconductor storage structure.

[0102] For some possible examples, see Figure 17 and Figure 18 After forming the spin-orbit moment layer 30, it also includes: forming an isolation layer 80 and a top electrode 90, the isolation layer 80 covers the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, the dielectric layer 50, the spin-orbit moment layer 30 and the substrate 10, and the top electrode 90 is connected to the storage magnetic tunnel junction 22 and extends above the isolation layer 80.

[0103] The material of the isolation layer 80 can be the same as that of the dielectric layer 50. For example, the isolation layer 80 and the dielectric layer 50 can both be made of silicon nitride, so that the isolation layer 80 and the dielectric layer 50 form an integral structure. The top electrode 90 penetrates the isolation layer 80 to contact and conduct with the storage magnetic tunnel junction 22. It can be formed by opening a hole in the isolation layer 80 and then filling it with a conductive material. The material of the top electrode 90 includes metal, such as copper. The top electrode 90 is also connected to an external circuit, for example, through a plug or conductive via 11 in the isolation layer 80 to conduct with the read circuit in the substrate 10.

[0104] In the method for forming a semiconductor storage structure in an embodiment of the present application, a spin-orbit moment initial layer 31 and a magnetic tunnel junction stacking layer 23 are formed, and the magnetic tunnel junction stacking layer 23 is located on the spin-orbit moment initial layer 31; the magnetic tunnel junction stacking layer 23 is etched to form a storage magnetic tunnel junction 22 and a dummy magnetic tunnel junction 21, and the dummy magnetic tunnel junction 21 is located next to the storage magnetic tunnel junction 22; a dielectric layer 50 is formed, and the dielectric layer 50 at least fills the gap between the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21; and the spin-orbit moment initial layer 31 is etched using the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21 and the dielectric layer 50 as a mask to form a spin-orbit moment layer 30. The storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21 and the dielectric layer 50 are used to pattern the spin-orbit moment initial layer 31. The spin-orbit moment layer 30 can be formed without separate photolithography, and there is no need to set a mask for the spin-orbit moment layer 30, which simplifies the formation process. At the same time, it can also avoid overlay offset between the storage magnetic tunnel junction 22 and the spin-orbit moment layer 30, ensure that the storage magnetic tunnel junction 22 and the spin-orbit moment layer 30 are aligned, thereby improving the write current efficiency and improving the performance of the semiconductor storage structure.

[0105] In some possible implementations, see Figures 30 to 32 ,as well as Figure 28 , forming a dielectric layer 50 (step S300), including: depositing an initial dielectric layer 51, the initial dielectric layer 51 at least covering the spin-orbit moment initial layer 31, the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21, and filling the gap between the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21; etching the initial dielectric layer 51, removing a portion of the initial dielectric layer 51, and the remaining initial dielectric layer 51 forms the dielectric layer 50.

[0106] The initial dielectric layer 51 can be formed by vapor deposition, such as plasma enhanced chemical vapor deposition (PECVD). In the initial stage of deposition of the initial dielectric layer 51, a thin layer of the initial dielectric layer 51 covers the top surface of the spin-orbit moment initial layer 31, the sidewalls of the storage magnetic tunnel junction 22, and the sidewalls of the dummy magnetic tunnel junction 21.

[0107] As the deposition thickness of the initial dielectric layer 51 increases, the initial dielectric layer 51 on the side walls of the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 slowly extends in a direction parallel to the top surface of the spin-orbit moment initial layer 31, that is, the initial dielectric layer 51 is deposited on the side walls of the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 and diffuses outward.

[0108] When the deposition thickness of the initial dielectric layer 51 reaches at least half of the minimum spacing between the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21, that is, the thickness of the initial dielectric layer 51 on the side walls of the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 is not less than half of the spacing between the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21, the initial dielectric layer 51 on the side walls of the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 contacts and is joined to the initial dielectric layer 51 above the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21 to form a complete and continuous step 52. This can achieve the formation of a pattern corresponding to the spin-orbit moment layer 30 as quickly as possible while keeping the deposition thickness of the initial dielectric layer 51 as low as possible.

[0109] like Figure 31 As shown, the sidewalls and top surface of the storage magnetic tunnel junction 22, as well as the initial dielectric layer 51 on the sidewalls and top surface of the dummy magnetic tunnel junction 21, are higher than the initial dielectric layer 51 on the top surface of the spin-orbit moment initial layer 31. The sidewalls and top surface of the storage magnetic tunnel junction 22, as well as the initial dielectric layer 51 on the sidewalls and top surface of the dummy magnetic tunnel junction 21 correspond to the pattern of forming the spin-orbit moment layer 30, and its height is approximately equal to that of the magnetic tunnel junction stack layer 23 (see FIG. Figure 21 ) and the total thickness of the mask layer 60 (if any).

[0110] The etching angle when etching the initial dielectric layer 51 can be 10° to 90°. For example, the initial dielectric layer 51 can be etched in the vertical direction using anisotropic etching. The vertical direction refers to the direction perpendicular to the top surface of the initial dielectric layer 51. The thickness of the initial dielectric layer 51 on the sidewalls of the storage magnetic tunnel junction 22 and the sidewalls of the dummy magnetic tunnel junction 21 is greater than the thickness of the initial dielectric layer 51 on the top surface of the storage magnetic tunnel junction 22, the top surface of the dummy magnetic tunnel junction 21, and the top surface of the spin-orbit moment initial layer 31. The initial dielectric layer 51 is generally sunken away from the surface of the spin-orbit moment initial layer 31. After etching the initial dielectric layer 51, the morphology of the step 52 of the initial dielectric layer 51 can be retained.

[0111] In some possible examples, the initial dielectric layer 51 is etched to remove the entire initial dielectric layer 51 on the top surfaces of the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, and the spin-orbit moment initial layer 31, and retain a portion of the initial dielectric layer 51 on the side walls of the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21. In this way, the top surfaces of the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21, and the spin-orbit moment initial layer 31 can be exposed, and the remaining initial dielectric layer 51 forms the dielectric layer 50.

[0112] It can be understood that when the etching conditions of the initial dielectric layer 51 cause the consumption rate of the initial dielectric layer 51 to be higher than that of the spin-orbit moment initial layer 31, it is necessary to remove the entire initial dielectric layer 51 on the top surface of the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21 and the spin-orbit moment initial layer 31, and change the etching conditions so that the consumption rate of the spin-orbit moment initial layer 31 is not lower than the consumption rate of the dielectric layer 50 and the mask layer 60 (if any), so that in the subsequent etching process of the spin-orbit moment initial layer 31, the dielectric layer 50 always exists above the area where the spin-orbit moment initial layer 31 needs to be retained, and the mask layer 60 (if any) exists above the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21, thereby ensuring the shape of the formed spin-orbit moment layer 30 and the performance of the semiconductor storage structure.

[0113] In other possible examples, part of the initial dielectric layer 51 on the top surface of the storage magnetic tunnel junction 22, the dummy magnetic tunnel junction 21 and the spin-orbit moment initial layer 31 is removed, and the initial dielectric layer 51 is thinned without exposing the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21. While ensuring that the step 52 morphology of the initial dielectric layer 51 is transferred downward, excessive consumption of the storage magnetic tunnel junction 22 / mask layer 60 (if any) can also be avoided.

[0114] It is understood that to facilitate etching of the spin-orbit moment initiation layer 31, the initial dielectric layer 51 can be thinned, retaining the step 52 morphology of the initial dielectric layer 51, and reducing the overall thickness of the initial dielectric layer 51. When etching the spin-orbit moment initiation layer 31, the etching conditions are modified so that the consumption rate of the spin-orbit moment initiation layer 31 is no less than the consumption rate of the dielectric layer 50 and the mask layer 60 (if any). This ensures that during the subsequent etching of the spin-orbit moment initiation layer 31, a sufficiently thick dielectric layer 50 is present above the area where the spin-orbit moment initiation layer 31 needs to be retained, and that the mask layer 60 (if any) is present above the storage magnetic tunnel junction 22 and the dummy magnetic tunnel junction 21. This ensures the shape of the formed spin-orbit moment layer 30 and the performance of the semiconductor storage structure.

[0115] In other possible examples, before etching the spin-orbit moment initial layer 31, part of the initial dielectric layer 51 may not be removed, and the entire deposited initial dielectric layer 51 may be retained. Afterwards, the initial dielectric layer 51 and the spin-orbit moment initial layer 31 are etched simultaneously to obtain the dielectric layer 50 and the spin-orbit moment layer 30.

[0116] It can be understood that when the etching conditions of the initial dielectric layer 51 do not consume the initial dielectric layer 51 at a rate no higher than that of the spin-orbit moment initial layer 31 , etching the spin-orbit moment initial layer 31 will not consume more initial dielectric layer 51 , and there is no need to pre-etch the initial dielectric layer 51 .

[0117] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor storage structure, characterized in that: include: A spin-orbit moment layer, and a storage magnetic tunnel junction, a dummy magnetic tunnel junction, and a dielectric layer arranged on the spin-orbit moment layer; The dummy magnetic tunnel junction is located beside the storage magnetic tunnel junction; The dielectric layer at least fills the gap between the storage magnetic tunnel junction and the dummy magnetic tunnel junction; The spin-orbit moment layer is formed by etching using the storage magnetic tunnel junction, the dummy magnetic tunnel junction and the dielectric layer as masks.

2. The semiconductor storage structure according to claim 1, wherein: Also includes: a substrate, wherein at least two conductive through holes are provided in the substrate, and the conductive through holes are located on both sides of the storage magnetic tunnel junction; The orthographic projections of the storage magnetic tunnel junction, the dummy magnetic tunnel junction, and the dielectric layer on the substrate cover at least two of the conductive through holes on both sides of the storage magnetic tunnel junction.

3. The semiconductor storage structure according to claim 2, wherein: The dummy magnetic tunnel junction is provided with one, and the dummy magnetic tunnel junction covers one corresponding conductive through hole; The dielectric layer also covers the side wall of the storage magnetic tunnel junction away from the dummy magnetic tunnel junction and correspondingly covers one of the conductive through holes.

4. The semiconductor storage structure according to claim 2, wherein: There are two dummy magnetic tunnel junctions; The two dummy magnetic tunnel junctions respectively cover one corresponding conductive through hole.

5. The semiconductor storage structure according to any one of claims 1 to 4, characterized in that: The storage magnetic tunnel junction and the dummy magnetic tunnel junction are formed by synchronous etching.

6. The semiconductor storage structure according to any one of claims 1 to 4, characterized in that: The distances between the side walls of the dummy magnetic tunnel junction and the storage magnetic tunnel junction that are opposite to each other are equal.

7. A method for forming a semiconductor storage structure, characterized in that: include: forming a spin-orbit moment initial layer and a magnetic tunnel junction stacking layer, wherein the magnetic tunnel junction stacking layer is located on the spin-orbit moment initial layer; Etching the magnetic tunnel junction stack layer to form a storage magnetic tunnel junction and a dummy magnetic tunnel junction, wherein the dummy magnetic tunnel junction is located next to the storage magnetic tunnel junction; forming a dielectric layer, wherein the dielectric layer at least fills a gap between the storage magnetic tunnel junction and the dummy magnetic tunnel junction; The spin-orbit moment initial layer is etched using the storage magnetic tunnel junction, the dummy magnetic tunnel junction and the dielectric layer as masks to form a spin-orbit moment layer.

8. The forming method according to claim 7, wherein: Forming the dielectric layer includes: Depositing an initial dielectric layer, wherein the initial dielectric layer at least covers the spin-orbit moment initial layer, the storage magnetic tunnel junction, and the dummy magnetic tunnel junction, and fills a gap between the storage magnetic tunnel junction and the dummy magnetic tunnel junction; The initial dielectric layer is etched to remove a portion of the initial dielectric layer, and the remaining initial dielectric layer forms the dielectric layer.

9. The forming method according to claim 8, wherein: Removing part of the initial dielectric layer, comprising: All of the initial dielectric layers on the top surfaces of the storage magnetic tunnel junction, the dummy magnetic tunnel junction, and the spin-orbit moment initial layer are removed to expose the storage magnetic tunnel junction and the dummy magnetic tunnel junction.

10. The forming method according to claim 8, wherein: The thickness of the initial dielectric layer on the sidewalls of the storage magnetic tunnel junction and the dummy magnetic tunnel junction is not less than half of the distance between the storage magnetic tunnel junction and the dummy magnetic tunnel junction.

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