Wafer bonding process with reduced overlay distortion

Abstract

An embodiment method includes determining an upper vacuum condition, a lower vacuum condition, a bond gap distance, and a striker pressure condition based on measuring residual distortion from a previously bonded wafer. The method includes applying the upper vacuum condition to the upper wafer using an upper wafer holder, the upper vacuum condition being applied to a back side of the upper wafer, and the upper wafer having a front side opposite the back side. The method includes applying the lower vacuum condition to a lower wafer using a lower wafer holder, the lower vacuum condition being applied to a back side of the lower wafer, and the lower wafer having a front side opposite the back side. The method includes positioning a front side of the upper wafer over a front side of the lower wafer to create the bond gap distance between the upper wafer and the lower wafer. The method includes impacting a back side of the upper wafer with a striker using the striker pressure condition to bond a front side of the upper wafer and a front side of the lower wafer together.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a wafer bonding process with reduced overlay distortion. Background Art

[0002] In the production of integrated circuits (ICs), precise alignment and bonding of multiple layers is crucial to ensuring the functionality and performance of the final device. Overlay distortion (also known as misalignment) refers to the misalignment or mismatch of patterns and features between different layers during the wafer bonding process. Overlay distortion can lead to various problems, such as reduced device yield, degraded electrical performance, and increased manufacturing costs.

[0003] Existing wafer bonding technologies, such as direct wafer bonding, thermocompression bonding, and adhesive bonding, have been used to achieve strong bonds between wafers. However, these methods often suffer from overlay distortion due to inherent mechanical and thermal stresses generated during the bonding process. These stresses can cause warping, bowing, or tilting of the bonded wafers, leading to misalignment of patterns and features, a phenomenon known as overlay distortion. Summary of the Invention

[0004] According to a preferred embodiment of the present invention, a method includes determining an upper vacuum condition, a lower vacuum condition, a bond gap distance, and a striker pressure condition based on measuring residual distortion from previously bonded wafers. The method includes applying the upper vacuum condition to an upper wafer using an upper wafer holder, the upper vacuum condition being applied to a rear side of the upper wafer, and the upper wafer having a front side opposite the rear side. The method includes applying the lower vacuum condition to a lower wafer using a lower wafer holder, the lower vacuum condition being applied to a rear side of the lower wafer, and the lower wafer having a front side opposite the rear side. The method includes positioning the front side of the upper wafer above the front side of the lower wafer to generate the bond gap distance between the upper and lower wafers. The method also includes striking the rear side of the upper wafer with a striker using the striker pressure condition to bond the front side of the upper wafer to the front side of the lower wafer.

[0005] A wafer bonding method for reducing overlay distortion includes: forming a first plurality of bonded wafers using multiple process recipes, the forming including: for each of the first plurality of bonded wafers, striking the back side of the first wafer with a striker to bond the first wafer to a second wafer, each of the first plurality of bonded wafers being formed using a different process recipe from the multiple process recipes. The method includes: measuring the overlay distortion of each of the first plurality of bonded wafers, and determining the residual overlay distortion of each of the first plurality of bonded wafers based on the measurement. The method includes: selecting one of the first plurality of bonded wafers having a lower residual overlay distortion value. The method includes: determining a target process recipe associated with forming the selected one of the first plurality of bonded wafers. And the method includes: forming a second plurality of bonded wafers using the target process recipe.

[0006] An adaptive wafer bonding method for reducing overlay distortion includes forming a plurality of bonded wafers by performing bonding cycles, each cycle comprising: receiving a wafer group to be bonded, the wafer group comprising a first wafer and a second wafer. Each cycle comprises: measuring the overlay distortion of a previously bonded wafer, and determining a residual overlay distortion of the previously bonded wafer based on the measurement. Each cycle comprises: determining a process recipe based on the previous residual overlay distortion. Each cycle comprises: positioning the first wafer to be aligned with the second wafer and separated by a bond gap distance. And each cycle comprises: striking the back side of the first wafer with a striker to bond the first wafer and the second wafer together to form a bonded wafer.

[0007] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1A is a schematic cross-sectional view of a direct bonding method, showing the initial alignment and spacing distance of the upper and lower wafers to be bonded;

[0010] Figure 1B is a cross-sectional schematic diagram of a direct bonding method, showing the start of the striker bringing the upper wafer to the lower wafer to be bonded;

[0011] Figure 1C is a schematic cross-sectional view of a direct bonding method showing that a striker has brought the upper and lower wafers into direct contact, causing the bond front to propagate across the surfaces of the wafers;

[0012] Figure 1Dis a schematic cross-sectional view of a direct bonding method, showing the combined wafer after a pre-bonding process step at room temperature of a conventional direct bonding method;

[0013] Figure 2A is a schematic diagram of two wafers that are patterned so that overlay distortion can be measured by a scanner once the wafers are bonded;

[0014] Figure 2B is a schematic diagram of two wafers that have been bonded using the direct bonding method, which has virtually no overlay distortion;

[0015] Figure 2C Schematic diagram of two wafers that have been bonded using a direct bonding method, where the overlay distortion is the result of one of the wafers being rotated;

[0016] Figure 2D Schematic diagram of two wafers that have been bonded using a direct bonding method, where the overlay distortion is the result of a translation in the wafers;

[0017] Figure 2E Schematic diagram of two wafers that have been bonded using a direct bonding method, where the overlay distortion is the result of expansion in one of the wafers;

[0018] Figure 2F is a schematic diagram of two wafers that have been bonded using a direct bonding method, where the overlay distortion present is the result of a combination of rotation, translation, and expansion of one of the wafers;

[0019] Figure 3A is a schematic diagram of a wafer holder in an embodiment, the wafer holder being a vacuum chuck with all chuck vacuum zones at the edge of the wafer enabled;

[0020] Figure 3B is a schematic diagram of a wafer holder in an embodiment, the wafer holder being a vacuum chuck with only half of the edge vacuum region of the vacuum chuck being enabled;

[0021] Figure 4 is a flow chart of a wafer bonding method for reducing overlay distortion according to an embodiment;

[0022] Figure 5 is a flow chart of the modified direct bonding method;

[0023] Figure 6 is a flow chart of an adaptive wafer bonding method for reducing overlay distortion according to an embodiment;

[0024] Figure 7 is a system diagram of an embodiment of a wafer processing tool for implementing the wafer bonding method of the present disclosure;

[0025] Figure 8 A flow chart illustrating a method for direct wafer bonding is presented;

[0026] Figure 9 A flow chart illustrating a method for determining a target process recipe for direct wafer bonding to reduce residual overlay distortion is presented; and

[0027] Figure 10 A flow chart illustrating a method for determining a target process recipe for direct wafer bonding in an adaptive approach is presented. DETAILED DESCRIPTION

[0028] Wafer bonding methods of the present disclosure are used in a variety of semiconductor processing applications to manufacture semiconductor devices. Some examples of semiconductor processing applications using wafer bonding methods include the manufacture of integrated circuits (ICs), the manufacture of microelectromechanical systems (MEMS) and nanoelectromechanical systems (NEMS), and the stacking of many processed layers of microelectronic devices (3D integration). There are many different wafer bonding methods, including direct bonding (also known as fusion bonding), thermocompression bonding, and adhesive bonding.

[0029] The quality of the bond between wafers depends on the uniformity and integrity of the bond, as well as the maintenance of wafer alignment across the entire wafer bonding interface. Overlay distortion (also known as misalignment) refers to the misalignment or mismatch of patterns and features between different surface layers during the wafer bonding process. Overlay distortion can lead to various problems such as reduced device yield, degraded electrical performance, and increased manufacturing costs. The minimum achievable overlay distortion usually depends on the manufacturing hardware.

[0030] The present disclosure describes a wafer bonding method. In various embodiments, the wafer bonding method generates a direct bonding recipe for a direct bonding method, thereby producing an optimized direct bonding recipe. The direct bonding recipe minimizes overlay distortion by identifying and adjusting bonding parameters. By systematically changing the bonding parameters of the best known recipe, the wafer bonding method improves (or fine-tunes) the best known recipe and produces a new wafer bonding process that minimizes wafer overlay distortion. As a result, overlay distortion is reduced, and semiconductor manufacturers do not have to purchase expensive new wafer processing tools to achieve similar results. Another result of reducing overlay distortion in bonded wafers is an increase in the yield of manufactured semiconductor devices.

[0031] This disclosure first describes the wafer bonding process, which is called direct bonding, and then continues with Figures 1A to 1D The bonding steps of the direct bonding process are shown in Figures 2A to 2F to show different examples of linear overlay distortion that can occur when bonding a pair of wafers in a direct bonding approach. Figures 3A to 3BAn exemplary wafer holder with various configurable chuck vacuum zones is described. Figure 4 and Figure 6 A flow chart describing the linear calibration and adaptive version of the wafer bonding method will be used. Figure 7 An embodiment wafer processing tool using direct bonding is described.

[0032] Direct bonding (also known as fusion bonding) is a wafer bonding method in which the surfaces of two wafers are brought into direct contact and bonded without the use of any adhesive or any other intermediate layer. The direct bond between the two wafers is the result of a chemical bond between the two surfaces of the wafers. The chemical bond formed can be the result of a van der Waals bond or a covalent bond. The direct bonding method includes the steps of wafer pretreatment, prebonding, bonding and annealing, and prebonding involves aligning and positioning the wafers to each other. The wafer surfaces should be clean, flat and smooth enough to achieve good bonding. However, bonding defects may occur when the wafers are bonded, which may lead to device failure in later processing steps. Overlay distortion is a type of bonding defect.

[0033] Figures 1A to 1D 1 shows a cross-sectional view of a wafer during a pre-bonding process for bonding wafer 50. Wafer 50 includes an upper wafer 104 and a lower wafer 106 to be bonded together. Figures 1A to 1D As shown, wafer 50 is positioned within a wafer bonding tool that includes an upper wafer holder 102, a lower wafer holder 108, a gap 110 separating upper wafer 104 and lower wafer 106, striker 100, and a bonding gap distance d (separating upper wafer 104 from lower wafer 106, initially at Figure 1A The upper wafer 104 is held to the upper wafer holder 102 by a pressure differential generated by applying a vacuum between the upper wafer 104 and the upper wafer holder 102. Similarly, the lower wafer 106 is held to the lower wafer holder 108 by a vacuum.

[0034] Figure 1A The initial configuration of wafer 50 is depicted after upper wafer 104 and lower wafer 106 are loaded, aligned, and positioned such that wafers 50 are separated by a bonding gap distance d.

[0035] Figure 1B The beginning of the process of bringing the upper wafer 104 into direct contact with the lower wafer 106 using the striker 100 is shown.

[0036] Once the wafers have been properly aligned and brought to a spacing of the bonding gap distance d, the striker 100 is applied to bring the wafers into direct contact. During this process, the upper wafer 104 is not fully released by the upper wafer holder 102, causing the upper wafer 104 to bow. A gap 110 begins to be squeezed out from between the upper wafer 104 and the lower wafer 106. In an embodiment, the gap 110 separating the wafers 50 can be air, and in different embodiments can also be an inert gas such as argon or nitrogen. In an embodiment, the gap 110 separating the two wafers 50 can include residual cleaning solution remaining after a pre-treatment step. In an embodiment, the striker 100 is integrated with the lower wafer holder 108 and initiates bonding by striking the lower wafer 106 towards the upper wafer 104.

[0037] After the process of striking the upper wafer 104 with the striker 100, the upper wafer 104 is in direct contact with the lower wafer 106 in a smaller area, such as Figure 1C As shown in FIG. 1 , after the upper wafer 104 contacts the lower wafer 106, a bonding front originating from the contact area propagates over the surfaces of the upper and lower wafers 104, 106. As the bonding front propagates, the upper wafer 104 is released from the upper wafer holder 102, bringing the entire surface of the upper wafer 104 into contact with the entire surface of the lower wafer 106. Additionally, as the direct bonding front propagates over the surfaces, a gap 110 separating the wafers is squeezed out from between the two wafers.

[0038] The bond formed between the upper wafer 104 and the lower wafer 106 is based on intermolecular interactions, which may be the result of van der Waals forces, hydrogen bonds, or strong covalent bonds.

[0039] Figure 1D The upper wafer 104 and the lower wafer 106 are shown bonded to form a bonded wafer. The striker 100 brings the upper wafer 104 and the lower wafer 106 into contact, and the bond front propagates across their surfaces, so that the upper and lower wafers are no longer separated by the dielectric and form a bonded wafer. Typically, after forming the bonded wafer, the bonded wafer will be exposed to elevated temperatures during an annealing process to help strengthen the bond between the two wafers. In some embodiments, only surface forces can hold the wafers together until annealing. After annealing, the direct bonding process is complete, and any overlay distortion caused by the bonding of the two wafers can no longer be mitigated.

[0040] Overlay distortions are generated by direct bonding methods in many ways and can be categorized as arising from linear distortion or from nonlinear distortion (referred to as residual). Linear distortions can be divided into three different categories: translational distortion, rotational distortion, or dilation distortion. Unlike nonlinear distortions, which can be a significant portion of the distortion, linear distortions are generally easier to prevent and address. Embodiments of this application describe different techniques for reducing overlay distortions specifically caused by residuals.

[0041] Typically, the same best known recipe is used for all wafers, so any wafer overlay distortion resulting from the direct bonding method remains constant and propagates to all wafers bonded using that recipe. By improving the direct bonding recipe, wafer overlay distortion is reduced, and the new recipe can be used for all future direct bonds performed by a specific wafer bonding tool.

[0042] A scanner can be used to scan a wafer that has been patterned to measure overlay distortion. Using measurements of the deviations of the patterned wafer, the scanner determines the overlay distortion by generating a distortion map. Figures 2A to 2F Examples of how linear overlay distortion and overlay distortion appear are shown in .

[0043] Figures 2A to 2F Shown are two wafers being patterned and the various types of linear overlay distortion that can occur after bonding.

[0044] Figure 2A is a schematic diagram of two wafers that are patterned so that overlay distortion can be measured by a scanner once the wafers are bonded using a direct bonding method. Figure 2A The wafers in the PCB have not yet been bonded. Figure 2A Shown are a first wafer 201 patterned with a left cross 202a and a right cross 202b, and a second wafer 203 patterned with a left square 204a and a right square 204b. Once the first wafer 201 and the second wafer 203 are bonded together, the alignment of the patterns (202a-b and 204a-b) can be used to measure overlay distortion.

[0045] Figure 2B An exemplary bonded wafer is shown with no overlay distortion. A first wafer 201 has been bonded to a second wafer 203 with the left cross 202a perfectly aligned with the left square 204a and the right cross 202b perfectly aligned with the right square 204b. Figure 2B is an ideal situation where there is no observable overlay distortion in the bonded wafer.

[0046] Figure 2CThis example illustrates rotational distortion between bonded wafers, which is a linear overlay distortion. Rotational distortion is the result of alignment differences between the upper and lower chucks in the direct bonding tool, as well as wafer handling differences between the upper and lower wafers. In this example, the centers of the first wafer 201 and the second wafer 203 are aligned, but there is rotation, resulting in misalignment of the left cross 202a with the left square 204a, and misalignment of the right cross 202b with the left square 204b. These factors lead the scanner to determine that the overlay distortion is the result of rotational distortion.

[0047] Figure 2D This example illustrates translational distortion between bonded wafers, which is linear overlay distortion. Translational distortion is the result of alignment differences between the upper and lower chucks in the direct bonding tool, as well as wafer handling differences between the upper and lower wafers. In this example, the center of the first wafer 201 and the center of the second wafer 203 are misaligned. Furthermore, the distances from the center of the left cross 202a to the center of the left square 204a and from the center of the right cross 202b to the center of the right square 204b are equidistant. These factors lead the scanner to determine that the overlay distortion is the result of translational distortion.

[0048] Figure 2E The figure shows expansion distortion between bonded wafers, which is a linear overlay distortion. Expansion distortion is the result of the wafers shrinking or expanding during the direct bonding process. Additional expansion distortion may be caused by each wafer having a different coefficient of thermal expansion (CTE), which will cause the wafers to expand at different rates during the annealing process. In this embodiment, the center of the first wafer 201 and the center of the second wafer 203 are aligned. The outer edges of the two wafers are not aligned. In addition, the center of the left cross 202a is equidistant from the center of the left square 204a and the center of the right cross 202b is equidistant from the center of the right square 204b, and the center of each pattern is equidistant towards the center of the wafer. These factors allow the scanner to determine that the overlay distortion is the result of expansion distortion.

[0049] Figure 2F The presence of all linear forms of coverage distortion is demonstrated. Figure 2F The resulting bonded wafers result from a combination of rotational, translational, and expansion distortions. The second wafer 203 has expanded, as is evident from the misalignment of the outer edges of the two wafers. The second wafer 203 has translated, as is evident from the misalignment of the centers of the wafers. And the second wafer 203 has rotated, as is evident from the fact that the left square 204a is roughly flush with the left cross 202a, while the right square 204b is below the right cross 202b.

[0050] Figures 2A to 2FAny overlay distortion present in the bonded wafer that is not represented by the linear overlay distortion shown is nonlinear overlay distortion. Nonlinear overlay distortion is also referred to as residual. The wafer bonding method of the present disclosure reduces the residual of direct bonding methods. This reduction in residual is achieved by identifying and modifying certain bonding parameters of the direct bonding recipe.

[0051] Figures 3A to 3B A vacuum chuck is shown that can be used as both an upper wafer holder and a lower wafer holder in embodiments. The vacuum chuck holds the wafer by using a vacuum to pump air out of a cavity behind the chuck, so that the air pressure holds the wafer in place. The cavity of the vacuum chuck is called a vacuum zone, such as the upper wafer holder vacuum zone, and different zones can be configured to be active or inactive. Figures 3A to 3B Two bonding parameters are presented that can be varied to minimize residue in direct bonding methods. In the examples, Figures 3A to 3B The vacuum zone shown is only one possible zone configuration. In an embodiment, the vacuum zone configuration may include multiple vacuum rings from the center to the edge of the vacuum chuck (although Figure 3B Only two are shown), and these rings can be further segmented (such as Figure 3B segments of the outer ring shown).

[0052] refer to Figure 3A , the vacuum chuck 301 can be the lower wafer holder 108 or the upper wafer holder 102 of FIG. 1 . One of the variable bonding parameters in the embodiment direct bonding method is the configuration of the vacuum zones of the vacuum chuck. These vacuum zones can be enabled or disabled. When the vacuum zones are enabled, a vacuum is applied between the wafer and the chuck to attract the wafer to the chuck. Either or both of these wafers (i.e., the upper wafer holder 102 and the lower wafer holder 108) can include a configurable vacuum zone. Figure 3A All vacuum regions at the edge of the vacuum chuck 301 are shown in an activated state 300, which is referred to as a full edge configuration.

[0053] refer to Figure 3B , the vacuum chuck 301 can be the lower wafer holder 108 or the upper wafer holder 102 of FIG. 1 . Figure 3B In the embodiment, only half of the vacuum area is in the enabled state 300, while the other vacuum areas are not enabled 303. This use case can be referred to as an edge-to-diagonal configuration. The same vacuum chuck can be operated in either full-edge or edge-to-diagonal configurations. In various embodiments, the percentage of non-enabled areas can be used as a bonding parameter. Figure 3B In the embodiment, this percentage is about 50%, but in other embodiments, this percentage can be designed to vary between 0% and 80%, as an example.

[0054] Figure 4 4 is a flow chart of a method for fine-tuning wafer bonding to reduce overlay distortion according to an embodiment of the present application.

[0055] The method begins at block 402 where a baseline recipe for a direct bonding method for bonding two wafers is used to bond the two wafers. In an embodiment, the bonding method used in block 402 is to bond the two wafers using a direct bonding method. Figure 5 The flow chart describes the wafer bonding method in more detail.

[0056] Figure 5 is a flow chart for starting the direct bonding method. Figure 5 Can mean happening in Figure 4 All steps in block 402 of FIG.

[0057] In block 502, the wafers are pre-treated to clean, planarize, smooth, and activate the wafer surfaces. Wafer pre-treatment can be performed to increase the potential bond strength between the two wafers to be bonded. The wafers are planarized and smoothed to increase the potential bonding surface area and ensure that there are no large gaps between the two wafers that could trap contaminants. If the wafers are sufficiently smoothed and planarized, bonding will begin as soon as the wafers come into atomic contact. The wafers can be cleaned to ensure that the two wafers are free of impurities that could cause particle, organic, or ionic contamination. Cleaning can be achieved through a variety of treatments, such as plasma treatment, UV / ozone cleaning, or wet chemical cleaning procedures. Surface activation fine-tunes the surface energy and friction along the bonding interface and can modify distortion during the bonding process. The activation process (or surface activation) involves bombarding the surface of the wafer with plasma to modify the surface. This modification creates active sites that terminate in dangling bonds. These active sites are where bonding occurs, and increasing the number of bonding sites increases the bonding energy. The quantity and uniformity of bonding sites also affect the propagation rate and subsequent distortion.

[0058] After the wafers have been pre-processed to produce pre-processed wafers (clean, flat, smooth, and surface activated wafers), the direct bonding method proceeds to block 504. In block 504, three variable bonding parameters are configured according to the bonding recipe for bonding the wafers. The three bonding parameters configured in block 504 include chuck vacuum pressure, upper chuck vacuum area, and lower chuck vacuum area.

[0059] Chuck vacuum pressure is the strength of the vacuum used by the vacuum chuck to hold the pre-processed wafer. The upper chuck vacuum zone and lower chuck vacuum zone are variable vacuum chambers of the vacuum chuck that can be configured to be enabled or disabled. The configuration regarding which chuck vacuum zones are enabled corresponds to the amount of surface area of ​​the pre-processed wafer that will be under vacuum. For example, Figure 3BThe illustrated chuck vacuum zone configuration (or edge diagonal configuration) will correspond to approximately 50% of the surface area of ​​the edge of the pre-processed wafer being under vacuum.

[0060] After configuring the bonding parameters of the vacuum chuck, the direct bonding method continues in block 506. In block 506, the pre-processed wafers (pre-processed upper wafer and pre-processed lower wafer) are placed in wafer holders in a process chamber of a wafer processing tool. In an embodiment, the pre-processed upper wafer is placed in the upper wafer holder, which is a vacuum chuck, such as Figures 3A to 3B In an embodiment, the pre-processed lower wafer is placed in a lower wafer holder, which is a vacuum chuck such as Figures 3A to 3B The vacuum chuck is shown. The pre-processed upper wafer is positioned so that the side to be bonded to the pre-processed lower wafer faces downward toward the pre-processed lower wafer. In other words, the back side of the pre-processed upper wafer is the side that contacts the upper wafer holder (upper vacuum chuck). The pre-processed lower wafer is positioned so that the side to be bonded to the pre-processed upper wafer faces upward toward the pre-processed upper wafer. In other words, the back side of the pre-processed lower wafer is the side that contacts the lower wafer holder (lower vacuum chuck).

[0061] After the pre-processed wafers are placed into their corresponding wafer holders and the chuck vacuum pressure, upper chuck vacuum zone, and lower chuck vacuum zone are configured, the direct bonding method continues in block 508. In block 508, another bonding parameter is configured according to the bonding recipe used in the direct bonding method. The bonding parameter configured in block 508 is the bond gap distance, which is the separation distance between the pre-processed upper wafer and the pre-processed lower wafer. The bond gap distance is Figure 1A Once the bond gap distance d is configured, the pre-processed wafer is brought to the standoff distance specified by the bonding recipe.

[0062] Once the pre-processed wafers have been brought to a separation distance that is approximately the bond gap distance specified by the bonding recipe in block 508, the direct bonding method proceeds to block 510. In block 510, the two pre-processed wafers are aligned to sub-micron accuracy by alignment measurements performed by an optical device (e.g., an infrared scanner). This can be achieved by moving the chucks relative to each other until an alignment sensing algorithm has determined that the two pre-processed wafers are aligned within sub-micron accuracy. This alignment process is a key step for reducing linear overlay distortion. In the event that the two pre-processed wafers are not properly aligned prior to bonding, linear overlay distortion will be the most dominant factor in the resulting overlay distortion of the bonded wafers.

[0063] After aligning the pre-processed wafers in box 510, the direct bonding method can proceed to box 512. In box 512, another variable bonding parameter, namely, the striker pressure, is configured according to the bonding recipe used. The striker pressure is the pressure that the striker will apply to make direct (atomic) contact between the pre-processed upper wafer and the pre-processed lower wafer. Once the striker pressure is configured, the striker advances to make direct contact between the pre-processed upper wafer and the pre-processed lower wafer at a single point. In an embodiment, the striker strikes downward from behind the middle of the pre-processed upper wafer and pushes the center of the pre-processed upper wafer downward to make direct contact with the pre-processed lower wafer. In an embodiment, the striker strikes downward from behind the edge of the pre-processed upper wafer and pushes the edge of the pre-processed upper wafer downward to make direct contact with the edge of the pre-processed lower wafer. In other embodiments, the pre-processed lower wafer is struck upward into the pre-processed upper wafer by the striker.

[0064] Starting the bonding process can be referred to as initiation. Once the wafers are brought into direct contact, a bond front propagates across the contacting surfaces of the two wafers. In block 513, the vacuum region is reduced / released in time with the bond front as it propagates across the surfaces to bond the two wafers together. The bond front is a wave that squeezes any dielectric material that may be between the two wafers and enables bond formation across the entire contacting surface between the two wafers. Direct bonding between the pre-treated wafer surfaces is based on intermolecular interactions, including van der Waals forces, hydrogen bonds, and strong covalent bonds.

[0065] Once the wafers have undergone start-up and the bond front has fully propagated across the contact surface between the two wafers, the direct bonding method proceeds to block 514. In block 514, the bonded wafers are annealed to strengthen the bond formed between the upper and lower wafers. Annealing is achieved by exposing the bonded wafers to a high temperature bake (e.g., several hundred degrees Celsius). By exposing the bonded wafers to a high temperature anneal, thermal energy is introduced into the system, which causes the formation of more hydrogen bonds and increases the area of ​​the contact surface, so that the diffusion of trapped hydrogen molecules along the interface is enhanced and the interface voids can be reduced in size or completely eliminated. This can also cause condensation of hydrogen bonds, the creation of covalent bonds, and increase the contact surface between the wafers, and can enhance the diffusion of trapped species into the bulk material. All of this increases the bond strength between the now annealed wafers. In some embodiments where copper electrical contacts are present at the bonding interface, metal bonding can occur during the annealing step to create an electrical connection at the bonding interface.

[0066] After annealing in block 514, an annealed wafer has been produced that can now be inspected to determine any overlay distortion present. In embodiments, overlay distortion is measured using various techniques (such as infrared scanning) after the annealing process of the direct bonding method. In other embodiments, overlay distortion is measured before annealing the bonded wafer, which enables inspection of overlay distortion caused by the room temperature bonding step of the direct bonding method. It should be noted that the wafer bonding method of the present disclosure is applicable regardless of whether the overlay distortion is measured before or after annealing the bonded wafer.

[0067] Figure 4 The direct bonding method can be utilized by using Figure 5 The subsequent steps of the flowchart described in the wafer bonding method determine the optimized (minimized residue) direct bonding recipe (or target process recipe).

[0068] Return Reference Figure 4 After bonding the two wafers to form a bonded wafer in block 402, the method proceeds to block 404. In block 404, the overlay distortion of the bonded wafer is measured to determine the residual of the bonded wafer. Determining the residual of the bonded wafer includes inspecting the bonded wafer using a measurement device. As previously described, the residual is the overlay distortion generated by nonlinear distortion. Once the measurement device resolves the linear distortion, the remaining distortion is assumed to be the result of a nonlinear source and is quantified and labeled as residual. The residual is typically expressed as a certain number of standard deviations from alignment. For example, for a particular direct bonding recipe, a bonded wafer may be measured and found to have a residual of three standard deviations of 41.72 nm in X and three standard deviations of 55.16 nm in Y. In this example, the residual means that 99.73% of the bonded wafers produced using the corresponding direct bonding recipe have a deviation from no nonlinear distortion (or perfect alignment of the bonded wafers) within 41.72 nm in X and within 55.16 nm in Y.

[0069] Once the remnants of bonded wafers manufactured using the starting best known recipe are determined in block 404, the wafer bonding method proceeds to block 406. In block 406, a new set of wafers is bonded using a new direct bonding recipe. The new direct bonding recipe is identical to the best known recipe, except for a change in a single bonding parameter. For example, instead of using a 60 μm bond gap distance, the new recipe uses a 40 μm bond gap distance. The determined remnants and bonding parameters of the best known recipe are stored for use by the optimization algorithm.

[0070] The bonding parameters that vary in the wafer bonding method of the present disclosure include the bond gap distance, the striker pressure (which can vary over time), the chuck vacuum pressure, the upper chuck vacuum area, the lower chuck vacuum area, and the timing of releasing the chuck vacuum area to correspond to the movement of the bonding front during the bonding of the two wafers. The bond gap distance is the distance between the upper wafer and the lower wafer before the striker is used to strike the wafers together. The configurable value of the bond gap distance typically varies from 5μm to 1000μm. The striker pressure is the pressure used by the striker to press the upper wafer into the lower wafer (or vice versa) at a single point to initiate the bonding front that bonds the two wafers together. The configurable value of the striker pressure typically varies from 0kPa to 100kPa, and the striker pressure can also vary over time (different values ​​over time). In an exemplary embodiment, the value of the striker pressure can be reduced after initial contact. The chuck vacuum pressure is the vacuum pressure that holds the wafer to be bonded to the vacuum chuck. The chuck vacuum pressure is the difference from atmospheric pressure, and therefore the configurable values ​​for the chuck vacuum pressure typically vary from 0 kPa to -100 kPa. The upper chuck vacuum zone and lower chuck vacuum zone correspond to the configuration of whether the vacuum cavity behind the vacuum chuck is enabled or not. As noted above, there may be different rings of chuck vacuum zones (not just the outer ring) segmented from the center to the edge of the vacuum chuck, and these rings are configurable in some embodiments. The different configurations of vacuum chuck zones are referred to as full edge, edge diagonal only, or all or more, which combine different settings for the various rings of chuck vacuum zones (not just the outer ring). In the full edge configuration, the vacuum cavities at the edge of the vacuum chuck are all enabled, which corresponds to 100% edge coverage (e.g., 100% edge coverage). Figure 3A In an edge-only diagonal configuration, only 30% to 50% of the vacuum cavity at the edge of the vacuum chuck is active (e.g., Figure 3B (depicted in Figure 2). The full configuration corresponds to all vacuum chambers of the vacuum chuck being enabled, which corresponds to 100% coverage of the entire surface area of ​​the wafer loaded in the vacuum chuck (not just the edge). The timing of releasing the chuck vacuum during bonding is also configurable and corresponds to releasing the vacuum in time as the bond front propagates across the wafer surface.

[0071] After a new bonded wafer is fabricated using a new bonding recipe with a single changed bonding parameter in block 406, the wafer bonding method proceeds to block 408. In block 408, the residual of the new bonded wafer fabricated in block 406 is measured. The determination of the residual may include the same method as described in block 404 and will not be repeated here for the sake of brevity. The determined residual and bonding parameters of the new bonding recipe are stored for use by the optimization algorithm.

[0072] Once the remnant of newly bonded wafers has been determined, the wafer bonding method proceeds to block 410, which has two possible outcomes. In block 410, the wafer bonding method checks whether a set of bonded wafers has been manufactured using new recipes, each of which changes one of the bonding parameters. There are two possibilities in block 410, either yes or no.

[0073] If there is no (or no) bonded wafer produced using a recipe that changes a single bonding parameter for all bonding parameters, the wafer bonding method returns to block 406 to produce a new bonded wafer using a new direct bonding recipe that changes a single bonding parameter of the best known method that has not been changed by the existing recipe. After the new bonded wafer is produced, the fine-tuning wafer bonding method proceeds to block 408 where the residue of the new bonded wafer is determined and stored along with the bonding parameters for use by the optimization algorithm. The wafer bonding method then proceeds to block 410 where another check is performed.

[0074] For the case where a bonded wafer already exists for all bonding parameters (or is produced using a recipe that changes a single bonding parameter), the wafer bonding method proceeds to block 412. In block 412, using the remnants of the existing recipe and the bonding parameters corresponding to those stored remnants, an optimization algorithm is employed to determine what changes in the bonding parameters minimize the remnants. In other words, the bonding parameters can be configured to minimize the remnants. The configuration of the bonding parameters can include setting minimum and maximum values ​​for each bonding parameter. In one embodiment, the bond gap distance d is designed to be between 30 μm and 75 μm. In one embodiment, the bond gap distance d is designed to be between 50 μm and 75 μm. In one embodiment, the bond gap distance d is designed to be between 30 μm and 50 μm. In one embodiment, the bond gap distance d is designed to be less than 50 μm. In an embodiment, the upper vacuum condition is designed to include a vacuum surface area of ​​the back side of the upper wafer that will be less than 50% (e.g., in an embodiment, as low as 0.5%); and a vacuum level that will be between 0 kPa and -100 kPa. In one embodiment, the upper vacuum condition is designed to have a vacuum surface area of ​​the back side of the upper wafer that will be between 30% and 50%. In one embodiment, the lower vacuum condition is designed to be less than -25 kPa. In one embodiment, the striker pressure condition is designed to be between 10 kPa and 25 kPa. In one embodiment, the lower vacuum condition is designed to have a second vacuum surface area of ​​the back side of the lower wafer that will be greater than 80%; and a vacuum level of the lower wafer that will be between 0 kPa and -100 kPa. In various embodiments, the ratio of enabled areas to non-enabled areas can be used as a bonding parameter. Figure 3BIn the embodiment shown, the ratio is approximately 50%, but in other embodiments, the ratio can be designed to vary between 0% and 100%, or 20% to 80%, as examples.

[0075] The optimization algorithm can be a linear programming algorithm, a genetic algorithm, a random forest algorithm, a regression algorithm, or other techniques. Once the optimization algorithm has determined a set of bonding parameters that minimizes the residuals in the bonded wafer, the set of bonding parameters is returned as a target (fine-tuned or calibrated) direct bonding recipe.

[0076] After determining the fine-tuned direct bonding recipe in block 412, the wafer bonding method proceeds to block 414. In block 414, the target direct bonding recipe can now be used by the wafer processing tool to produce future bonded wafers with minimized residue. It should be noted that the wafer bonding method is applicable to any wafer processing tool that uses a direct bonding method to bond wafers with a striker. Therefore, the wafer bonding method can optimize the bonding recipe used in existing wafer processing tools to minimize residue in bonded wafers.

[0077] Figure 4 A version of the wafer bonding method can be described as a linear calibration fine-tuned wafer bonding method, where a fine-tuned wafer bonding recipe is determined once and then used for future wafer fabrication. In other words, the direct bonding recipe of the wafer handling tool is calibrated to minimize residuals. In an embodiment, the wafer bonding method can be an adaptive calibration method, where the direct bonding recipe of the wafer handling tool is calibrated and improved each time a bonded wafer is manufactured. The adaptive fine-tuned wafer bonding method is as follows: Figure 6 As displayed.

[0078] Figure 6 6 is a flow chart of an adaptive fine-tuning wafer bonding method for reducing overlay distortion. The adaptive fine-tuning wafer bonding method begins with a pair of pre-processed wafers (upper wafer 104 and lower wafer 106). The pre-processed wafers are placed inside a wafer processing tool 606, and the wafer processing tool will use a direct bonding method that initially uses the best known direct bonding recipe (such as Figure 5 The direct bonding method shown bonds the pre-processed upper wafer 602 and the pre-processed lower wafer 106 together.

[0079] Wafer processing tool 606 manufactures bonded wafer 608. Bonded wafer 608 is then scanned using scanner 610 to measure overlay distortion. Scanner 610 can be any type of scanner capable of measuring overlay distortion, such as an infrared scanner. This can be achieved by using scanner 610 to generate a distortion map that can be used by the optimization algorithm.

[0080] After the bonded wafer 608 has been scanned with the scanner 610, the residual is determined using the measured overlay distortion from the scanner 610. In block 612, the residual is determined and then used to improve the wafer bonding recipe (block 614) in order to minimize the residual.

[0081] An improved wafer bonding recipe is determined by using an optimization algorithm, which may be a linear programming algorithm, a genetic algorithm, a random forest algorithm, a regression algorithm, or other techniques. In block 614, the improved (or fine-tuned) wafer bonding recipe is determined and then transferred to the wafer processing tool 606 to be used as the direct bonding recipe for the next bonded wafer manufactured using the direct bonding method.

[0082] Now returning to the wafer processing tool 606, the wafer processing tool 606 uses the wafer bonding recipe to produce a new bonded wafer 608. The new bonded wafer 608 will then be scanned by the scanner 610, the remnants of the bonded wafer will be determined in 612, and the optimization algorithm will again improve the direct wafer bonding recipe in 614. Therefore, Figure 6 The wafer bonding method presented is an adaptive fine-tuning wafer bonding method that produces a fine-tuned wafer bonding recipe for each new bonded wafer manufactured or for a group of wafers.

[0083] exist Figure 7 A system diagram of a wafer processing tool 606 is shown in FIG. Figure 4 and Figure 6 Either linear calibration or adaptive fine tuning wafer bonding methods.

[0084] Figure 7 FIG1 is a system diagram of a wafer processing tool 606 that can implement the fine-tuned wafer bonding method of the present disclosure to bond pre-processed wafers. The wafer processing tool 606 includes a processing chamber 700 having a striker 100, an upper wafer holder 102, an upper wafer holder vacuum region 706, a lower wafer holder 108, and a lower wafer holder vacuum region 708. The processing chamber 700 is connected to a processor 712 and a memory 714.

[0085] The process chamber 700 is where the direct bonding method is used to bond a set of pre-processed wafers. The process chamber 700 provides a controlled environment, such as temperature, atmospheric pressure, gas inlet and outlet, etc. In an embodiment, the process chamber 700 includes all the elements required to perform bonding of pre-processed wafers, such as the striker 100, the upper wafer holder 102 and the upper wafer holder vacuum region 706, the lower wafer holder 108 and the lower wafer holder vacuum region 708.

[0086] The striker 100 is a tool used to establish physical contact between the two pre-processed wafers by applying a configurable amount of pressure (referred to as the striker pressure). In an embodiment, the striker is positioned within the upper wafer holder 102 and can be pushed downward through the upper wafer holder 102 to apply pressure on the pre-processed upper wafer, thereby pushing it downward into direct contact with the pre-processed lower wafer. In an embodiment, the striker 100 is positioned within the lower wafer holder 108 and can be pushed upward through the lower wafer holder 108 to apply pressure on the pre-processed lower wafer, thereby pushing it upward into direct contact with the pre-processed upper wafer.

[0087] The upper wafer holder 102 is a device that holds the wafer during the bonding process in the wafer processing tool 606. In an embodiment, the upper wafer holder 102 may include a chuck, such as Figures 3A to 3B The vacuum chuck holds the wafer by using a vacuum to pump air out of a cavity behind the vacuum chuck so that the air pressure will hold the wafer in place. The cavity of the vacuum chuck is called a vacuum zone, such as the upper wafer holder vacuum zone 706, and different zones can be configured to be enabled or disabled. In an embodiment, the upper wafer vacuum zone can be configured so that all zones are enabled, such as Figure 3A In another embodiment, the upper wafer vacuum zone 710 can be configured so that only half of the edge chuck vacuum zones are enabled, while the others are disabled, such as Figure 3B shown.

[0088] The lower wafer holder 108 is a device that holds the wafer during the bonding process in the wafer handling tool 606. In an embodiment, the lower wafer holder 108 can be a vacuum chuck. The vacuum chuck holds the wafer by using a vacuum to pump air out of a cavity behind the vacuum chuck so that the air pressure will hold the wafer in place. The cavity of the vacuum chuck is called a vacuum zone, such as the lower wafer holder vacuum zone 708, and different zones can be configured to be enabled or disabled. In an embodiment, the lower wafer vacuum zone can be configured so that all zones are enabled, such as Figure 3A In another embodiment, the lower wafer holder vacuum zone 708 may be configured so that only half of the chuck vacuum zone is enabled and the others are disabled, such as Figure 3B shown.

[0089] The processor 712 can be any device that can execute instructions stored in the memory 714 to bond wafers in the wafer processing tool 606. The processor 712 can execute the wafer bonding method of the present disclosure to fine-tune the wafer bonding recipe used by the wafer processing tool 606. The processor 712 issues the processing conditions (bonding parameters) of the wafer bonding recipe to the processing chamber 700. The processor 712 also implements an optimization algorithm to fine-tune the wafer bonding recipe by using the residuals and bonding parameters of the recipe set stored in the memory 714 to minimize residuals. The processor 712 can be a single processor with multiple cores or multiple processors comprising a distributed computing system.

[0090] The memory 714 can be any device that can store instructions to be executed by the processor 712 and store overlay distortion measurements (such as the determined residual and bonding parameters used in a particular direct bonding recipe) to be used in an optimization algorithm to determine a fine-tuned direct bonding recipe. The memory 714 can also store instructions for fine-tuning wafer bonding methods executed by the processor 712. The memory 714 can also be used to store distortion maps generated by the scanner. The memory 714 can include both non-volatile memory and volatile memory. Some of the instructions can be stored in different parts of the memory, which can be stored in different systems.

[0091] By implementing the wafer bonding method of the present disclosure in a wafer processing tool 606 (e.g. Figure 7 The presented method determines a fine-tuned wafer bonding recipe that minimizes residue. By minimizing residue in overlay distortion, semiconductor manufacturers can improve device yield without increasing manufacturing costs.

[0092] Figure 8 A flow chart illustrating an embodiment of the present disclosure is presented.

[0093] In an embodiment, a method includes determining an upper vacuum condition, a lower vacuum condition, a bond gap distance, and a striker pressure condition based on measuring residual distortion from a previously bonded wafer (block 802). The method further includes applying the upper vacuum condition to an upper wafer using an upper wafer holder, the upper vacuum condition being applied to a backside of the upper wafer, the upper wafer having a front side opposite the backside (block 804). The method further includes applying the lower vacuum condition to a lower wafer using a lower wafer holder, the lower vacuum condition being applied to a backside of the lower wafer, the lower wafer having a front side opposite the backside (block 806). The method further includes positioning the front side of the upper wafer over the front side of the lower wafer to create the bond gap distance between the upper and lower wafers (block 808). The method further includes striking the backside of the upper wafer with a striker using the striker pressure condition to bond the front side of the upper wafer to the front side of the lower wafer (block 810).

[0094] The above boxes can be used as Figure 4 and Figure 5 For example, in an embodiment, block 810 may be implemented as Figure 4 As another example, in an embodiment, block 808 may be implemented as Figure 5 508 in the .

[0095] Figure 9 A flow chart illustrating an embodiment of the present disclosure is presented.

[0096] In an embodiment, a method includes forming a first plurality of bonded wafers using a plurality of process recipes (block 902). The forming includes, for each of the first plurality of bonded wafers, striking a backside of the first wafer with a striker to bond the first wafer to a second wafer, each of the first plurality of bonded wafers being formed using a different process recipe from the plurality of process recipes (block 904). The method further includes measuring an overlay distortion of each of the first plurality of bonded wafers and determining a residual overlay distortion of each of the first plurality of bonded wafers based on the measurement (block 906). The method further includes selecting one of the first plurality of bonded wafers having a lower residual overlay distortion value (block 908). The method further includes determining a target process recipe associated with forming the selected one of the first plurality of bonded wafers (block 910). And the method further includes forming a second plurality of bonded wafers using the target process recipe (block 912).

[0097] The above boxes can be used as Figure 4 For example, in an embodiment, block 904 may be implemented as Figure 4 406 in the .

[0098] Figure 10 A flow chart illustrating an embodiment of the present disclosure is presented.

[0099] In an embodiment, a method includes forming a plurality of bonded wafers by performing bonding cycles (block 1002). Each cycle includes receiving a wafer set to be bonded, the wafer set including a first wafer and a second wafer (block 1004). Each cycle further includes measuring an overlay distortion of a previously bonded wafer and determining a residual overlay distortion of the previously bonded wafer based on the measurement (block 1006). Each cycle further includes determining a process recipe based on the previous residual overlay distortion (block 1008). Each cycle further includes positioning the first wafer to align with the second wafer and to be separated by a bond gap distance (block 1010). And each cycle further includes striking a back side of the first wafer with a striker to bond the first wafer and the second wafer together to form a bonded wafer (block 1012).

[0100] The above boxes can be used as Figure 6 For example, in an embodiment, block 1008 may be implemented as Figure 6 614 in the .

[0101] Exemplary embodiments of the present invention are described below. Other embodiments are apparent from the overall description and claims presented herein.

[0102] Example 1. A method includes determining an upper vacuum condition, a lower vacuum condition, a bond gap distance, and a striker pressure condition based on measuring residual distortion from a previously bonded wafer. The method includes applying the upper vacuum condition to an upper wafer using an upper wafer holder, the upper vacuum condition being applied to a rear side of the upper wafer, and the upper wafer having a front side opposite the rear side. The method includes applying the lower vacuum condition to a lower wafer using a lower wafer holder, the lower vacuum condition being applied to a rear side of the lower wafer, and the lower wafer having a front side opposite the rear side. The method includes positioning the front side of the upper wafer above the front side of the lower wafer to create the bond gap distance between the upper wafer and the lower wafer. And the method includes striking the rear side of the upper wafer with a striker using the striker pressure condition to bond the front side of the upper wafer to the front side of the lower wafer.

[0103] Example 2. The wafer bonding method of Example 1, wherein applying the upper vacuum condition comprises applying vacuum to a first vacuum surface area at a first vacuum level, the first vacuum surface area being between 0.1% and 5% of the total area of ​​the backside of the upper wafer, and the first vacuum level being between 0 kPa and -100 kPa. The wafer bonding method of Example 1, wherein applying the lower vacuum condition comprises applying vacuum to a second vacuum surface area at a second vacuum level, the second vacuum surface area being between 80% and 100% of the total area of ​​the backside of the lower wafer, and the second vacuum level being between 0 kPa and -100 kPa. The wafer bonding method of Example 1, wherein the striker pressure condition is between 10 kPa and 25 kPa. And the wafer bonding method of Example 1, wherein the bond gap distance is between 30 μm and 75 μm.

[0104] Example 3. The wafer bonding method of one of Examples 1 or 2, wherein the bonding gap distance is between 50 μm and 75 μm, the bonding gap distance is between 30 μm and 50 μm, or the bonding gap distance is less than 50 μm.

[0105] Example 4. The wafer bonding method of one of Examples 1 to 3, wherein the lower vacuum condition is less than -25 kPa.

[0106] Example 5. The wafer bonding method of one of Examples 1 to 4, wherein the upper vacuum condition comprises a first vacuum surface area of ​​less than 50% of the total area of ​​the back side of the upper wafer.

[0107] Example 6. The wafer bonding method of one of Examples 1 to 5, further comprising an annealing process for enhancing the bonding of the upper wafer and the lower wafer, the annealing process comprising exposing the bonded upper and lower wafers to a temperature exceeding 100°C.

[0108] Example 7. A method includes forming a first plurality of bonded wafers using a plurality of process recipes, the forming including, for each of the first plurality of bonded wafers, striking the back side of the first wafer with a striker to bond the first wafer to a second wafer, each of the first plurality of bonded wafers being formed using a different process recipe from the plurality of process recipes. The method includes measuring an overlay distortion of each of the first plurality of bonded wafers, and determining a residual overlay distortion of each of the first plurality of bonded wafers based on the measurement. The method includes selecting one of the first plurality of bonded wafers having a lower residual overlay distortion value. The method includes determining a target process recipe associated with forming the selected one of the first plurality of bonded wafers. And the method includes forming a second plurality of bonded wafers using the target process recipe.

[0109] Example 8. The method of example 7, wherein each of the plurality of process recipes differs from another of the plurality of process recipes in only one bonding parameter.

[0110] Example 9. The method of one of Examples 7 or 8, further comprising applying a first vacuum condition to the first wafer using an upper wafer holder, the first vacuum condition being applied to a back side of the first wafer, and the first wafer having a front side opposite the back side. The method further comprises applying a second vacuum condition to the second wafer using a second wafer holder, the second vacuum condition being applied to a back side of the second wafer, and the second wafer having a front side opposite the back side. The method further comprises positioning the front side of the second wafer above the front side of the second wafer to create a bonding gap distance between the first wafer and the second wafer, wherein the striking is performed under a striker pressure condition to bond the first wafer to the second wafer.

[0111] Example 10. The method of one of Examples 7 to 9, wherein each of the plurality of process recipes comprises the first vacuum condition, the second vacuum condition, the bond gap distance, and the striker pressure condition.

[0112] Example 11. The method of one of Examples 7 to 10, wherein applying the first vacuum condition includes having a plurality of chuck vacuum zones, each having a vacuum level, and activating a subset of the chuck vacuum zones surrounding the first wafer during the forming.

[0113] Example 12. The method of one of examples 7 to 11, wherein applying the first vacuum condition includes having a plurality of chuck vacuum zones, wherein vacuum levels of adjacent ones of the chuck vacuum zones are different during the forming.

[0114] Example 13. The method of one of Examples 7 to 12, further comprising receiving the target process recipe at a process controller, and enabling a plurality of chuck vacuum zones in the first wafer holder and the second wafer holder based on the target process recipe.

[0115] Example 14. The method of one of examples 7 to 13, further comprising receiving the target process recipe at a process controller, and changing the tappet pressure condition of the tappet based on the target process recipe.

[0116] Example 15. The fine-tuning wafer bonding method of one of Examples 7 to 14, further comprising annealing the bonded wafer, wherein measuring the overlay distortion is performed after the annealing.

[0117] Example 16. A method includes forming a plurality of bonded wafers by performing bonding cycles, each cycle comprising: receiving a wafer group to be bonded, the wafer group comprising a first wafer and a second wafer. Each cycle comprises: measuring an overlay distortion of a previously bonded wafer, and determining a residual overlay distortion of the previously bonded wafer based on the measurement. Each cycle comprises: determining a process recipe based on the previous residual overlay distortion. Each cycle comprises: positioning the first wafer to be aligned with the second wafer and separated by a bond gap distance. And each cycle comprises: striking the back side of the first wafer with a striker to bond the first wafer and the second wafer together to form a bonded wafer.

[0118] Example 17. The method of Example 16, wherein the striking comprises striking a central portion of the first wafer.

[0119] Example 18. The method of one of Examples 16 or 17, wherein the striking comprises striking a peripheral region of the first wafer.

[0120] Example 19. The method of one of Examples 16 to 18, wherein the measuring comprises scanning the bonded wafer with an infrared scanner and generating a distortion map.

[0121] Example 20. A method as described in one of Examples 16 to 19, wherein determining the process recipe includes: having a distortion model for the bonded wafer; generating a residual distortion map from the distortion map; and selecting a new process recipe to minimize the residual distortion based on the distortion model, the process recipe, and the residual distortion map, the process recipe including values ​​for the bond gap distance and the pressure with which the striker strikes the first wafer.

[0122] Example 21. The method of any one of Examples 16 to 20, further comprising applying a first vacuum condition to the first wafer using a first wafer holder, the first vacuum condition being applied to a back side of the first wafer, the first wafer having a front side opposite the back side, and further comprising applying a second vacuum condition to the second wafer using a second wafer holder, the second vacuum condition being applied to a back side of the second wafer, the second wafer having a front side opposite the back side, wherein the process recipe includes the first vacuum condition and the second vacuum condition.

[0123] Example 22. The method of one of Examples 16 to 21, wherein each cycle further comprises annealing the bonded wafer.

[0124] Example 23. The method of one of examples 16 to 22, wherein the annealing is performed at a temperature exceeding 150°C.

[0125] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the present invention, will be apparent to those skilled in the art by reference to the description. Accordingly, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method comprising: determining an upper vacuum condition, a lower vacuum condition, a bonding gap distance, and a striker pressure condition based on measuring residual distortion from a previously bonded wafer; applying the upper vacuum condition to an upper wafer using an upper wafer holder, the upper vacuum condition being applied to a back side of the upper wafer, and the upper wafer having a front side opposite the back side; applying the lower vacuum condition to a lower wafer using a lower wafer holder, the lower vacuum condition being applied to a back side of the lower wafer, and the lower wafer having a front side opposite the back side; positioning the front side of the upper wafer over the front side of the lower wafer to create the bonding gap distance between the upper wafer and the lower wafer; as well as The striker pressure condition is used to strike the back side of the upper wafer with a striker to bond the front side of the upper wafer and the front side of the lower wafer together.

2. The wafer bonding method according to claim 1, in, Applying the upper vacuum condition includes applying vacuum to a first vacuum surface area at a first vacuum level, the first vacuum surface area being between 0.1% and 5% of a total area of ​​the back side of the upper wafer, and the first vacuum level being between 0 kPa and -100 kPa; wherein applying the lower vacuum condition comprises applying vacuum to a second vacuum surface area at a second vacuum level, the second vacuum surface area being between 80% and 100% of a total area of ​​the back side of the lower wafer, the second vacuum level being between 0 kPa and -100 kPa; wherein the firing pin pressure condition is between 10 kPa and 25 kPa; and The bonding gap distance is between 30 μm and 75 μm.

3. The wafer bonding method according to claim 1, wherein: The lower vacuum condition is less than -25 kPa. 4 . The wafer bonding method of claim 1 , further comprising an annealing process for enhancing bonding of the upper wafer and the lower wafer, the annealing process comprising exposing the bonded upper and lower wafers to a temperature exceeding 100° C.

5. A method comprising: Forming a first plurality of bonded wafers using a plurality of process recipes, the forming comprising: for each of the first plurality of bonded wafers, striking a back side of the first wafer with a striker to bond the first wafer to a second wafer, each of the first plurality of bonded wafers being formed using a different process recipe from the plurality of process recipes; measuring an overlay distortion of each of the first plurality of bonded wafers and determining a residual overlay distortion of each of the first plurality of bonded wafers based on the measurement; selecting one of the first plurality of bonded wafers having a lower residual overlay distortion value; determining a target process recipe associated with forming a selected one of the first plurality of bonded wafers; and A second plurality of bonded wafers is formed using the target process recipe.

6. The method of claim 5, wherein: Each of the plurality of process recipes differs from another of the plurality of process recipes in only one bonding parameter.

7. The method of claim 5, further comprising: applying a first vacuum condition to the first wafer using an upper wafer holder, the first vacuum condition being applied to a back side of the first wafer, and the first wafer having a front side opposite the back side; applying a second vacuum condition to a second wafer using a second wafer holder, the second vacuum condition being applied to a back side of the second wafer, and the second wafer having a front side opposite the back side; as well as The front side of the second wafer is positioned over the front side of the second wafer to create a bonding gap distance between the first wafer and the second wafer, wherein the striking is performed under a striker pressure condition to bond the first wafer to the second wafer.

8. The method of claim 7, wherein: Each of the plurality of process recipes includes the first vacuum condition, the second vacuum condition, the bonding gap distance, and the striker pressure condition.

9. The method of claim 8, wherein: Applying the first vacuum condition includes having a plurality of chuck vacuum zones, each of the plurality of chuck vacuum zones having a vacuum level; and A subset of the chuck vacuum region surrounding the first wafer is enabled during the forming.

10. The method of claim 8, wherein: Applying the first vacuum condition includes having a plurality of chuck vacuum zones, wherein vacuum levels of adjacent ones of the chuck vacuum zones are different during the forming.

11. The method of claim 7, further comprising: receiving the target process recipe at a process controller; as well as A plurality of chuck vacuum zones in the first wafer holder and the second wafer holder are enabled based on the target process recipe.

12. The method of claim 7, further comprising: receiving the target process recipe at a process controller; as well as A striker pressure condition of the striker is changed based on the target process recipe.

13. The fine-tuning wafer bonding method according to claim 7, further comprising annealing the bonded wafer, wherein: The measuring of the overlay distortion is performed after the annealing.

14. A method comprising: Multiple bonded wafers are formed by performing bonding cycles, each cycle comprising: receiving a wafer set to be bonded, the wafer set comprising a first wafer and a second wafer, measuring an overlay distortion of a previously bonded wafer and determining a residual overlay distortion of the previously bonded wafer based on the measurement, Determine the process recipe based on the previous residual coverage distortion, positioning the first wafer in alignment with and separated by a bonding gap distance from the second wafer, and The back side of the first wafer is struck with a striker to bond the first wafer and the second wafer together to form a bonded wafer.

15. The method of claim 14, wherein: The striking includes striking a central portion of the first wafer.

16. The method of claim 14, wherein: The striking includes striking a peripheral area of ​​the first wafer.

17. The method of claim 14, wherein: The measurement involves scanning the bonded wafer with an infrared scanner and generating a distortion map.

18. The method of claim 14, wherein: Determine the process recipe includes: having a distortion model for the bonded wafer; generating a residual distortion map from the distortion map; and A new process recipe is selected based on the distortion model, the process recipe, and the residual distortion map to minimize the residual distortion, the process recipe including values ​​of the bond gap distance and a pressure with which the striker strikes the first wafer.

19. The method of claim 14, further comprising: applying a first vacuum condition to the first wafer using a first wafer holder, the first vacuum condition being applied to a back side of the first wafer, and the first wafer having a front side opposite the back side; as well as A second vacuum condition is applied to the second wafer using a second wafer holder, the second vacuum condition being applied to a back side of the second wafer, and the second wafer having a front side opposite the back side, wherein the process recipe includes the first vacuum condition and the second vacuum condition.

20. The method of claim 14, wherein: Each cycle further includes annealing the bonded wafer.

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