Reducing DCO frequency overlap induced limit cycles in hybrid and digital PLL

Abstract

A method includes observing that a digitally controlled oscillator (DCO) frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region.

Description

[0001] Priority declaration

[0002] This application claims the benefit of the priority date of U.S. Provisional Patent Application Serial No. 63 / 371,105, filed on August 11, 2022, entitled “MITIGATE DCO OVERLAP INDUCED LIMIT CYCLE IN HYBRID AND DIGITAL PLL S,” the contents and disclosure of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more examples generally relate to a clock tracking circuit for tracking an output clock to a reference clock. One or more examples relate to reducing the undesirable effects of frequency redundancy in a digitally controlled oscillator of a clock tracking circuit. Background Art

[0004] Clock tracking circuits, such as phase-locked loops and delay-locked loops, are circuits that are used to track clocks and other oscillating signals. The output signal of the clock tracking circuit is locked to the phase and frequency of a reference signal. Clock tracking circuits are used in a variety of operating contexts, including when two signals with a known relationship are used to transmit information. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0006] Figure 1A is a graph depicting a line representing changes in a DCO control code over time and another line representing a phase error signal generated by a PLL exhibiting interference.

[0007] Figure 1B is a line depicting changes in DCO control codes over time according to one or more examples and representing changes in DCO control codes by exhibiting less or no interference (with Figure 1A FIG. 2 is a graph of another line of a phase error signal generated by a PLL (compared to FIG. 2 ).

[0008] Figure 2 is a block diagram depicting an integral path portion for bypassing a DCO frequency overlap region in a PLL according to one or more examples.

[0009] Figure 3 is a block diagram depicting an apparatus for generating an adjustment signal according to one or more examples.

[0010] Figure 4is a block diagram illustrating an apparatus for bypassing DCO control codes corresponding to DCO frequency overlap regions according to one or more examples.

[0011] Figure 5 is a block diagram illustrating an apparatus for bypassing DCO control codes corresponding to DCO frequency overlap regions according to one or more examples.

[0012] Figure 6 is a flow chart depicting a process for bypassing DCO frequency overlap regions in a PLL according to one or more examples.

[0013] Figure 7 is a flow chart depicting a process for observing that a DCO frequency is at a boundary of a DCO frequency overlap region according to one or more examples.

[0014] Figure 8 is a flow chart depicting a process for bypassing at least a portion of a DCO frequency overlap region according to one or more examples.

[0015] Fig. 9 is a flow chart depicting a process for bypassing at least a portion of a DCO frequency overlap region according to one or more examples.

[0016] Fig.10 is a flow diagram depicting a method for bypassing at least a portion of a DCO frequency overlap region according to one or more examples.

[0017] Fig.11 is a block diagram depicting an apparatus for tracking a clock (and may also be referred to herein as a "clock tracking circuit") according to one or more examples.

[0018] Fig.12 are block diagrams of circuits that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. DETAILED DESCRIPTION

[0019] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of illustration specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0020] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structure or component must be identical in size, composition, configuration, or any other attribute.

[0021] The following description may include examples to help enable a person of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary", "by way of example", and "for example" means that the relevant description is illustrative, and while the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the scope of the examples of the present disclosure to the specified components, steps, features, functions, etc.

[0022] It should be readily understood that the components of the examples as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. Although various aspects of the examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0023] In addition, the specific implementations shown and described are only examples and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific implementations shown and described are only exemplary and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the partitioning of logic between block definitions and individual blocks is an example of a specific implementation. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0024] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For clarity of presentation and description, some of the figures may illustrate a signal as a single signal. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0025] The various illustrative logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer is configured to execute computing instructions (e.g., software code) associated with the examples disclosed herein.

[0026] Examples may be described in terms of processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts may describe operable actions as continuous processes, many of these actions may be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of the actions may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, but is not limited thereto. In addition, the methods disclosed herein may be implemented by hardware, software, or both. If implemented in software, a function may be stored or sent to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, which include any media that facilitates transferring a computer program from one location to another.

[0027] Any reference to elements herein using names such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitations are explicitly stated. Rather, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0028] As used herein, the term "substantially" in reference to a given parameter, attribute, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied by at least 90%, by at least 95%, or even by at least 99%.

[0029] As used herein, any relative terms (such as "above", "below", "on", "below", "upper", "lower", but not limited to) are used for clarity and convenience in understanding the present disclosure and the drawings, and do not imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0030] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, then the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, then there are no intervening elements or layers. The term "connected" may be used interchangeably with the term "coupled" in this specification and have the same meaning, unless otherwise expressly indicated or the context would indicate otherwise to one of ordinary skill in the art.

[0031] A clock signal, or just "clock," is a signal that oscillates between a high state and a low state in a reliably predictable manner. Circuits can operate in response to the edges of the clock to coordinate their actions.

[0032] A phase-locked loop (PLL) generates an output signal that exhibits a phase or frequency that has a predetermined relationship with the phase or frequency of a reference signal. Such a predetermined relationship between the phase or frequency of the output signal and the reference signal is caused and maintained and is referred to herein as "tracking". The predetermined relationship may be that the frequency of the output signal is the same as or a multiple of the frequency of the reference signal. As a non-limiting example, the frequency of the output signal may be 1 / 200 times, 1 / 10 times, 10 times, or 200 times the frequency of the reference signal. When the PLL reliably tracks the output signal to the reference signal, it is referred to as "locking" or being in a "locked state". When locked, if the phase or frequency of the reference signal changes, the PLL correspondingly adjusts the phase or frequency of the output signal to maintain the predetermined relationship.

[0033] A typical PLL includes an electronic oscillator that is controlled by the PLL to generate an output signal that tracks a reference signal. The electronic oscillator may include one or more control element groups (e.g., capacitors, inductors, delay circuits, but not limited thereto), which are voltage-controlled, current-controlled, digitally controlled, or a combination or sub-combination thereof. Depending on the circumstances, enabling and disabling the corresponding control element changes the capacitance, inductance, or delay of the electronic oscillator in a predictable manner, which changes the output frequency of the electronic oscillator in a predictable manner. As a non-limiting example, increasing the capacitance, inductance, or delay of the electronic oscillator reduces its output frequency. Reducing the capacitance, inductance, or delay of the electronic oscillator increases its output frequency.

[0034] The electronic oscillator may include multiple inputs for controlling (enabling / disabling) various control element groups and thus governing the phase and frequency of the output signal. Non-limiting examples of electronic oscillators include: a voltage controlled oscillator (VCO) that generates an output signal exhibiting a phase or frequency governed by the voltage of the control signal; a current controlled oscillator (CCO) that generates an output signal exhibiting a phase or frequency governed by the current of the control signal; a digitally controlled oscillator (DCO) that generates an output signal exhibiting a phase or frequency governed at least in part by the value of a control code; and combinations / sub-combinations thereof.

[0035] The PLL may include one or more control paths for controlling the electronic oscillator via one or more control inputs of the electronic oscillator. Non-limiting examples of control paths include: a proportional control path for instantaneous correction of the phase difference between the feedback signal and the reference signal; and an integral control path for forcing the average frequency of the electronic oscillator toward a target frequency. Such control paths may include analog circuits, digital circuits, or a combination thereof. A PLL that includes only an analog control path is referred to as an "analog PLL". A PLL that includes only a digital control path is referred to as a "digital PLL". A PLL that includes a combination of an analog control path and a digital control path is sometimes referred to as a "hybrid PLL" or a "mixed mode PLL".

[0036] When utilizing a DCO, digital and hybrid PLLs utilize digital control codes to govern the output signal of the PLL. The control code sets the number of control elements in the DCO via a digital control input (or just "digital input") of the DCO, so setting the value of the control code sets the number of control elements at the DCO, and thus sets the frequency of the DCO ("DCO frequency"). A typical convention is to configure the PLL so that increasing the value of the control code increases the DCO frequency (i.e., increasing the value of the control code decreases the number of control elements set, which increases the DCO frequency), and decreasing the value of the control code decreases the DCO frequency (i.e., by increasing the number of control elements set, which decreases the DCO frequency). Other conventions may be utilized without exceeding the scope of the present disclosure.

[0037] In a digital PLL, certain values ​​of the control code are associated with specific frequency sub-ranges of the DCO. Generally speaking, the DCO should provide continuous frequencies in a predefined frequency range. Discontinuities (also referred to as "gaps") in the frequency range of the DCO cause jitter, which is generally undesirable. A discontinuity is a specific frequency or sub-range within the predefined frequency range of the DCO that is skipped when the value of the control code increases or decreases monotonically. Gaps can occur in the frequency range, for example, due to process voltage temperature (PVT) variations and mismatches that occur more generally during the manufacture of the DCO or PLL.

[0038] Frequency redundancy is sometimes implemented at the DCO to ensure continuity of the frequency range. The DCO is intentionally configured to exhibit overlapping frequency sub-ranges for a range of values ​​of the control code (each such overlap is referred to herein as a "DCO frequency overlap region") to ensure continuous frequency coverage (i.e., no frequency gaps) even when exposed to PVT variations. Frequency overlap requires overlapping portions of the frequency sub-ranges for the DCO codes.

[0039] During operation, when the PLL increases or decreases the control code from one set of values ​​to another set of values ​​(representing a first frequency sub-range to a second frequency sub-range), the DCO frequency backtracks and traces back the portion of the DCO frequency range for the set of values ​​corresponding to the DCO frequency overlap region. Crossing the DCO frequency overlap region can disturb the phase error of the PLL, and this disturbance can manifest as a limit cycle in the control code. In the context of the PLL, a limit cycle is a repetitive pattern or oscillation in the behavior of the PLL control code or state variables, which occurs when the PLL cannot reach a stable state and instead gets used to a periodic or repetitive behavior. Limit cycles degrade jitter performance. Therefore, frequency redundancy can bring a compromise of degraded jitter performance.

[0040] When crossing a DCO frequency overlap region, the DCO frequency traces back and then resumes increasing or decreasing with monotonically increasing or decreasing control codes. The DCO frequency traces back a portion of a previous DCO frequency sub-range, and the portion represents a DCO frequency overlap region between the previous DCO frequency sub-range and the current DCO frequency sub-range. Reducing the number of DCO frequency overlap regions experienced by the PLL reduces the limit cycle caused by DCO frequency tracing back. The number of DCO frequency overlap regions is reduced by increasing or decreasing the value of the control code by an adjustment amount, thereby skipping some or all values ​​of the value of the control code associated with the DCO frequency overlap region, while still avoiding gaps in the DCO frequency range.

[0041] One or more examples generally relate to reducing limit cycles due to DCO frequency overlap regions in clock tracking circuits and methods and apparatus including the reduction.

[0042] One or more examples generally relate to a method that includes: detecting that a boundary of DCO overlap has been reached; determining a direction of an integral control path; determining an amount of DCO overlap at the detected boundary; and at least temporarily adjusting an integral control signal based at least in part on the determined amount of DCO overlap at the detected boundary.

[0043] Figure 1A is a graph depicting a line representing changes in a DCO control code over time and another line representing a phase error signal generated by a PLL having an output signal at least partially governed by the DCO control code.The phase error signal generated by the PLL exhibits interference as discussed below.

[0044] Line 102 represents the relationship between the value of the DCO control code and time (or the DCO control code and the duration of time). The y-axis is the value of the DCO control code increasing from the bottom of the axis toward the top of the axis. The x-axis is time, increasing from left to right.

[0045] Line 104 represents a phase error signal generated by a PLL having an output signal governed at least in part by the DCO control code represented by line 102. The y-axis is the amount of delay (where one of the positive or negative signs represents an advance delay and the other of the positive or negative signs represents a lag delay). The x-axis is time, increasing from left to right.

[0046] At about time T0, line 102 exhibits a change from a first value to a second value, and then after time T0, line 102 gradually increases from the second value to a third value and then increases over a time duration from time T0 to T1. The third value is between the first value and the second value. The range of DCO control codes between the second value and the third value corresponds to a DCO frequency overlap region of the DCOs controlled by these DCO control codes.

[0047] Prior to time T0, line 104 is generally horizontal, indicating a generally stable phase error. At approximately time T0, line 104 exhibits a disturbance 106: a dislocation to a higher phase error (i.e., a larger delay) and then line 104 decreases over the time duration from time T0 to T1 to the same phase error prior to time T0. Disturbances 106 correspond to a DCO frequency overlap region corresponding to a range of values ​​between the second value and the third value.

[0048] Figure 1B is a graph depicting a line representing changes in a DCO control code over time and another line representing a phase error signal generated by a PLL having an output signal at least partially governed by the DCO control code according to one or more examples. Figure 1B The depicted phase error signal exhibits (with Figure 1A The depicted phase error signal has little or no interference.

[0049] Line 108 represents the relationship between DCO control code value and time (or DCO control code value and time duration). The y-axis is the value of the DCO control code increasing from the bottom of the axis toward the top of the axis. The x-axis is time, increasing from left to right.

[0050] Line 110 represents a phase error signal generated by a PLL having an output signal governed at least in part by the DCO control code represented by line 108. The y-axis is the amount of delay (where one of the positive or negative signs represents an advance delay and the other of the positive or negative signs represents a lag delay). The x-axis is time, increasing from left to right.

[0051] At approximately time T0, line 108 exhibits a change from a first value to an adjusted value (also referred to herein as a "changed value"), and then after time T0, line 108 increases from the adjusted value. Also depicted (for ease of reference) is a second value corresponding to Figure 1A The adjusted value is between the first value and the second value. It is noteworthy that row 108 never exhibits the second value. At time T o At , line 108 changes from the first value to the adjusted value and never equals the range of values ​​corresponding to the DCO frequency overlap region, i.e., second value ≤ DCO control code < adjusted value. Figure 1A Compared to line 104 of FIG. 1 , line 110 (phase error signal) does not exhibit interference (eg, interference 106) due to DCO frequency overlap.

[0052] Figure 2is a block diagram depicting an integral path portion 200 for bypassing a DCO frequency overlap region in a PLL according to one or more examples.

[0053] The integration path portion 200 includes a digital integrator 202 and a logic circuit 212. The digital integrator 202 includes a register 206.

[0054] The integral path portion 200 is part of the integral control path of the PLL. The integral path portion 200 processes the digital phase error signal to generate a frequency error signal. More specifically, the integral path portion 200 integrates the frequency information and filters out the fast phase error information. Therefore, compared with the change of the error signal used for the proportional control of the PLL, the frequency error signal generated by the integral path portion 200 changes slowly, and the PLL responds faster to any phase error, but little or no frequency information is detected from the error signal. The frequency error signal generated by the integral path portion 200 can be used as a DCO control code (here, DCO control code 210) that can be applied to the integral input of the DCO of the PLL. Therefore, the frequency error signal / DCO control code generated by the integral path portion 200 represents any gradual drift of the PLL's attempt to correct the frequency.

[0055] The digital integrator 202 receives the digital phase error signal 208 and generates a DCO control code 210. As a non-limiting example, the digital integrator 202 may be a digital signal processor (DSP) or other logic circuit. The digital phase error signal 208 is a binary representation of a phase error signal representing a phase difference between two clock signals. The DCO control code 210 represents the frequency error information (i.e., frequency error signal) of the digital phase error signal 208.

[0056] The digital integrator 202 accumulates a digital input signal (e.g., a discrete time signal or discrete samples of a continuous time signal, but not limited thereto) over time and generates an output signal corresponding to an integrated value 216, which is stored at the register 206. When the digital input signal is a digital phase error signal 208, the integrated value 216 represents the frequency error information in the digital phase error signal 208. As discussed above, in a digital PLL, the bits of the integrated value 216 (i.e., register bits) can be used as control codes provided to the integration input of the DCO. Therefore, the bits of the integrated value 216 can be utilized to control (i.e., set) the DCO frequency.

[0057] Since the DCO control code 210 can be utilized to set the DCO frequency and the DCO control code 210 is based on the bits of the integral value 216, the integral value 216 can be set to bypass at least a portion of the DCO frequency overlap region. As a non-limiting example, in the absence of external influences, the integral value 216 monotonically increases or decreases depending on whether the PLL is increasing or decreasing the DCO frequency. When the DCO control code 210 matches the DCO control code value associated with the boundary of the DCO frequency overlap region, the integral value 216 can be set (e.g., increased, decreased, or directly set to a new value, as the case may be) by a certain amount ("adjustment amount") to bypass (or in another way, "skip") at least some (i.e., some or all) of those DCO control code values ​​associated with the DCO frequency overlap region. The DCO control code value associated with the DCO frequency overlap region is the value or range of values ​​of the DCO control code 210 corresponding to the DCO frequency overlap region. As a non-limiting example, bypassing at least some of those DCO control code values ​​may reduce limit cycles and jitter associated therewith.

[0058] Logic circuit 212 receives DCO control code 210 and generates adjustment signal 214 to set integration value 216, which is stored at register 206 of digital integrator 202. As a non-limiting example, logic circuit 212 can be a digital logic circuit. Adjustment signal 214 is a signal used by integration path portion 200 (more specifically, logic circuit 212) to set integration value 216. As a non-limiting example, adjustment signal 214 can represent an amount to increase or decrease integration value 216 or a new value to which integration value 216 is to be set equal to. The amount of increase or decrease in integration value 216 caused by adjustment signal 214 is proportional to the value / magnitude of adjustment signal 214.

[0059] In one or more examples, the logic circuit 212 generates the adjustment signal 214 at least in part in response to observing that the value of the DCO control code 210 is associated with a boundary of the DCO frequency overlap region. As a non-limiting example, the value of the DCO control code 210 may correspond to a frequency at or near a boundary of the DCO frequency overlap region. In one or more examples, the value of the DCO control code associated with the boundary of the DCO frequency overlap region may be predetermined and stored at the logic circuit 212. After observing that the DCO control code 210 corresponds to the boundary, the logic circuit 212 determines a new value of the integrated value 216 or an amount by which the integrated value 216 stored at the register 206 should be increased or decreased to bypass the DCO frequency overlap region (“adjustment amount”), and generates the adjustment signal 214 proportional to the determined adjustment amount. In one or more examples, the logic circuit 212 may determine the new value by determining the adjustment amount and adding the adjustment amount to the current value of the DCO control code 210 or subtracting the adjustment amount from the current value of the DCO control code. In one or more examples, the predetermined adjustment amount or new value can be stored at and utilized by logic circuit 212 .

[0060] Any suitable technique may be utilized to set the integrated value 216 stored at the register 206 via the adjustment signal 214. In one or more examples, the gain of the digital integrator 202 may be a variable gain expressed according to a gain function. Such a gain function may be based at least in part on one or more gain definition parameters of the digital integrator 202. In one or more examples, the adjustment signal 214 may change the gain of the digital integrator 202, which affects the integrated value 216 stored at the register 206. By changing the gain, the integration process may be controlled, thereby allowing the integrated value 216 to be adjusted.

[0061] The gain of the digital integrator 202 may be set via one or more gain definition parameters of the digital integrator 202. The specific gain definition parameters will depend on the specific implementation of the digital integrator 202. Non-limiting examples include: an accumulation register that accumulates the phase error or phase error samples over time; or a numerical integration algorithm for discrete time calculations that is used to calculate the integrated value and update the integrated value 216 accordingly.

[0062] In the case of an accumulation register, non-limiting examples of gain definition parameters include: accumulation step size, accumulation time, or a gain factor applied to the accumulator output. The accumulation step size is used in the accumulation register to determine how many steps or increments each input value contributes to the accumulation value stored at the accumulation register (the accumulation value corresponds to the integral value 216). Adjusting the step size controls the gain of the digital integrator 202. Increasing the step size increases the gain of the digital integrator 202 (resulting in a higher gain), while decreasing the step size decreases the gain of the digital integrator 202 (resulting in a lower gain). The accumulation time is the rate ("update rate") at which the accumulation value stored at the register 206 is updated, which affects the gain of the digital integrator 202. As a non-limiting example, the accumulation time can be controlled via the rate of the clock signal applied to the digital integrator 202. Changing the time interval between updates controls the effective gain of the digital integrator 202. Increasing the update rate increases the effective gain of the digital integrator 202 (resulting in a higher gain), while decreasing the update rate decreases the effective gain of the digital integrator 202 (resulting in a lower gain). The scaling factor is a function or value applied to the value provided to or received from the accumulation register. Such scaling factors can be fixed values ​​or can be dynamically adjusted. The scaling factor is multiplied or divided by the accumulation value, thereby effectively controlling the gain of the digital integrator 202.

[0063] The register 206 receives and stores the integrated value 216, and the DCO control code 210 is based on at least some of the bits of the register 206 that are utilized to represent the accumulated integrated value 216. For a given number N of register bits of the register 206, 2^ N The steps are applied to the input of the DCO for integral control of the DCO frequency. The corresponding step size corresponds to an incremental change in the DCO frequency.

[0064] Figure 3 is a block diagram illustrating an apparatus 300 for generating an adjustment signal according to one or more examples. The apparatus 300 is Figure 2 Non-limiting example of logic circuit 212.

[0065] Apparatus 300 includes a boundary detector 302 and a lookup table 306 (or "LUT 306"). Lookup table 306 includes boundary codes 308 and adjustment values ​​310. Boundary detector 302 includes boundary codes 304.

[0066] The boundary detector 302 detects the presence of one or more signals of interest (herein, boundary codes 304) within an input signal (herein, DCO control code 210) and generates a detector output (herein, boundary detection signal 312) to indicate the presence or absence of the one or more signals of interest. The boundary detector 302 receives the DCO control code 210 and generates the boundary detection signal 312 to indicate the detection of the presence of the boundary code 304 in the DCO control code 210. As non-limiting examples, the boundary detector 302 can be a logic circuit that performs signal detection or pattern matching. The boundary code 304 represents a value of the DCO control code that is predetermined to be associated with a frequency that defines an upper boundary and a lower boundary of a frequency range in a DCO frequency overlap region.

[0067] Boundary detector 302 compares the value of DCO control code 210 with boundary code 304 and generates boundary detection signal 312 at least in part in response to the comparison. Boundary detection signal 312 indicates whether a boundary of the DCO frequency overlap region has been detected. In one or more examples, boundary detector 302 generates boundary detection signal 312 having a first value in response to determining that DCO control code 304 matches one of boundary codes 210, and generates boundary detection signal 312 having a different second value in response to determining that none of boundary codes 304 matches DCO control code 210.

[0068] In one or more examples, the particular boundary code 304 detected by the boundary detector 302 is based at least in part on the state of the DCO frequency (increasing or decreasing). The boundary detector 302 can detect the presence of a first subset of boundary codes 304 when the DCO frequency is increasing, and detect the presence of a different second subset of boundary codes 304 when the DCO frequency is decreasing. In one or more examples, the boundary detector 302 can detect the state of the DCO frequency (increasing or decreasing) using any suitable technique.

[0069] In one or more examples, boundary detector 302 can infer an increase in DCO frequency in response to an increase in DCO control code 210, and a decrease in DCO frequency in response to a decrease in DCO control code 210. In one or more examples, boundary detector 302 can use any suitable technique to determine whether DCO control code 210 is increasing or decreasing.

[0070] As a non-limiting example, the boundary detector 302 may monitor an average change in the digital phase error signal 208 and determine the direction information based at least in part on the average change. Additionally or alternatively, the boundary detector 302 may monitor an average change in the value of the DCO control code and determine the direction information based at least in part on the average change.

[0071] As another non-limiting example, the boundary detector 302 may determine whether to increase the DCO frequency or decrease the DCO frequency based on the direction information in the digital phase error signal 208 (the receipt of the digital phase error signal 208 is not in progress). Figure 3 2 and should be understood to be optional). If the digital phase error signal 208 is generated by a switch-mode phase detector, the increment and decrement signals generated by the switch-mode phase detector may be decoded to determine direction information about the digital phase error signal 208, and thus the DCO frequency. As a non-limiting example, if the digital integrator 202 increments more on average (e.g., increments the integrated value 216 and thus increments the DCO control code 210), the boundary detector 302 should detect when the DCO control code 210 approaches a value corresponding to an upper boundary of the DCO frequency overlap region. If the digital integrator 202 decrements more on average (e.g., decrements the integrated value 216 and thus decrements the DCO control code 210), the boundary detector 302 should detect when the DCO control code 210 approaches a value corresponding to a lower boundary of the DCO frequency overlap region.

[0072] In one or more examples, boundary detector 302 can maintain historical DCO control codes (eg, store them in memory, but not limited thereto) and determine whether the DCO control code is increasing or decreasing based on a difference between a previous DCO control code and a current DCO control code.

[0073] The lookup table 306 associates an input value (here, the value of the DCO control code 210) with an output value (here, the adjustment value 310). In one or more examples, the lookup table 306 maps the input value by utilizing the input value (or a value derived from the input value) as an address associated with a location in a memory or memory array where the lookup table 306 (memory not depicted) stores the output value. The lookup table 306 retrieves the output value from the memory using the input value as the address.

[0074] Lookup table 306 receives DCO control code 210 at an input and boundary detection signal 312 at an enable input, and provides adjustment signal 214 in response, at least in part, to the signal. A direct mapping between boundary code 308 and adjustment value 310 is provided at lookup table 306. When boundary detection signal 312 is asserted, lookup table 306 is enabled and attempts to retrieve an adjustment value associated with DCO control code 210.

[0075] The adjustment value 310 represents an amount to increase or decrease the integrated value 216 or a new value to which the integrated value 216 will be set equal to in order to bypass the DCO control code value predetermined to correspond to the DCO frequency overlap region. The corresponding adjustment value 310 may be predetermined. As a non-limiting example, the adjustment value 310 may be predetermined and stored during calibration of the DCO or PLL.

[0076] In one or more examples, the stored adjustment value 310 may be represented by a sign (positive or negative), and thus the adjustment signal 214 may be represented by a sign (positive or negative). The corresponding adjustment value 310 and adjustment signal 214 are represented by a sign to indicate whether the offset represented by the adjustment value 310 or adjustment signal 214 is to be applied from the bottom of the range of DCO code values ​​associated with the DCO frequency overlap region or from the top of the range to bypass the DCO control corresponding to the DCO frequency overlap region. When approaching the upper boundary code, the offset is applied from the bottom of the range and therefore has a positive sign. When approaching the lower boundary code, the offset is applied from the top of the range and therefore has a negative sign.

[0077] Figure 4 4 is a block diagram illustrating an apparatus 400 for bypassing DCO control codes corresponding to DCO frequency overlap regions according to one or more examples. The apparatus 400 includes a counter 402 and a detector 404. The apparatus 400 is a non-limiting example of the integral path portion 200.

[0078] Counter 402 receives direction signal 406, clock signal 408 (clk signal 408), and reset signal 410. Direction signal 406 indicates whether the DCO control code is increasing or decreasing. Any suitable technique may be utilized to determine the direction information indicated by direction signal 406, such as, but not limited to, utilizing an average change in the value of a phase error signal or a DCO control code. In one or more examples, direction signal 406 may be generated by additional logic circuitry external to counter 402 or by logic circuitry of counter 402 (e.g., counter 402 is a counting logic circuitry that receives a signal indicating a phase error or a DCO control code and determines direction information based thereon).

[0079] The clk signal 408 may be a local clock, a system clock, a reference clock of a PLL, a feedback clock of a PLL, or derived from any of the foregoing (eg, a divided version, but not limited thereto).

[0080] In one or more examples, the counter 402 operates as follows: if the direction signal 406 indicates that the digital phase error signal 208 is decreasing, the counter 402 decrements the value of the count 418 by a predetermined amount at each clock cycle. If the direction signal indicates that the digital phase error signal 208 is increasing, the counter 402 increments the value of the count 418 by a predetermined amount at each clock cycle.

[0081] The counter 402 resets the value of the count 418 in response to the assertion of the reset signal 410. In response to the reset signal 410 being asserted and the direction signal 406 indicating that the digital phase error signal 208 is decreasing, the counter 402 resets the value of the count 418 to the top of the DCO control code range minus a predetermined adjustment amount to bypass a value corresponding to the DCO frequency overlap region. In response to the reset signal 410 being asserted and the direction signal 406 indicating that the digital phase error signal 208 is increasing, the counter 402 resets the value of the count 418 to the bottom of the DCO control code range plus a predetermined adjustment amount to bypass a value corresponding to the DCO frequency overlap region. The DCO control code 210 may be based at least in part on the count 418.

[0082] Detector 404 (which may also be referred to herein as "threshold detector 404") detects when count 418 crosses a value of threshold signal 412. The value of threshold signal 412 may be changed or set by circuitry not shown. When the value of count 418 is increasing (and therefore the DCO control code is increasing), detector 404 detects the crossing from a value below threshold signal 412 to a value above the signal. When the value of count 418 is decreasing (and therefore the DCO control code is decreasing), detector 404 detects the crossing from a value above threshold signal 412 to a value below the signal. Detector 404 asserts reset signal 410 at least in part in response to detecting the crossing of the value of threshold signal 412.

[0083] In this example, the adjustment signal 214 is a reset signal 410 , in response to which the counter 402 sets the count 418 to a value equal to the reset value.

[0084] Figure 5 is a block diagram illustrating an apparatus 500 for bypassing DCO control codes corresponding to DCO frequency overlap regions according to one or more examples. Apparatus 500 is a non-limiting example of an integral path portion 200.

[0085] The apparatus 500 includes a counter 504, a detector 506, and a multiplexer 502. The multiplexer 502 selects one of the step size signals 508 as the selected step size signal 518 in response to a selection signal 522 generated by the detector 506. The step size signal 508 includes at least two steps representing different quantities.

[0086] The counter 504 receives the selected step signal 518, the direction signal 520, and the clock signal 512 (clk signal 512) output by the multiplexer 502. The value of the selected step signal 518 indicates the amount by which the counter 504 increments or decrements the value of the count 516 at each clock cycle. The direction signal 520 indicates whether the counter 504 increments or decrements the value of the count 516 at each clock cycle. Any suitable technique may be utilized to determine the direction information indicated by the direction signal 520. As a non-limiting example, the direction information indicated by the direction signal 520 may be determined based on an average change in the value of the phase error signal. The direction signal 520 may be generated by additional logic circuitry external to the counter 504 or by logic circuitry of the counter 504 (e.g., the counter 504 is a counting logic circuit that receives a signal indicating a phase error and determines the direction information based thereon).

[0087] In one or more examples, the counter 504 operates as follows: if the direction signal 520 indicates that the value of the count 516 is decreasing (and therefore if the DCO control code is decreasing), the counter 504 decrements the value of the count 516 by the selected step size signal 518 at each clock cycle. If the direction signal 520 (and therefore if the DCO control code is increasing) indicates that the value of the count 516 is increasing (and therefore if the DCO control code is increasing), the counter 504 increments the value of the count 516 by the selected step size signal 518 at each clock cycle.

[0088] Detector 506 (which may also be referred to herein as "threshold detector 506") observes when the value of count 516 crosses the value of threshold signal 510 and sets select signal 522 based on the type of crossing it observes. The value of threshold signal 510 may be set by circuitry not shown. In response to observing that the value of count 516 is increasing, detector 506 detects a crossing from a value below threshold signal 510 to a value above the signal (a first type of crossing). In response to observing that the value of count 516 is decreasing, detector 506 detects a crossing from a value above threshold signal 510 to a value below the signal (a second type of crossing that is different from the first type of crossing). Detector 506 sets select signal 522 at least in part in response to observing a crossing of the threshold and the type of crossing it observes.

[0089] In one or more examples, the detector 506 can pre-associate the value to which the select signal 522 is set with a particular input of the multiplexer 502 and a corresponding step signal of the step signal 508 received at the corresponding input of the multiplexer 502. In one or more examples, the detector 506 controls the selected step signal 518 via the select signal 522 and the multiplexer 502 to a value sufficient to bypass the range of values ​​of the count 516 associated with the DCO frequency overlap region, and then in a subsequent clock cycle, it controls the selected step signal 518 via the select signal 522 and the multiplexer 502 to a value associated with a DCO step size or a normal step size.

[0090] The DCO control code 210 can be based on the count 516. In this example, the adjustment signal 214 is a selected step size signal 518 used by the counter 504 to increment or decrement the value of the count 516.

[0091] Figure 6 6 is a flow chart depicting a process 600 for bypassing DCO frequency overlap regions in a PLL according to one or more examples. As a non-limiting example, some or all of the operations of process 600 may be performed by Figure 2 The integral path portion 200, Figure 3 The device 300, Figure 4 The device 400, Figure 5 The method is performed by the device 500 or a PLL including the device.

[0092] Although the example process 600 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 600. In other examples, different components of an example device or system implementing the process 600 may perform functions substantially simultaneously or in a particular order.

[0093] In one or more examples, process 600 includes observing that the DCO frequency is at a boundary of a DCO frequency overlap region at operation 602. In one or more examples, process 600 may include inferring that the DCO frequency is at a boundary of a DCO frequency overlap region in response to observing that the DCO control code has crossed a threshold set at or near a control code associated with a boundary of the DCO frequency overlap region.

[0094] In one or more examples, process 600 includes bypassing at least a portion of the DCO frequency overlap region at operation 604. Process 600 may bypass at least the portion of the DCO frequency overlap region in response to observing in operation 602 that the DCO frequency is at a boundary of the DCO frequency overlap region.

[0095] Figure 7 is a flow chart depicting a process 700 for observing that a DCO frequency is at a boundary of a DCO frequency overlap region according to one or more examples.

[0096] Although the example process 700 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 700. In other examples, different components of an example device or system implementing the process 700 may perform functions substantially simultaneously or in a particular order.

[0097] In one or more examples, process 700 includes receiving a current control code for an integration input of a DCO at operation 702. The current control code may be bits of an accumulated value used as a control code output by a digital integrator.

[0098] In one or more examples, process 700 includes, at operation 704 , determining a direction of a current control code based at least in part on a difference between the current control code and a previous control code.

[0099] In one or more examples, process 700 includes, at operation 706, selecting a set of control codes that are predetermined to correspond to a boundary of a DCO frequency overlap region based at least in part on the determined direction of the current control code. In one or more examples, the corresponding control codes of the set may correspond exactly to the boundary or may be at a predetermined distance before the boundary to give time to set the adjustment value. In other words, in some examples, the boundary codes may be predetermined to detect an approaching boundary of a corresponding DCO frequency overlap region.

[0100] In one or more examples, process 700 includes, at operation 708 , comparing the current control code to the selected set of control codes.

[0101] In one or more examples, process 700 includes, at operation 710 , observing, at least in part in response to the comparing, that the DCO frequency is at a boundary of a DCO frequency overlap region.

[0102] In one or more examples, process 700 optionally includes, at operation 712 , indicating that the DCO frequency is at a boundary of the DCO frequency overlap region if the current control code is observed to correspond to a boundary of the DCO frequency overlap region.

[0103] In one or more examples, process 700 optionally includes, at operation 714 , indicating that the DCO frequency is not at a boundary of the DCO frequency overlap region if it is observed that the current control code does not correspond to a boundary of the DCO frequency overlap region.

[0104] Figure 8 8 is a flow chart depicting a process 800 for bypassing at least a portion of a DCO frequency overlap region according to one or more examples. As a non-limiting example, some or all of the operations of process 800 may be performed by Figure 2 The integral path portion 200 or Figure 3 The device 300, Figure 4 The device 400 or Figure 5 The device 500 is used to execute.

[0105] Although the example process 800 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 800. In other examples, different components of an example device or system implementing the process 800 may perform functions substantially simultaneously or in a particular order.

[0106] In one or more examples, process 800 includes, at operation 802, obtaining an adjustment value associated with a control code indicated by a received boundary detection signal. The received boundary detection signal is generated in response to observing a boundary of a DCO frequency overlap region, for example, as described in reference Figure 7 as described.

[0107] In one or more examples, process 800 includes, at operation 804 , generating an adjustment signal proportional to the adjustment value.

[0108] In one or more examples, process 800 includes, at operation 806 , providing an adjustment signal to a digital integrator that provides a control code to an integration input of the DCO.

[0109] Fig. 9 is a flow chart depicting a process for bypassing at least a portion of a DCO frequency overlap region according to one or more examples.

[0110] Although the example process 900 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 900. In other examples, different components of the example device or system implementing the process 900 may perform functions substantially simultaneously or in a particular order.

[0111] According to one or more examples, process 900 includes, at operation 902 , counting up or down by a predetermined step signal.

[0112] According to one or more examples, process 900 includes, at operation 904 , observing a count crossing a threshold signal.

[0113] According to one or more examples, process 900 includes, at operation 906 , setting a count to a predetermined value in response, at least in part, to observing a crossing.

[0114] Fig.10 is a flow diagram depicting a method for bypassing at least a portion of a DCO frequency overlap region according to one or more examples.

[0115] Although the example routines depict a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without substantially affecting the functionality of the routines. In other examples, different components of the example devices or systems implementing the routines may perform functions substantially simultaneously or in a particular order.

[0116] According to one or more examples, process 1000 includes, at operation 1002 , counting up or down by a step signal.

[0117] According to one or more examples, process 1000 includes, at operation 1004 , observing a count crossing a threshold signal.

[0118] According to one or more examples, process 1000 includes setting a step size signal at least in part in response to observing the crossing, at operation 1006. In one or more examples, at operation 1006, in response to observing the crossing, setting the step size signal to a different larger value.

[0119] Fig.11 is a block diagram depicting an apparatus 1100 for tracking a clock (and may also be referred to herein as "clock tracking circuit 1100") according to one or more examples. In one or more examples, the clock tracking circuit 1100 may be a hybrid PLL or a digital PLL.

[0120] The clock tracking circuit 1100 generally operates to generate an output clock signal 1108 phase-locked and frequency-locked to a reference clock signal 1114. The clock tracking circuit 1100 includes an error detector 1102, a controller 1104, and a digitally controlled oscillator 1106. The controller 1104 includes a DCO frequency overlap region bypass circuit 1118.

[0121] The error detector 1102 receives the reference clock signal 1114 and the feedback clock signal 1116 and generates an error signal 1112 at least partially in response thereto. More specifically, the error detector 1102 generates an error signal that is proportional to the phase difference and frequency difference between the two input signals. More specifically, the magnitude and direction of the error signal are proportional to the phase and frequency difference between the input signals. If the phase and frequency of the two input signals are substantially the same, the magnitude and direction of the error signal 1112 will be zero, indicating that the phase and frequency of the two signals are the same. If the phase or frequency difference between the two input signals is different, the magnitude and direction of the error signal 1112 will be non-zero and proportional to the difference between the phase (and indirectly, frequency) of the two input signals.

[0122] In the case where the error detector 1102 is a binary phase detector that generates a binary signal, the error detector 1102 may generate the error signal 1112 as a binary signal having two separate and distinct component signals, an UP signal and a DOWN signal. The error detector 1102 generates the UP signal and the DOWN signal as a series of pulses, wherein the pulses on the corresponding one of the UP signal and the DOWN signal indicate the magnitude and direction of the error signal 1112. The UP pulse indicates that the phase or frequency of one of the input signals leads the other input signal, and the DOWN pulse indicates that the phase or frequency of one of the input signals lags behind the other input signal. The magnitude of the error signal 1112 is represented by the number of pulses generated in the UP signal or the DOWN signal within a given time period. A larger number of pulses indicates a larger phase or frequency difference between the two input signals, and a smaller number of pulses indicates a smaller phase or frequency difference.

[0123] The reference clock signal 1114 may be generated by any suitable clock source for a given operating context. The feedback clock signal 1116 may be the same as the output clock signal 1108 generated by the clock tracking circuit 1100 (e.g., the output clock signal 1108 is directly provided to the input of the error detector 1102, but is not limited thereto), or may be a clock signal that indicates the phase and frequency of the output clock signal 1108. For example, the phase and frequency of the feedback clock signal 1116 may be the same as or different from the output clock signal 1108, but in either case, can be related to the phase and frequency of the output clock signal 1108. In one or more examples, the feedback clock signal 1116 may be a divided version of the output clock signal 1108 (e.g., via a divider or buffer, but is not limited thereto). In one or more, the error detector 1102 may be any suitable error detector for generating a digital signal representing the phase error between the reference clock signal 1114 and the feedback clock signal 1116, and as a non-limiting example, may be a switch-mode phase detector, but is not limited thereto.

[0124] The digitally controlled oscillator 1106 is an electronic oscillator for generating an output clock signal 1108 in response at least in part to a control signal 1110 , which is a digital control signal or a digital control code. The control signal 1110 is fed to an input of the digitally controlled oscillator 1106 .

[0125] The controller 1104 provides a control signal 1110 to the digitally controlled oscillator 1106 to adjust the output clock signal 1108. In one or more examples, the controller 1104 may include circuitry (analog circuitry, digital circuitry, or both) to provide a proportional control path and an integral control path for controlling the digitally controlled oscillator 1106. The integral control path may include an integral path portion 200 that implements a DCO frequency overlap region bypass circuit 1118. Because the controller 1104 sets the control signal 1110 via the DCO frequency overlap region bypass circuit 1118, the clock tracking circuit 1100 may exhibit reduced DCO frequency overlap-induced limit cycles.

[0126] Those of ordinary skill in the art will appreciate that the functional elements (eg, functions, operations, actions, processes or methods) of the examples disclosed herein may be implemented in any suitable hardware, software, firmware or a combination thereof. Fig.12 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated.In some examples, some or all parts of the functional elements disclosed herein may be performed by hardware specifically for executing the functional elements.

[0127] Those of ordinary skill in the art will appreciate that the functional elements (eg, functions, operations, actions, processes or methods) of the examples disclosed herein may be implemented in any suitable hardware, software, firmware or a combination thereof. Fig.12 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated.In some examples, some or all parts of the functional elements disclosed herein may be performed by hardware specifically for executing the functional elements.

[0128] Fig.121 is a block diagram of an apparatus 1200 (also referred to herein as "circuit 1200" or "circuitry 1200") that may be used to implement various functions, operations, actions, processes, or methods disclosed herein in some examples. Circuit 1200 includes one or more processors 1202 (sometimes referred to herein as "processor 1202") operably coupled to one or more data storage devices 1206 (sometimes referred to herein as "storage 1206"). Storage 1206 includes machine executable code 1208 stored thereon, and processor 1202 includes logic circuit 1204. Machine executable code 1208 includes information describing functional elements that may be implemented (e.g., executed) by logic circuit 1204. Logic circuit 1204 is adapted to implement (e.g., execute) the functional elements described by machine executable code 1208. When the functional elements described by machine executable code 1208 are executed, circuit 1200 should be viewed as dedicated hardware for performing the functional elements disclosed herein. In some examples, processor 1202 may execute the functional elements described by machine executable code 1208 sequentially, concurrently (eg, on one or more different hardware platforms), or in one or more parallel process flows.

[0129] When implemented by logic circuitry 1204 of processor 1202, machine executable code 1208 adapts processor 1202 to perform operations of the examples disclosed herein. By way of non-limiting example, machine executable code 1208 adapts processor 1202 to perform some or all operations related to reducing limit cycles caused by DCO frequency overlap in hybrid and digital PLLs as discussed herein. By way of further non-limiting example, machine executable code 1208 may adapt processor 1202 to perform some or all operations related to one or more of process 600, process 700, process 800, process 900, or process 1000.

[0130] Likewise, by way of non-limiting example, machine executable code 1208 may adapt processor 1202 to perform some or all of the features, functions, or operations disclosed herein for one or more of device 100, device 200, device 300, device 400, device 500, or system 1100.

[0131] The processor 1202 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer, and the general-purpose computer executes or is configured to execute functional elements corresponding to the machine executable code 1208 (e.g., software code, firmware code, hardware description) associated with the examples of the present disclosure. It should be noted that the general-purpose processor (which may also be referred to as a host processor or simply a host in this article) may be a microprocessor, but in an alternative, the processor 802 may include any conventional processor, controller, microcontroller, or state machine. The processor 1202 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0132] In some examples, storage device 1206 includes volatile data storage device (e.g., random access memory (RAM)), non-volatile data storage device (e.g., flash memory, hard disk drive, solid state drive, erasable programmable read-only memory (EPROM), but not limited to this). In some examples, processor 1202 and storage device 1206 may be implemented as a single device (e.g., semiconductor device product, system on chip (SOC), but not limited to this). In some examples, processor 1202 and storage device 1206 may be implemented as separate devices.

[0133] In some examples, machine executable code 1208 may include computer readable instructions (e.g., software code, firmware code). By way of non-limiting example, the computer readable instructions may be stored by storage device 1206, directly accessed by processor 1202, and executed by processor 1202 using at least logic circuit 1204. Likewise, by way of non-limiting example, the computer readable instructions may be stored on storage device 1206, transferred to a memory device (not shown) for execution, and executed by processor 802 using at least logic circuit 1204. Thus, in some examples, logic circuit 1204 includes electrically configurable logic circuit 1204.

[0134] In some examples, machine executable code 1208 may describe hardware (e.g., circuitry) to be implemented in logic circuit 1204 to perform a functional element. The hardware may be described at any of a variety of abstraction levels, from low-level transistor layout to a high-level description language. At a high level of abstraction, a hardware description language (HDL) may be used, such as an IEEE standard hardware description language (HDL). By way of non-limiting example, a , S YSTEM V ERILOG TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL).

[0135] The HDL description may be converted into a description at any of a variety of other abstraction levels as desired. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations performed by the hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of the logic circuit 1204 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, a discrete gate or transistor logic element, a discrete hardware component, or a combination thereof of a programmable logic device. Therefore, in some examples, the machine executable code 1208 may include an HDL, RTL, GL description, a mask-level description, other hardware descriptions, or any combination thereof.

[0136] In examples where the machine executable code 1208 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 1206) may implement the hardware description described by the machine executable code 1208. By way of non-limiting example, the processor 1202 may include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 1204 may be electrically controlled to implement circuitry corresponding to the hardware description into the logic circuit 1204. Likewise, by way of non-limiting example, the logic circuit 1204 may include hard-wired logic components manufactured by a manufacturing system (not shown, but including the storage device 1206) according to the hardware description of the machine executable code 1208.

[0137] Regardless of whether the machine executable code 1208 includes computer readable instructions or a hardware description, the logic circuit 1204 is adapted to perform the functional elements described by the machine executable code 1208 when implementing the functional elements of the machine executable code 1208. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0138] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that performs the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, a processing device, but not limited thereto). In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0139] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or various subcombinations of certain elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0140] The terms used in this disclosure and in particular in the appended claims (e.g., the body of the appended claims, but not limited thereto) are generally intended to be "open" terms (e.g., the term "comprising" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," but not limited thereto). As used herein, the term "each" means "some or all." As used herein, the terms "each and every" mean "all."

[0141] Additionally, if a specific number of introduced claim expressions is intended, such intent will be expressly recited in the claim, and in the absence of such a recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim expressions. However, the use of such phrases should not be construed to imply that a claim expression introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim expression to an example containing only one such expression, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "a kind" (e.g., "a" and / or "a" may be interpreted to mean "at least one" or "one or more", but not limited to such); the same is true when a claim expression is introduced using a definite article.

[0142] Furthermore, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted as intending at least the recited number (e.g., the unmodified recitation "two recitations" without other modifiers intends at least two recitations, or two or more recitations, but is not limited thereto). Furthermore, in those instances where a convention similar to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but are not limited thereto.

[0143] In addition, any separate word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0144] Additional non-limiting examples include:

[0145] Embodiment 1: A device comprising: a digital integrator for generating a frequency error signal based at least in part on a digital phase error signal; and a logic circuit for setting an integrated value of the digital phase error signal stored at a register of the digital integrator.

[0146] Embodiment 2: The apparatus according to embodiment 1, wherein in order to set the integrated value of the digital phase error signal stored at the register of the digital integrator, the logic circuit is used to: adjust the gain of the digital integrator.

[0147] Embodiment 3: The device according to any one of embodiments 1 and 2, wherein in order to adjust the gain of the digital integrator, the logic circuit is used to: set parameters that control the integration of the digital phase error signal at the digital integrator.

[0148] Embodiment 4: The device according to any one of embodiments 1 to 3, wherein the parameter comprises: an accumulation step size, an accumulation time or a scaling factor.

[0149] Embodiment 5: A device according to any one of embodiments 1 to 4, wherein the logic circuit includes: a boundary detector; and a lookup table (LUT), the lookup table (LUT) being responsive to the boundary detector, wherein the LUT associates an adjustment value with a boundary code.

[0150] Embodiment 6: The apparatus of any one of Embodiments 1 to 5, wherein the logic circuit for setting the integration value is based at least in part on a corresponding adjustment value.

[0151] Embodiment 7: A device according to any one of embodiments 1 to 6, wherein the digital integrator includes a counter, which is used to count up and down, and wherein the logic circuit includes a threshold detector, which is used to set the counter to a predetermined value at least partially in response to the count and the threshold.

[0152] Embodiment 8: A device according to any one of embodiments 1 to 7, wherein the logic circuit includes: a detector, which is used to set a selection signal in response to a count and a threshold; and a multiplexer, which is used to receive a step signal and output a selected step signal in response to the selection signal, and wherein the digital integrator includes a counter, which is used to increment or decrement the count by an amount corresponding to the selected step signal.

[0153] Embodiment 9: A method, the method comprising: observing that a DCO frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region.

[0154] Embodiment 10: A method according to embodiment 9, wherein observing that the DCO frequency is at the boundary of the DCO frequency overlapping region includes: receiving a current control code for an integral input to the DCO; determining a direction of the current control code based at least in part on a difference between the current control code and a previous control code; comparing the current control code to a set of control codes; and observing that the DCO frequency is at the boundary of the DCO frequency overlapping region at least in part in response to the comparison.

[0155] Embodiment 11: The method according to any one of embodiments 9 and 10 includes: in response to observing that the current control code corresponds to the boundary of the DCO frequency overlapping region, indicating that the DCO frequency is at the boundary of the DCO frequency overlapping region.

[0156] Embodiment 12: The method according to any one of embodiments 9 to 11, the method comprising: indicating that the DCO frequency is not at the boundary of the DCO frequency overlapping region in response to observing that the current control code does not correspond to the boundary of the DCO frequency overlapping region.

[0157] Embodiment 13: The method of any one of Embodiments 9 to 12, the method comprising selecting a set of control codes predetermined to correspond to a boundary of a DCO frequency overlap region based at least in part on the determined direction of the current control code.

[0158] Embodiment 14: A method according to any one of embodiments 9 to 13, wherein bypassing at least a portion of the DCO frequency overlapping region includes: obtaining an adjustment value associated with a control code identified by a boundary detection signal; generating an adjustment signal proportional to the adjustment value; and providing the adjustment signal to a digital integrator that provides a control code to an integral input of the DCO.

[0159] Embodiment 15: A method according to any one of embodiments 9 to 14, the method comprising: incrementing or decrementing a count according to a predetermined step signal; observing that the count is at a value of a threshold signal; and setting the count to a predetermined value at least in part in response to observing the crossing.

[0160] Embodiment 16: A method according to any one of embodiments 9 to 15, the method comprising: counting up or down according to a step signal; observing that the count crosses a threshold signal; and setting the step signal to a larger value at least partially in response to observing that the count crosses the threshold signal.

[0161] Embodiment 17: A device comprising: a digitally controlled oscillator (DCO) of a hybrid or digital clock tracking circuit, the DCO including an input for integral control of the DCO; and a controller for generating a control code for the input for integral control of the digitally controlled oscillator, wherein the controller utilizes the control code to reduce limit cycles caused by DCO frequency overlap.

[0162] Embodiment 18: The apparatus according to embodiment 17 comprises: an error detector for generating an error signal representing a difference between an output of the DCO and a reference signal, wherein the controller for generating the control code to reduce the difference is represented by the error detector.

[0163] Embodiment 19: The apparatus of any one of Embodiments 17 and 18, wherein the controller sets the value of the control code to bypass the DCO frequency overlap region of a DCO.

[0164] Embodiment 20: The apparatus of any one of Embodiments 17 to 19, wherein the controller sets a bypass value of the control code, the bypass value corresponding to a DCO frequency within a DCO frequency overlap region.

[0165] Although the present disclosure describes the present invention with respect to certain illustrative examples, those of ordinary skill in the art will recognize and understand that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrative examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features from another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A device, comprising: a digital integrator for generating a frequency error signal based at least in part on the digital phase error signal; and A logic circuit is provided for setting an integrated value of the digital phase error signal stored at a register of the digital integrator.

2. The apparatus of claim 1 , wherein to set the integrated value of the digital phase error signal stored at the register of the digital integrator, the logic circuit is configured to: Adjust the gain of the digital integrator.

3. The apparatus of claim 2, wherein to adjust the gain of the digital integrator, the logic circuit is configured to: Parameters are set that control integration of the digital phase error signal at the digital integrator.

4. The apparatus according to claim 3, wherein the parameters include: Accumulation step size, accumulation time, or scaling factor.

5. The apparatus of claim 1 , wherein the logic circuit comprises: Boundary detector; and A look-up table (LUT) is responsive to the boundary detector, wherein the LUT associates an adjustment value with a boundary code.

6. The apparatus of claim 5, wherein the logic for setting the integration value is based at least in part on a corresponding adjustment value.

7. The apparatus of claim 1 , wherein the digital integrator comprises a counter for incrementing and decrementing counts, and wherein the logic circuit comprises a threshold detector for setting the counter to a predetermined value in response, at least in part, to the count and a threshold.

8. The apparatus of claim 1, wherein the logic circuit comprises: a detector for setting a selection signal in response to the count and the threshold; and a multiplexer for receiving a step size signal and outputting a selected step size signal in response to the selection signal, and wherein the digital integrator includes a counter for incrementing or decrementing the count by an amount corresponding to the selected step size signal.

9. A method comprising: It is observed that the DCO frequency is at the boundary of the DCO frequency overlap region; as well as At least a portion of the DCO frequency overlap region is bypassed.

10. The method of claim 9, wherein observing that the DCO frequency is at the boundary of the DCO frequency overlap region comprises: receiving a current control code for an integral input of the DCO; determining a direction of the current control code based at least in part on a difference between the current control code and a previous control code; comparing the current control code with a set of control codes; as well as Responsive at least in part to the comparing, an observation is made that the DCO frequency is at the boundary of the DCO frequency overlap region.

11. The method according to claim 10, comprising: In response to observing that the current control code corresponds to the boundary of the DCO frequency overlapping region, indicating that the DCO frequency is at the boundary of the DCO frequency overlapping region.

12. The method according to claim 10, comprising: In response to observing that the current control code does not correspond to the boundary of the DCO frequency overlap region, indicating that the DCO frequency is not at the boundary of the DCO frequency overlap region.

13. The method according to claim 10, comprising: A set of control codes predetermined to correspond to boundaries of a DCO frequency overlap region is chosen based at least in part on the determined direction of the current control code.

14. The method of claim 9, wherein bypassing at least a portion of the DCO frequency overlap region comprises: obtaining an adjustment value associated with a control code identified by a boundary detection signal; generating an adjustment signal proportional to the adjustment value; as well as The adjustment signal is provided to a digital integrator which provides a control code to the integration input of the DCO.

15. The method according to claim 9, comprising: Count up or down according to a predetermined step signal; observing that the count is at a value of a threshold signal; as well as The count is set to a predetermined value in response, at least in part, to observing the crossing.

16. The method according to claim 9, comprising: Count up or down according to the step signal; observing that the count crosses a threshold signal; as well as The step size signal is set to a larger value in response, at least in part, to observing the count crossing the threshold signal.

17. A device, comprising: a digitally controlled oscillator (DCO) of a hybrid or digital clock tracking circuit, the DCO including an input for integral control of the DCO; and A controller is provided for generating a control code for the input of the integral control of the digitally controlled oscillator, wherein the controller utilizes the control code to reduce limit cycles caused by DCO frequency overlap.

18. The device according to claim 17, comprising: an error detector for generating an error signal representing a difference between an output of the DCO and a reference signal, wherein the controller for generating the control code to reduce the difference is represented by the error detector.

19. The apparatus of claim 18, wherein the controller sets the value of the control code to bypass a DCO frequency overlap region of the DCO.

20. The apparatus of claim 17, wherein the controller sets a bypass value of the control code, the bypass value corresponding to a DCO frequency within a DCO frequency overlap region.

Images