Deep trench capacitors (dtc) employing bypass metal trace signal routing and related integrated circuit (IC) packages and methods of manufacture

Abstract

Deep trench capacitors (DTC) employing bypass metal trace signal routing that supports signal bypass routing, and related integrated circuit (IC) packages and methods of manufacture are disclosed. The DTC includes an external metallization layer (e.g., a redistribution layer (RDL)) that provides an external interface to the DTC. In an exemplary aspect, in order to make available signal wirings that can be extended through the DTC, an external metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled to capacitors in the DTC. These additional metal interconnects are interconnected to each other through metal traces (e.g., metal lines) in an external metallization layer of the DTC to provide bypass signal routing through the DTC. This contrasts with a signal path in the package substrate in which the DTC is coupled or embedded must be routed around the DTC in the package substrate.

Description

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 816,502, filed on Aug. 1, 2022, entitled “DEEP TRENCH CAPACITORS (DTCs) EMPLOYING BYPASS METAL TRACE SIGNAL ROUTING, AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS,” which is hereby incorporated by reference in its entirety. Background Art

[0002] I. Public Domain

[0003] The field of the present disclosure relates to integrated circuit (IC) packages including one or more semiconductor dies supported by a packaging substrate, and more particularly to coupling capacitors to the packaging substrate of the IC package to support signal processing and / or power integrity.

[0004] II. Background

[0005] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages (also referred to as "semiconductor packages" or "chip packages"). The IC package includes one or more semiconductor die, which are mounted on a package substrate and electrically coupled to the package substrate to provide physical support and electrical interfaces for the die(s). The die(s) are electrically connected to metal interconnects (e.g., metal traces, metal wires) in the top metallization layer of the package substrate. The package substrate may also include one or more other metallization layers, which include metal interconnects (e.g., metal traces, metal wires) with vertical interconnect paths (through holes), which couple these metal interconnects together between adjacent metallization layers to provide an electrical interface to the die(s) through the package substrate. The package substrate also includes a bottom external metallization layer, which includes metal interconnects coupled to outside metal interconnects (e.g., ball grid array (BGA) interconnects) to provide an external interface between the die(s) in the IC package. The outer metal interconnects may also be coupled (eg, soldered) to traces in a printed circuit board (PCB) to attach the IC package to the PCB, thereby interfacing its die(s) with other circuitry coupled to the PCB.

[0006] Capacitors are usually included in IC packages. Capacitors can be coupled to IC packages to provide decoupling capacitance for circuits in the die, thereby shunting noise from one circuit (e.g., a power supply circuit) to another circuit (e.g., a power supply circuit). Capacitors can also be coupled to IC packages as part of the filter circuit of the die. Such capacitors can be provided as deep trench capacitors (DTCs). DTCs are formed similarly to semiconductor devices, and therefore have the advantage of being able to be manufactured using semiconductor manufacturing methods. The advantage of using DTCs is that DTCs can be arranged closer to the circuits in the IC package. DTCs include vertical semiconductor devices formed in deep trenches in a silicon substrate to form parallel plate capacitors. Each capacitor is formed by an internal electrode, which serves as an internal conductive layer surrounded by a dielectric material in a given trench. An outer plate as an external conductive layer is arranged in the trench adjacent to the dielectric material, so that a capacitor is formed between the inner electrode and the outer plate. DTCs can be coupled to the outer surface of the package substrate, which is also coupled to the die in the IC package as a die side capacitor (DSC). The DTC may also be coupled to the opposite outer surface of the package substrate on which the die is arranged as a pad side capacitor (LSC). The DTC may also be embedded in the package substrate of the IC package. For example, the capacitor may be embedded in the core substrate of the core package substrate. In each of these examples of the DTC, the metal interconnect / metal traces in the metallization layer of the package substrate provide electrical connections between the die and the DTC.

[0007] Public Overview

[0008] Various aspects disclosed herein include deep trench capacitors (DTCs) that use bypass metal trace signal routing. Related integrated circuit (IC) packages and manufacturing methods are also disclosed. The DTC can be coupled to or embedded in a package substrate of an IC package to provide capacitance to a circuit in a semiconductor die ("die") in the IC package. The DTC is coupled to the die by metal wires in the metallization layer (or layers) of the package substrate that couple the DTC to the die. In an exemplary aspect, the DTC includes a substrate in which a groove is arranged. The capacitor is formed in the groove, wherein the metal contacts (i.e., terminals) of the capacitor are arranged adjacent to the outer surface of the substrate. The DTC also includes an external metallization layer (e.g., a redistribution layer (RDL)) that provides an external interface to the DTC. The external metallization layer includes an insulating layer having metal interconnects (e.g., metal pads), which are arranged in the insulating layer and coupled to the metal contacts of the capacitor. Metal bumps can be formed in openings in the insulating layer and coupled to metal interconnects to provide an interface between the metal bumps and the capacitors in the DTC. In an exemplary aspect, in order to make the signal path that can extend through the DTC available, the external metallization layer of the DTC also includes additional metal interconnects. In one example, these additional metal interconnects in the external metallization layer of the DTC are not coupled to the capacitors in the DTC. These additional metal interconnects are interconnected to each other through metal traces (e.g., metal lines) in the external metallization layer of the DTC to provide bypass signal routing through the DTC. For example, in the case where the DTC is coupled or embedded in a packaging substrate, the metal interconnects that need to be coupled to each other in the multiple metallization layers of the packaging substrate can each be coupled to the additional metal interconnects interconnected in the external metallization layer of the DTC to provide a bypass signal path through the DTC. This is in contrast to the wiring signal path that must surround the DTC in the packaging substrate. As another example, multiple additional metal interconnects that are interconnected can be formed in the external metallization layer of the DTC to provide multiple signal bypass routings extending through the DTC.

[0009] In this regard, in an exemplary aspect, a DTC is provided. The DTC includes a substrate including a first surface and a first side. The DTC also includes a first capacitor arranged in the substrate. The first capacitor includes a first conductive layer and a second conductive layer. The DTC also includes a metallization layer adjacent to the first surface. The metallization layer includes an insulating layer; a first metal contact arranged in the insulating layer and coupled to the first conductive layer; a second metal contact arranged in the insulating layer and coupled to the second conductive layer; a third metal contact arranged in the insulating layer, the third metal contact adjacent to the first surface of the substrate; and a fourth metal contact arranged in the insulating layer, the fourth metal contact adjacent to the first surface of the substrate. The metallization layer also includes a first metal line arranged in the insulating layer, the first metal line coupling the third metal contact to the fourth metal contact.

[0010] In another exemplary aspect, a method of manufacturing a DTC is provided. The method includes providing a substrate, the substrate including a first surface and a first side. The method also includes forming a first capacitor in the substrate, the first capacitor including a first conductive layer and a second conductive layer. The method also includes forming a metallization layer adjacent to the first surface of the substrate, including: forming an insulating layer, forming a first metal contact arranged in the insulating layer and coupled to the first conductive layer, forming a second metal contact in the insulating layer and coupled to the second conductive layer, forming a third metal contact in the insulating layer and adjacent to the first surface of the substrate, forming a fourth metal contact arranged in the insulating layer and adjacent to the first surface of the substrate, and forming a first metal line in the insulating layer coupled to the third metal contact and the fourth metal contact.

[0011] In another exemplary aspect, an IC package is provided. The IC package includes a package substrate, the package substrate including a first surface and one or more first metallization layers, each first metallization layer including one or more metal interconnects. The IC package also includes a die coupled to the first surface of the package substrate. The IC package also includes a DTC coupled to the package substrate. The DTC includes a substrate, the substrate including a first surface and a first side. The DTC also includes a first capacitor arranged in the substrate. The first capacitor includes a first conductive layer and a second conductive layer. The DTC also includes a metallization layer adjacent to the first surface. The metallization layer includes an insulating layer; a first metal contact arranged in the insulating layer and coupled to the first conductive layer; a second metal contact arranged in the insulating layer and coupled to the second conductive layer; a third metal contact arranged in the insulating layer, the third metal contact adjacent to the first surface of the substrate; and a fourth metal contact arranged in the insulating layer, the fourth metal contact adjacent to the first surface of the substrate. The metallization layer also includes a first metal line arranged in the insulating layer, the first metal line coupling the third metal contact to the fourth metal contact. The one or more first metallization layers further include a third metallization layer including a first metal interconnect coupled to a third metal contact. The third metallization layer further includes a second metal interconnect coupled to a fourth metal contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A is a side view of an exemplary integrated circuit (IC) package including a package substrate having a deep trench capacitor (DTC) including a pad side capacitor (LSC), a die side capacitor (DSC), and an embedded DTC;

[0014] Figure 1B yes Figure 1A, which illustrates a capacitor pad of the DTC coupled to a metal interconnect in an external metallization layer of the package substrate to couple the DTC to the external metallization layer of the package substrate, and further illustrates a signal trace routed around the capacitor pad;

[0015] Figure 2 is a side view of another IC package including a DTC in the form of a DSC, the DTC including additional metal interconnects interconnected to each other by metal lines in an external metallization layer of the DTC to provide bypass signal routing through the DTC;

[0016] Figure 3 is a side view of another IC package including a package substrate having a deep trench capacitor (DTC), the deep trench capacitor including a pad side capacitor (LSC), a die side capacitor (DSC), and an embedded DTC, wherein the DTC has an external metallization layer including additional metal interconnects interconnected to each other by metal lines in an external metallization layer of the DTC to provide bypass signal routing through the DTC;

[0017] Figure 4A is a side view of an exemplary DTC including an outer metallization layer having metal interconnects coupled to metal contacts (i.e., terminals) of capacitors formed in trenches in a substrate, and wherein the outer metallization layer further includes additional metal interconnects interconnected to each other through metal lines in the outer metallization layer of the DTC to provide bypass signal routing through the DTC;

[0018] Figure 4B yes Figure 4A a top view of an external metallization layer in a DTC in FIG. 5 illustrating metal interconnects coupled to metal contacts of a capacitor, and additional metal interconnects coupled to each other by metal lines formed in the external metallization layer to provide bypass signal routing through the DTC;

[0019] Figure 5A is a bottom view of an outer metallization layer of an exemplary package substrate showing metal interconnects configured to be coupled to a DTC and metal signal routing around the DTC;

[0020] Figure 5B yes Figure 5A Close-up view of;

[0021] Figure 5C is a bottom view of another external metallization layer of an exemplary package substrate illustrating signal routing through a DTC including the external metallization layer, the external metallization including additional metal interconnects interconnected to each other by metal lines to provide bypass signal routing through the DTC;

[0022] Figure 6is a flow chart illustrating an exemplary manufacturing process for manufacturing a DTC including additional metal interconnects interconnected to each other by metal lines in an outer metallization layer of the DTC to provide a DTC including but not limited to Figure 2-4B and DTC in 5C) bypass signal wiring;

[0023] Figures 7A-7C is a flow chart illustrating another exemplary manufacturing process for manufacturing a DTC including additional metal interconnects interconnected to each other by metal lines in an outer metallization layer of the DTC to provide a DTC (including but not limited to) Figure 2-4B and DTC in 5C) bypass signal wiring;

[0024] Figures 8A-8H is based on Figures 7A-7C an exemplary DTC manufacturing process in order to manufacture a DTC during an exemplary manufacturing stage;

[0025] Figures 9A-9C is a flow chart illustrating an exemplary IC package manufacturing process for manufacturing an IC package, the manufacturing process including coupling a DTC to a package substrate of the IC package, wherein the DTC includes an external metallization layer including additional metal interconnects interconnected to each other by metal lines to provide a plurality of metal interconnects through the DTC (including but not limited to Figure 2-4B and DTC in 5C) bypass signal wiring;

[0026] Figures 10A-10F is based on Figures 9A-9C exemplary manufacturing stages during the manufacture of an IC package of an exemplary IC package manufacturing process;

[0027] Fig.11 is a block diagram of an exemplary processor-based system that may include components that may include an IC package that includes a DTC that includes additional metal interconnects interconnected to each other by metal lines in an external metallization layer of the DTC to provide a processor-based system that includes ... a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that includes a DTC that Figure 2-4B , 5C and 8A-8H) bypass signal wiring, including but not limited to Figure 2 and 10A -10F IC package, and according to but not limited to Figures 7A-7C and any of the exemplary manufacturing processes in 9A-9C; and

[0028] Fig.12 is a block diagram of an exemplary wireless communication device that may include various radio frequency (RF) components that may include an IC package that includes a DTC that includes additional metal interconnects interconnected to each other through metal lines in an external metallization layer of the DTC to provide communication through the DTC (including but not limited to Figure 2-4B, 5C and 8A-8H) bypass signal wiring, including but not limited to Figure 2 and 10A -10F IC package, and according to but not limited to Figures 7A-7C and any of the exemplary manufacturing processes in 9A-9C.

[0029] Detailed Description

[0030] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or superior to other aspects.

[0031] Various aspects disclosed herein include deep trench capacitors (DTCs) that use bypass metal trace signal routing. Related integrated circuit (IC) packages and manufacturing methods are also disclosed. The DTC can be coupled to or embedded in a package substrate of an IC package to provide capacitance to a circuit in a semiconductor die ("die") in the IC package. The DTC is coupled to the die by metal wires in the metallization layer (or layers) of the package substrate that couple the DTC to the die. In an exemplary aspect, the DTC includes a substrate in which a groove is arranged. The capacitor is formed in the groove, wherein the metal contacts (i.e., terminals) of the capacitor are arranged adjacent to the outer surface of the substrate. The DTC also includes an external metallization layer (e.g., a redistribution layer (RDL)) that provides an external interface to the DTC. The external metallization layer includes an insulating layer having metal interconnects (e.g., metal pads), which are arranged in the insulating layer and coupled to the metal contacts of the capacitor. Metal bumps can be formed in openings in the insulating layer and coupled to metal interconnects to provide an interface between the metal bumps and the capacitors in the DTC. In an exemplary aspect, in order to make the signal path that can extend through the DTC available, the external metallization layer of the DTC also includes additional metal interconnects. In one example, these additional metal interconnects in the external metallization layer of the DTC are not coupled to the capacitors in the DTC. These additional metal interconnects are interconnected to each other through metal traces (e.g., metal lines) in the external metallization layer of the DTC to provide bypass signal routing through the DTC. For example, in the case where the DTC is coupled or embedded in a packaging substrate, the metal interconnects that need to be coupled to each other in the multiple metallization layers of the packaging substrate can each be coupled to the additional metal interconnects interconnected in the external metallization layer of the DTC to provide a bypass signal path through the DTC. This is in contrast to the wiring signal path that must surround the DTC in the packaging substrate. As another example, multiple additional metal interconnects that are interconnected can be formed in the external metallization layer of the DTC to provide multiple signal bypass routings extending through the DTC.

[0032] exist Figure 2Before discussing examples of DTCs with external metallization layers in FIG. 1 (these external metallization layers include bypass metal line signal routing to support bypass metal line signal routing of signals through the DTC), the following reference is made to Figure 1A and 1B An example of an IC package including a DTC without bypass metal line signal routing is first described.

[0033] Figure 1A 1 is a side view of an IC package 100 including a pad side capacitor (LSC) 102, a die side capacitor (DSC) 104, and a DTC in the form of a package substrate embedded DTC 106. The IC package 100 includes a die 108 coupled to a package substrate 110. As an example, the LSC 102, the DSC 104, and / or the embedded DTC 106 may be provided in the IC package 100 to couple to various circuits in the die 108 to shunt noise from one circuit (e.g., a power supply circuit) to another circuit (e.g., a power supply circuit), or as part of a filtering circuit in the die 108. Such capacitors may be provided as deep trench capacitors (DTCs). DTCs are formed similarly to semiconductor devices and therefore have the advantage of being able to be manufactured using semiconductor manufacturing methods. The advantage of using DTCs is that they can be arranged closer to the die 108 in the IC package 100.

[0034] The LSC 102 is mounted on a bottom surface 112 of a package substrate 110. The LSC 102 is electrically coupled to the die 108 by coupling the LSC 102 to a metal interconnect 114, which is coupled to a metal line 116 in the metallization layer(s) of the package substrate 110. The metal line 116 is directly or indirectly coupled to a die interconnect 118 to couple the LSC 102 to the die 108. In this example, the DSC 104 is mounted on a top surface 120 of the package substrate 110. Therefore, in order not to interfere with the die 108, the DSC 104 is mounted to the package substrate 110 in an area laterally displaced from the die 108 in the horizontal direction (X-axis and Y-axis direction). The DSC 104 is also electrically coupled to the die 108 by coupling the DSC 104 to a metal interconnect 122, which is coupled to a metal line 124 in the metallization layer(s) of the package substrate 110. The metal lines 124 are coupled directly or indirectly to the die interconnects 118 to couple the DSC 104 to the die 108. The embedded DTC 106 is embedded in the package substrate 110 of the IC package 100. The embedded DTC 106 is also electrically coupled to the die 108 by coupling the embedded DTC 106 to the metal interconnects 126, which are coupled to the metal lines 128 in the metallization layer(s) of the package substrate 110. The metal lines 128 are coupled directly or indirectly to the die interconnects 118 to couple the embedded DTC 106 to the die 108.

[0035] Figure 1B yes Figure 1A 1, which illustrates the metal capacitor pads 130(1), 130(2) of the DTC 132 coupled to the outer metallization layer 134 of the packaging substrate 110 to couple the DTC 132 to the packaging substrate 110. As an example, the DTC 132 may be Figure 1A 1, an LSC 102, a DSC 104, or an embedded DTC 106 in an IC package 100 in the embodiment of the present invention. Metal interconnects 136(1), 136(2) in the form of metal pads are exposed through openings in the solder resist layer of the outer metallization layer 134. In this manner, when the capacitor pads 130(1), 130(1) of the DTC 132 are aligned in the vertical direction (Z-axis direction) above the metal interconnects 136(1), 136(2) and coupled to the metal interconnects 136(1), 136(2), the DTC 132 is electrically coupled to the package substrate 110. As discussed above, the metal lines coupled to the metal interconnects 136(1), 136(2) in the package substrate 110 can be routed and coupled to the package substrate 110 as shown in FIG. Figure 1A A metal interconnect is shown coupled to the die interconnect 118 of the die 108 to couple the DTC 132 to the die 108 .

[0036] Continue to refer to Figure 1B , the metal interconnects 136(1), 136(2) and metal lines in the package substrate 110 below the capacitor pads 130(1), 130(2) that provide signal paths for the DTC 132 consume space in the vertical direction (Z-axis direction) in the package substrate 110. The space may be consumed not only in the outer metallization layer 134 of the package substrate 110, but also in an area in an additional metallization layer below the outer metallization layer 134 below the DTC 132. This may actually provide a "forbidden zone" in the package substrate 110 in the area consumed by the DTC 132, wherein other signal paths provided in the package substrate 110 that are not related to the connection to the DTC 132 cannot intrude. Thus, as shown in FIG. Figure 1B As shown, metal lines 138(1), 138(2) of other signal paths in the packaging substrate 110 near the metal interconnects 136(1), 136(2) of the DTC 132 are routed in the lateral area of ​​the packaging substrate 110 around the DTC 132. This causes the signals carried on these metal lines 138(1), 138(2) to be longer in length, thereby increasing the signal path resistance, thereby causing additional signal delays in such signals. This also results in less efficient signal routing and use of routing space in the packaging substrate 110. This can result in an increase in the number of metallization layers required to provide adequate signal routing in the packaging substrate 110, thereby increasing the area and cost of the packaging substrate 110.

[0037] Figure 2 is a side view of an exemplary IC package 200 including a DTC 202 in the form of a DSC attached to a first die side 204(1) of a package substrate 206. As discussed in greater detail below, the DTC 202 employs bypass metal trace signal routing in an external metallization layer 208 of the DTC 202 to support bypass routing of signals through the DTC 202. In this manner, the DTC 202 supports routing of signals through the DTC 202, wherein such signals do not have to be routed around the DTC 202.

[0038] In this regard, Figure 2 The IC package 200 in the embodiment includes a semiconductor die ("die") 210 coupled to a first side 204(1) of a package substrate 206. The die 210 includes a die interconnect 212 (e.g., a metal pad) coupled to a metal interconnect 214(1) (e.g., a metal trace, a metal line) in an external metallization layer 216(1) of the package substrate 206 via an external metal bump 218 (e.g., a solder bump, a solder joint, a ball grid array (BGA) interconnect, a microbump). In this example, the package substrate 206 also includes additional metallization layers 216(2)-216(X), each additional metallization layer 216(2)-216(X) having a respective metal interconnect 214(2)-214(X) (e.g., a metal trace, a metal line) interconnected via a respective via 220(1)-220(3) (e.g., a metal pillar). In this manner, signals can be routed to the die 210 via signal routing between metal interconnects 214(1)-214(X) coupled by vias 220(1)-220(3) in metallization layers 216(1)-216(X) in the package substrate 206. A second outer metallization layer 216(X) provided on a second side 204(2) of the package substrate 206 opposite to the first side 204(1) of the package substrate 206 in a vertical direction (Z-axis direction) supports an outer surface interconnect 222 (e.g., solder ball, BGA interconnect) for providing an external interface to the package substrate 206 and the die 210 in the IC package 200.

[0039] Continue to refer to Figure 2, similar to the die 210, in this example, the DTC 202 is also coupled to the external metallization layer 216(1) of the package substrate 206. The DTC 202 includes metal interconnects 214(1) (e.g., metal traces, metal lines) coupled to the external metallization layer 216(1) of the package substrate 206 via external metal bumps 227 (e.g., solder bumps, solder joints, ball grid array (BGA) interconnects) to couple the capacitor(s) in the DTC 202 to metal contacts 224 (e.g., metal pads) of the package substrate 206. In this example, the metal contacts 224 are arranged in the external metallization layer 208 of the DTC 202 adjacent to the first surface 204(1) of the package substrate 206. The metal contacts 224 are coupled to the conductive layers of the capacitors 226(1), 226(2) in the DTC 202, which are arranged in trenches formed in the substrate 228 of the DTC 202. An advantage of the DTC 202 is that the DTC 202 can be coupled to the package substrate 206 closer to the die 210 to reduce resistive losses. The DTC 202 can also be manufactured separately similar to a conductor device, and then picked up, placed on the package substrate 206 and coupled to the package substrate 206 similar to the die 210 in the manufacture of the IC package 200. By coupling the DTC 202 to the package substrate 206, the capacitors 226(1), 226(2) in the DTC 202 can be electrically coupled to the package substrate 206 by coupling the metal contacts 224 to the metal interconnects 214(1) in the external metallization layer 216(1) via the metal bumps 227. The capacitors 226(1), 226(2) may be coupled to the die 210 through the package substrate 206 to couple to circuits in the die 210, such as to provide filtering components or as part of a power distribution network (PDN) for the die 210. The metal interconnects 214(1) in the external metallization layer 216(1) coupled to the DTC 202 may form a keep-out zone (KoZ) 230 in the package substrate 206 where other metal lines used to route other signals may have to be avoided and routed around them in the horizontal planes (X-axis and Y-axis planes) to avoid interfering with signal routing in the package substrate 206 for the DTC 202.

[0040] As discussed in more detail below, in this example, in order to provide bypass signal routing in the DTC 202, the DTC 202 in this example also includes additional second metal contacts 232(1), 232(2). Similar to the metal contacts 224, the additional second metal contacts 232(1), 232(2) are also arranged in the outer metallization layer 208 of the DTC 202. In this example, the second metal contacts 232(1), 232(2) are not coupled to the capacitors 226(1), 226(2). Instead, the second metal contacts 232(1), 232(2) are coupled to each side of a metal line (e.g., a metal trace) arranged in the outer metallization layer 208 to provide a signal routing path between the second metal contacts 232(1), 232(2). If it is desired to route a signal for the KoZ 230 of the DTC 202 in the package substrate 206 through the metallization layers 216(1)-216(X) of the package substrate 206, the metal interconnect 214(1)-214(X) for such routed signal may be coupled to the second metal contact 232(1) of the DTC 202 by coupling it to the metal bump 227 (which is coupled to the second metal contact 232(1)). Another second metal contact 232(2) may then be coupled to the metal interconnect 214(1)-214(X), which continues to carry the signal in the package substrate 206 by coupling the metal bump 227 to which the other second metal contact 232(2) is coupled to the metal interconnect 214(1)-214(X). The metal lines arranged in the outer metallization layer 208 of the DTC 202 and coupling the second metal contacts 232(1), 232(2) to each other provide a signal routing path through the DTC 202 in an area that would normally be a portion of the KoZ 230 of the package substrate 206. In other words, in the DTC 202, the second metal contacts 232(1), 232(2) and the metal lines coupled thereto provide a signal routing bypass that allows the signal to be routed upward from the package substrate 206 and through the DTC 202 and then back downward and continue in the package substrate 206. This is in contrast to having to route this signal path laterally around the DTC 202 (in the X and Y axis directions) and outside of the KoZ 230 in the package substrate 206 for more efficient signal routing.

[0041] Figure 3 is a side view of another IC package 300, the IC package 300 including Figure 2 The package substrate 206 in the IC package 200 is used to illustrate the DTC (such as Figure 2 The IC package 300 in this example includes a DTC 202 in FIG. Figure 2DTC 202 (1)-202 (3) of DTC 202 in . Similar to Figure 2 In the DTC 202, DTC 202(1)-DTC 202(3) each has an outer metallization layer 208, and the outer metallization layer 208 includes additional metal contacts 232(1), 232(2) interconnected with each other through metal lines in the outer metallization layer 208 to provide bypass signal routing through DTC 202(1)-DTC 202(3). Figure 3 As shown, DTC 202 (1) is a DSC, which is similar to Figure 2 The IC package 200 in FIG. 1 is coupled to a first die side 204(1) of a package substrate 206. The DTC 202(2) is an LSC coupled to a second side 204(2) of the package substrate 206. The DTC 202(2) is an embedded DTC embedded within metallization layers 216(1)-216(X) of the package substrate 206. Figure 3 In each example of DTCs 202(1)-202(3) in the package substrate 206, the second metal contacts 232(1)-232(2) may then be coupled to metal interconnects 214(1)-214(X) of the package substrate 206 to continue to carry signals routed through the corresponding DTCs 202(1)-202(3) in the package substrate 206.

[0042] To illustrate additional exemplary details of a DTC including additional metal interconnects interconnected to each other by metal lines in an outer metallization layer of the DTC to provide bypass signal routing through the DTC, a Figure 4A and 4B . Figure 4A It can be used as Figure 2 The DTC 202 in the IC package 200 and Figure 3 4 is a side view of an exemplary DTC 402 that is included with any of the DTCs 202 ( 1 )- 202 ( 3 ) in the IC package 300 . Figure 4B yes Figure 4A A top view of the outer metallization layer 408 in the DTC 402 in FIG. Figure 4A and 4B An exemplary DTC 402 is described herein.

[0043] In this regard, if Figure 4A As shown, DTC 402 includes a substrate 428, which may be a semiconductor substrate, such as a silicon substrate. Substrate 428 has a first surface 404(1) and a second surface 404(2) opposite to first surface 404(1) in a vertical direction (Z-axis direction). First surface 404(1) and second surface 404(2) of substrate 428 are arranged in corresponding horizontal planes P1 and P2 (XY-axis planes). Figure 4A , the first surface 404(1) is located above the second surface 404(2) in the vertical direction (Z-axis direction). The DTC 402 includes a first capacitor 406(1) and a second capacitor 406(2) arranged in corresponding grooves 409(1), 409(2), and the corresponding grooves 409(1), 409(2) are arranged in the substrate 428. The first capacitor 406(1) includes first and second conductive layers 410(1), 410(2) separated by a dielectric material 412. The first conductive layer 410(1) and the second conductive layer 410(2) of the first capacitor 406(1) are arranged in the substrate 428 between the first surface 404(1) and the second surface 404(2) of the substrate 428. The second capacitor 406(2) includes first and second conductive layers 414(1), 414(2) separated by a dielectric material 416. The first conductive layer 414 ( 1 ) and the second conductive layer 414 ( 2 ) of the second capacitor 406 ( 2 ) are arranged in the substrate 428 between the first surface 404 ( 1 ) and the second surface 404 ( 2 ) of the substrate 428 .

[0044] Continue to refer to Figure 4A , the DTC 402 also includes an outer metallization layer 408 arranged adjacent to the first surface 404(1) of the substrate 428. The outer metallization layer 408 is arranged in a third horizontal plane P3 (X-axis and Y-axis plane) that is orthogonal to the horizontal planes P1 and P2. In this example, the outer metallization layer 408 includes an insulating layer 418 made of a dielectric material. The insulating layer 418 insulates the first capacitor 406(1) and the second capacitor 406(2). For example, the insulating layer 418 can be made of a solder resist material and can be a solder resist layer. The first metal contact 420(1) and the second metal contact 420(2) are arranged in the insulating layer 418 adjacent to the first surface 404(1) and coupled to the corresponding first conductive layer 410(1) and the second conductive layer 410(2) of the first capacitor 406(1). When the DTC 402 is coupled to another contact (such as Figure 2 and 3 When the DTC 402 is coupled to another contact (such as an external metallization layer 208 in the IC package 200, 300 in FIG. 1 ), the first metal contact 420(1) and the second metal contact 420(2) provide an external interface to the first capacitor 406(1). The third metal contact 422(1) and the fourth metal contact 422(2) are also arranged in the insulating layer 418 adjacent to the first surface 404(1) and coupled to the respective first conductive layer 414(1) and the second conductive layer 414(2) of the second capacitor 406(2). Figure 2 and 3When the third metal contact 422(1) and the fourth metal contact 422(2) are connected to the external metallization layer 208 in the IC package 200, 300 in the embodiment of the present invention, the third metal contact 422(1) and the fourth metal contact 422(2) provide an external interface to the second capacitor 406(2). An opening 424 is formed in the insulating layer 418 to expose the metal contacts 420(1), 420(2), 422(1), 422(2) to allow metal interconnects (e.g., solder balls) formed in the openings 424 to couple to the metal contacts 420(1), 420(2), 422(1), 422(2).

[0045] Continue to refer to Figure 4A In order to provide a bypass signal routing path through the DTC 402, additional metal contacts 426(1), 426(2) are also formed in the insulating layer 418. In this example, the additional metal contacts 426(1), 426(2) are not coupled to the capacitors 406(1), 406(2) (via their metal contacts 420(1), 420(2), 422(1), 422(2)). In this example, the additional metal contacts 426(1), 426(2) are formed adjacent to the outer sides 430(1), 430(2) of the substrate 428, so that the first capacitor 406(1) and the second capacitor 406(2) are arranged between the additional metal contacts 426(1), 426(2) in the substrate 428 in the horizontal direction (X-axis direction and Y-axis direction). The outer sides 430(1), 430(2) of the substrate 428 are arranged in respective vertical planes P4, P5 (Y-axis plane and Z-axis plane) that are orthogonal to the horizontal planes P1, P2 of the first surface 404(1) and the second surface 404(2) of the substrate 428. Figure 4B As shown in the top view of DTC 402 and its external metallization layer 408 in FIG. 4 , metal lines 432(2) (e.g., metal traces) are formed in insulating layer 418 that couple additional metal contacts 426(1), 426(2) together. Openings 424 are also formed in insulating layer 418 to expose additional metal contacts 426(1), 426(2) to allow metal interconnects (e.g., solder balls) formed in openings 424 to couple to additional metal contacts 426(1), 426(2). In this manner, if it is desired to provide signals routed through DTC 402, circuits can be coupled to additional metal contacts 426(1), 426(2) to provide a signal routing path from additional metal contact 426(1) to additional metal contact 426(2) that extends through insulating layer 418 of metallization layer 408 through DTC 402.

[0046] As an example, the external metallization layer 408 can be a redistribution layer (RDL). The external metallization layer 408 includes metal contacts 420(1), 420(2), 422(1), 422(2), 426(1), 426(2) formed and redistributed in different areas of the insulating layer 418 to provide a metal interface to the DTC 402 in a desired location in the horizontal plane P3 of the metallization layer 408.

[0047] Figure 4B yes Figure 4A A top view of the DTC 402 in FIG. Figure 4B As shown in , metal contacts may be formed in two (2) dimensions (X and Y dimensions) to provide an interface to the first capacitor 406 (1) and the second capacitor 406 (2) and to provide an additional bypass signal routing path through the DTC 402. In this regard, as shown in FIG. Figure 4B As shown, metal contacts are formed in a plurality of contact rows CR(1)-CR(4) in an outer metallization layer 408. Note that this example may include more or fewer contact rows. In this example, each contact row CR(1)-CR(4) has a respective metal contact 420(1)(1), 420(1)(2)-420(4)(1), 420(4)(2) ( Figure 4A In this example, each contact row CR(1)-CR(4) also has a corresponding metal contact 422(1)(1), 422(1)(2)-422(4)(2), 422(4)(2)( Figure 4A ). Each contact row CR(1)-CR(4) also has corresponding additional metal contacts 426(1)(1), 426(1)(2)-426(4)(1), 426(4)(2) to provide a bypass signal wiring path through the DTC 402. The metal contacts 420(1)(1), 420(1)(2)-420(4)(1), 420(4)(2); 422(1)(1), 422(1)(2)-422(4)(1), 422(4)(2); 426(1)(1), 426(1)(2)-426(4)(1), 426(4)(2) in each corresponding contact row CR1-CR4 are aligned along the corresponding longitudinal axis LA1-LA4 in the horizontal direction (X-axis direction).

[0048] In this example, by providing four (4) contact rows CR(1)-CR(4), four (4) bypass signal routing paths can be provided. In this regard, each contact row CR(1)-CR(4) includes a corresponding additional metal contact 426(1)(1), 426(1)(2)-426(4)(1), 426(4)(2). The metal contact 426(1)(1) in the first contact row CR1 is coupled to a first metal line 432(1) formed in the insulating layer 418, wherein the first metal line 432(1) is coupled to a metal contact 426(2)(1) in the second contact row CR2. The first metal line 432(1) extends along a longitudinal axis LA1 in a horizontal direction (X-axis direction) adjacent to the first contact row CR1. The first metal line 432(1) forms a first bypass signal routing SR1 between the metal contacts 426(1)(1), 426(2)(1) through the DTC 402. The metal contact 426(2)(1) in the second contact row CR2 is coupled to a second metal line 432(2) formed in the insulating layer 418, wherein the second metal line 432(2) is coupled to the metal contact 426(1)(1) in the first contact row CR2. The second metal line 432(2) extends between the first contact row CR1 and the second contact row CR2 along the longitudinal axis LA2 in the horizontal direction (X-axis direction). The second metal line 432(2) forms a second bypass signal wiring SR2 between the metal contacts 426(2)(1), 426(1)(2) through the DTC 402. The metal contact 426(3)(1) in the third contact row CR3 is coupled to a third metal line 432(3) formed in the insulating layer 418, wherein the third metal line 432(2) is coupled to the metal contact 426(3)(2) in the third contact row CR3. The third metal line 432(3) extends between the second contact row CR2 and the third contact row CR3 along the longitudinal axis LA3 in the horizontal direction (X-axis direction). The third metal line 432(3) forms a third bypass signal wiring SR3 between the metal contacts 426(3)(1) and 426(3)(2) through the DTC 402. The metal contact 426(4)(1) in the fourth contact row CR4 is coupled to the fourth metal line 432(4) formed in the insulating layer 418, wherein the fourth metal line 432(2) is coupled to the metal contact 426(4)(2) in the fourth contact row CR4. The fourth metal line 432(4) extends between the third contact row CR3 and the fourth contact row CR4 along the longitudinal axis LA3 in the horizontal direction (X-axis direction). The fourth metal line 432(4) forms a fourth bypass signal wiring SR4 between the metal contacts 426(4)(1) and 426(4)(2) through the DTC 402.

[0049] like Figure 4BAs shown and as discussed above, the first metal contacts 426(1)(1), 426(2)(1), 426(3)(1), 426(4)(1) in the corresponding contact rows CR1-CR4 can be coupled to the second metal contacts 426(1)(2), 426(2)(2), 426(3)(2), 426(4)(2) in the same contact row CR1-CR4 or in different contact rows CR1-CR4. For example, the metal contacts 426(3)(1), 426(4)(1) in the third contact row CR3 and the fourth contact row CR4 are coupled to the corresponding metal contacts 426(3)(2), 426(4)(2) in the same corresponding third contact row CR3 and the fourth contact row CR4. However, the metal contacts 426(1)(1), 426(2)(1) in the corresponding first contact row CR1 and the second contact row CR2 are coupled to the corresponding second metal contacts 426(2)(2) and the first metal contacts 426(1)(2) in the corresponding second contact row CR2 and the first contact row CR1.

[0050] To explain the DTC (such as Figure 2-4B Additional details of the benefits of DTC 202, 202(1)-202(3) and 402) in Figures 5A-5C , the DTC includes additional metal interconnects formed in the metallization layers and interconnected to each other by metal lines in the outer metallization layers to provide bypass signal routing through the DTC. Figure 5A 5 is a bottom view of an outer metallization layer 500 of an exemplary package substrate 502 showing metal interconnects 510, 512. Figure 5A Neutralization Figure 5B As shown in the close-up view in FIG, the metal interconnect 510 is coupled to the external interconnect 514 to provide a signal routing path extending in the horizontal direction (X-axis direction and Y-axis direction) around the two DTCs 516(1), 516(2). The DTCs 516(1), 516(2) in this example do not include additional metal interconnects formed in the metallization layer and interconnected to each other by metal lines in the external metallization layer to provide bypass signal routing through the DTCs 516(1), 516(2). This allows the signal routing paths 518(1), 518(2) provided in the metal interconnect 510 to be routed around the DTC 516(1), thereby extending the length of the signal routing paths 518(1), 518(2). However, as Figure 5C As shown in , if the DTC 520 is coupled to the package substrate 502, signal routing paths 522(1), 522(2) extending through the DTC 520 may be provided, the DTC 520 including additional metal interconnects formed in a metallization layer and interconnected to each other by metal lines in an external metallization layer to provide bypass signal routing through the DTC 520.

[0051] A manufacturing process may be used to manufacture a DTC, which includes metal lines formed in metallization layers and interconnected with each other through external metallization layers to provide a DTC (including but not limited to Figure 2-4B and additional metal interconnects for bypass signal routing of DTCs 202, 202(1)-202(3), 402, 520 in 5C. In this regard, Figure 6 is a flow chart illustrating an exemplary manufacturing process 600 for manufacturing a DTC including additional metal interconnects interconnected with each other by metal lines in an outer metallization layer of the DTC to provide a DTC including, but not limited to, Figure 2-4B and 5C DTC 202, 202 (1) - 202 (3), 402, 520) bypass signal wiring. Figure 4A and 4B DTC 402 in the discussion Figure 6 600, but note that the manufacturing process 600 is not limited to manufacturing similar Figure 4A and 4B DTC 402 in DTC.

[0052] In this regard, if Figure 6 As shown in FIG. 6 , the first step of the manufacturing process 600 in this example is to provide a substrate 428, which includes a first surface 404 (1), a first side 430 (1), 430 (2), and a second surface 404 (2) opposite to the first surface 404 (1) ( Figure 6 The next step in the manufacturing process 600 is to form a first capacitor 406(1), 406(2) in the substrate 428, the first capacitor 406(1), 406(2) including a first conductive layer 410(1), 414(1) and a second conductive layer 410(2), 414(2) ( Figure 6 The next step in the manufacturing process 600 is to form a metallization layer 408 ( Figure 6 The first step in forming the metallization layer 408 may be to form an insulating layer 418 ( Figure 6 The next step in forming the metallization layer 408 may be to form first metal contacts 420(1), 422(1) disposed in the insulating layer 418 and coupled to the first conductive layers 410(1), 414(1). Figure 6 The next step in forming the metallization layer 408 may be to form second metal contacts 420(2), 422(2) ( Figure 6The next step in forming the metallization layer 408 may be to form a third metal contact 426(1) in the insulating layer 418 and adjacent to the first surface 404(1) of the substrate 428 ( Figure 6 The next step in forming the metallization layer 408 may be to form a fourth metal contact 426(2) disposed in the insulating layer 418 and adjacent to the first surface 404(1) of the substrate 428 ( Figure 6 The next step in forming the metallization layer 408 may be to form a first metal line 432(1) ( ) coupled to the third metal contact 426(1) and the fourth metal contact 426(2) in the insulating layer 418. Figure 6 618 in FIG.

[0053] Other manufacturing processes may also be used to manufacture DTCs, which include metal lines formed in metallization layers and interconnected with each other through external metallization layers to provide a DTC (including but not limited to Figure 2-4B and additional metal interconnects for bypass signal routing of DTCs 202, 202(1)-202(3), 402, 520 in 5C. In this regard, Figures 7A-7C is a flow chart illustrating another exemplary manufacturing process 700 for manufacturing a DTC including metal lines formed in metallization layers and interconnected to each other by external metallization layers to provide a DTC including but not limited to Figure 2-4B and additional metal interconnects for bypass signal routing of DTCs 202, 202(1)-202(3), 402, 520 in 5C). Figures 8A-8H is based on Figures 7A-7C The manufacturing process 700 in FIG. 7 shows exemplary manufacturing stages 800A-800H during the manufacture of a DTC. Figure 4A and 4B DTC 402 in the discussion Figures 7A-7C The manufacturing process 700 in Figures 8A-8H 800A-800H in the manufacturing process), but note that this is not limiting.

[0054] In this regard, if Fig. 8A As shown in manufacturing stage 800A in FIG. 8 , the first step in manufacturing the DTC 402 is to provide a substrate 428 ( Fig. 7A702 in the manufacturing process 700). The substrate 428 is formed of a semiconductor material in which trenches 409 are to be formed for arranging a conductive layer in the trenches with an intermediate dielectric layer to form a capacitor. For example, the substrate 428 may be a silicon material. The substrate 428 may also be provided as a wafer 800 so that a plurality of DTCs 402 may be formed simultaneously in the wafer 800 in the manufacturing process 700 and then singulated in a later manufacturing process. Note that in this example, only one DTC 402 is illustrated as being in the wafer 800. Figures 7A-7C 428 in the manufacturing process 700, but this is not limiting. Figure 8B As shown in manufacturing stage 800B in FIG. 7 , the next step in manufacturing process 700 is to form trench 409 in substrate 428 so that a conductive layer can be arranged in trench 409 to form a capacitor ( Fig. 7A 4. (block 704 in FIG. 4A ). The trench 409 may be formed by etching into the first surface 404 ( 1 ) of the substrate 428 and down into the substrate 428 to a desired depth.

[0055] Then, if Figure 8C As shown in manufacturing stage 800C in FIG. 7 , the next step in manufacturing process 700 is to form capacitor 406 ( Fig. 7A 406). For example, to form capacitor 406, a doped conductive region 802 of a second conductive type (e.g., p+) of opposite polarity to the first conductive type may be disposed in trench 409. A second conductive layer 410(2) is disposed on doped conductive region 802 in trench 409. A dielectric material 412 is then disposed on second conductive layer 410(2) in trench 409. First conductive layer 410(1) is disposed in dielectric layer 412 in trench 409. Subsequently, as further described in Figure 8C As shown in manufacturing stage 800C in FIG. 1 , a metal layer 804 is disposed on the first surface 404 ( 1 ) in contact with the second conductive layer 410 ( 2 ) to provide a metal contact 806 , thereby facilitating providing a conductive contact interface ( Fig. 7A 806 in block 706). A passivation layer 808 is then disposed on the metal layer 804 to provide portions of the metal layer 410 that will not be exposed when providing the metal contacts 420 ( Fig. 7A 706 in FIG.

[0056] Then, if Fig.8D As shown in manufacturing stage 800D in FIG. 8 , an insulating layer 810 is disposed on the passivation layer 808 ( Figure 7B808 in block 708). In this example, the insulating layer 810 is a solder resist layer made of a material that is resistant to solder. Subsequently, a mask layer 812 is arranged on the insulating layer 408 so that a photolithographic mask can be applied to form an opening in the insulating layer 408 and the passivation layer 808 above the metal contact 806 of the capacitor 406 ( Figure 7B Then, as in block 708 of FIG. Fig. 8E As shown in manufacturing stage 800E in FIG. 8 , a photolithographic mask is applied to form an opening 813 ( 814 ) in the insulating layer 810 and the passivation layer 808 above the metal contact 806 of the capacitor 406. Figure 7B This provides access to metal contacts 806 so that electrical connection to capacitor 406 can be achieved. Figure 8F As shown in manufacturing stage 800F in FIG. 8 , the mask layer 812 is removed and metal contacts 420 , 426 are formed on the insulating layer 810 ( Figure 7B 412). Metal contacts 420 are formed in openings 412 and in contact with metal contacts 806 to provide an electrical interface to capacitor 406. Metal contacts 426 are used to provide bypass signal routing through DTC 402. For example, metal contacts 426 may be formed as redistribution metal pads in insulating layer 418, wherein redistribution metal lines 432 interconnect the metal contacts, such that outer metallization layer 408 is an RDL. This allows an RDL process to be used to form additional metal contacts 426 interconnected by metal lines 432 to form a signal bypass routing path in outer metallization layer 408 of DTC 402. Forming metal contacts 426 by an RDL process allows metal contacts 426 to be repositioned in the horizontal direction (X-axis and Y-axis directions) to provide a designed location for bypass signal lines.

[0057] Then, if Figure 8G As shown in manufacturing stage 800G in FIG. 8 , the insulating layer 418 of the outer metallization layer 408 is arranged on the metal contacts 420, 426 ( Figure 7C 414). The insulating layer 418 and the metal contacts 420, 426 are the outer metallization layer 408 of the DTC 402. Figure 8G As shown in manufacturing stage 800G in FIG. 8 , an under bump metallization (UBM) layer 816 is disposed over metal contacts 420 , 426 in preparation for external interconnects (e.g., solder balls) to be formed in contact with UBM layer 816 to provide an external interface (eg, solder balls) to capacitor 406 . Figure 7C 714 in FIG. 1 ). Then, as shown in FIG. Figure 8H As shown in manufacturing stage 800H in FIG. 8 , an outer interconnect 818 ( Figure 7C 716 in FIG.

[0058] A manufacturing process may also be used to manufacture an IC package including a DTC, the DTC including metal lines formed in metallization layers and interconnected to each other through an external metallization layer to provide a circuit through the DTC (including but not limited to Figure 2 IC package 200 and Figure 2-4B , 5C and 8A-8H) of DTC 202, 202 (1) - 202 (3), 402, 520). In this regard, Figures 9A-9C is a flow chart illustrating another exemplary manufacturing process 900 for manufacturing an IC package including a die interconnected to a DTC including metal lines formed in metallization layers and interconnected to each other through external metallization layers to provide a circuit through the DTC (including but not limited to Figure 2-4B and additional metal interconnects for bypass signal routing of DTCs 202, 202(1)-202(3), 402, 520 in 5C). Figures 10A-10F is based on Figures 9A-9C Exemplary manufacturing stages 1000A-1000F during the manufacture of an IC package of the manufacturing process 900 in FIG. Figure 2 IC packaging 200 to discuss Figures 9A-9C The manufacturing process 900 in Figures 10A-10F 00A-1000F in the manufacturing process), but note that this is not limiting.

[0059] In this regard, if Fig. 10A As shown in manufacturing stage 1000A in FIG. 1 , the first step in manufacturing IC package 200 is to provide or manufacture package substrate 206 ( Fig. 9A 902 in FIG. 1 ). Then, as shown in FIG. Fig. 10B As shown in manufacturing stage 1000B in FIG. 1 , the next step in manufacturing IC package 200 is to couple die 210 (via metal bumps 218) to outer surface 204(1) of package substrate 206 and to couple DTC 202 (via outer metal bumps 227) to outer surface 204(1) of package substrate 206. Fig. 9A 904 in FIG. 1 ). Then, as Fig. 10C As shown in manufacturing stage 1000C in FIG. 1 , the next step in manufacturing IC package 200 is to place an underfill material 1002 below die 910 and DTC 202 on outer surface 204 (1) of package substrate 206 to support die 910 and DTC 202 on package substrate 206 ( Fig. 9B 906 in FIG. 1 ). Then, as Fig. 10D As shown in manufacturing stage 1000D in FIG. 1 , the next step in manufacturing IC package 200 is to place an overmold material 1004 on die 210 and DTC 202 to protect and insulate die 210 and DTC 202 ( Fig. 9B 908 in the figure).

[0060] Then, if Fig. 10E As shown in manufacturing stage 1000E in FIG. 1 , the next step in manufacturing IC package 200 is to form external interconnects 222 in openings in external metallization layer 216 (X) of package substrate 206 to provide external interfaces (eg, for die 210 and / or DTC 202 in IC package 200) Fig. 9C 910 in FIG. 1 ). Then, as Fig.10F As shown in manufacturing stage 1000F in FIG. 1 , the next step in manufacturing IC package 200 is to singulate IC package 200 ( Fig. 9C For example, in previous manufacturing stages 1000A-1000E, IC package 200 may have been manufactured along with other IC packages on a wafer in which package substrate 206 is provided for multiple IC packages.

[0061] It should be noted that the term "external" is a relative term and is not necessarily limited to components described as being "top" or "bottom" components above or below another component. It should also be noted that components described herein as being "disposed in" a layer or packaging substrate are not limited to being completely disposed in this layer or packaging substrate. It should also be noted that the term "outside" as used herein is used to describe a component with respect to a packaging substrate that is fully or partially exposed from an outer surface of the packaging substrate.

[0062] IC packages including DTC(s) (including but not limited to Figure 2 and 10A -10F), the DTC(s) include additional metal interconnects interconnected to each other by metal lines in the outer metallization layer of the DTC to provide a DTC (including but not limited to Figure 2-4B , 5C and 8A-8H) of the DTC) and in accordance with but not limited to Figures 7A-7Cand any of the exemplary manufacturing processes in 9A-9C, and according to any aspect disclosed herein, can be provided or integrated in any processor-based device. Non-limiting examples include: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet device, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a laptop computer, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor aircraft.

[0063] In this regard, Fig.11 An example of a processor-based system 1100 is illustrated that includes circuitry that may be provided in one or more IC packages 1102(1)-1102(7). IC packages 1102(1)-1102(7) (including but not limited to Figure 2 and 10A -10F) may include DTC(s), which include additional metal interconnects interconnected to each other by metal lines in the outer metallization layer of the DTC to provide through the DTC (including but not limited to Figure 2-4B , 5C and 8A-8H) of the DTC) and in accordance with but not limited to Figures 7A-7C and any of the exemplary manufacturing processes in 9A-9C. In this example, the processor-based system 1100 may be formed as an IC 1104 in an IC package 1102 and formed as a system on a chip (SoC) 1106. The processor-based system 1100 includes a central processing unit (CPU) 1108, which includes one or more processors 1110, which may also be referred to as CPU cores or processor cores. The CPU 1108 may have a cache memory 1112 coupled to the CPU 1108 for fast access to temporarily stored data. The CPU 1108 is coupled to a system bus 1114 and may couple master devices and slave devices included in the processor-based system 1100 to each other. As is well known, the CPU 1108 communicates with these other devices by exchanging address, control, and data information on the system bus 1114. For example, the CPU 1108 may communicate a bus transaction request to a memory controller 1116, which is an example of a slave device. Although in Fig.11 Not illustrated, multiple system buses 1114 may be provided, with each system bus 1114 constituting a different fabric.

[0064] Other master devices and slave devices may be connected to the system bus 1114. Fig.11 1102(7), as an example, these devices may include a memory system 1120 including a memory controller 1116 and a memory array(s) 1118, one or more input devices 1122, one or more output devices 1124, one or more network interface devices 1126, and one or more display controllers 1128. Each of the memory system(s) 1120, one or more input devices 1122, one or more output devices 1124, one or more network interface devices 1126, and one or more display controllers 1128 may be provided in the same or different IC packages 1102(2)-1102(7). The input device(s) 1122 may include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s) 1124 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) 1126 may be any device configured to allow data exchange to and from the network 1130. The network 1130 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a Bluetooth TM Network, and the Internet. The network interface device(s) 1126 may be configured to support any type of communication protocol desired.

[0065] The CPU 1108 may also be configured to access the display controller(s) 1128 via the system bus 1114 to control information sent to the one or more displays 1132. The display controller(s) 1128 send information to be displayed to the display(s) 1132 via the one or more video processors 1134, which process the information to be displayed into a format suitable for the display(s) 1132. By way of example, the display controller(s) 1128 and the video processor(s) 1134 may be included as ICs in the same or different IC packages 1102(2), 1102(3), and in the same or different IC package 1102 that contains the CPU 1108. The display(s) 1132 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, and the like.

[0066] Fig.12An exemplary wireless communication device 1200 is illustrated that includes radio frequency (RF) components formed from one or more ICs 1202, wherein any of the ICs 1202 may be included in an IC package 1203 (including but not limited to Figure 2 and 10A -10F) in an IC package, the IC package 1203 includes a DTC, the DTC includes additional metal interconnects interconnected to each other by metal lines in an external metallization layer of the DTC to provide a DTC (including but not limited to Figure 2-4B , 5C and 8A-8H) of the DTC) and according to but not limited to Figures 7A-7C As an example, the wireless communication device 1200 may include or be provided in any of the above-mentioned devices. Fig.12 As shown in , the wireless communication device 1200 includes a transceiver 1204 and a data processor 1206. The data processor 1206 may include a memory to store data and program codes. The transceiver 1204 includes a transmitter 1208 and a receiver 1210 that support two-way communication. In general, the wireless communication device 1200 may include any number of transmitters 1208 and / or receivers 1210 for any number of communication systems and frequency bands. All or part of the transceiver 1204 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed signal ICs, etc.

[0067] The transmitter 1208 or the receiver 1210 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted between RF and baseband in multiple stages, such as from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage for the receiver 1210. In a direct conversion architecture, the signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig.12 In the wireless communication device 1200 in FIG. 1 , the transmitter 1208 and the receiver 1210 are implemented using a direct conversion architecture.

[0068] In the transmit path, the data processor 1206 processes data to be transmitted and provides I and Q analog output signals to the transmitter 1208. In the exemplary wireless communication device 1200, the data processor 1206 includes digital-to-analog converters (DACs) 1212(1), 1212(2) to convert digital signals generated by the data processor 1206 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0069] Within transmitter 1208, low pass filters 1214(1), 1214(2), respectively, filter the I and Q analog output signals to remove undesired signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 1216(1), 1216(2) respectively amplify the signals from low pass filters 1214(1), 1214(2) and provide I and Q baseband signals. Up converter 1218 upconverts the I and Q baseband signals via mixers 1220(1), 1220(2) with I and Q TX LO signals from a transmit (TX) local oscillator (LO) signal generator 1222 to provide upconverted signals 1224. Filter 1226 filters the upconverted signals 1224 to remove undesired signals caused by the upconversion and noise in the receive band. A power amplifier (PA) 1228 amplifies the up-converted signal 1224 from the filter 1226 to obtain a desired output power level and provides a transmit RF signal that is routed through a duplexer or switch 1230 and transmitted via an antenna 1232 .

[0070] In the receive path, antenna 1232 receives a signal transmitted by a base station and provides a received RF signal that is routed through a duplexer or switch 1230 and provided to a low noise amplifier (LNA) 1234. The duplexer or switch 1230 is designed to operate with a specific receive (RX) and TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1234 and filtered by filter 1236 to obtain the desired RF input signal. Down-conversion mixers 1238(1), 1238(2) mix the output of filter 1236 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1240 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1242(1), 1242(2) and further filtered by low pass filters 1244(1), 1244(2) to obtain I and Q analog input signals, which are provided to the data processor 1206. In this example, the data processor 1206 includes analog-to-digital converters (ADCs) 1246(1), 1246(2) to convert the analog input signals into digital signals to be further processed by the data processor 1206.

[0071] exist Fig.12In the wireless communication device 1200 of the embodiment of the present invention, the TX LO signal generator 1222 generates I and Q TX LO signals for up-conversion, and the RX LO signal generator 1240 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1248 receives timing information from the data processor 1206 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 1222. Similarly, the RX PLL circuit 1250 receives timing information from the data processor 1206 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 1240.

[0072] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information desired. In order to clearly explain this interchangeability, various illustrative components, frames, modules, circuits and steps have been generally described above in the form of their functionality. How such functionality is implemented depends on specific applications, design choices, and / or design constraints imposed on the overall system. The technician can implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as causing departure from the scope of the present disclosure.

[0073] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in cooperation with a DSP core, or any other such configuration).

[0074] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read and write information from / to the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0075] It is also noted that the operation steps described in any exemplary aspect of this article are described in order to provide examples and discussions. The described operations can be performed in many different orders except for the order illustrated. In addition, the operation described in a single operation step can actually be performed in multiple different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It should be understood that, as is obvious to those skilled in the art, the operation steps illustrated in the flow chart can be modified in many different ways. Those skilled in the art will also understand that any of a variety of different technologies and techniques can be used to represent information and signals. For example, the data, instructions, commands, information, signals, bits, code elements and code chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0076] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the universal principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but should be granted the broadest scope consistent with the principles and novel features disclosed herein.

[0077] Implementation examples are described in the following numbered clauses:

[0078] 1. A deep trench capacitor (DTC), comprising:

[0079] a substrate comprising a first surface and a first side;

[0080] a first capacitor disposed in the substrate, the first capacitor comprising a first conductive layer and a second conductive layer;

[0081] A metallization layer adjacent to the first surface, the metallization layer comprising:

[0082] Insulation layer;

[0083] a first metal contact disposed in the insulating layer and coupled to the first conductive layer;

[0084] a second metal contact disposed in the insulating layer and coupled to the second conductive layer;

[0085] a third metal contact disposed in the insulating layer, the third metal contact being adjacent to the first surface of the substrate;

[0086] a fourth metal contact disposed in the insulating layer, the fourth metal contact being adjacent to the first surface of the substrate; and

[0087] A first metal line is disposed in the insulating layer, the first metal line coupling the third metal contact to the fourth metal contact.

[0088] 2. The DTC of clause 1, wherein the third metal contact and the fourth metal contact are not coupled to the first capacitor.

[0089] 3. The DTC of clause 1 or 2, wherein the metallization layer further comprises:

[0090] a fifth metal contact disposed in the insulating layer, the fifth metal contact being adjacent to the first surface of the substrate;

[0091] a sixth metal contact disposed in the insulating layer, the sixth metal contact being adjacent to the first surface of the substrate; and

[0092] A second metal line is disposed in the insulating layer, the second metal line coupling the fifth metal contact to the sixth metal contact.

[0093] 4. The DTC of any one of clauses 1 to 3, wherein the metallization layer further comprises:

[0094] a first contact row comprising first and second metal contacts aligned along a first longitudinal axis; and

[0095] a second contact row comprising a fifth metal contact and a sixth metal contact aligned along a second longitudinal axis parallel to the first longitudinal axis, the fifth metal contact coupled to the first conductive layer and the sixth metal contact coupled to the second conductive layer;

[0096] The first metal line is arranged between the first contact row and the second contact row along a third longitudinal axis parallel to the first longitudinal axis.

[0097] 5. The DTC of clause 4, wherein the metallization layer further comprises:

[0098] a third contact row, the third contact row comprising a seventh metal contact and an eighth metal contact aligned along a fourth longitudinal axis parallel to the first longitudinal axis and disposed between the first longitudinal axis and the second longitudinal axis, the seventh metal contact coupled to the first conductive layer and the eighth metal contact coupled to the second conductive layer;

[0099] a ninth metal contact disposed in the insulating layer, the ninth metal contact being adjacent to the first surface of the substrate;

[0100] a tenth metal contact disposed in the insulating layer, the tenth metal contact being adjacent to the first surface of the substrate; and

[0101] A second metal line is arranged in the insulating layer, the second metal line coupling the ninth metal contact to the tenth metal contact, the second metal line being arranged between the second contact row and the third contact row along a fifth longitudinal axis parallel to the first longitudinal axis.

[0102] 6. A DTC as in clause 4 or 5, wherein:

[0103] The third metal contact is arranged in the first contact row; and

[0104] The fourth metal contact is arranged in the first contact row.

[0105] 7. A DTC as in clause 4 or 5, wherein:

[0106] The third metal contact is arranged in the first contact row; and

[0107] The fourth metal contact is arranged in the second contact row.

[0108] 8. The DTC of any one of clauses 1 to 7, wherein the metallization layer further comprises:

[0109] a fifth metal contact disposed in the insulating layer, the fifth metal contact being adjacent to the first surface of the substrate; and

[0110] A second metal line is disposed in the insulating layer, the second metal line coupling the third metal contact to the fifth metal contact.

[0111] 9. The DTC of any one of clauses 1 to 8, wherein the first capacitor is arranged between a first surface of the substrate and a second surface of the substrate opposite to the first surface.

[0112] 10. The DTC of any of clauses 1 to 9, wherein the first capacitor is arranged in the substrate between the third metal contact and the fourth metal contact.

[0113] 11. A DTC as claimed in any one of clauses 1 to 10, wherein:

[0114] The first surface of the substrate is arranged in a first plane;

[0115] The first side of the substrate is arranged in a second plane orthogonal to the first plane; and

[0116] A second surface of the substrate opposite to the first surface is arranged in a third plane parallel to the first plane.

[0117] 12. The DTC of any one of clauses 1 to 11, further comprising one or more grooves arranged in the substrate, the one or more grooves each comprising an opening in the first surface of the substrate;

[0118] Wherein a first capacitor is disposed within the one or more trenches.

[0119] 13. The DTC of any one of clauses 1 to 12, further comprising a second capacitor arranged in the substrate, the second capacitor comprising a third conductive layer and a fourth conductive layer;

[0120] Wherein the metallization layer further comprises:

[0121] a fifth metal contact disposed in the insulating layer and coupled to the third conductive layer; and

[0122] A sixth metal contact is disposed in the insulating layer and coupled to the fourth conductive layer.

[0123] 14. A DTC as claimed in any one of clauses 1 to 13, wherein:

[0124] The metallization layer includes a redistribution layer (RDL); and

[0125] The first metal line includes an RDL metal line coupling the third metal contact to the fourth metal contact.

[0126] 15. The DTC of any one of clauses 1 to 14, wherein the metallization layer comprises a solder resist layer, wherein the insulating layer comprises a solder resist material.

[0127] 16. A DTC as in any of clauses 1 to 15, wherein the DTC is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet device; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player, a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

[0128] 17. A method of manufacturing a deep trench capacitor (DTC), comprising:

[0129] providing a substrate including a first surface and a first side;

[0130] forming a first capacitor in a substrate, the first capacitor comprising a first conductive layer and a second conductive layer; and

[0131] Forming a metallization layer adjacent to the first surface of the substrate, comprising:

[0132] forming an insulating layer;

[0133] forming a first metal contact disposed in the insulating layer and coupled to the first conductive layer;

[0134] a second metal contact formed in the insulating layer and coupled to the second conductive layer;

[0135] a third metal contact formed in the insulating layer and adjacent to the first surface of the substrate;

[0136] forming a fourth metal contact disposed in the insulating layer and adjacent to the first surface of the substrate; and

[0137] A first metal line coupled to the third metal contact and the fourth metal contact is formed in the insulating layer.

[0138] 18. The method of clause 17, further comprising not coupling the third metal contact and the fourth metal contact to the first capacitor.

[0139] 19. The method of clause 17 or 18, wherein forming the metallization layer further comprises:

[0140] a fifth metal contact formed in the insulating layer and adjacent to the first surface of the substrate;

[0141] a sixth metal contact formed in the insulating layer and adjacent to the first surface of the substrate; and

[0142] A second metal line coupled to the fifth metal contact and the sixth metal contact is formed in the insulating layer.

[0143] 20. The method of any one of clauses 17 to 19, wherein the metallization layer further comprises:

[0144] A first contact row formed in the insulating layer includes:

[0145] forming a first metal contact in the insulating layer, the first metal contact coupled to the first conductive layer; and

[0146] forming a second metal contact aligned with the first metal contact in the insulating layer along the first longitudinal axis and coupled to the second conductive layer;

[0147] Forming a second contact row includes:

[0148] forming a fifth metal contact in the insulating layer coupled to the first conductive layer; and

[0149] a sixth metal contact formed in the insulating layer aligned with the first metal contact along a second longitudinal axis and coupling the second metal contact to the second conductive layer, the second longitudinal axis being parallel to the first longitudinal axis; and

[0150] Forming the first metal line further includes forming the first metal line between the first contact row and the second contact row along a third longitudinal axis parallel to the first longitudinal axis.

[0151] 21. The method of any one of clauses 17 to 20, further comprising:

[0152] forming a metal layer on the first surface of the substrate;

[0153] forming the insulating layer adjacent to the metal layer;

[0154] forming a mask layer on the insulating layer;

[0155] Openings are formed in the insulating layer to form:

[0156] a fifth metal contact coupled in the metal layer to the first conductive layer;

[0157] a sixth metal contact coupled in the metal layer to the second conductive layer;

[0158] a seventh metal contact in the metal layer and adjacent to the first surface of the substrate; and

[0159] An eighth metal contact is in the metal layer adjacent to the first surface of the substrate.

[0160] 22. The method of clause 21, wherein:

[0161] Forming the first metal contact further includes forming the first metal contact in contact with the fifth metal contact;

[0162] Forming the second metal contact further includes forming the second metal contact in contact with the sixth metal contact;

[0163] Forming the third metal contact further includes forming the third metal contact in contact with the seventh metal contact; and

[0164] Forming the fourth metal contact further includes forming the fourth metal contact in contact with the eighth metal contact.

[0165] 23. The method of any of clauses 17 to 22, wherein forming a first metal line coupled to the third metal contact and the fourth metal contact in the insulating layer comprises forming a redistribution metal line coupled to the third metal contact and the fourth metal contact in the insulating layer.

[0166] 24. An integrated circuit (IC) package, comprising:

[0167] a packaging substrate comprising a first surface and one or more first metallization layers, each first metallization layer comprising one or more metal interconnects;

[0168] a die coupled to the first surface of the package substrate; and

[0169] A deep trench capacitor (DTC) coupled to a package substrate, the DTC comprising:

[0170] a substrate comprising a third surface, a first side, and a fourth surface opposite the first surface;

[0171] a first capacitor disposed in the substrate, the first capacitor comprising a first conductive layer and a second conductive layer; and

[0172] A second metallization layer adjacent to the third surface, the second metallization layer comprising:

[0173] Insulation layer;

[0174] a first metal contact disposed in the insulating layer and coupled to the first conductive layer;

[0175] a second metal contact disposed in the insulating layer and coupled to the second conductive layer;

[0176] a third metal contact disposed in the insulating layer, the third metal contact being adjacent to a third surface of the substrate;

[0177] a fourth metal contact disposed in the insulating layer, the fourth metal contact being adjacent to a fourth surface of the substrate; and

[0178] a first metal line disposed in the insulating layer, the first metal line coupling the third metal contact to the fourth metal contact;

[0179] in:

[0180] The one or more first metallization layers further include a third metallization layer including a first metal interconnect coupled to a third metal contact; and

[0181] The third metallization layer further includes a second metal interconnect coupled to a fourth metal contact.

[0182] 25. The IC package of clause 24, wherein the first capacitor is coupled to the first surface of the package substrate.

[0183] 26. The IC package of clause 24, wherein the first capacitor is coupled to a second surface of the package substrate opposite the first surface.

[0184] 27. The IC package of clause 24, wherein the first capacitor is embedded in a package substrate.

[0185] 28. An IC package as claimed in any one of clauses 24 to 27, wherein:

[0186] The die is coupled to a second metal interconnect of the one or more metal interconnects in the package substrate;

[0187] The die is coupled to a third metal interconnect of the one or more metal interconnects in the package substrate;

[0188] The second metal interconnect is coupled to the first metal contact; and

[0189] The third metal interconnect is coupled to the second metal contact.

[0190] 29. The IC package of any of clauses 24 to 28, wherein the third metal contact and the fourth metal contact are not coupled to the first capacitor.

[0191] 30. The IC package of any one of clauses 24 to 29, wherein the second metallization layer further comprises:

[0192] a first contact row comprising first and second metal contacts aligned along a first longitudinal axis; and

[0193] a second contact row comprising a fifth metal contact and a sixth metal contact aligned along a second longitudinal axis parallel to the first longitudinal axis, the fifth metal contact coupled to the first conductive layer and the sixth metal contact coupled to the second conductive layer;

[0194] The first metal line is arranged between the first contact row and the second contact row along a third longitudinal axis parallel to the first longitudinal axis.

[0195] 31. An IC package as defined in clause 30, wherein:

[0196] The third metal contact is arranged in the first contact row; and

[0197] The fourth metal contact is arranged in the first contact row.

[0198] 32. An IC package as defined in clause 30, wherein:

[0199] The third metal contact is arranged in the first contact row; and

[0200] The fourth metal contact is arranged in the second contact row.

[0201] 33. An IC package as claimed in any one of clauses 24 to 32, wherein:

[0202] The second metallization layer includes a redistribution layer (RDL); and

[0203] The first metal line includes an RDL metal line coupling the third metal contact to the fourth metal contact.

Claims

1. A deep trench capacitor (DTC), comprising: a substrate comprising a first surface and a first side; a first capacitor disposed in the substrate, the first capacitor comprising a first conductive layer and a second conductive layer; a metallization layer adjacent to the first surface, the metallization layer comprising: Insulation layer; a first metal contact disposed in the insulating layer and coupled to the first conductive layer; a second metal contact disposed in the insulating layer and coupled to the second conductive layer; a third metal contact disposed in the insulating layer, the third metal contact being adjacent to the first surface of the substrate; a fourth metal contact disposed in the insulating layer, the fourth metal contact being adjacent to the first surface of the substrate; and A first metal line is disposed in the insulating layer, the first metal line coupling the third metal contact to the fourth metal contact.

2. The DTC of claim 1, wherein the third metal contact and the fourth metal contact are not coupled to the first capacitor.

3. The DTC of claim 1, wherein the metallization layer further comprises: a fifth metal contact disposed in the insulating layer, the fifth metal contact being adjacent to the first surface of the substrate; a sixth metal contact disposed in the insulating layer, the sixth metal contact being adjacent to the first surface of the substrate; as well as A second metal line is disposed in the insulating layer, the second metal line coupling the fifth metal contact to the sixth metal contact.

4. The DTC of claim 1, wherein the metallization layer further comprises: a first contact row, the first contact row comprising the first metal contacts and the second metal contacts aligned along a first longitudinal axis; as well as a second contact row, the second contact row comprising a fifth metal contact and a sixth metal contact aligned along a second longitudinal axis parallel to the first longitudinal axis, the fifth metal contact coupled to the first conductive layer and the sixth metal contact coupled to the second conductive layer; The first metal line is arranged between the first contact row and the second contact row along a third longitudinal axis parallel to the first longitudinal axis.

5. The DTC of claim 4, wherein the metallization layer further comprises: a third contact row, the third contact row comprising a seventh metal contact and an eighth metal contact aligned along a fourth longitudinal axis parallel to the first longitudinal axis and disposed between the first longitudinal axis and the second longitudinal axis, the seventh metal contact coupled to the first conductive layer and the eighth metal contact coupled to the second conductive layer; a ninth metal contact disposed in the insulating layer, the ninth metal contact being adjacent to the first surface of the substrate; a tenth metal contact disposed in the insulating layer, the tenth metal contact being adjacent to the first surface of the substrate; as well as A second metal line is arranged in the insulating layer, the second metal line couples the ninth metal contact to the tenth metal contact, and the second metal line is arranged between the second contact row and the third contact row along a fifth longitudinal axis parallel to the first longitudinal axis.

6. The DTC of claim 4, wherein: The third metal contacts are arranged in the first contact row; and The fourth metal contact is arranged in the first contact row.

7. The DTC of claim 4, wherein: The third metal contacts are arranged in the first contact row; and The fourth metal contact is arranged in the second contact row.

8. The DTC of claim 1, wherein the metallization layer further comprises: a fifth metal contact disposed in the insulating layer, the fifth metal contact being adjacent to the first surface of the substrate; as well as A second metal line is disposed in the insulating layer, the second metal line coupling the third metal contact to the fifth metal contact.

9. The DTC of claim 1, wherein the first capacitor is disposed between the first surface of the substrate and a second surface of the substrate opposite to the first surface.

10. The DTC of claim 1, wherein the first capacitor is disposed in the substrate between the third metal contact and the fourth metal contact.

11. The DTC of claim 1, wherein: The first surface of the substrate is arranged in a first plane; The first side of the substrate is arranged in a second plane orthogonal to the first plane; and A second surface of the substrate opposite to the first surface is arranged in a third plane parallel to the first plane.

12. The DTC of claim 1, further comprising one or more grooves disposed in the substrate, the one or more grooves each comprising an opening in the first surface of the substrate; Wherein the first capacitor is arranged within the one or more trenches.

13. The DTC of claim 1, further comprising a second capacitor disposed in the substrate, the second capacitor comprising a third conductive layer and a fourth conductive layer; The metallization layer further comprises: a fifth metal contact disposed in the insulating layer and coupled to the third conductive layer; as well as A sixth metal contact is disposed in the insulating layer and coupled to the fourth conductive layer.

14. The DTC of claim 1, wherein: The metallization layer includes a redistribution layer (RDL); and The first metal line includes an RDL metal line coupling the third metal contact to the fourth metal contact.

15. The DTC of claim 1, wherein the metallization layer comprises a solder resist layer, wherein the insulating layer comprises a solder resist material.

16. A DTC as described in claim 1, wherein the DTC is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet device; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

17. A method of manufacturing a deep trench capacitor (DTC), comprising: providing a substrate including a first surface and a first side; forming a first capacitor in the substrate, the first capacitor comprising a first conductive layer and a second conductive layer; as well as Forming a metallization layer adjacent to the first surface of the substrate, comprising: forming an insulating layer; forming a first metal contact disposed in the insulating layer and coupled to the first conductive layer; a second metal contact formed in the insulating layer and coupled to the second conductive layer; a third metal contact formed in the insulating layer and adjacent to the first surface of the substrate; forming a fourth metal contact disposed in the insulating layer and adjacent to the first surface of the substrate; and A first metal line coupled to the third metal contact and the fourth metal contact is formed in the insulating layer.

18. The method of claim 17, further comprising not coupling the third metal contact and the fourth metal contact to the first capacitor.

19. The method of claim 17, wherein forming the metallization layer further comprises: a fifth metal contact formed in the insulating layer and adjacent to the first surface of the substrate; a sixth metal contact formed in the insulating layer and adjacent the first surface of the substrate; as well as A second metal line coupled to the fifth metal contact and the sixth metal contact is formed in the insulating layer.

20. The method of claim 17, wherein the metallization layer further comprises: A first contact row formed in the insulating layer comprises: forming the first metal contact in the insulating layer, the first metal contact coupled to the first conductive layer; and forming the second metal contact, the second metal contact aligned with the first metal contact in the insulating layer along a first longitudinal axis and the second metal contact coupled to the second conductive layer; Forming a second contact row includes: forming a fifth metal contact in the insulating layer coupled to the first conductive layer; and a sixth metal contact formed in the insulating layer aligned with the first metal contact along a second longitudinal axis parallel to the first longitudinal axis and coupling the second metal contact to the second conductive layer; and Forming a first metal line further includes forming the first metal line between the first row of contacts and the second row of contacts along a third longitudinal axis parallel to the first longitudinal axis.

21. The method of claim 17, further comprising: forming a metal layer on the first surface of the substrate; forming the insulating layer adjacent to the metal layer; forming a mask layer on the insulating layer; forming openings in the insulating layer to form: a fifth metal contact in the metal layer coupled to the first conductive layer; a sixth metal contact in the metal layer coupled to the second conductive layer; a seventh metal contact in the metal layer adjacent to the first surface of the substrate; as well as An eighth metal contact is in the metal layer adjacent to the first surface of the substrate.

22. The method of claim 21, wherein: Forming the first metal contact further includes forming the first metal contact in contact with the fifth metal contact; Forming the second metal contact further includes forming the second metal contact in contact with the sixth metal contact; Forming the third metal contact further includes forming the third metal contact in contact with the seventh metal contact; and Forming the fourth metal contact further includes forming the fourth metal contact in contact with the eighth metal contact.

23. The method of claim 17, wherein forming the first metal line coupled to the third metal contact and the fourth metal contact in the insulating layer comprises: A redistribution metal line coupled to the third metal contact and the fourth metal contact is formed in the insulating layer.

24. An integrated circuit (IC) package, comprising: a packaging substrate comprising a first surface and one or more first metallization layers, each first metallization layer comprising one or more metal interconnects; a die coupled to the first surface of the package substrate; as well as A deep trench capacitor (DTC) coupled to a package substrate, the DTC comprising: a substrate comprising a third surface, a first side, and a fourth surface opposite to the first surface; a first capacitor disposed in the substrate, the first capacitor comprising a first conductive layer and a second conductive layer; and A second metallization layer adjacent to the third surface, the second metallization layer comprising: Insulation layer; a first metal contact disposed in the insulating layer and coupled to the first conductive layer; a second metal contact disposed in the insulating layer and coupled to the second conductive layer; a third metal contact disposed in the insulating layer, the third metal contact being adjacent to the third surface of the substrate; a fourth metal contact disposed in the insulating layer, the fourth metal contact being adjacent to the fourth surface of the substrate; and a first metal line disposed in the insulating layer, the first metal line coupling the third metal contact to the fourth metal contact; in: The one or more first metallization layers further include a third metallization layer including a first metal interconnect coupled to the third metal contact; and The third metallization layer further includes a second metal interconnect coupled to the fourth metal contact.

25. The IC package of claim 24, wherein the first capacitor is coupled to the first surface of the package substrate.

26. The IC package of claim 24, wherein the first capacitor is coupled to a second surface of the package substrate opposite the first surface.

27. The IC package of claim 24, wherein the first capacitor is embedded in the package substrate.

28. The IC package of claim 24, wherein: the die being coupled to a second metal interconnect of the one or more metal interconnects in the packaging substrate; the die being coupled to a third metal interconnect of the one or more metal interconnects in the packaging substrate; the second metal interconnect coupled to the first metal contact; as well as The third metal interconnect is coupled to the second metal contact.

29. The IC package of claim 24, wherein the third metal contact and the fourth metal contact are not coupled to the first capacitor.

30. The IC package of claim 24, wherein the second metallization layer further comprises: a first contact row, the first contact row comprising the first metal contacts and the second metal contacts aligned along a first longitudinal axis; as well as a second contact row, the second contact row comprising a fifth metal contact and a sixth metal contact aligned along a second longitudinal axis parallel to the first longitudinal axis, the fifth metal contact coupled to the first conductive layer and the sixth metal contact coupled to the second conductive layer; The first metal line is arranged between the first contact row and the second contact row along a third longitudinal axis parallel to the first longitudinal axis.

31. The IC package of claim 30, wherein: The third metal contacts are arranged in the first contact row; and The fourth metal contact is arranged in the first contact row.

32. The IC package of claim 30, wherein: The third metal contacts are arranged in the first contact row; and The fourth metal contact is arranged in the second contact row.

33. The IC package of claim 24, wherein: The second metallization layer comprises a redistribution layer (RDL); and The first metal line includes an RDL metal line coupling the third metal contact to the fourth metal contact.

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