Conversion circuit, electronic device and operating method

Abstract

A conversion circuit, electronic device, and operating method are disclosed. The conversion circuit includes a front-end resistor-capacitor circuit and a modulation circuit, wherein the front-end resistor-capacitor circuit is coupled to the modulation circuit. The front-end resistor-capacitor circuit includes a capacitor under test and is configured to output a current phase shift corresponding to the capacitor under test under the drive of a first differential frequency signal. The modulation circuit is configured to modulate the current phase shift and output a digital signal. This conversion circuit can achieve a wider measurement range and better suppress external common-mode interference.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a switching circuit, electronic device, and method of operation. Background Technology

[0002] In high-precision sub-nanometer mechatronic systems, the position of key components needs to be accurately located. However, due to the complexity of the working environment, it is not practical to manually adjust a component. Therefore, it is necessary to design displacement sensors with sufficiently high precision. At the same time, in order to measure displacement over a wide range, the dynamic range of the sensor is required.

[0003] In the complex environment of industrial production, many external factors need to be considered. In wireless, battery-powered applications, high-efficiency systems are required. Simultaneously, low-frequency and high-frequency interference from the external environment can couple into the readout circuit, affecting measurement accuracy. Furthermore, parasitic capacitance on the electrode plate under test also reduces precision. Therefore, it is necessary to design a high-efficiency capacitive displacement sensor chip that suppresses external interference and parasitic capacitance. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a conversion circuit, the conversion circuit comprising: a front-end resistor-capacitor circuit and a modulation circuit, the front-end resistor-capacitor circuit being coupled to the modulation circuit; the front-end resistor-capacitor circuit including a capacitor under test and configured to output a current phase shift corresponding to the capacitor under test under the drive of a first differential frequency signal; the modulation circuit being configured to modulate the current phase shift and output a digital signal.

[0005] For example, in the conversion circuit provided in at least one embodiment of this disclosure, the capacitor under test includes a first capacitor and a second capacitor; the first differential frequency signal includes a first frequency signal and a second frequency signal, the first frequency signal and the second frequency signal being out of phase; the front-end resistor-capacitor circuit further includes: a first resistor, a second resistor, a third resistor and a fourth resistor; the first end of the first resistor is electrically connected to the first electrode of the first capacitor, the first end of the second resistor is electrically connected to the first electrode of the second capacitor, the second electrode of the first capacitor and the second electrode of the second capacitor are electrically connected, the first end of the third resistor is connected to a first node between the first capacitor and the first resistor, the first end of the fourth resistor is connected to a second node between the second capacitor and the second resistor, the second end of the third resistor is connected to the first frequency signal, and the second end of the fourth resistor is connected to the second frequency signal.

[0006] For example, in a conversion circuit provided in at least one embodiment of this disclosure, the front-end resistor-capacitor circuit is coupled to the modulation circuit, including: the first input terminal of the modulation circuit is electrically connected to the second terminal of the first resistor, and the second input terminal of the modulation circuit is electrically connected to the second terminal of the second resistor, so as to couple with the front-end resistor-capacitor circuit.

[0007] For example, at least one embodiment of the present disclosure provides a conversion circuit that further includes a resistor-capacitor compensation circuit connected to the same node as the front-end resistor-capacitor circuit to be coupled to the modulation circuit, the resistor-capacitor compensation circuit being configured to be driven by a second differential frequency signal, the second differential frequency signal having the opposite polarity to the first differential frequency signal.

[0008] For example, in the conversion circuit provided in at least one embodiment of this disclosure, the resistor-capacitor compensation circuit includes: a first adjustable capacitor, a second adjustable capacitor, a first compensation resistor, a second compensation resistor, a third compensation resistor, and a fourth compensation resistor; a first terminal of the first compensation resistor is electrically connected to a first electrode of the first adjustable capacitor, a first terminal of the second compensation resistor is electrically connected to a first electrode of the second adjustable capacitor, a second electrode of the first adjustable capacitor and a second electrode of the second adjustable capacitor are electrically connected and connected to a first voltage terminal, a first terminal of the third compensation resistor is connected to a third node between the first adjustable capacitor and the first compensation resistor, a first terminal of the fourth compensation resistor is connected to a fourth node between the second adjustable capacitor and the second compensation resistor, a second terminal of the third compensation resistor is connected to a second frequency signal, and a second terminal of the fourth compensation resistor is connected to the first frequency signal.

[0009] For example, in the conversion circuit provided in at least one embodiment of this disclosure, the modulation circuit includes an integrator, an input chopper, and an output chopper; the integrator includes a first-stage integrator and a second-stage integrator; the input terminal of the first-stage integrator is connected to the front-end resistor-capacitor circuit, and the first-stage integrator and the second-stage integrator are cascaded to form a second-order integrator; the first-stage integrator includes an integrating capacitor and an amplification circuit, the amplification circuit including a first-stage operational amplifier, a second-stage operational amplifier, and a feedforward operational amplifier; the first-stage operational amplifier and the second-stage operational amplifier are cascaded, and the output terminal of the feedforward amplifier is electrically connected to the output terminal of the second-stage operational amplifier; the first terminal of the integrating capacitor is electrically connected to the input terminal of the first-stage operational amplifier, and the second terminal of the integrating capacitor is electrically connected to the output terminal of the second-stage operational amplifier; the first-stage operational amplifier adopts a common-source common-gate structure, and the drain of the first-stage operational amplifier is electrically connected to the output chopper; the input chopper is electrically connected to the first terminal of the integrating capacitor and is multiplexed as a demodulator.

[0010] For example, in the conversion circuit provided in at least one embodiment of this disclosure, the input terminal of the feedforward operational amplifier is electrically connected to the first terminal of the integrating capacitor.

[0011] For example, in the conversion circuit provided in at least one embodiment of this disclosure, the input terminal of the feedforward operational amplifier is electrically connected to the input terminal of the first-stage operational amplifier, and the modulation circuit further includes an intermediate chopper; the intermediate chopper is electrically connected to the input terminal of the feedforward operational amplifier.

[0012] For example, at least one embodiment of the present disclosure provides a conversion circuit that further includes: a comparator and a phase selector; the input terminal of the comparator is electrically connected to the output terminal of the integrator, and the output terminal of the comparator is electrically connected to the input terminal of the phase selector; the comparator is configured to sample the signal output by the integrator to obtain an output signal and feed the output signal back to the input terminal of the phase selector; the input terminal of the phase selector is electrically connected to the output terminal of the comparator, and the output terminal of the phase selector is electrically connected to the input chopper and the output chopper, respectively; the phase selector is configured to select a reference phase signal, obtain a phase error signal based on the output signal and the reference phase signal, and feed the phase error signal back to the integrator.

[0013] For example, in a conversion circuit provided in at least one embodiment of this disclosure, the second-stage integrator includes a transconductance-capacitance integrator.

[0014] For example, at least one embodiment of the present disclosure provides a conversion circuit that further includes: an on-chip reference frequency source, the on-chip reference frequency source being configured to generate a reference frequency signal and generate the first differential frequency signal based on the reference frequency signal.

[0015] At least one embodiment of this disclosure also provides an electronic device, which includes the conversion circuit provided in at least one embodiment of this disclosure.

[0016] For example, an electronic device provided in at least one embodiment of this disclosure further includes an electrode plate, a first side of which is electrically connected to the capacitor under test to be coupled to the front-end resistor-capacitor circuit.

[0017] At least one embodiment of this disclosure also provides an operation method for an electronic device, the operation method comprising: acquiring a first digital signal output by the conversion circuit when the electrode plate has no displacement change; acquiring a second digital signal output by the conversion circuit after the electrode plate has undergone displacement change; determining the amount of change of the first digital signal and the second digital signal; and determining the magnitude of the displacement change based on the mapping relationship between the amount of change and capacitance and displacement. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0019] Figure 1A This is a schematic diagram of a capacitive displacement sensor (Single-ended CDC) with a single-point detection structure;

[0020] Figure 1B This is a schematic diagram of a capacitive displacement sensor (Pseudo-differential CDC) with a dual-input structure;

[0021] Figure 2 A schematic block diagram of a conversion circuit provided for at least one embodiment of this disclosure;

[0022] Figure 3 A schematic diagram of a conversion circuit provided for at least one embodiment of this disclosure;

[0023] Figure 4 A schematic diagram of an amplifier circuit provided for at least one embodiment of this disclosure;

[0024] Figure 5 A schematic block diagram of another conversion circuit provided in at least one embodiment of this disclosure;

[0025] Figure 6 A schematic diagram of another conversion circuit provided in at least one embodiment of this disclosure;

[0026] Figure 7 A schematic diagram of a frequency source for generating a reference frequency signal, provided for at least one embodiment of this disclosure;

[0027] Figure 8 A schematic diagram of the basic timing of a frequency source circuit for generating a reference frequency signal, provided for at least one embodiment of this disclosure;

[0028] Figure 9 A schematic diagram of a chopper error amplifier and a notch filter provided for at least one embodiment of this disclosure;

[0029] Figure 10 A schematic diagram illustrating the suppression of external common-mode noise interference by a conversion circuit provided in at least one embodiment of this disclosure;

[0030] Figure 11 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure; and

[0031] Figure 12 A flowchart illustrating an operation method of an electronic device provided in at least one embodiment of this disclosure. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0034] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0035] Current sensor circuits can be broadly categorized into two technical solutions: eddy current sensors (ECS) and capacitive displacement sensors. Eddy current sensors offer good robustness and stability, and are less susceptible to interference from temperature, humidity, and electromagnetic fields. However, they also have some drawbacks. For instance, to eliminate the skin effect and achieve sufficiently high accuracy, a very high excitation frequency (>100MHz) is required, leading to significant power consumption and the adverse effects of self-heating. Capacitive displacement sensors utilize on-chip passive components as the front end, with the readout circuit processing the input signals such as voltage, current, phase, and frequency. This approach offers advantages in terms of power consumption and area, but its disadvantages include lower absolute accuracy of on-chip passive components and susceptibility to temperature variations.

[0036] Figure 1AThis is a schematic diagram of a capacitive displacement sensor (Single-ended CDC) employing a single-point detection structure. (See diagram below.) Figure 1A As shown, a single probe and the electrode plate under test constitute the capacitance Cs to be measured. The probe is a moving part of the capacitive displacement sensor and is usually connected to the object being measured. When the probe moves relative to the electrode plate under test, the distance d between them changes, resulting in a change in the capacitance value. By measuring the change in capacitance, the displacement can be calculated. However, this single-point detection structure results in the floating target node not having a defined potential. If there is a parasitic capacitance Cp between the electrode plate under test and the external environment, it will lead to external noise charge Q. N and useful signal charge Q S The capacitor under test, parasitic capacitance, and readout circuit form a loop, and the measured capacitance is the series connection of the capacitor under test and the parasitic capacitance. In addition, external electromagnetic interference will couple to the input terminal of the readout circuit, both of which will cause a decrease in sensor performance.

[0037] Figure 1B This is a schematic diagram of a pseudo-differential capacitive displacement sensor (CDC) with a dual-input structure. Figure 1B As shown, its dual-input structure solves the problems of parasitic capacitance Cp and floating detection. For suppressing external interference, it is necessary to ensure that the capacitors under test at both ends, Cs1 and Cs2, are matched. This structure reduces the influence of external interference by averaging with multiple probes, but the circuit does not have a design to suppress common-mode interference in the event of mismatch.

[0038] Currently, some solutions achieve wide-range capacitance / resistance measurement by providing multiple current values ​​to the front-end circuit. However, the drawback is that multi-range measurement reduces the linearity of the transfer curve and the signal-to-noise ratio (SNR) of the measurement.

[0039] This disclosure provides a conversion circuit, including: a front-end resistor-capacitor circuit and a modulation circuit, wherein the front-end resistor-capacitor circuit is coupled to the modulation circuit; the front-end resistor-capacitor circuit includes a capacitor under test and is configured to output a current phase shift corresponding to the capacitor under test under the drive of a first differential frequency signal; the modulation circuit is configured to modulate the current phase shift and output a digital signal.

[0040] The conversion circuit provided in at least one embodiment of this disclosure can output a wider current phase shift range by setting a front-end resistor-capacitor circuit, thereby achieving a wider measurement range; and by implementing low-frequency and high-frequency filtering through the front-end resistor-capacitor circuit and the modulation circuit respectively, it can better suppress external common-mode interference.

[0041] Figure 2 This is a schematic block diagram of a conversion circuit provided for at least one embodiment of the present disclosure.

[0042] For example, such as Figure 2 As shown, the conversion circuit 100 includes a front-end resistor-capacitor circuit 101 and a modulation circuit 102, with the front-end resistor-capacitor circuit 101 coupled to the modulation circuit 102. The front-end resistor-capacitor circuit 101 includes the capacitor under test and is configured to output the current phase shift corresponding to the capacitor under test under the drive of a first differential frequency signal; the modulation circuit 102 is configured to modulate the current phase shift and output a digital signal.

[0043] For example, a front-end resistor-capacitor circuit can generate a current phase shift (phase offset) related to the value of the capacitance under test, driven by a first differential frequency signal. For instance, the magnitude of the current phase shift is proportional to the value of the capacitance under test. In some examples, the front-end resistor-capacitor circuit may include a first-order current-mode low-pass filter composed of passive RC (resistor-capacitor) components.

[0044] For example, the modulation circuit can convert a continuously changing analog signal (such as the current phase shift mentioned above) into a discrete digital signal. The modulation circuit can be, for example, a first-order phase domain continuous-time Delta-Sigma modulator, a second-order phase domain continuous-time Delta-Sigma modulator, etc., and the embodiments disclosed herein are not limited thereto.

[0045] For example, the digital signal may include a bitstream or other forms of discrete-time signal, and this disclosure does not limit this. The digital signal output by the modulation circuit can be read and analyzed by a digital signal processing unit to measure the capacitance value under test.

[0046] For example, the first differential frequency signal includes a signal form that represents information through the difference between two frequency signals. The first differential frequency signal can be provided by external circuitry or by other modules built into the conversion circuitry, and this disclosure does not limit this.

[0047] The conversion circuit provided in the above embodiments of this disclosure suppresses external common-mode interference. External common-mode interference passes sequentially through a front-end resistor-capacitor circuit and a modulation circuit. The front-end resistor-capacitor circuit, acting as a high-pass network, can filter low-frequency interference; the modulation circuit, with its anti-aliasing function, can be considered a low-pass filter, filtering high-frequency input interference. Therefore, the conversion circuit provided in the above embodiments of this disclosure can suppress both low-frequency and high-frequency external common-mode interference.

[0048] Figure 3 This is a schematic diagram of a conversion circuit provided for at least one embodiment of the present disclosure. Figure 3 for Figure 2 A specific example of the conversion circuit shown.

[0049] For example, such as Figure 3 As shown, the conversion circuit 200 includes a front-end resistor-capacitor circuit 201 and a modulation circuit 202, with the front-end resistor-capacitor circuit 201 coupled to the modulation circuit 202. The front-end resistor-capacitor circuit 201 includes the capacitor C to be measured. S1 and C S2 And is configured as a first differential frequency signal and Under the drive, the output capacitance C under test is... S1 and C S2 The corresponding current phase shift; the modulation circuit 202 adopts a second-order phase-domain continuous-time Delta-Sigma modulator (PD-DSM) scheme, which is configured to modulate the current phase shift and output a digital signal BS.

[0050] For example, such as Figure 3 As shown, in the front-end resistor-capacitor circuit 201, the capacitor to be tested includes the first capacitor C. S1 Second capacitor C S2 The first differential frequency signal includes a first frequency signal. Second frequency signal First frequency signal Second frequency signal Inverted phase.

[0051] For example, such as Figure 3 As shown, the front-end resistor-capacitor circuit 201 also includes a first resistor R. S1 The second resistor R S2 The third resistor R S3 and the fourth resistor R S4 First resistor R S1 ~Fourth resistor R S4 Each of them includes a first terminal and a second terminal, the first capacitor C S1 Second capacitor C S2 Each of the components includes a first terminal and a second terminal. The first resistor R S1 The first terminal and the first capacitor C S1 The first electrode is electrically connected, and the second resistor R S2 The first terminal and the second capacitor C S2 The first electrode is electrically connected, and the first capacitor C is connected. S1 The second electrode and the second capacitor C S2 The second electrode is electrically connected, and the third resistor R S3 The first terminal is connected to the first capacitor C S1 and the first resistor R S1 The first node N1 and the fourth resistor R betweenS4 The first terminal is connected to the second capacitor C S2 Second resistor R S2 The second node N2 and the third resistor R S3 The second end is connected to the first frequency signal The fourth resistor R S4 The second end is connected to the second frequency signal .

[0052] For example, the values ​​of the first capacitor and the second capacitor can be equal, and the capacitance value of the capacitor under test can be equal to the value of the first capacitor or the second capacitor.

[0053] For example, the resistance values ​​of the first resistor, the second resistor, the third resistor, and the fourth resistor can be equal.

[0054] For example, the front-end resistor-capacitor circuit is a passive RC (resistor-capacitor) first-order current-mode low-pass filter. Under the drive of the first differential frequency signal, the phase shift of the output current is as shown in equation (1):

[0055]

[0056] in, Cs is the resistance value in the front-end resistor-capacitor circuit (i.e., the value of the first resistor, the second resistor, the third resistor, or the fourth resistor), and Cs is the capacitance value to be measured (i.e., the value of the first capacitor or the second capacitor).

[0057] For example, such as Figure 3 As shown, the first input terminal I1 of the modulation circuit 202 is connected to the first resistor R. S1 The second terminal (i.e., not connected to the first capacitor C) S1 One end of the connection is electrically connected to the second input terminal I2 of the modulation circuit 202 and the second resistor R. S2 The second terminal is electrically connected to couple with the front-end resistor-capacitor circuit 201, thus forming a closed loop. Under the action of negative feedback, the feedback phase of the modulation circuit is orthogonal to the phase of the input current determined by the capacitor under test, the average value of the bit stream is stable, and it corresponds one-to-one with the capacitor under test.

[0058] For example, a modulation circuit may include an integrator, an input chopper, and an output chopper. Figure 3 As shown, the modulation circuit 202 includes an integrator, an input chopper 202a, and an output chopper 202b. The integrator includes a first-stage integrator 2021 and a second-stage integrator 2022. The input terminal of the first-stage integrator 2021 is connected to the front-end resistor-capacitor circuit 201. The first-stage integrator 2021 and the second-stage integrator 2022 are cascaded to form a second-order integrator. The first-stage integrator includes an integrating capacitor C. int1 and amplifier circuits.

[0059] The modulation circuit provided in this embodiment employs a second-order feedforward scheme. The first-stage integrator is an active integrator, which allows the input point of the modulation circuit to be a low-impedance virtual point, reducing phase error. A large capacitor, such as a 64pF capacitor, is used for the integrating capacitor to reduce the output swing of the first-stage integrator and ensure the linearity of the second-stage integrator. For simplicity, the second-stage integrator can use, for example, a transconductance-capacitor (gm-C) integrator structure. The feedforward coefficient c1 and the integrating coefficient c2 are expressed as follows:

[0060]

[0061] in, For the transconductance of the second-stage integrator Sampling frequency, The capacitor is for the gm-C integrator.

[0062] For example, such as Figure 3 The modulation circuit 202 shown may also include a comparator 2023 and a phase selector 2024.

[0063] For example, such as Figure 3 As shown, the input terminal of comparator 2023 and the output terminal of integrator (i.e. Figure 3 The output of the second-stage integrator 2022 is electrically connected, and the output of the comparator 2023 is electrically connected to the input of the phase selector 2024. The comparator 2023 is configured to sample the signal output by the integrator to obtain an output signal and feed the output signal back to the input of the phase selector 2024.

[0064] For example, such as Figure 3 As shown, the input terminal of phase selector 2024 is electrically connected to the output terminal of comparator 2023, and the output terminal of phase selector 2024 is electrically connected to input chopper 202a and output chopper 202b respectively. Phase selector 2024 is configured to select a reference phase signal and obtain a phase error signal based on the output signal and the reference phase signal, so as to feed the phase error signal back to the integrator.

[0065] The specific working principle of the above modulation circuit is as follows: the chopper demodulator receives the current phase shift output from the front-end resistor-capacitor circuit, and selects the reference phase based on the phase selector. The polarity of the integrating current is controlled, and the DC component of the current integration is either positive or negative within one sampling period. Due to the large loop gain of the modulation circuit, the average integrating current is 0 when it finally stabilizes. At this point, the average phase of the phase selector output is orthogonal to the input phase shift, and the average value of the bit stream represents the current phase shift of the front-end resistor-capacitor circuit input and the value of the capacitance under test.

[0066] For example, the reference phase of the phase selector in this embodiment of the present disclosure It can be 90 degrees or 180 degrees to achieve a higher capacitance measurement range.

[0067] Figure 4 This is a schematic diagram of an amplifier circuit provided for at least one embodiment of the present disclosure. Figure 4 for Figure 3 A specific example of the amplifier circuit in the first-stage integrator of the modulation circuit shown.

[0068] For example, such as Figure 4 As shown, the amplifier circuit is located in the first-stage integrator and is a two-stage common-source cascode amplifier with feedforward compensation. It is used to provide a large loop gain for the entire loop and ensure the accuracy of the negative feedback.

[0069] For example, such as Figure 4 As shown, the amplifier circuit includes a first-stage operational amplifier gm1, a second-stage operational amplifier gm2, and a feedforward operational amplifier gm3. The first-stage operational amplifier gm1 and the second-stage operational amplifier gm2 are cascaded, and the output of the feedforward amplifier gm3 is electrically connected to the output of the second-stage operational amplifier gm2. The first-stage operational amplifier gm1 employs current multiplexing and cascode technology; terminals b and c are the input terminals of the first-stage operational amplifier gm1, and... Figure 3 Integrating capacitor C int1 The first terminal is electrically connected.

[0070] For example, such as Figure 4 As shown, the first-stage operational amplifier gm1 uses both PMOS and NMOS transistors as inputs, achieving a larger transconductance compared to a single-input transistor under the same current, which helps reduce thermal noise. For better energy efficiency, the second-stage operational amplifier gm2 and the third-stage operational amplifier gm3 employ the same current multiplexing structure.

[0071] For common-mode stability, for example, such as Figure 4 As shown, common-mode feedback circuits (CMFB1 and CMFB3) are used at the output terminals (gh) of the first-stage operational amplifier gm1 and the output terminals (ef) of the second and third-stage operational amplifiers. Since the third-stage operational amplifier gm3 uses a large current, the second common-mode feedback circuit (CMFB3) feeds back to the PMOS current source transistor of the third-stage operational amplifier gm3.

[0072] For example, such as Figure 4 As shown, the first-stage operational amplifier gm1 adopts a current-reused and common-source cascode structure. The drain (gh terminal) of the first-stage operational amplifier gm1 is electrically connected to the output chopper to reduce the impact of chopping.

[0073] In at least one embodiment of this disclosure, the input chopper can be located in different positions.

[0074] Figure 3 and Figure 4 This illustrates one configuration for the input chopper. For example, as shown... Figure 3 and Figure 4 As shown, the input terminal (bc) of the feedforward operational amplifier is connected to the integrating capacitor C. int1 The first terminal is electrically connected to the input chopper and the integrating capacitor C. int1 The first terminal is electrically connected and multiplexed as a demodulator to reduce the number of choppers in the phase domain Delta-Sigma modulator.

[0075] For example, another configuration of the input chopper is as follows: the input terminal of the feedforward operational amplifier is electrically connected to the input terminal of the first-stage operational amplifier, and the input chopper is still electrically connected to the first terminal of the integrating capacitor; in this case, the modulation circuit also includes an intermediate chopper, which is electrically connected to the input terminal of the feedforward operational amplifier.

[0076] In some examples, the conversion circuit provided in at least one embodiment of this disclosure includes a front-end resistor-capacitor circuit and a modulation circuit, and may further include a resistor-capacitor compensation circuit connected to the same node as the front-end resistor-capacitor circuit to be coupled to the modulation circuit. The resistor-capacitor compensation circuit is configured to be driven by a second differential frequency signal, the second differential frequency signal having the opposite polarity to the first differential frequency signal.

[0077] In some examples, the conversion circuit provided in at least one embodiment of this disclosure includes a front-end resistor-capacitor circuit and a modulation circuit, and may further include an on-chip reference frequency source. The on-chip reference frequency source is configured to generate a reference frequency signal and generate a first differential frequency signal based on the reference frequency signal.

[0078] Figure 5 This is a schematic block diagram of another conversion circuit provided for at least one embodiment of the present disclosure.

[0079] For example, such as Figure 5 As shown, the conversion circuit 300 provided in at least one embodiment of this disclosure includes a front-end resistor-capacitor circuit 301 and a modulation circuit 302, and may further include a resistor-capacitor compensation circuit 303 and an on-chip reference frequency source 304. For a description of the front-end resistor-capacitor circuit 301 and the modulation circuit 302, please refer to the description of the front-end resistor-capacitor circuit and the modulation circuit in the above embodiments, which will not be repeated here.

[0080] For example, such as Figure 5As shown, the resistor-capacitor compensation circuit 303 is connected to the same node as the front-end resistor-capacitor circuit 301 to be coupled to the modulation circuit 302. The resistor-capacitor compensation circuit 303 is configured to be driven by a second differential frequency signal, which has the opposite polarity to the first differential frequency signal. The on-chip reference frequency source 304 is configured to generate a reference frequency signal and generate the first differential frequency signal based on the reference frequency signal.

[0081] Figure 6 This is a schematic diagram of another conversion circuit provided in at least one embodiment of the present disclosure. Figure 6 for Figure 5 The shown is a specific example of a conversion circuit.

[0082] For example, such as Figure 6 As shown, the conversion circuit 400 provided in at least one embodiment of this disclosure includes a front-end resistor-capacitor circuit 401, a modulation circuit 402, a resistor-capacitor compensation circuit 403, and an on-chip reference frequency source 404.

[0083] For example, such as Figure 6 As shown, the on-chip reference frequency source 404 includes a resistor-capacitor oscillator (RC OSC) and a clock generation circuit. The RC OSC generates a reference frequency signal. Reference frequency signal and external reference frequency signal The output signal is processed by a clock generation circuit to obtain a reference phase signal after being multiplexed by a multiplexer (MUX). , and the first frequency signal Thus, the first differential frequency signal is obtained.

[0084] For example, such as Figure 6 As shown, the resistor-capacitor compensation circuit 403 is connected to the same node as the front-end resistor-capacitor circuit 401 to be coupled to the modulation circuit 402. The resistor-capacitor compensation circuit 403 is configured to be driven by a second differential frequency signal, which has the opposite polarity to the first differential frequency signal.

[0085] For example, such as Figure 6 As shown, the resistor-capacitor compensation circuit 403 includes a first adjustable capacitor C. T1 The second adjustable capacitor C T2 First compensation resistor R c1 Second compensation resistor R c2 The third compensation resistor R c3 and the fourth compensation resistor R c4 First compensation resistor R c1 The first terminal is connected to the first adjustable capacitor C T1 The first electrode is electrically connected, and the second compensation resistor Rc2 The first terminal and the second adjustable capacitor C T2 The first electrode is electrically connected, and the first adjustable capacitor C is connected. T1 The second electrode and the second adjustable capacitor C T2 The second electrode is electrically connected to and connected to the first voltage terminal, which can be grounded; the third compensation resistor R c3 The first terminal is connected to the first adjustable capacitor C T1 and the first compensation resistor R c1 The third node M1 and the fourth compensation resistor R c4 The first terminal is connected to the second adjustable capacitor C T2 Second compensation resistor R c2 The fourth node M2, the third compensation resistor R c3 The second end is connected to the second frequency signal The second terminal of the fourth resistor is connected to the first frequency signal. It should be noted that the first compensation resistor R in the resistor-capacitor compensation circuit 403 c1 ~Fourth compensation resistor R c4 It can be used with the first resistor R in the front-end resistor-capacitor circuit. s1 ~Fourth resistor R s1 The first and second adjustable capacitors in the resistor-capacitor compensation circuit 403 can be of the same type as the first and second capacitors in the front-end resistor-capacitor circuit.

[0086] See Figure 6 The resistor-capacitor compensation circuit is similar to the front-end resistor-capacitor circuit, including the same type of on-chip resistor and adjustable capacitor. The drive signal for the resistor-capacitor compensation circuit uses the opposite polarity to that of the front-end resistor-capacitor circuit. When parasitic capacitances exist, such as those generated by pins or packages, the front-end resistor-capacitor circuit and the resistor-capacitor compensation circuit are connected to the same node but with opposite polarities. This is achieved by adjusting the first adjustable capacitor C. T1 Second adjustable capacitor C T2 The size of the first adjustable capacitor C can completely compensate for the effects of parasitic capacitance. T1 Or the second adjustable capacitor C T2 It's not a single capacitor; it can be considered as multiple capacitors connected in parallel. However, whether they are connected in parallel depends on the switch in the branch, and the switch can be manually adjusted externally via a configuration register. Therefore, the actual first adjustable capacitor C... T1 Or the second adjustable capacitor C T2 The value is adjusted externally based on the actual size of the parasitic capacitance. Different parasitic capacitances may result in different register values.

[0087] Figure 7This is a schematic diagram of a frequency source for generating a reference frequency signal, provided for at least one embodiment of the present disclosure. Figure 6 A specific example of an RC OSC in an on-chip reference frequency source.

[0088] For example, such as Figure 7 As shown, the frequency source includes a differential RC front end, a chopper error amplifier, a notch filter, a voltage-controlled oscillator (VCO), and a clock generator.

[0089] The differential RC front end provides the initial oscillation signal, which is processed by the differential structure to generate a stable and interference-resistant signal; the chopper error amplifier detects the error between signals and eliminates offset voltage and low-frequency noise through chopping technology; the notch filter removes specific frequency noise introduced by chopping and other circuits; the voltage-controlled oscillator (VCO) adjusts the output frequency according to the control voltage provided by the chopper error amplifier to ensure that the frequency is stable at the set value; the clock generation circuit further processes the high-frequency signal output by the VCO to generate a clock signal that meets the system requirements.

[0090] Figure 8 This is a schematic diagram of the basic timing of a frequency source circuit for generating a reference frequency signal, provided for at least one embodiment of the present disclosure.

[0091] See Figure 7 and Figure 8 The frequency source circuit operates in three stages: a reset stage, a discharge stage, and an integration stage. During the reset stage, the signal... and Reset the upper plate of capacitor C0 to VDD / GND; during the charging and discharging phase, control... and The signal causes charge on C0 to flow into or out through R0; during the integration phase, the chopper error amplifier will... and The voltage difference is amplified, the notch filter flattens the output of the chopper error amplifier, and the voltage-controlled oscillator outputs a signal of the corresponding frequency according to this level. The whole system acts as a frequency-locked loop (FLL) to lock the output period of the voltage-controlled oscillator to Equation (3):

[0092]

[0093] in, It is the frequency division number. and These are the resistance and capacitance values ​​at the front end of the differential RC circuit.

[0094] Figure 9 This is a schematic diagram of a chopper error amplifier and a notch filter provided for at least one embodiment of the present disclosure.

[0095] For example, such as Figure 9 As shown, the error amplifier used in the frequency source is a high-gain cascode common-source amplifier to provide a large loop gain for the entire loop, ensuring the accuracy of the negative feedback. Simultaneously, its output impedance and output load capacitance constitute the dominant poles of the entire system, ensuring loop stability. Furthermore, chopping technology is introduced to reduce the impact of low-frequency noise and offset on the system. The input chopper (not shown in the figure) is placed at the front end of the differential RC circuit, and the output chopper is placed at... Figure 7 The location shown.

[0096] The output of the chopper error amplifier is filtered by a notch filter to restore the output signal to a DC level for controlling the subsequent voltage-controlled oscillator. At the same time, transistors D1 and D2 are added to reduce the impact of charge injection on the output DC level.

[0097] The working principle of temperature effect compensation using an on-chip reference frequency source in this embodiment includes the following: Since the on-chip resistor has a large temperature coefficient (TC), if the front-end resistor-capacitor circuit is driven only by a fixed frequency, the phase shift of the output current of the front-end resistor-capacitor circuit will drift significantly with temperature. Equation (4) is the expression for the change of resistance in the front-end resistor-capacitor circuit with temperature, where, R is at room temperature T0 S The resistance value, It is R S Temperature coefficient.

[0098]

[0099] Substituting equation (4) into equation (1), we obtain equation (5). As can be seen from equation (5), if a fixed frequency is used to drive the front-end resistor-capacitor circuit, the phase shift of the output current is not only related to the capacitor under test, but will also change with temperature.

[0100]

[0101] To address the aforementioned issues, this embodiment generates a reference frequency signal with the same temperature coefficient on-chip, and a frequency-locked-loop (FLL) circuit locks the output period of the voltage-controlled oscillator as shown in equation (3). Substituting into equation (1), the phase shift of the output current of the front-end resistor-capacitor circuit can be obtained as shown in equation (6). and They are resistors of the same type, therefore / It is a fixed value that is independent of temperature.

[0102]

[0103] Therefore, following the above method, the phase shift of the output current of the front-end resistor-capacitor circuit will not drift with temperature.

[0104] Figure 10 This diagram illustrates the suppression of external common-mode noise interference by a conversion circuit provided in at least one embodiment of this disclosure. The sampling theorem requires that aliasing will not occur in the frequency domain only when the input signal frequency is less than FS / 2 (Nyquist bandwidth). External input noise can be considered as part of the input signal. When the interference (i.e., external noise) frequency is very high, assuming it is 10Fs+1k (Fs is much greater than 1k), aliasing will occur. That is, the high-frequency signal energy of 10Fs+1k will fold into the useful signal band (within the range of 0-FS / 2), and the high-frequency energy of 10Fs+1k will appear at 1kHz. Therefore, interference suppression is necessary first. For example, as... Figure 10 As shown, its front end and the first-stage integrator exhibit a bandpass transfer function, which has a suppressive effect on high-frequency noise. Therefore, high-frequency noise is first suppressed and then folded, reducing its impact on the useful signal.

[0105] Figure 11 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0106] For example, such as Figure 11 As shown, the electronic device 600 includes a conversion circuit 601 and an electrode plate 602. This electronic device 600 can be, for example, a capacitive displacement sensor.

[0107] For example, the conversion circuit 601 can be the conversion circuit provided in any of the above embodiments.

[0108] For example, the first side of the electrode plate 602 is electrically connected to the capacitor under test to couple with the front-end resistor-capacitor circuit.

[0109] The electronic device provided in at least one embodiment of this disclosure, by setting a conversion circuit that can achieve a wider measurement range and better suppress external common-mode interference, can provide more accurate and reliable measurement results.

[0110] Figure 12 A flowchart illustrating an operation method of an electronic device provided in at least one embodiment of this disclosure. For example, such as... Figure 12 As shown, the operation method of the electronic device provided in at least one embodiment of this disclosure includes the following steps S10-S30.

[0111] Step S10: Obtain the first digital signal output by the conversion circuit when the electrode plate has no displacement change.

[0112] For example, the first digital signal corresponds to the capacitance value under test when the electrode plate has no displacement change.

[0113] Step S20: Obtain the second digital signal output by the conversion circuit after the electrode plate displacement changes.

[0114] For example, the second digital signal corresponds to the capacitance value under test when the electrode plate undergoes a displacement change.

[0115] Step S30: Determine the amount of change in the first digital signal and the second digital signal, and determine the magnitude of the displacement change based on the mapping relationship between the amount of change and the capacitance and displacement.

[0116] For example, the changes in the first and second digital signals reflect the changes in the capacitance under test. The magnitude of the displacement change can be determined based on the change in capacitance and the mapping relationship between capacitance and displacement. This mapping relationship includes the capacitance calculation formula, as shown in equation (7):

[0117]

[0118] Where S represents the area directly opposite the two electrode plates, and d represents the distance between the two electrode plates. It is a constant called the dielectric constant, which is related to the properties of the dielectric, while k is the electrostatic constant. The change in distance between the two electrode plates is the displacement.

[0119] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0120] The following points should be noted regarding this disclosure:

[0121] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0122] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0123] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0124] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A conversion circuit comprising a front-end resistance-capacitance circuit and a modulation circuit, the front-end resistance-capacitance circuit being coupled with the modulation circuit; wherein, the front-end resistance-capacitance circuit comprises a to-be-measured capacitance and is configured to output a current phase shift corresponding to the to-be-measured capacitance under the driving of a first differential frequency signal; the modulation circuit is configured to modulate the current phase shift and output a digital signal; wherein the to-be-measured capacitance comprises a first capacitance and a second capacitance; the first differential frequency signal comprises a first frequency signal and a second frequency signal, and the first frequency signal and the second frequency signal are opposite in phase; the front-end resistance-capacitance circuit further comprises a first resistance, a second resistance, a third resistance and a fourth resistance; a first end of the first resistance is electrically connected with a first pole of the first capacitance, a first end of the second resistance is electrically connected with a first pole of the second capacitance, a second pole of the first capacitance and a second pole of the second capacitance are electrically connected, a first end of the third resistance is connected to a first node between the first capacitance and the first resistance, a first end of the fourth resistance is connected to a second node between the second capacitance and the second resistance, a second end of the third resistance is connected to the first frequency signal, and a second end of the fourth resistance is connected to the second frequency signal.

2. The conversion circuit of claim 1, wherein, the front-end resistance-capacitance circuit is coupled with the modulation circuit, comprising: a first input end of the modulation circuit is electrically connected with a second end of the first resistance, and a second input end of the modulation circuit is electrically connected with a second end of the second resistance, so as to be coupled with the front-end resistance-capacitance circuit. 3.The conversion circuit of claim 1, further comprising a resistance-capacitance compensation circuit, wherein, the resistance-capacitance compensation circuit is connected to the same node as the front-end resistance-capacitance circuit to be coupled with the modulation circuit, and the resistance-capacitance compensation circuit is configured to be driven by a second differential frequency signal, the second differential frequency signal being opposite in polarity to the first differential frequency signal.

4. The conversion circuit of claim 3, wherein, the resistance-capacitance compensation circuit comprises a first adjustable capacitance, a second adjustable capacitance, a first compensation resistance, a second compensation resistance, a third compensation resistance and a fourth compensation resistance; a first end of the first compensation resistance is electrically connected with a first pole of the first adjustable capacitance, a first end of the second compensation resistance is electrically connected with a first pole of the second adjustable capacitance, a second pole of the first adjustable capacitance and a second pole of the second adjustable capacitance are electrically connected and connected to a first voltage end, a first end of the third compensation resistance is connected to a third node between the first adjustable capacitance and the first compensation resistance, a first end of the fourth compensation resistance is connected to a fourth node between the second adjustable capacitance and the second compensation resistance, a second end of the third compensation resistance is connected to the second frequency signal, and a second end of the fourth compensation resistance is connected to the first frequency signal.

5. The conversion circuit of any one of claims 1-4, wherein, the modulation circuit comprises an integrator, an input chopper and an output chopper; the integrator comprises a first-stage integrator and a second-stage integrator; wherein, An input terminal of the first-stage integrator is connected to the front-end resistor-capacitor circuit, and the first-stage integrator and the second-stage integrator are cascaded to form a second-order integrator. The first-stage integrator comprises an integration capacitor and an amplification circuit, and the amplification circuit comprises a first-stage operational amplifier, a second-stage operational amplifier and a feed-forward stage operational amplifier; wherein, The first-stage operational amplifier is cascaded with the second-stage operational amplifier, and an output terminal of the feed-forward stage amplifier is electrically connected with an output terminal of the second-stage operational amplifier; a first terminal of the integration capacitor is electrically connected with an input terminal of the first-stage operational amplifier, and a second terminal of the integration capacitor is electrically connected with an output terminal of the second-stage operational amplifier; The first-stage operational amplifier adopts a common-source common-gate structure, and a drain of the first-stage operational amplifier is electrically connected with the output chopper. The input chopper is electrically connected with the first terminal of the integration capacitor and is multiplexed as a demodulator.

6. The conversion circuit of claim 5, wherein, An input terminal of the feed-forward stage operational amplifier is electrically connected with the first terminal of the integration capacitor.

7. The conversion circuit of claim 5, wherein, An input terminal of the feed-forward stage operational amplifier is electrically connected with the input terminal of the first-stage operational amplifier, and the modulation circuit further comprises an intermediate chopper. The input terminal of the feed-forward stage operational amplifier is electrically connected with the input terminal of the first-stage operational amplifier.

8. The conversion circuit of claim 5, further comprising: A comparator and a phase selector; wherein, An input terminal of the comparator is electrically connected with an output terminal of the integrator, an output terminal of the comparator is electrically connected with an input terminal of the phase selector, and the comparator is configured to sample a signal output by the integrator to obtain an output signal and feed the output signal back to the input terminal of the phase selector; An input terminal of the phase selector is electrically connected with an output terminal of the comparator, and an output terminal of the phase selector is electrically connected with the input chopper and the output chopper respectively, and the phase selector is configured to select a reference phase signal, obtain a phase error signal based on the output signal and the reference phase signal, and feed the phase error signal back to the integrator.

9. The conversion circuit of claim 5, wherein, The second-stage integrator comprises a transconductance-capacitance integrator.

10. The conversion circuit of any one of claims 1-4, further comprising an on-chip reference frequency source, wherein, The on-chip reference frequency source is configured to generate a reference frequency signal and generate the first differential frequency signal based on the reference frequency signal.

11. An electronic device comprising the conversion circuit of any one of claims 1-10.

12. The electronic device of claim 11, further comprising an electrode plate, wherein A first side of the electrode plate is electrically connected with the to-be-measured capacitor to be coupled with the front-end resistor-capacitor circuit.

13. An operating method of the electronic device of claim 12, comprising: obtaining a first digital signal output by the conversion circuit when the electrode plate has no displacement change; obtaining a second digital signal output by the conversion circuit after the electrode plate has a displacement change; determining a change amount of the first digital signal and the second digital signal, and determining a size of the displacement change according to a mapping relationship between the change amount and a capacitance and a displacement.

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