Test sample and its preparation method

Abstract

The present invention provides a test sample and a preparation method thereof. The preparation method includes: forming an initial sample, including: forming a groove in a semiconductor substrate layer, the groove extending from one side surface of the semiconductor substrate layer into a part of the semiconductor substrate layer; forming a superlattice layer on the inner wall of the groove and the surface of the semiconductor substrate layer on the side of the groove; forming an insulating protective layer on the side surface of the superlattice layer facing away from the semiconductor substrate layer; forming a conductive layer on the side surface of the insulating protective layer facing away from the superlattice layer, and the groove on the side of the conductive layer facing away from the insulating protective layer serves as a void; cutting the initial sample by using a focused ion beam to form a test sample, and the cutting surface used for cutting passes through the void and is perpendicular to the semiconductor substrate layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a test sample and a preparation method thereof. Background Art

[0002] In the field of photonic crystal surface emitting lasers (PCSELs), by introducing a periodic two-dimensional photonic crystal micro-nano structure into the photonic crystal surface emitting laser through a secondary epitaxial technology, the light field mode can be regulated to obtain higher performance. At the same time, the core technology of PCSEL is to prepare buried air holes. Different from the material growth on a traditional two-dimensional (2D) planar substrate, growing buried air holes on the surface of an uneven three-dimensional (3D) micro-nano structure is a rather complex process. There are also many difficulties in conducting kinetic research on this process. First, the three-dimensional (3D) micro-nano structure often has crystal planes in multiple different directions. During the secondary epitaxial process, the material will grow along different crystal directions at different rates simultaneously based on different crystal planes. With too many crystal planes involved, the research difficulty increases. Second, after the secondary epitaxy, the air holes are completely buried. It is necessary to expose the air holes through methods such as cleavage or FIB (Focused Ion Beam) sample preparation before further research can be carried out on them, increasing the difficulty of sample preparation.

[0003] The heterojunction-superlattice epitaxial technology is currently the main means for studying crystal orientation and kinetics of materials. Its characteristic lies in the periodic alternating growth of epitaxial layers with different components during epitaxy. Due to the difference in relative atomic mass and contrast of epitaxial layers with different components, a transmission electron microscope (TEM) can distinguish different epitaxial layers and directionally measure the growth thickness of materials in different crystal directions, thereby studying its growth mechanism. Preparing a test sample through FIB is an important step among them. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is how to reduce the damage of the test sample, and thus provide a test sample and a preparation method thereof.

[0005] The present application provides a test sample, including: a semiconductor substrate layer, in which there is a groove extending from one side surface of the semiconductor substrate layer to a part of the semiconductor substrate layer; a superlattice layer located on the inner wall of the groove and the surface of the semiconductor substrate layer on the side of the groove; an insulating protective layer located on the side surface of the superlattice layer facing away from the semiconductor substrate layer; and a conductive layer located on the side surface of the insulating protective layer facing away from the superlattice layer. The groove on the side of the conductive layer facing away from the insulating protective layer serves as a void.

[0006] Optionally, the material of the insulating protective layer contains at least silicon oxide.

[0007] Optionally, the width dimension of the test sample in the first direction is 60 nm to 80 nm, and the first direction is parallel to the surface of the semiconductor substrate layer.

[0008] Optionally, the thickness of the insulating protective layer is 10 nm to 30 nm.

[0009] Optionally, the concentration of Al atoms in the insulating protective layer decreases, increases, or remains unchanged in the direction from the superlattice layer to the conductive layer.

[0010] This application also provides a method for preparing a test sample, including: forming an initial sample, including: forming a groove in the semiconductor substrate layer, the groove extending from one surface of the semiconductor substrate layer to a part of the semiconductor substrate layer; forming a superlattice layer on the inner wall of the groove and the surface of the semiconductor substrate layer on the side of the groove; forming an insulating protective layer on the surface of the superlattice layer facing away from the semiconductor substrate layer; forming a conductive layer on the surface of the insulating protective layer facing away from the superlattice layer, and the groove on the side of the conductive layer facing away from the insulating protective layer serves as a void; using a focused ion beam to cut the initial sample to form a test sample, and the cutting surface used for cutting passes through the void and is perpendicular to the semiconductor substrate layer.

[0011] Optionally, forming the insulating protective layer includes: forming a semiconductor film on the surface of the superlattice layer facing away from the semiconductor substrate layer, and the semiconductor film contains Al atoms; oxidizing the semiconductor film to form the insulating protective layer.

[0012] Optionally, the material of the semiconductor film includes Al y Ga (1-y) As, where y is greater than 0.95 and less than 1.

[0013] Optionally, the superlattice layer and the semiconductor film are continuously formed in the same chamber.

[0014] Optionally, the superlattice layer and the semiconductor film are continuously formed in the same chamber by using metalorganic chemical vapor deposition technology.

[0015] Optionally, in the direction from the side of the semiconductor film facing the superlattice layer to the side of the semiconductor film facing away from the superlattice layer, the concentration of Al atoms in the semiconductor film decreases, increases, or remains unchanged; the concentration of Al atoms in the insulating protective layer decreases, increases, or remains unchanged in the direction from the superlattice layer to the conductive layer.

[0016] The technical solution of the present invention has the following beneficial effects:

[0017] In the method for preparing a test sample provided by the technical solution of the present invention, during the process of forming the conductive layer and during the process of cutting the initial sample, the insulating protective layer can protect the superlattice layer and reduce the damage to the superlattice layer.

[0018] Furthermore, forming the insulating protective layer includes: forming a semiconductor film on a surface of the superlattice layer facing away from the semiconductor substrate layer, where the semiconductor film contains Al atoms; oxidizing the semiconductor film to form the insulating protective layer. Since the semiconductor film contains Al atoms, due to the oxygen affinity of Al, the semiconductor film is easily oxidized to form the insulating protective layer, realizing in-situ growth control.

[0019] Furthermore, the superlattice layer and the semiconductor film can be continuously formed in the same chamber. This can reduce the introduction of other impurity atoms at the interface between the superlattice layer and the semiconductor film, improve the sample preparation efficiency, and ensure data in-situ. Secondly, when the superlattice layer and the semiconductor film are continuously formed in the same chamber, the damage to the superlattice layer is extremely small. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a flowchart of the method for preparing a test sample according to an embodiment of the present application;

[0022] Figures 2 to 7 It is a schematic structural diagram of the preparation process of a test sample according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] On this basis, the embodiments of the present application provide a test sample and a method for preparing the same, which reduce the damage to the test sample.

[0024] The following will clearly and completely describe the technical solutions of the present invention with reference to the drawings. Obviously, the described embodiments are some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0025] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0026] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] An embodiment of the present invention provides a method for preparing a test sample. Refer to Figure 1 , including:

[0028] Step S1: Form an initial sample, including: forming a groove in the semiconductor substrate layer, the groove extending from one side surface of the semiconductor substrate layer to a part of the semiconductor substrate layer; forming a superlattice layer on the inner wall of the groove and the surface of the semiconductor substrate layer on the side of the groove; forming an insulating protective layer on the side surface of the superlattice layer facing away from the semiconductor substrate layer; forming a conductive layer on the side surface of the insulating protective layer facing away from the superlattice layer, and the groove on the side of the conductive layer facing away from the insulating protective layer serves as a void.

[0029] Step S2: Cut the initial sample with a focused ion beam to form a test sample. The cutting surface used for cutting passes through the void and is perpendicular to the semiconductor substrate layer.

[0030] In this embodiment, during the process of forming the conductive layer and during the process of cutting the initial sample, the insulating protective layer can protect the superlattice layer and reduce the damage to the superlattice layer.

[0031] In this embodiment, forming the insulating protective layer includes: forming a semiconductor film on the side surface of the superlattice layer facing away from the semiconductor substrate layer, the semiconductor film containing Al atoms; oxidizing the semiconductor film to form the insulating protective layer. Since the semiconductor film contains Al atoms, due to the oxygen affinity of Al, the semiconductor film is easily oxidized to form an insulating protective layer, realizing in-situ growth control.

[0032] The following will introduce the preparation process of the test sample in detail with reference to Figures 2 to 7 Form an initial sample.

[0033] Refer to Figures 2 to 6 , and form an initial sample.

[0034] Reference Figure 2 A groove 110 is formed in the semiconductor substrate layer 100, and the groove 110 extends from one side surface of the semiconductor substrate layer 100 into a part of the semiconductor substrate layer 100.

[0035] The material of the semiconductor substrate layer 100 can be a group III-V compound semiconductor, a silicon wafer or a sapphire. The group III-V compound semiconductor includes but is not limited to GaAs, GaSb, GaN or InP.

[0036] One side surface of the semiconductor substrate layer 100 has a three-dimensional concavo-convex structure, and the three-dimensional concavo-convex structure includes a plurality of protrusions and grooves 110 corresponding to the protrusions. The size of the protrusions is in the micron or nanometer scale. The size of the grooves 110 is in the micron or nanometer scale.

[0037] Reference Figure 3 A superlattice layer 120 is formed on the inner wall of the groove 110 and the surface of the semiconductor substrate layer 100 on the side of the groove 110.

[0038] In one embodiment, the process of forming the superlattice layer 120 includes metalorganic chemical vapor deposition.

[0039] In one embodiment, forming the superlattice layer 120 includes: forming an alternately stacked first semiconductor layer 121 and second semiconductor layer 122 on the inner wall of the groove 110 and the surface of the semiconductor substrate layer 100 on the side of the groove 110. The material of the second semiconductor layer 122 is different from the material of the first semiconductor layer 121.

[0040] In one embodiment, the material of the first semiconductor layer 121 includes any one of AlAs, GaAs and AlGaAs. The material of the second semiconductor layer 122 includes any one of AlAs, GaAs and AlGaAs.

[0041] If the thicknesses of the first semiconductor layer 121 and the second semiconductor layer 122 are too thick, the number of periods of the first semiconductor layer 121 and the second semiconductor layer 122 is restricted, which brings difficulties to the kinetic research of the superlattice layer 120; if the thicknesses of the first semiconductor layer 121 and the second semiconductor layer 122 are too thin, it is difficult to measure the thicknesses of the first semiconductor layer 121 and the second semiconductor layer 122, and it is also difficult to distinguish the first semiconductor layer 121 and the second semiconductor layer 122 under a transmission electron microscope. If the thickness difference between the first semiconductor layer 121 and the second semiconductor layer 122 is too small or too large, it will affect the first semiconductor layer 121 and the second semiconductor layer 122 under a transmission electron microscope and affect the difficulty of measuring the thicknesses of the first semiconductor layer 121 and the second semiconductor layer 122. Therefore, in one embodiment, the thickness of the first semiconductor layer 121 is 8 nm - 15 nm, such as 8 nm, 10 nm, 12 nm or 15 nm; the thickness of the second semiconductor layer 122 is 1 nm - 5 nm, such as 1 nm, 3 nm or 5 nm.

[0042] Reference Figure 4 and Figure 5 , an insulating protective layer 131 is formed on the surface of the superlattice layer 120 facing away from the semiconductor substrate layer 100.

[0043] Reference Figure 4 , a semiconductor film 130 is formed on the surface of the superlattice layer 120 facing away from the semiconductor substrate layer 100, and the semiconductor film 130 contains Al atoms.

[0044] In one embodiment, the material of the semiconductor film 130 includes Al y Ga (1-y) As, where y is greater than 0.95 and less than 1. Using Al y Ga (1-y) As with a high Al component is beneficial to the subsequent oxidation to form a dense composite alumina film, and the composite alumina film is the subsequent insulating protective layer. The oxidation degree of the insulating protective layer and the thickness difference of the insulating protective layer can be observed under a transmission electron microscope in different crystal orientations, and the kinetic process can be restored.

[0045] In one embodiment, the process of forming the semiconductor film 130 includes a metalorganic chemical vapor deposition process. Forming the semiconductor film 130 by the metalorganic chemical vapor deposition process causes minimal damage to the surface of the superlattice layer 120.

[0046] In one embodiment, the superlattice layer 120 and the semiconductor film 130 are continuously formed in the same chamber. This can reduce the introduction of other impurity atoms at the interface between the superlattice layer 120 and the semiconductor film 130, improve the sample preparation efficiency, and ensure data in-situ.

[0047] In one embodiment, a metal-organic chemical vapor deposition process is used to continuously form a superlattice layer 120 and a semiconductor film 130 in the same chamber, with minimal damage to the superlattice layer 120.

[0048] In one embodiment, the thickness of the semiconductor film 130 is 10 nm - 30 nm. If the thickness of the semiconductor film 130 is too thin, it is not sufficient to oxidize to obtain an adequate insulating protective layer, and the protective effect of the insulating protective layer 131 on the superlattice layer 120 is weakened; if the thickness of the semiconductor film 130 is too thick, it is not conducive to forming sufficient voids, and it is difficult to determine the position of cutting the initial sample through the light transmittance of the voids, increasing the sample preparation difficulty.

[0049] In one embodiment, the growth temperature used in the process of forming the semiconductor film 130 is 680 °C - 700 °C.

[0050] In one embodiment, the growth rate of the semiconductor film 130 is 4 Å - 8 Å / s.

[0051] Reference Figure 5 , the semiconductor film 130 is oxidized to form an insulating protective layer 131 on the semiconductor film 130.

[0052] In one embodiment, the process of oxidizing the semiconductor film 130 is a wet oxidation process. The wet oxidation process provides a high-temperature and high-humidity water vapor environment, which improves the density of the formed insulating protective layer 131. The protective effect of the insulating protective layer 131 on the superlattice layer 120 is improved.

[0053] In one embodiment, the oxidation time of the wet oxidation process is 6 h - 24 h.

[0054] In other embodiments, the process of oxidizing the semiconductor film 130 is a dry oxidation process.

[0055] In one embodiment, the insulating protective layer 131 contains at least silicon oxide. Silicon oxide has a relatively high hardness, and the insulating protective layer 131 has better support performance. Subsequently, it is beneficial to form a thinner test sample, which is convenient for using a transmission electron microscope to photograph the structure of the test sample.

[0056] In one embodiment, in the direction from the side of the semiconductor film 130 facing the superlattice layer 120 to the side of the semiconductor film 130 facing away from the superlattice layer 120, the concentration of Al atoms in the semiconductor film 130 decreases or increases. The degree of oxidation of the semiconductor film 130 is different in different crystal orientations, and the thickness of the insulating protective layer 131 is different in different crystal orientations. The concentration difference of Al atoms in the semiconductor film 130 can increase the thickness difference of the insulating protective layer 131 in different crystal orientations, and the kinetic process can be further restored by observing the gradient characteristics of the insulating protective layer 131 under a transmission electron microscope. Correspondingly, in the direction from the side of the insulating protective layer 131 facing the superlattice layer 120 to the side of the insulating protective layer 131 facing away from the superlattice layer 120, the concentration of Al atoms in the insulating protective layer 131 decreases or increases.

[0057] In one embodiment, in the direction from the side of the semiconductor film 130 facing the superlattice layer 120 to the side of the semiconductor film 130 facing away from the superlattice layer 120, the concentration of Al atoms in the semiconductor film 130 remains unchanged; in the direction from the side of the insulating protective layer 131 facing the superlattice layer 120 to the side of the insulating protective layer 131 facing away from the superlattice layer 120, the concentration of Al atoms in the insulating protective layer 131 remains unchanged.

[0058] In one embodiment, when the material of the semiconductor film 130 includes Al y Ga (1-y) As, the material of the insulating protective layer 131 is a mixture of Al 2 O 3 、Ga 2 O 3 and As 2 O 5 mixture.

[0059] In one embodiment, the insulating protective layer 131 includes a first sub-insulating protective layer and a second sub-insulating protective layer. The second sub-insulating protective layer is located on the side of the first sub-insulating protective layer facing away from the superlattice layer 120. The material of the second sub-insulating protective layer is a mixture of Al 2 O 3 、Ga 2 O 3 and As 2 O 5 mixture, and the material of the first sub-insulating protective layer is Al x Ga 1-x As y O 1-y 。

[0060] Reference Figure 6, a conductive layer 140 is formed on the surface of the insulating protective layer 131 facing away from the superlattice layer 120, and the groove on the side of the conductive layer 140 facing away from the insulating protective layer 131 serves as the void 110a.

[0061] The process of forming the conductive layer 140 includes a sputtering process.

[0062] During the process of forming the conductive layer 140 by using the sputtering process, the insulating protective layer 131 can protect the superlattice layer 120, avoid ion bombardment of the superlattice layer 120 by the sputtering process, and reduce the damage to the superlattice layer 120.

[0063] In one embodiment, the concentration of Al atoms in the insulating protective layer 131 decreases or increases in the direction from the superlattice layer to the conductive layer. In another embodiment, the concentration of Al atoms in the insulating protective layer 131 remains unchanged in the direction from the superlattice layer to the conductive layer.

[0064] Reference Figure 7 , a focused ion beam 150 is used to cut the initial sample to form a test sample, and the cutting surface used for cutting passes through the void 110a and is perpendicular to the semiconductor substrate layer 100.

[0065] The focused ion beam includes, for example, a Ga ion beam.

[0066] The insulating protective layer 131 can reduce the influence of the focused ion beam to form a high current in the superlattice layer.

[0067] During the process of using the focused ion beam 150 to cut the initial sample, the insulating protective layer 131 can protect the superlattice layer 120.

[0068] Since the insulating protective layer 131 can protect the superlattice layer 120, the success rate of preparing the test sample is improved.

[0069] The test sample is used for testing under a transmission electron microscope. According to the different conductivities of the first semiconductor layer 121 and the second semiconductor layer 122, the first semiconductor layer 121 and the second semiconductor layer 122 can be clearly distinguished by using a transmission electron microscope.

[0070] This application provides a test sample, including: a semiconductor substrate layer, having a groove in the semiconductor substrate layer, the groove extending from one surface of the semiconductor substrate layer to a part of the semiconductor substrate layer; a superlattice layer, located on the inner wall of the groove and the surface of the semiconductor substrate layer on the side of the groove; an insulating protective layer, located on the surface of the superlattice layer facing away from the semiconductor substrate layer; a conductive layer, located on the surface of the insulating protective layer facing away from the superlattice layer, and the groove on the side of the conductive layer facing away from the insulating protective layer serves as a void.

[0071] Optionally, the material of the insulating protective layer contains at least silicon oxide.

[0072] Optionally, the width dimension of the test sample in the first direction is 60 nm to 80 nm, and the first direction is parallel to the surface of the semiconductor substrate layer.

[0073] Optionally, the thickness of the insulating protective layer is 10 nm - 30 nm, such as 10 nm, 20 nm or 30 nm.

[0074] Optionally, the concentration of Al atoms in the insulating protective layer decreases, increases or remains unchanged in the direction from the superlattice layer to the conductive layer.

[0075] Obviously, the above embodiments are merely examples for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. The obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for preparing a test sample, characterized in that: include: Forming an initial sample, including: forming a groove in a semiconductor substrate layer, wherein the groove extends from a side surface of the semiconductor substrate layer to a part of the semiconductor substrate layer; forming a superlattice layer, including: forming a first semiconductor layer and a second semiconductor layer alternately stacked and having different materials on the inner wall of the groove and the surface of the semiconductor substrate layer on the side of the groove; forming an insulating protection layer on a side surface of the superlattice layer away from the semiconductor substrate layer, including: forming a semiconductor film on a side surface of the superlattice layer away from the semiconductor substrate layer, wherein the semiconductor film has Al atoms and has a thickness of 10nm-30nm, and oxidizing the semiconductor film so that the semiconductor film forms the insulating protection layer; forming a conductive layer on a side surface of the insulating protection layer away from the superlattice layer, wherein the groove on the side of the conductive layer away from the insulating protection layer serves as a gap; Using a focused ion beam to cut the initial sample to form a test sample, wherein the cutting surface used in the cutting passes through the gap and is perpendicular to the semiconductor substrate layer; wherein the superlattice layer and the semiconductor film are continuously formed in the same chamber; The test sample is used to distinguish the first semiconductor layer and the second semiconductor layer under a transmission electron microscope; the width of the test sample in a first direction is 60nm~80nm, and the first direction is parallel to the surface of the semiconductor substrate layer.

2. The method for preparing a test sample according to claim 1, characterized in that: The material of the semiconductor film includes Al y Ga (1-y) As, y is greater than 0.95 and less than 1.

3. The method for preparing a test sample according to claim 1, characterized in that: The superlattice layer and the semiconductor film are continuously formed in the same chamber by adopting a metal organic chemical vapor deposition process.

4. The method for preparing a test sample according to claim 1, characterized in that: In a direction from the semiconductor film toward the superlattice layer to the semiconductor film away from the superlattice layer, the concentration of Al atoms in the semiconductor film decreases, increases, or remains unchanged, and the concentration of Al atoms in the insulating protection layer decreases, increases, or remains unchanged from the superlattice layer to the conductive layer.

5. The method for preparing a test sample according to claim 1, characterized in that: The insulating protection layer contains at least silicon oxide.

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