A circuit arrangement for a photoacoustic system

Abstract

The application discloses a kind of circuit devices for photoacoustic system, belong to laser gas detection photoelectric instrument technical field.For the poor portability of phase-locked amplifier and function signal generator, and the problem that preamplifier transimpedance amplifier is difficult to effectively amplify quartz tuning fork signal, a circuit device suitable for photoacoustic spectroscopy system is designed based on STM32L431RCT6.The circuit mainly includes: main control chip circuit, power supply circuit of digital module and part of analog module, system clock and frequency division circuit, reference clock generation circuit, quartz tuning fork signal amplifier and power supply circuit, composite signal generator circuit, ultra-low noise reference voltage generation circuit, signal conditioning circuit and ADC acquisition circuit, analog switch circuit;The device integrates phase-locked amplifier, function signal generator and quartz tuning fork signal amplifier, and realizes miniaturization and low power consumption.At the same time, an anti-interference shield is designed for the independently operated quartz tuning fork signal amplifier, so that its anti-interference ability is improved.

Description

Technical Field

[0001] This invention belongs to the field of laser gas detection optoelectronic instrument technology, specifically relating to a circuit device for a photoacoustic system. Background Technology

[0002] Technological advancements, while accelerating social development, have also altered the composition of the atmosphere, impacting human health and the environment. Therefore, accurate and rapid detection of pollutants has become a research hotspot, and real-time measurement of atmospheric pollutant concentrations is crucial for assessing environmental quality. Among numerous gas detection technologies, photoacoustic spectroscopy, with its high selectivity, high detection accuracy, long lifespan, and low maintenance costs, has long been a focus of research, from its principles to its applications. Quartz-enhanced photoacoustic spectroscopy (QEPAS) is a new development in traditional photoacoustic spectroscopy. This technology not only retains the advantages of photoacoustic spectroscopy, such as zero background, no wavelength selectivity, and a response signal proportional to the excitation light power, but also possesses characteristics such as high quality factor, narrow response bandwidth, immunity to environmental noise, compact structure, and low cost. Therefore, this technology has received widespread attention since its inception.

[0003] Currently, laser gas detection systems based on quartz-enhanced photoacoustic spectroscopy are mostly constructed from discrete lock-in amplifiers, function generators, preamplifier transimpedance amplifiers, quartz tuning fork detectors, and laser temperature and flow control instruments. The entire system is bulky, heavy, and consumes a lot of power, making it inconvenient to carry for outdoor detection. This completely overshadows the advantages of the quartz tuning fork detector itself: small size and zero power consumption. Furthermore, because the signal from the quartz tuning fork is extremely small, the feedback resistor of a typical transimpedance amplifier needs to be above MΩ, meaning a very high current-to-voltage gain is required. However, commonly used transimpedance amplifiers often struggle to simultaneously achieve wide bandwidth and high current-to-voltage gain, resulting in less than ideal amplification of the high-frequency, extremely small-amplitude quartz tuning fork signal. Additionally, the large offset voltage and bias current of most high-gain-bandwidth product operational amplifiers can cause the quartz tuning fork signal to be submerged in noise, preventing proper signal amplification. Moreover, transimpedance amplifier circuit boards are mostly used only on laboratory benches; in outdoor environments, especially with strong electromagnetic interference, the amplification of extremely small signals will also be affected. Summary of the Invention

[0004] To address the issues of poor portability of lock-in amplifiers and function generators, and the difficulty of effectively amplifying quartz tuning fork signals using preamplifiers, this invention provides a circuit device for photoacoustic systems.

[0005] To achieve the above objectives, the present invention employs the following technical solutions:

[0006] A circuit device for a photoacoustic system, the circuit device comprising a lock-in amplifier module, a composite signal generator module, a quartz tuning fork signal amplifier module, a signal channel conversion module, and a host computer;

[0007] The lock-in amplifier module includes a main control chip circuit, a power supply circuit for digital modules and some analog modules, a system clock and frequency division circuit, a reference clock generation circuit, an ultra-low noise reference voltage generation circuit, a signal conditioning circuit, and an ADC acquisition circuit.

[0008] The composite signal generator module includes a main control chip circuit, a power supply circuit for digital modules and some analog modules, a system clock and frequency division circuit, a reference clock generation circuit, and a composite signal generator circuit.

[0009] The quartz tuning fork signal amplifier module includes a quartz tuning fork signal amplifier and a power supply circuit.

[0010] The signal channel conversion module includes analog switching circuitry.

[0011] The main control chip circuit consists of an STM32L431RCT6 low-power microcontroller and peripheral circuits; the STM32L431RCT6 low-power microcontroller includes a timer.

[0012] The power supply circuit for the digital module and some analog modules is a low-dropout linear regulator (LDO), which features low output ripple, high power supply rejection ratio and low noise, ensuring the stability and accuracy of the circuit.

[0013] The system clock and frequency divider circuit uses a high-frequency active crystal oscillator to generate the system clock. This clock not only serves as the reference for the clock generation circuit but also generates a lower-frequency clock signal through the frequency divider circuit for use by the main control chip. Furthermore, impedance matching is implemented along the transmission path of the high-frequency clock signal to prevent signal distortion and performance degradation during transmission.

[0014] The reference clock generation circuit consists of a direct frequency synthesizer (DDS), a bandpass filter, and a comparator.

[0015] The quartz tuning fork signal amplifier and power supply circuit are quartz tuning fork signal amplifier and power supply circuit; the quartz tuning fork signal amplifier is a transimpedance amplifier, but a MOS transistor is added in the feedback loop near the input end; the power supply circuit is an ultra-high power supply rejection ratio, ultra-low noise LDO power supply chip, providing positive and negative voltages.

[0016] The composite signal generator circuit consists of a high-precision external DAC and a follower;

[0017] The ultra-low noise reference voltage generation circuit consists of a reference voltage source and a low-pass filter with a very low cutoff frequency. The ultra-low noise reference voltage generated by the reference voltage source provides a voltage reference for the composite signal generator circuit, signal conditioning circuit, and ADC acquisition circuit. The reference voltage source can generate an ultra-low noise reference voltage, and the noise can be further reduced by the low-pass filter with a very low cutoff frequency. However, in actual circuit design, the use of high-capacitance capacitors may lead to instability of the operational amplifier or even self-oscillation. To solve this potential stability problem, a combination of isolation resistors and compensation capacitors is added to the circuit. This design can enhance the stability of the system.

[0018] The signal conditioning circuit and ADC acquisition circuit are divided into two parts: the signal conditioning circuit and the ADC acquisition circuit. The signal conditioning circuit uses an instrumentation amplifier to amplify the small voltage signal to be measured by a suitable factor and adds a suitable DC bias to the voltage signal to be measured to prevent it from exceeding the measurement range of the ADC. The ADC acquisition circuit is a high-precision, high-speed pseudo-differential input ADC. This ADC uses the SPI protocol to transmit data and has a fast communication rate.

[0019] An anti-interference shield was designed for the quartz tuning fork signal amplifier to ensure its stable operation in complex electromagnetic environments.

[0020] The signal conditioning circuit is designed with a second-order active bandpass filter to improve the signal-to-noise ratio of the signal under test.

[0021] The composite signal generator module is equipped with a fourth-order low-pass filter. The sinusoidal signal generated by the main control chip is input into this filter to remove high-frequency components. After this processing, a sinusoidal signal with undistorted waveform is finally obtained.

[0022] The analog switch circuit has two analog switches. The first analog switch is responsible for selecting the output channel of the composite signal generator, and is used to switch the output signal waveform and output port. The second analog switch is responsible for selecting the input channel of the signal conditioning circuit, and is used to switch the input port of the signal conditioning circuit and select the signal at one end of the quartz tuning fork interface.

[0023] The output signal waveform includes the composite signal generated by the composite signal generator circuit and the square wave signal; the output port is divided into a direction facing the external interface and an interface direction connected to one end of the quartz tuning fork; when the output port points to the external interface, the signal is used to modulate the system, and then the second harmonic is demodulated by the lock-in amplifier, at which time the system is in the working mode of measuring gas concentration; when the output port is connected to one end of the quartz tuning fork, the lock-in amplifier demodulates the first harmonic, and the system switches to the working mode of detecting the resonant frequency of the quartz tuning fork;

[0024] The signal conditioning circuit has two input port options: one is an external interface, which directly receives photoacoustic signals in the form of voltage; the other is the output signal of a quartz tuning fork signal amplifier, which is specifically used to demodulate the photoacoustic signals of the system.

[0025] The signal selection of the quartz tuning fork interface is divided into two cases: one is grounding, in which one end of the quartz tuning fork interface is grounded before demodulating the quartz tuning fork signal; the other is connecting to the output signal of the composite signal generator, in which one end of the quartz tuning fork interface is connected to the output signal of the composite signal generator before detecting the resonant frequency of the quartz tuning fork.

[0026] The clock signal generation process in the reference clock generation circuit is as follows: a direct frequency synthesizer generates a sine wave signal with a specific frequency, the sine wave signal is then filtered by a bandpass filter, and an appropriate DC bias is added through a pull-up resistor; subsequently, the sine wave signal is sent to a comparator, which converts the sine wave signal into a square wave signal, which is used as the reference clock signal A.

[0027] Reference clock signal A generates two PWM waves via the timer of the main control chip: clock B and clock C, which control the ADC acquisition rate and the DAC to generate waveforms at specific frequencies, respectively. The coordinated operation of clock B and clock C ensures that the ADC acquisition signal has no phase shift, facilitating subsequent data processing and demodulation to obtain the second harmonic signal. The data acquired by the ADC is sent to the main control chip via the SPI interface. The main control chip multiplies the received data with its internal sine and cosine tables and then accumulates the results to obtain two data sets, denoted as data A and data B. After a period of accumulation, a set of data A and data B is formed. This set is then processed using a multiple moving average filtering algorithm. Finally, the square root of the sum of the squares of data A and data B is calculated to obtain a set of data C. Data C is the signal amplitude demodulated by the lock-in amplifier, i.e., the second harmonic amplitude of the photoacoustic signal. Data C is then sent to the host computer via the serial port.

[0028] The composite signal generation process in the composite signal generator circuit is as follows: the square wave signal generated by the main control chip is directly changed in terms of its high and low levels by modifying the contents of the square wave table, and then connected to a follower to improve its load capacity, thus directly obtaining the square wave signal required by the system; the sine signal generated by the main control chip is filtered and used as the reference signal of the external DAC, and a new sine signal with controllable amplitude is obtained by writing the external DAC parameters, which serves as the modulation signal required by the system.

[0029] Meanwhile, the main control chip periodically sends sawtooth wave table data to the external DAC, allowing the external DAC to generate a low-frequency sawtooth wave signal with controllable amplitude and frequency. This signal serves as the scanning signal required by the system. The modulation signal and the scanning signal are combined to generate a composite signal.

[0030] The method for combining the modulation signal and the scanning signal is as follows: First, the DC bias in the modulation signal is filtered out using a capacitor of appropriate size. Then, the required DC bias is increased using a pull-up resistor, with the pull-up level sourced from the low-frequency scanning signal. In this way, the low-frequency scanning signal and the modulation signal without DC bias can be simply added together, achieving a function similar to an adder, ultimately generating a composite signal.

[0031] In summary, the composite signal generator can generate signals with the following characteristics: 1. Square wave signals with controllable frequency and high / low levels, used for intensity modulation of the system; 2. Composite signals composed of low-frequency sawtooth wave signals with controllable frequency and high / low levels and high-frequency sine wave signals with controllable frequency and amplitude, used for wavelength modulation of the system. This composite signal generator design not only improves signal accuracy and flexibility but also meets the system's requirements for complex modulation signals.

[0032] Compared with the prior art, the present invention has the following advantages:

[0033] 1. This invention can generate composite and square wave signals adapted to the requirements of QEPAS systems, thereby effectively replacing traditional commercial function signal generators. Furthermore, the circuitry of this invention exhibits superior performance in signal demodulation, achieving a noise level of 3uV and a resolution of 3uV, sufficient to replace commercial latching devices in system applications.

[0034] 2. This invention addresses three major challenges faced by traditional transimpedance amplifiers in amplifying quartz tuning fork signals, proposing solutions: First, it solves the problem that traditional transimpedance amplifiers struggle to simultaneously achieve wide bandwidth and high current-voltage gain, resulting in poor performance when amplifying high-frequency, weak quartz tuning fork signals. Second, it overcomes the problem that operational amplifiers with high gain-bandwidth products easily cause quartz tuning fork signals to be submerged in noise due to their large offset voltage and bias current. Finally, this invention also addresses the issue that most transimpedance amplifier circuit boards are only suitable for laboratory environments, and their ability to amplify weak signals is limited outdoors, especially under conditions of strong electromagnetic interference.

[0035] 3. In view of the shortcomings of the current QEPAS system, such as the large size, heavy weight and high power consumption of the lock-in amplifier, composite signal generator and preamplifier transimpedance amplifier, this invention successfully integrates these three key components through highly integrated design, realizing miniaturization and low power consumption design. Its size is reduced to 5cm*8cm and the power consumption is as low as 350mW, which greatly improves the portability of the system and the convenience of field exploration. Attached Figure Description

[0036] Figure 1The present invention relates to the main control chip and its peripheral circuits. The main control chip is an STM32L431RCT6 low-power microcontroller.

[0037] Figure 2 This is a power supply circuit diagram for the digital module and part of the analog module of the present invention;

[0038] Figure 3 This invention relates to the system clock and frequency divider circuit;

[0039] Figure 4 This is the reference clock generation circuit of the present invention;

[0040] Figure 5 This is a circuit diagram of the quartz tuning fork signal amplifier and power supply of the present invention;

[0041] Figure 6 This is a circuit diagram of the composite signal generator of the present invention;

[0042] Figure 7 This is a circuit diagram of the ultra-low noise reference voltage generation system of the present invention;

[0043] Figure 8 This is a diagram of the signal conditioning circuit and ADC acquisition circuit of the present invention;

[0044] Figure 9 This is a circuit diagram of the analog switch of the present invention;

[0045] Figure 10 This is a physical illustration of the present invention;

[0046] Figure 11 This is the overall schematic diagram of the present invention;

[0047] Figure 12 Photoacoustic signal of water vapor measured by QEPAS system demodulated by SR830, signal amplitude: 7.8313*10 -5 V, Noise: 2.2932*10 -6 V, SNR: 34.15;

[0048] Figure 13 The image shows the photoacoustic signal of water vapor of the same concentration measured by the QEPAS demodulation system of this invention. Its SNR is 31.26, which is 91.5% of that of SR830. Detailed Implementation

[0049] To gain a deeper understanding of this invention, we will provide a comprehensive and detailed description. However, this invention has various implementations and is not limited to the specific examples listed herein. These examples are presented to enhance a full understanding of the disclosure of this invention.

[0050] A circuit device for a photoacoustic system, the circuit device comprising a lock-in amplifier module, a composite signal generator module, a quartz tuning fork signal amplifier module, a signal channel conversion module, and a host computer, the overall schematic diagram of which is attached. Figure 11 As shown.

[0051] The lock-in amplifier module includes a main control chip circuit, a power supply circuit for digital modules and some analog modules, a system clock and frequency division circuit, a reference clock generation circuit, an ultra-low noise reference voltage generation circuit, a signal conditioning circuit, and an ADC acquisition circuit.

[0052] The composite signal generator module includes a main control chip circuit, a power supply circuit for digital modules and some analog modules, a system clock and frequency division circuit, a reference clock generation circuit, and a composite signal generator circuit.

[0053] The quartz tuning fork signal amplifier module includes a quartz tuning fork signal amplifier and a power supply circuit.

[0054] The signal channel conversion module includes analog switching circuitry.

[0055] The main control chip circuit consists of an STM32L431RCT6 low-power microcontroller and peripheral circuitry; the STM32L431RCT6 low-power microcontroller includes a timer; see attached. Figure 1 As shown. STM32 microcontroller pins PB6 and PB7 are the TX and RX pins of the serial port, responsible for transmitting data with the host computer. Resistor R11 is a pull-down resistor, pulling the STM32 microcontroller's PH3 / BOOT0 pin low to set the STM32 microcontroller's startup mode. Ferrite bead L2, capacitor C25, and capacitor E1 are used for filtering, providing a stable analog reference voltage to the STM32 microcontroller's VDDA pin. Capacitors C28, C29, C30, and C31 are filter capacitors, providing stable power supply voltages to STM32 microcontroller pins 19, 32, 48, and 64, respectively. Resistor R14 connects analog ground and digital ground, effectively reducing noise inrush from digital ground to analog ground and protecting the stability of analog ground.

[0056] The power supply circuits for the digital modules and some analog modules are low-dropout linear regulators (LDOs), characterized by low output ripple, high power supply rejection ratio, and low noise, ensuring the stability and accuracy of the circuit; as shown in the attached figure. Figure 2As shown. U7 is an LDO, with pin 5 outputting a stable 2.5V voltage, used as the power supply for the ADC. U8 is an LDO, with pin 5 outputting a stable 1.5V voltage, used as the reference voltage for the reference clock generation circuit. U6 is an LDO, with pin 5 outputting a stable 3.3V voltage, used as the power supply for the analog circuit. U10 is an LDO, with pin 5 outputting a stable 3.3V voltage, used as the power supply for the digital circuit. The digital and analog circuits are powered separately to prevent noise from the digital circuit from coupling into the noise-sensitive analog circuit, ensuring the accurate and stable operation of the analog circuit.

[0057] The system clock and frequency divider circuit uses a high-frequency active crystal oscillator to generate the system clock. This clock not only serves as the reference for the clock generation circuit but also generates a lower-frequency clock signal for the main control chip via the frequency divider circuit. Furthermore, impedance matching design is implemented along the transmission path of the high-frequency clock signal to prevent signal distortion and performance degradation during transmission; see attached... Figure 3 As shown. X1 is a high-frequency active crystal oscillator, with pin 3 outputting a 64MHz high-frequency system clock signal. Resistors R1, R4, R5, and R6 are impedance matching resistors to ensure the stability of the high-frequency clock signal. U3 and U4 are D flip-flops, forming a frequency divider circuit. The system clock generates a lower-frequency clock signal through R4, U3, and U4, which is connected to pin 5 of the STM32 microcontroller as the microcontroller's clock. Simultaneously, the system clock is connected through R1 to pin 8 of U5 in the reference clock generation circuit, serving as a clock reference.

[0058] The ultra-low noise reference voltage generation circuit consists of a reference voltage source and a low-pass filter with a very low cutoff frequency, as shown in the attached diagram. Figure 7As shown, the ultra-low noise reference voltage generated by the reference voltage source, after processing, provides a voltage reference for the composite signal generator circuit, signal conditioning circuit, and ADC acquisition circuit. The reference voltage source can generate an ultra-low noise reference voltage, and the noise can be further reduced by a low-pass filter with a very low cutoff frequency. However, in actual circuit design, the use of high-capacitance capacitors may lead to instability of the operational amplifier or even self-oscillation. To solve this potential stability problem, a combination of isolation resistors and compensation capacitors is added to the circuit. This design can enhance the stability of the system. U20 is the reference voltage source, and pin 6 outputs the ultra-low noise reference voltage. Resistor R37 and capacitor C67 form a low-pass filter with a very low cutoff frequency, which can further reduce the noise of the reference voltage. Resistors R36 and R38 and capacitors C65 and C70 are isolation resistors and compensation capacitors, which, together with U22, form a follower and output an ultra-low noise reference voltage REF3V3. This voltage is connected to pin 1 of U21 in the ADC acquisition circuit as the reference voltage for the ADC. Similarly, generate reference voltages REFDAC and REF1V65, and connect them to pin 15 of U17 in the composite signal generator circuit and pin 3 of U24A in the signal conditioning circuit, respectively.

[0059] The signal conditioning circuit and ADC acquisition circuit are divided into two parts: the signal conditioning circuit and the ADC acquisition circuit, as shown in the attached diagram. Figure 8As shown, the signal conditioning circuit uses an instrumentation amplifier to amplify the small voltage signal under test by a suitable factor and adds a suitable DC bias to the signal to prevent it from exceeding the ADC measurement range. The instrumentation amplifier has advantages such as low DC offset and low drift, high common-mode rejection ratio, high input impedance, and low noise, providing clear and accurate amplification and processing of small signals. Simultaneously, the signal conditioning circuit incorporates a second-order active bandpass filter, which effectively improves the signal-to-noise ratio of the signal under test. The ADC acquisition circuit is a high-precision, high-speed pseudo-differential input ADC. The pseudo-differential signal connection reduces noise. In pseudo-differential mode, the signal is connected to the positive terminal of the input, and the signal reference ground is connected to the negative terminal of the input. The pseudo-differential input reduces the influence caused by the difference in potential (ground circulation current) between the signal source and the reference ground, thus improving measurement accuracy. This ADC uses the SPI protocol for data transmission, offering a fast communication rate. U13A, U13B, and resistors and capacitors constitute a second-order active bandpass filter. The signal is input through C43, output from pin 7 of U13B, and then connected to pin 4 of U23. U23 is an instrumentation amplifier responsible for amplifying the input signal. U24A forms an inverting amplifier circuit, and U24B forms a second-order active low-pass filter. The amplified and filtered signal is connected to pin 3 of U21 and sampled by the DAC. U21 is an ADC; its pin 6 is connected to PA11 of the STM32 microcontroller, and the microcontroller controls the sampling; its pin 7 is connected to PB15 of the STM32 microcontroller to transmit data to the microcontroller; and its pin 8 is connected to pin 1 of U9 in the reference clock generation circuit.

[0060] The reference clock generation circuit consists of a direct frequency synthesizer (DDS), a bandpass filter, and a comparator. The DDS generates a sine wave signal with a specific frequency. This sine wave signal is then filtered by a specially designed bandpass filter, and an appropriate DC bias is added through pull-up resistors. After this processing, the signal is fed into the comparator, which converts it into a square wave signal, which is used as the reference clock signal, as shown in the attached diagram. Figure 4 As shown. U5 is the DDS, and its pins 13, 14, and 15 are connected to the PC2, PC0, and PC1 pins of the STM32 microcontroller, respectively. The microcontroller sends data to the DDS via these three lines in SPI mode. The signal generated by the DDS is output from pin 20, and after filtering and other processing, it is sent to comparator U9. The final reference clock signal is output from pin 1 of U9, which is connected to PA0 and PB13 of the STM32 microcontroller, and also to pin 8 of U21.

[0061] The clock signal generation process in the reference clock generation circuit is as follows: a direct frequency synthesizer generates a sine wave signal with a specific frequency, the sine wave signal is then filtered by a bandpass filter, and an appropriate DC bias is added through a pull-up resistor; subsequently, the sine wave signal is sent to a comparator, which converts the sine wave signal into a square wave signal, which is used as the reference clock signal A.

[0062] Reference clock signal A generates two PWM waves via the timer of the main control chip: clock B and clock C, which control the ADC acquisition rate and the DAC to generate waveforms at specific frequencies, respectively. The coordinated operation of clock B and clock C ensures that the ADC acquisition signal has no phase shift, facilitating subsequent data processing and demodulation to obtain the second harmonic signal. The data acquired by the ADC is sent to the main control chip via the SPI interface. The main control chip multiplies the received data with its internal sine and cosine tables and then accumulates the results to obtain two data sets, denoted as data A and data B. After a period of accumulation, a set of data A and data B is formed. This set is then processed using a multiple moving average filtering algorithm. Finally, the square root of the sum of the squares of data A and data B is calculated to obtain a set of data C. Data C is the signal amplitude demodulated by the lock-in amplifier, i.e., the second harmonic amplitude of the photoacoustic signal. Data C is then sent to the host computer via the serial port.

[0063] Clock C is configured as the clock source for Direct Memory Access (DMA) on the main control chip, used to control the DMA transfer rate. The DMA is responsible for transferring the sine wave table and square wave table stored in memory to the digital-to-analog converter (DAC) of the main control chip. By precisely controlling the frequency of clock C, sine and square wave signals with controllable frequencies can be generated, and these signals have a wide frequency range, making them particularly suitable for generating medium- and high-frequency composite signals required by QEPAS systems. Given the high frequency requirements of QEPAS systems, a strategy of reducing the number of data points in the sine wave table is needed to effectively reduce the processing burden on the main control chip's DMA. However, this method introduces a problem: unwanted high-frequency components are mixed into the sine signal. To solve this problem, a fourth-order low-pass filter is designed. The sine signal generated by the main control chip is input into this filter to remove the high-frequency components. After this processing, a sine signal with undistorted waveform is finally obtained.

[0064] The composite signal generator circuit consists of a high-precision external DAC and a follower; as shown in the attached diagram. Figure 6As shown; U1A and U1B form a fourth-order low-pass filter. The signal is input through one end of resistor R2, which is connected to pin PA4 of the STM32 microcontroller. The sine wave generated by the microcontroller is output from resistor R7 after passing through the fourth-order low-pass filter, and then connected to pin 12 of U17 as a reference voltage. U17 is a DAC, and its pins 7, 8, and 9 are connected to pins PC4, PB0, and PC5 of the STM32 microcontroller, respectively. The microcontroller sends data to the DAC via these three lines in SPI mode, controlling the DAC to generate a composite signal. The generated composite signal is then passed through a follower and connected to pin 10 of U18 in the analog switch circuit. U19B forms a follower. The STM32 microcontroller outputs a square wave through pin PA5, which is then connected to pin 6 of U18 after passing through the follower.

[0065] The composite signal generation process in the composite signal generator circuit is as follows: the square wave signal generated by the main control chip is directly changed in terms of its high and low levels by modifying the contents of the square wave table, and then connected to a follower to improve its load capacity, thus directly obtaining the square wave signal required by the system; the sine signal generated by the main control chip is filtered and used as the reference signal of the external DAC, and a new sine signal with controllable amplitude is obtained by writing the external DAC parameters, which serves as the modulation signal required by the system.

[0066] Meanwhile, the main control chip periodically sends sawtooth wave table data to the external DAC, allowing the external DAC to generate a low-frequency sawtooth wave signal with controllable amplitude and frequency. This signal serves as the scanning signal required by the system. The modulation signal and the scanning signal are combined to generate a composite signal.

[0067] The method for combining the modulation signal and the scanning signal is as follows: First, the DC bias in the modulation signal is filtered out using a capacitor of appropriate size. Then, the required DC bias is increased using a pull-up resistor, with the pull-up level sourced from the low-frequency scanning signal. In this way, the low-frequency scanning signal and the modulation signal without DC bias can be simply added together, achieving a function similar to an adder, ultimately generating a composite signal.

[0068] In summary, the composite signal generator can generate signals with the following characteristics: 1. Square wave signals with controllable frequency and high / low levels, used for intensity modulation of the system; 2. Composite signals composed of low-frequency sawtooth wave signals with controllable frequency and high / low levels and high-frequency sine wave signals with controllable frequency and amplitude, used for wavelength modulation of the system. This composite signal generator design not only improves signal accuracy and flexibility but also meets the system's requirements for complex modulation signals.

[0069] The quartz tuning fork signal amplifier and power supply circuit are as follows: Figure 5As shown, the quartz tuning fork signal amplifier is a transimpedance amplifier, but a MOSFET is added in the feedback loop near the input. At this point, the input impedance changes from the op-amp's input impedance to the MOSFET's gate impedance of hundreds of MΩ, significantly reducing the impact of the op-amp's offset voltage and bias current on the quartz tuning fork signal. Simultaneously, the MOSFET's large input impedance and extremely small gate current have almost no impact on the quartz tuning fork's small signal, ensuring signal integrity. The op-amp uses a high-speed operational amplifier, and the feedback resistor uses a large resistor of several MΩ. This allows the designed amplifier circuit to simultaneously possess the advantages of wide bandwidth and high current-to-voltage gain, making it very suitable for amplifying quartz tuning fork signals. The power supply circuit uses an ultra-high power supply rejection ratio, ultra-low noise LDO power supply chip, providing both positive and negative voltages. The current signal generated by the quartz tuning fork sensor contains negative components; therefore, using a positive and negative power supply system ensures the integrity and accuracy of the signal during transmission. In contrast, if only a single power supply scheme is used, a significant increase in additional circuit components is required to maintain signal integrity. This not only increases the system's complexity but may also introduce additional noise interference, thus affecting signal quality. From this perspective, using a positive and negative power supply method can effectively reduce the overall signal noise level of the system. Furthermore, an anti-interference shield was designed for the independently operating quartz tuning fork signal amplifier. The application of this shield significantly improves the amplifier's anti-interference capability, ensuring its stable operation in complex electromagnetic environments, and further guaranteeing the clarity and reliability of signal transmission, as shown in the attached diagram. Figure 10 As shown. JP4 is the interface for the quartz tuning fork sensor. Pin 1 receives the quartz tuning fork signal, and pin 2 connects to pin 1 of U14 in the analog switch circuit. The analog switch circuit changes the state of pin 2 of JP4. U16 is a MOSFET, and U15 is a high-speed operational amplifier. U16 and U15 together form a quartz tuning fork signal amplifier. The amplified signal is output from pin 1 of U15 and then connected to pin 10 of U14 in the analog switch circuit. The analog switch circuit determines whether the amplified quartz tuning fork signal is input to the ADC acquisition circuit.

[0070] The analog switch circuit contains two analog switches. Low on-resistance analog switches are selected to prevent signal distortion. The first analog switch is responsible for selecting the output channel of the composite signal generator, used to switch the output signal waveform and output port. The second analog switch is responsible for selecting the input channel of the signal conditioning circuit, used to switch the input port of the signal conditioning circuit and select the signal at one end of the quartz tuning fork interface; as shown in the attached diagram. Figure 9As shown; U14 is an analog switch, with pins 13 and 7 connected to PC7 and PC9 pins of the STM32 microcontroller, respectively, for controlling the state of the analog switch; pins 1 and 10 are connected to pin 2 of JP4 and pin 1 of U15 in the quartz tuning fork signal amplifier and power supply circuit, respectively; pin 9 is connected to C43 in the signal conditioning circuit. U18 is an analog switch, with pin 1 connected to PC8 pin of the STM32 microcontroller, for controlling the state of the analog switch; pins 10 and 6 are connected to pin 1 of U19A and pin 7 of U19B in the composite signal generator circuit, respectively.

[0071] The output signal waveform includes the composite signal generated by the composite signal generator circuit and the square wave signal; the output port is divided into a direction facing the external interface and an interface direction connected to one end of the quartz tuning fork; when the output port points to the external interface, the signal is used to modulate the system, and then the second harmonic is demodulated by the lock-in amplifier, at which time the system is in the working mode of measuring gas concentration; when the output port is connected to one end of the quartz tuning fork, the lock-in amplifier demodulates the first harmonic, and the system switches to the working mode of detecting the resonant frequency of the quartz tuning fork;

[0072] The signal conditioning circuit has two input port options: one is an external interface, which directly receives photoacoustic signals in the form of voltage; the other is the output signal of a quartz tuning fork signal amplifier, which is specifically used to demodulate the photoacoustic signals of the system.

[0073] The signal selection of the quartz tuning fork interface is divided into two cases: one is grounding, in which one end of the quartz tuning fork interface is grounded before demodulating the quartz tuning fork signal; the other is connecting to the output signal of the composite signal generator, in which one end of the quartz tuning fork interface is connected to the output signal of the composite signal generator before detecting the resonant frequency of the quartz tuning fork.

[0074] The signal channel conversion module includes analog switching circuitry.

[0075] The analog switch circuit has two analog switches. The first analog switch is responsible for selecting the output channel of the composite signal generator, and is used to switch the output signal waveform and output port. The second analog switch is responsible for selecting the input channel of the signal conditioning circuit, and is used to switch the input port of the signal conditioning circuit and select the signal at one end of the quartz tuning fork interface.

[0076] The output signal waveform includes the composite signal generated by the composite signal generator circuit and the square wave signal; the output port is divided into a direction facing the external interface and an interface direction connected to one end of the quartz tuning fork; when the output port points to the external interface, the signal is used to modulate the system, and then the second harmonic is demodulated by the lock-in amplifier, at which time the system is in the working mode of measuring gas concentration; when the output port is connected to one end of the quartz tuning fork, the lock-in amplifier demodulates the first harmonic, and the system switches to the working mode of detecting the resonant frequency of the quartz tuning fork;

[0077] The signal conditioning circuit has two input port options: one is an external interface, which directly receives photoacoustic signals in the form of voltage; the other is the output signal of a quartz tuning fork signal amplifier, which is specifically used to demodulate the photoacoustic signals of the system.

[0078] The signal selection of the quartz tuning fork interface is divided into two cases: one is grounding, in which one end of the quartz tuning fork interface is grounded before demodulating the quartz tuning fork signal; the other is connecting to the output signal of the composite signal generator, in which one end of the quartz tuning fork interface is connected to the output signal of the composite signal generator before detecting the resonant frequency of the quartz tuning fork.

[0079] Test Procedure: A QEPAS system was built using a commercial laser and temperature and flow control instruments. This system was used to measure the photoacoustic signal of water vapor in a confined space. Since the water vapor concentration in the confined space is stable, the resulting photoacoustic signal is also stable. The photoacoustic signal was first demodulated using a Stanford SR830 lock-in amplifier, and the results are as follows. Figure 12 As shown, the second harmonic amplitude of the signal is 7.8313*10. -5 V, noise level is 2.2932*10 -6 V, SNR is 34.15. Then the same photoacoustic signal was demodulated using the circuit of this invention, and the result is as follows. Figure 13 As shown in the figure, the second harmonic amplitude of the signal is 8.13*10. -5 V, noise level is 2.6*10 -6 V, with an SNR of 31.26, can achieve 91.5% of the SNR of SR830.

[0080] Contents not described in detail in this specification are prior art known to those skilled in the art. Although illustrative specific embodiments of the invention have been described above to facilitate understanding by those skilled in the art, it should be understood that the invention is not limited to the scope of the specific embodiments. Various modifications are readily apparent to those skilled in the art as long as they fall within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of this invention are protected.

Claims

1. A circuit device for a photoacoustic system, characterized in that, The circuit device includes a lock-in amplifier module, a composite signal generator module, a quartz tuning fork signal amplifier module, a signal channel conversion module, and a host computer; The lock-in amplifier module includes a main control chip circuit, a power supply circuit for digital modules and some analog modules, a system clock and frequency division circuit, a reference clock generation circuit, an ultra-low noise reference voltage generation circuit, a signal conditioning circuit, and an ADC acquisition circuit. The composite signal generator module includes a main control chip circuit, a power supply circuit for digital modules and some analog modules, a system clock and frequency division circuit, a reference clock generation circuit, and a composite signal generator circuit. The quartz tuning fork signal amplifier module includes a quartz tuning fork signal amplifier and a power supply circuit. The signal channel conversion module includes analog switching circuitry; The main control chip circuit consists of an STM32L431RCT6 low-power microcontroller and peripheral circuits; the STM32L431RCT6 low-power microcontroller includes a timer. The power supply circuit for the digital module and some analog modules is a low-dropout linear regulator. The system clock and frequency divider circuit are generated by a high-frequency active crystal oscillator. The reference clock generation circuit consists of a direct frequency synthesizer, a bandpass filter, and a comparator. The quartz tuning fork signal amplifier and power supply circuit are quartz tuning fork signal amplifier and power supply circuit; the quartz tuning fork signal amplifier is a transimpedance amplifier, but a MOS transistor is added in the feedback loop near the input end; the power supply circuit is an ultra-high power supply rejection ratio, ultra-low noise LDO power supply chip, providing positive and negative voltages; The composite signal generator circuit consists of a high-precision external DAC and a follower; The ultra-low noise reference voltage generation circuit consists of a reference voltage source and a low-pass filter; the ultra-low noise reference voltage generated by the reference voltage source provides a voltage reference for the composite signal generator circuit, the signal conditioning circuit and the ADC acquisition circuit. The signal conditioning circuit and ADC acquisition circuit are divided into two parts: the signal conditioning circuit and the ADC acquisition circuit. The signal conditioning circuit uses an instrumentation amplifier to amplify the small voltage signal to be measured by a suitable factor and adds a suitable DC bias to the voltage signal to be measured to prevent it from exceeding the measurement range of the ADC. The ADC acquisition circuit is a pseudo-differential input ADC, which uses the SPI protocol to transmit data.

2. The circuit device for an optoacoustic system according to claim 1, characterized in that, Adding an isolation resistor and a compensation capacitor to the ultra-low noise reference voltage generation circuit enhances the system's stability. An anti-interference shield is designed for the quartz tuning fork signal amplifier to ensure its stable operation in complex electromagnetic environments. The signal conditioning circuit is designed with a second-order active bandpass filter to improve the signal-to-noise ratio of the signal under test. The composite signal generator module is designed with a fourth-order low-pass filter. The sinusoidal signal generated by the main control chip is input into this filter to filter out the high-frequency components.

3. A circuit device for an optoacoustic system according to claim 2, characterized in that, The analog switch circuit has two analog switches. The first analog switch is responsible for selecting the output channel of the composite signal generator, and is used to switch the output signal waveform and output port. The second analog switch is responsible for selecting the input channel of the signal conditioning circuit, and is used to switch the input port of the signal conditioning circuit and select the signal at one end of the quartz tuning fork interface. The output signal waveform includes the composite signal generated by the composite signal generator circuit and the square wave signal; the output port is divided into a direction facing the external interface and an interface direction connected to one end of the quartz tuning fork; when the output port points to the external interface, the signal is used to modulate the system, and then the second harmonic is demodulated by the lock-in amplifier, at which time the system is in the working mode of measuring gas concentration; when the output port is connected to one end of the quartz tuning fork, the lock-in amplifier demodulates the first harmonic, and the system switches to the working mode of detecting the resonant frequency of the quartz tuning fork; The signal conditioning circuit has two input port options: one is an external interface, which directly receives photoacoustic signals in the form of voltage; the other is the output signal of a quartz tuning fork signal amplifier, which is specifically used to demodulate the photoacoustic signals of the system. The signal selection of the quartz tuning fork interface is divided into two cases: one is grounding, in which one end of the quartz tuning fork interface is grounded before demodulating the quartz tuning fork signal; the other is connecting to the output signal of the composite signal generator, in which one end of the quartz tuning fork interface is connected to the output signal of the composite signal generator before detecting the resonant frequency of the quartz tuning fork.

4. A circuit device for an optoacoustic system according to claim 3, characterized in that, The clock signal generation process in the reference clock generation circuit is as follows: a direct frequency synthesizer generates a sine wave signal with a specific frequency, the sine wave signal is then filtered by a bandpass filter, and an appropriate DC bias is added through a pull-up resistor; subsequently, the sine wave signal is sent to a comparator, which converts the sine wave signal into a square wave signal, which is used as the reference clock signal A. Reference clock signal A generates two PWM waves through the timer of the main control chip: clock B and clock C, which respectively control the ADC acquisition rate and the DAC to generate waveforms of specific frequencies; the coordinated operation of clock B and clock C ensures that the ADC acquisition signal has no phase shift. The data acquired by the ADC is sent to the main control chip via the SPI interface. The main control chip multiplies the received data with its internal sine and cosine tables respectively and then accumulates the results to obtain two data points, denoted as data A and data B. After a period of accumulation, a set of data A and data B is formed. The set is then processed using a multiple moving average filtering algorithm. Finally, the arithmetic square root of the sum of the squares of data A and data B is calculated to obtain a set of data C. Data C is the signal amplitude demodulated by the lock-in amplifier, i.e., the second harmonic amplitude of the photoacoustic signal. Data C is then sent to the host computer via the serial port.

5. A circuit device for an optoacoustic system according to claim 4, characterized in that, The composite signal generation process in the composite signal generator circuit is as follows: the square wave signal generated by the main control chip is directly changed by modifying the contents of the square wave table to change its high and low levels, and then connected to a follower to improve its load capacity, so as to obtain the square wave signal required by the system; the sine wave signal generated by the main control chip is filtered and used as the reference signal of the external DAC, and the same frequency sine wave signal with controllable amplitude is obtained by writing the external DAC parameters, which is used as the modulation signal required by the system. Meanwhile, the main control chip periodically sends sawtooth wave table data to the external DAC, allowing the external DAC to generate a low-frequency sawtooth wave signal with controllable amplitude and frequency. This signal serves as the scanning signal required by the system. The modulation signal and the scanning signal are combined to generate a composite signal.

6. A circuit device for an optoacoustic system according to claim 5, characterized in that, The method for combining the modulation signal and the scanning signal is as follows: first, the DC bias in the modulation signal is filtered out by a capacitor of appropriate size, and then the required DC bias is increased by a pull-up resistor. The source of the pull-up level is the low-frequency scanning signal.

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