Display substrate, display panel, display device and manufacturing method of display panel

Abstract

The invention discloses a display substrate, a display panel, a display device and a manufacturing method of the display panel. The display substrate comprises a plurality of heating wiring groups, the heating wire group comprises at least two heating wires extending along the second direction, and a first leading-out end and a second leading-out end which are connected with the heating wires; a first binding terminal group; the first binding terminal group comprises a first binding terminal pair, and the first binding terminal pair comprises two first binding terminals; one end of one first binding terminal in the first binding terminal pair is electrically connected with the first leading-out end, and one end of the other first binding terminal in the first binding terminal pair is electrically connected with the second leading-out end; and the detection pad group comprises two detection pads which are arranged along the second direction.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate, a display panel, a display device and a method for manufacturing a display panel. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation and easy to carry. It has been rapidly developed in recent years and has gradually replaced the traditional cathode ray tube display (CRT) and has occupied a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small sized products, covering almost all major electronic products in today's information society, such as LCD TV, high-definition digital TV, computer (desktop and notebook), mobile phone, tablet computer, navigation system, car display, projection display, video camera, digital camera, electronic watch, calculator, electronic instrument, meter, public display and virtual display, etc. Summary of the invention

[0003] The present invention provides a display substrate, a display panel, a display device and a method for manufacturing a display panel. The display substrate has a display area and a peripheral area located outside the display area; wherein the display substrate comprises:

[0004] substrate;

[0005] A plurality of heating wiring groups, at least part of which is located in the display area, and the plurality of heating wiring groups are arranged along a first direction and extend along a second direction; the heating wiring group comprises: at least two heating wirings extending along the second direction, and a first lead-out end and a second lead-out end connected to the heating wirings;

[0006] A first binding terminal group is located in the peripheral area; the first binding terminal group includes: a plurality of first binding terminal pairs arranged along a first direction, the first binding terminal pair includes two first binding terminals; one end of one of the first binding terminals in the first binding terminal pair is electrically connected to the first lead-out terminal, and one end of another of the first binding terminals in the first binding terminal pair is electrically connected to the second lead-out terminal;

[0007] A detection pad group, comprising: two detection pads arranged along the second direction; one of the detection pads is configured to receive a first detection signal to provide the first detection signal to one of the first binding terminals in each of the first binding terminal pairs, and the other of the detection pads is configured to receive a second detection signal to provide the second detection signal to the other of the first binding terminals in each of the first binding terminal pairs.

[0008] In a possible implementation manner, a plurality of first transfer electrodes are located in the peripheral area and on a side of the first binding terminal away from the substrate; the first transfer electrodes overlap with the orthographic projection of the first binding terminal on the substrate at least in part of the orthographic projection of the substrate, and are electrically connected through vias at the overlapping positions;

[0009] The first transfer electrode includes: a first transfer portion and a second transfer portion; the first transfer portion and the second transfer portion both extend along the second direction, and the first transfer portion is located on a side of the first transfer portion away from the display area;

[0010] The width of the second transition portion in the first direction is smaller than the width of the second transition portion in the first direction; in the first direction, the minimum spacing between adjacent second transition portions is larger than the minimum distance between adjacent first transition portions.

[0011] In a possible implementation, the detection pad includes: a first detection electrode, and a second transfer electrode located on a side of the first detection electrode facing away from the substrate;

[0012] At least part of the orthographic projection of the second switching electrode on the substrate overlaps with the orthographic projection of the first detection electrode on the substrate, and the electrodes are electrically connected at the overlapping position through a via hole.

[0013] In a possible implementation manner, the second switching electrode includes: a third switching portion and a fourth switching portion; the fourth switching portion is located at a side of the third switching portion away from the display area;

[0014] The width of the fourth transition portion in the second direction is smaller than the width of the third transition portion in the second direction; in the second direction, the minimum distance between adjacent fourth transition portions is larger than the minimum distance between adjacent third transition portions.

[0015] In a possible implementation, the first detection electrode includes: a first hollow portion, and a first surrounding portion located outside the first hollow portion; the orthographic projection of the third transition portion on the substrate covers the orthographic projection of the first surrounding portion on the substrate.

[0016] In a possible implementation manner, the detection pad further includes: a second detection electrode located on a side of the first detection electrode facing the substrate;

[0017] The orthographic projection of the second detection electrode on the substrate overlaps with the orthographic projection of the first detection electrode on the substrate.

[0018] In a possible implementation, the second detection electrode includes: a second hollow portion, and a second surrounding portion located outside the second hollow portion; an orthographic projection of the second surrounding portion on the substrate overlaps with an orthographic projection of the first surrounding portion on the substrate.

[0019] In a possible implementation manner, the display substrate further includes: an electrostatic structure and a first grounding line; and the detection pad is connected to the first grounding line via the electrostatic structure.

[0020] In a possible implementation, the display substrate includes: a plurality of gate lines extending along a first direction, a plurality of data lines extending along the second direction, a common electrode, and a plurality of pixel electrodes;

[0021] The display substrate further comprises: a first detection circuit and a second detection circuit located in the peripheral area; the first detection circuit comprises: a plurality of first transistors, a first signal line, and a second signal line; the second detection circuit comprises: a plurality of second transistors, a third signal line, and a fourth signal line; the first transistor comprises: a first control electrode, a first source electrode, and a first drain electrode; the second transistor comprises: a second control electrode, a second source electrode, and a second drain electrode;

[0022] The first control electrode of each of the first transistors is electrically connected to the first signal line; the first source electrode of each of the first transistors is electrically connected to the second signal line, and the first drain electrode of each of the first transistors is electrically connected to the gate line; the second control electrode of each of the second transistors is electrically connected to the third signal line; the second source electrode of each of the second transistors is electrically connected to the fourth signal line, and the second drain electrode of each of the second transistors is electrically connected to the data line.

[0023] In a possible implementation, the plurality of gate lines include: a plurality of first sub-gate lines and a plurality of second sub-gate lines; the plurality of data lines include: a plurality of first sub-data lines, a plurality of second sub-data lines, and a plurality of third sub-data lines; the plurality of first transistors include: a plurality of first sub-transistors and a plurality of second sub-transistors; the second signal line includes: a first sub-signal line and a second sub-signal line; the plurality of second transistors include: a plurality of third sub-transistors, a plurality of fourth sub-transistors, and a plurality of fifth sub-transistors; the fourth signal line includes: a third sub-signal line, a fourth sub-signal line, and a fifth sub-signal line;

[0024] The first source of each of the first sub-transistors is electrically connected to the first sub-signal line, and the first drain of each of the first sub-transistors is electrically connected to the first sub-gate line; the first source of each of the second sub-transistors is electrically connected to the second sub-signal line, and the first drain of each of the second sub-transistors is electrically connected to the second sub-gate line;

[0025] The second source of each of the third sub-transistors is electrically connected to the third sub-signal line, and the second drain of each of the third sub-transistors is electrically connected to the first sub-data line; the second source of each of the fourth sub-transistors is electrically connected to the fourth sub-signal line, and the second drain of each of the fourth sub-transistors is electrically connected to the second sub-data line; the second source of each of the fifth sub-transistors is electrically connected to the fifth sub-signal line, and the second drain of each of the fifth sub-transistors is electrically connected to the third sub-data line.

[0026] In a possible implementation, the data line is located on a side of the layer where the gate line is located away from the substrate, and the common electrode is located on a side of the layer where the data line is located away from the layer where the gate line is located; the pixel electrode is located on a side of the common electrode away from the layer where the data line is located; and the heating wiring is located between the layer where the data line is located and the layer where the common electrode is located;

[0027] The heating trace and the first binding terminal are made of the same layer and the same material; the first transfer electrode and one of the pixel electrode or the common electrode are made of the same layer and the same material.

[0028] The embodiment of the present disclosure further provides a display panel, which includes the display substrate provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the display substrate.

[0029] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0030] The present disclosure also provides a method for manufacturing a display panel, which includes:

[0031] The front-drive display substrate and the counter substrate are assembled; wherein the front-drive display substrate includes the display substrate provided in the embodiment of the present invention, and further includes: a first detection line and a second detection line; the first detection line is connected to one of the detection pads, and the second detection line is connected to the other detection pad; one of the first binding terminals in each of the first binding terminal pairs is connected to the first detection line, and the other of the first binding terminals in each of the first binding terminal pairs is connected to the second detection line;

[0032] Testing the display panel after box assembly;

[0033] When it is confirmed that the display panel is a first type of display panel, the display panel is cut, wherein at least a portion of the first detection line is cut off, and at least a portion of the second detection line is cut off.

[0034] In a possible implementation manner, the detecting the display panel after the packing includes:

[0035] Among the first signal line, the second signal line, the third signal line and the fourth signal line, providing an effective level signal to the first signal line, the second signal line and the third signal line, providing a first detection signal to one of the detection pads, and providing a second detection signal to another detection pad;

[0036] When the display panel displays a black screen, confirming that the display panel is the first type of display panel;

[0037] When the display panel has poor linearity or displays a grayscale image, the display panel is confirmed to be a second type of display panel.

[0038] In a possible implementation manner, the detecting the display panel after the packing includes:

[0039] Among the first signal line, the second signal line, the second signal line and the fourth signal line, providing an effective level signal to the first signal line, the second signal line and the fourth signal line, and providing a first detection signal to one of the detection pads, and providing a second detection signal to another detection pad;

[0040] When the display panel displays a black screen, confirming that the display panel is the first type of display panel;

[0041] When the display panel displays a white screen, it is confirmed that the display panel is a second type of display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1A A schematic diagram of a front-drive display substrate provided in an embodiment of the present disclosure;

[0043] Figure 1B A connection diagram of a heating wiring group provided in an embodiment of the present disclosure;

[0044] Figure 1C A connection diagram of another heating wiring group provided in an embodiment of the present disclosure;

[0045] Figure 2A for Figure 1A An enlarged schematic diagram of the position of the middle dashed line frame S01;

[0046] Figure 2B for Figure 2A A schematic diagram of the first binding terminal in FIG.

[0047] Figure 2C for Figure 2A Schematic diagram of a single film layer of the first transfer electrode;

[0048] Figure 2D for Figure 2A A schematic cross-sectional view along the dotted line A1-A1';

[0049] Figure 3A for Figure 1A An enlarged schematic diagram of the position of the middle dashed line frame S02;

[0050] Figure 3B for Figure 3A A schematic diagram of the layer where the second detection electrode is located;

[0051] Figure 3C for Figure 3A Schematic diagram of the film layers of the active layer;

[0052] Figure 3D for Figure 3A A schematic diagram of the layer where the first detection electrode is located;

[0053] Figure 3E for Figure 3A Schematic diagram of the film layer where the first detection line and the second detection line are located;

[0054] Figure 3F for Figure 3A Schematic diagram of the film layer where the second transfer electrode is located;

[0055] Figure 4 A schematic diagram of a manufacturing process of a display substrate provided by an embodiment of the present invention;

[0056] Figure 5A One of the schematic diagrams of the display substrate structure provided by the embodiment of the present disclosure;

[0057] Figure 5B for Figure 5A Schematic diagram of the film layer where the middle grid line is located;

[0058] Figure 5C for Figure 5A Schematic diagram of the film layer where the active layer is located;

[0059] Figure 5D for Figure 5A Schematic diagram of the film layer where the data line is located;

[0060] Figure 5E for Figure 5A Schematic diagram of the film layer where the lower left layer is heated;

[0061] Fig. 5F for Figure 5A Schematic diagram of the film layer where the common electrode is located;

[0062] Figure 5G for Figure 5A Schematic diagram of the film layer where the pixel electrode is located;

[0063] Figure 5H for Figure 5A A schematic cross-sectional view along the dotted line A2-A2';

[0064] Figure 6 A schematic diagram of a first detection circuit provided by an embodiment of the present invention;

[0065] Figure 7 A schematic diagram of a second detection circuit provided by an embodiment of the present invention;

[0066] Figure 8 for Figure 5A Schematic diagram of the corresponding detection signal line;

[0067] Fig.9A It may be a partial schematic diagram of the second peripheral area BB2;

[0068] Fig. 9B for Fig.9A A schematic cross-sectional view along the dotted line A3-A3';

[0069] Fig.10 for Fig.9A Schematic diagram of the corresponding detection signal;

[0070] Fig.11A It may be a partial schematic diagram of the fourth peripheral area BB4;

[0071] Fig. 11B for Fig.11A A schematic diagram of the stacking of the heating trace J and the common electrode 5;

[0072] Fig. 11C It may be a partial schematic diagram of the first peripheral area BB1;

[0073] Fig.11D for Fig. 11C A schematic diagram of the stacking of the heating trace J and the common electrode 5;

[0074] Fig.11E Can be Fig.11A or Fig. 11C A schematic cross-sectional view at the dashed line A4-A4';

[0075] Fig.12 For Fig.11A Schematic diagram of the corresponding detection signal;

[0076] Fig.13 A schematic diagram of the display panel manufacturing process provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0077] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0078] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0079] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0080] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0081] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0082] See also Figure 5A-5H As shown, Figure 5A This is one of the schematic diagrams of the display substrate structure provided in the embodiment of the present disclosure. Figure 5B for Figure 5A Schematic diagram of the film layer where the middle grid line is located. Figure 5C for Figure 5A Schematic diagram of the film layer where the active layer is located, Figure 5D for Figure 5A Schematic diagram of the film layer where the data line is located. Figure 5E for Figure 5A Schematic diagram of the film layer where the lower left layer is heated. Fig. 5F for Figure 5A Schematic diagram of the film layer where the common electrode is located, Figure 5G for Figure 5A Schematic diagram of the film layer where the pixel electrode is located, Figure 5H for Figure 5A A schematic cross-sectional view along the dotted line A2-A2';

[0083] The embodiment of the present disclosure provides a display substrate comprising: a plurality of gate lines 2 extending along a first direction X, a plurality of data lines 3 extending along a second direction Y, a plurality of heating traces J, a common electrode 5, and a plurality of pixel electrodes 4; the data lines 3 are located on a side of a layer where the gate lines 2 are located away from a substrate 1, and the common electrodes 5 are located on a side of a layer where the data lines 3 are located away from a layer where the gate lines 2 are located; the pixel electrodes 4 are located on a side of the common electrodes 5 away from a layer where the data lines 3 are located; the heating traces J are located between a layer where the data lines 3 are located and a layer where the common electrodes 5 are located; the heating traces J and a first binding terminal C1 are in the same layer and made of the same material; and the first transfer electrode D1 is in the same layer and made of the same material as one of the pixel electrode 4 or the common electrode 5.

[0084] Optional, combined Figure 4As shown, during the manufacturing process of the display substrate, a gate line layer (the gate line layer may include multiple gate lines 2 extending along a first direction), a gate insulating layer 91, an active layer (may include multiple active patterns 60), a data line layer (the data line layer may include multiple data lines 3 extending along a second direction), a first passivation layer 92, a heating structure layer (may include a heating trace J), ​​a second passivation layer 93, a common electrode layer (the common electrode layer may be a transparent conductive layer), a third passivation layer 94, and a pixel electrode layer (the pixel electrode layer may include multiple pixel electrodes 4) may be formed in sequence on the substrate 1; the above is only one film layer stacking structure of the display substrate provided in the embodiment of the present disclosure. In a specific implementation, the display substrate may also be stacked in other ways, and the embodiment of the present disclosure is not limited here.

[0085] In a low temperature environment, the viscosity of liquid crystal is high, and the display screen needs a heating function inside the box to increase the temperature of the liquid crystal in order to display normally. Designing a heating wire inside the box to increase the temperature is a very effective solution. Due to the addition of heating wires, the process difficulty increases, the number of masks increases, and the resulting defective rate will increase. Due to problems such as particles in the product production process, short circuits between the heating wire and other signal film layers will occur, causing the module product to become a defective product, wasting IC, FPC, backlight and other module materials. Therefore, it is very necessary to screen out these defective products related to the heating wire before bonding, which can avoid material waste and save costs.

[0086] See also Figure 1A , Figure 2A-2D , Figure 3A-Figure 3F As shown, Figure 1A A schematic diagram of a front-drive display substrate provided in an embodiment of the present disclosure, Figure 2A for Figure 1A The enlarged schematic diagram of the position of the dashed line frame S01, Figure 2B for Figure 2A Schematic diagram of the first binding terminal in, Figure 2C for Figure 2A Schematic diagram of a single film layer of the first transfer electrode, Figure 2D for Figure 2A A schematic cross-sectional view along the dotted line A1-A1' in FIG. Figure 3A for Figure 1A The enlarged schematic diagram of the position of the dashed line frame S02, Figure 3B for Figure 3A Schematic diagram of the layer where the second detection electrode is located, Figure 3C for Figure 3A Schematic diagram of the active layer film, Figure 3D for Figure 3A Schematic diagram of the layer where the first detection electrode is located, Figure 3E for Figure 3ASchematic diagram of the film layer where the first detection line and the second detection line are located, Figure 3F for Figure 3A Schematic diagram of the film layer where the second transfer electrode is located, the embodiment of the present invention provides a display substrate, having a display area AA, and a peripheral area BB located outside the display area AA; wherein, it includes:

[0087] Substrate 1;

[0088] A plurality of heating wiring groups JZ, at least part of the plurality of heating wiring groups JZ are located in the display area AA, and the plurality of heating wiring groups JZ are arranged along the first direction X and extend along the second direction Y; the heating wiring group JZ includes: at least two heating wirings J extending along the second direction Y, and a first lead-out terminal JO1 and a second lead-out terminal JO2 connected to the heating wiring J; optionally, the plurality of heating wiring groups JZ may include: a plurality of first heating wiring groups JZ1, and a plurality of second heating wiring groups JZ2; the first heating wiring group JZ1 may include: a plurality of first heating wirings J1 extending along the second direction Y; at least part of the first heating wiring group JZ1 is located in the display area AA, for heating the display area AA; the second heating wiring group JZ2 may include: a plurality of second heating wirings J2 extending along the second direction Y; the plurality of second heating wiring groups JZ2 may be located in the peripheral area BB, for heating the peripheral area BB; the heating wiring J includes: a first heating wiring J1, and a second heating wiring J2;

[0089] A first binding terminal group C is located in the peripheral area BB; the first binding terminal group C includes: a plurality of first binding terminal pairs C0 arranged along the first direction X, the first binding terminal pair C0 includes two first binding terminals C1; one end of one of the first binding terminals C1 in the first binding terminal pair C0 is electrically connected to the first lead-out terminal JO1, and one end of the other first binding terminal C1 in the first binding terminal pair C0 is electrically connected to the second lead-out terminal JO2;

[0090] The detection pad group E includes: two detection pads E1 arranged along the second direction Y; one of the detection pads E1 is configured to receive a first detection signal to provide the first detection signal to one of the first binding terminals C1 in each first binding terminal pair C0, and the other detection pad E1 is configured to receive a second detection signal to provide the second detection signal to the other first binding terminal C1 in each first binding terminal pair C0.

[0091] In the disclosed embodiment, the display substrate includes: a plurality of heating trace groups, a plurality of first binding terminal pairs C0, and two detection pads E1. A first detection signal (e.g., a positive polarity signal) can be loaded onto one of the detection pads E1, and a second detection signal (e.g., a negative polarity signal) can be loaded onto the other detection pad E1. The first detection signal can be loaded onto the first lead-out terminal JO1 via the first binding terminal C1 in the first binding terminal pair C0, and the second detection signal can be loaded onto the second lead-out terminal JO2 via the other first binding terminal C1 in the first binding terminal pair C0, thereby forming a detection loop. That is, by connecting at least two ends of the heating traces J in parallel and then connecting them to the two detection pads E1 respectively, before the display panel is bonded (bonded) to the control chip IC, it can be detected whether the heating traces J are short-circuited with the gate lines, data lines or common electrodes (or common traces), thereby reducing the waste of materials of the control chip IC, the flexible circuit board, etc.

[0092] In one possible implementation, combining Figure 1A , Figure 2A-2D , Figure 3A-Figure 3F As shown, before cutting, the display panel (which can be used as a precursor substrate) may include: a first detection line H1, and a second detection line H2; the first detection line H1 is connected to one of the detection pads E1, and the second detection line H2 is connected to another detection pad E1; one of the first binding terminals C1 in each first binding terminal pair C0 is connected to the first detection line H1, and the other first binding terminal C1 in each first binding terminal pair C0 is connected to the second detection line H2. After the display panel is inspected, the periphery of the display panel can be cut, for example, along the Figure 1A The first dotted line S1 and the second dotted line S2 in the circuit are cut, wherein at least a portion of the first detection line H1 and the second detection line H2 can be cut off. The first detection line H1 and the second detection line H2 can be made of the same layer and material as the heating line J.

[0093] In one possible implementation, see Figure 1A As shown, the peripheral area BB may also include: a first peripheral area BB1, a second peripheral area BB2, a third peripheral area BB3, and a fourth peripheral area BB4; the first peripheral area BB1 and the fourth peripheral area BB4 are arranged opposite to each other, and the second peripheral area BB2 and the third peripheral area BB3 may be connected to the first peripheral area BB1 and the fourth peripheral area BB4; the first peripheral area BB1 may be provided with a terminal group connected to the data line, the second peripheral area BB2 and the third peripheral area BB3 may be provided with a terminal group connected to the gate line (the gate drive circuit GOA may not be integrated on the display substrate), and the first binding terminal group C connected to the heating trace J may be located in the fourth peripheral area BB4.

[0094] In one possible implementation, see Figure 1B and Figure 1C As shown, the heating wire group JZ may include a plurality of heating wires J; in the same heating wire group JZ, one end of each heating wire J (for example, an end close to the first peripheral area BB1) is connected to each other, and the other end of each heating wire J (for example, an end close to the fourth peripheral area BB4) can be divided into two groups, and the same group is connected to each other to form two output ends; for example, Figure 1B As shown, the heating wire group JZ may include two heating wires J, one end of the two heating wires J (for example, an end close to the first peripheral area BB1) is connected to each other, and the other end of the two heating wires J (for example, an end close to the fourth peripheral area BB4) is respectively used as the first lead-out terminal JO1 and the second lead-out terminal JO2; in another possible implementation manner, see Figure 1C As shown, the heating wiring group JZ includes four heating wirings J, one ends of the four heating wirings J (for example, an end close to the first peripheral area BB1) are connected to each other, and the other ends of the four heating wirings J (for example, an end close to the fourth peripheral area BB4) are connected together in pairs to form a first lead-out terminal JO1 and a second lead-out terminal JO2, respectively.

[0095] In the disclosed embodiment, the display substrate has a plurality of heating wiring groups JZ. In the same heating wiring group JZ, the ends of each heating wiring J near the first peripheral area BB1 are electrically connected, and the ends of some adjacent heating wiring J near the fourth peripheral area BB4 are electrically connected. That is, by connecting some heating wirings J in parallel, the density of the heating wirings J can be reduced, and the spacing between the heating wirings J coming out of the display area AA can be increased, thereby providing more wiring space for other structures (such as light-sensing structures).

[0096] In a possible embodiment, the display substrate includes: a plurality of pixel electrode columns extending along the second direction Y and arranged along the first direction X; the pixel electrode columns include: a plurality of pixel electrodes 4 arranged along the second direction Y; the orthographic projection of the first heating line J1 on the substrate 1 can be located at the orthographic projection of the gap between two adjacent pixel electrode columns on the substrate 1; optionally, one first heating line J1 may be provided for each pixel (one pixel may include three sub-pixels); optionally, three first heating lines J1 may be provided for each pixel (one pixel may include three sub-pixels), that is, one first heating line J1 may be provided for each sub-pixel.

[0097] In one possible implementation, see Figure 2A-2DAs shown, the display substrate further includes: a plurality of first transfer electrodes D1, which are located in the peripheral area BB and on the side of the first binding terminal C1 away from the substrate 1; at least a portion of the orthographic projection of the first transfer electrode D1 on the substrate 1 overlaps with the orthographic projection of the first binding terminal C1 on the substrate 1, and is electrically connected through a via hole at the overlapping position; for example, the first transfer electrode D1 is electrically connected to the first binding terminal C1 at the overlapping position through a first via hole group K10, and the first via hole group K10 may include a plurality of first via holes K1; optionally, the resistance of the first transfer electrode D1 may be greater than the resistance of the first detection line H1, the second detection line H2 and / or the first binding terminal C1, and the first transfer electrode D1 may be provided in the same layer and the same material as one of the pixel electrode 4 and the common electrode 5;

[0098] The first transfer electrode D1 includes: a first transfer portion D11 and a second transfer portion D12; the first transfer portion D11 and the second transfer portion D12 both extend along the second direction Y, and the second transfer portion D12 is located at a side of the first transfer portion D1 away from the display area AA;

[0099] A width a2 of the second transition portion D12 in the first direction X is smaller than a1 of the first transition portion D11 in the first direction X. In the first direction X, a minimum spacing a4 between adjacent second transition portions D12 is larger than a minimum spacing a3 between adjacent first transition portions D11.

[0100] In the disclosed embodiment, the display substrate further includes: a plurality of first transfer electrodes D1, that is, the first binding terminal C1 is transferred to the first detection line H1 and the second detection line H2 through the first transfer electrode D1. Since the resistance of the first transfer electrode D1 (for example, the first transfer electrode D1 may be indium tin oxide in the same layer as one of the pixel electrode 4 and the common electrode 5) is larger than the metal resistance, static electricity may be prevented from entering and damaging the first binding terminal C1. Moreover, the first transfer electrode D1 includes: a first transfer portion D11 and a second transfer portion D12. The second transfer portion D12 is located on a side of the first transfer portion D1 away from the display area AA. The minimum spacing a4 between adjacent second transfer portions D12 is greater than the minimum distance a3 between adjacent first transfer portions D11. That is, increasing the spacing between adjacent second transfer portions D12 may reduce the problem that when debris or particles generated by cutting of the display panel fall on two adjacent second transfer portions D12, the second transfer portions D12 may be short-circuited with each other, thereby causing the display panel to display poorly.

[0101] In one possible implementation, see Figure 2A-2DAs shown, before the display panel is cut, the display substrate may have a plurality of pads F, which can improve the electrostatic breakdown caused by the antenna effect that occurs when the first detection line H1 and the second detection line H2 are long and generate more charges. The pads F can concentrate the other charges on the first detection line H1 and the second detection line H2 to the position with the pads F, thereby preventing the risk of static electricity accumulating on the first binding terminal C1 and causing damage to the first binding terminal C1.

[0102] In one possible implementation, combining Figure 3A-Figure 3F As shown, the detection pad E1 includes: a first detection electrode E11, and a second transfer electrode D2 located on the side of the first detection electrode E11 away from the substrate 1; optionally, the first detection electrode E11 can be in the same layer and material as the data line 3; the second transfer electrode D2 can be in the same layer and material as the first transfer electrode D1;

[0103] At least part of the orthographic projection of the second transfer electrode D2 on the substrate 1 overlaps with the orthographic projection of the first detection electrode E11 on the substrate 1, and is electrically connected through a via at the overlapping position. For example, the second transfer electrode D2 is electrically connected to the first detection electrode E11 at the overlapping position through a second via group K20, and the second via group K20 may include a plurality of second vias K2. In the disclosed embodiment, the detection pad E1 includes: a first detection electrode E11, and a second transfer electrode D2 located on the side of the first detection electrode E11 away from the substrate 1; wherein, since the resistance of the second transfer electrode D2 (for example, the second transfer electrode D2 may be indium tin oxide in the same layer as one of the pixel electrode 4 and the common electrode 5) is greater than the metal resistance, the probability of static electricity entering and damaging the first binding terminal C1 can be reduced.

[0104] In one possible implementation, combining Figure 3A-Figure 3F As shown, the second transition electrode D2 includes: a third transition portion D21, and a fourth transition portion D22; the fourth transition portion D22 is located on a side of the third transition portion D21 away from the display area AA; a width b2 of the fourth transition portion D22 in the second direction Y is smaller than a width b1 of the third transition portion D21 in the second direction Y; in the second direction Y, a minimum distance b4 between adjacent fourth transition portions D22 is greater than a minimum distance b4 between adjacent third transition portions D21. In the disclosed embodiment, the second transfer electrode D2 includes: a third transfer portion D21, and a fourth transfer portion D22; the fourth transfer portion D22 is located on a side of the third transfer portion D21 away from the display area AA; the minimum distance b4 between adjacent fourth transfer portions D22 is greater than the minimum distance b4 between adjacent third transfer portions D21, that is, increasing the spacing between adjacent fourth transfer portions D22 can reduce the problem that debris or particles generated by cutting of the display panel fall on two adjacent fourth transfer portions D22, which easily causes a short circuit between the fourth transfer portions D22, thereby causing the display panel to have a poor display.

[0105] In one possible implementation, combining Figure 3A-Figure 3F As shown, the first detection electrode E11 includes: a first hollow portion E111 and a first surrounding portion E112 located outside the first hollow portion E111; the orthographic projection of the third adapter portion D21 on the substrate 1 covers the orthographic projection of the first surrounding portion E112 on the substrate 1.

[0106] In one possible implementation, combining Figure 3A-Figure 3F As shown, the detection pad E1 further includes: a second detection electrode E12 located on the side of the first detection electrode E11 facing the substrate 1; the orthographic projection of the second detection electrode E12 on the substrate 1 overlaps with the orthographic projection of the first detection electrode E11 on the substrate 1. Optionally, the second detection electrode E12 can be in the same layer and material as the gate line 2.

[0107] In one possible implementation, combining Figure 3A-Figure 3F As shown, the second detection electrode E12 includes: a second hollow portion E121 and a second surrounding portion E122 located outside the second hollow portion E121; the orthographic projection of the second surrounding portion E122 on the substrate 1 overlaps with the orthographic projection of the first surrounding portion E112 on the substrate 1.

[0108] In one possible implementation, combining Figure 3A-Figure 3F As shown, the detection pad E1 may further include: a first mark 61 (such as Figure 3A "+" in the middle), and the second mark 62 (such as Figure 3A The first mark 61 and the second mark 62 can be in the same layer and the same material as the active pattern 60.

[0109] In one possible implementation, combining Figure 3A-Figure 3F As shown, the display substrate further includes: an electrostatic structure ESD, and a first ground line GND; the detection pad E1 is connected to the first ground line GND via the electrostatic structure ESD. In the disclosed embodiment, the other side of the detection pad E1 is connected to the first ground line GND via the electrostatic structure ESD, which can conduct away the static electricity on the first detection line H1 and the second detection line H2, preventing the static electricity from breaking down the first binding terminal C1.

[0110] In one possible implementation, combining Figure 3A-Figure 3F As shown, the display substrate further includes: a first common line 51 located at a side of the first ground line GND away from the detection pad E1; the first ground line GND, the first common line 51, and the gate line 2 can be in the same layer and the same material.

[0111] In one possible implementation, see Figure 6 , Figure 7As shown, the display substrate further includes: a first detection circuit Q1 located in the peripheral area BB, and a second detection circuit Q2; optionally, the first detection circuit Q1 may be the second peripheral area BB2 or the third peripheral area BB3; the second detection circuit Q2 may be the first peripheral area BB1; the first detection circuit Q1 includes: a plurality of first transistors T1, a first signal line G1, and a second signal line G2; the second detection circuit Q2 includes: a plurality of second transistors T2, a third signal line G3, and a fourth signal line G4; the first transistor T1 includes: a first control electrode T1A, a first source electrode T1B, and a first drain electrode T1C; the second transistor T2 includes: a second control electrode T2A, a second source electrode T2B, and a second drain electrode T2C;

[0112] The first control electrode T1A of each first transistor T1 is electrically connected to the first signal line G1; the first source electrode T1B of each first transistor T1 is electrically connected to the second signal line G2, and the first drain electrode T1C of each first transistor T1 is electrically connected to the gate line 2; the second control electrode T2A of each second transistor T2 is electrically connected to the third signal line G3; the second source electrode T2B of each second transistor T2 is electrically connected to the fourth signal line G4, and the second drain electrode T2C of each second transistor T2 is electrically connected to the data line 3.

[0113] In the embodiment of the present disclosure, the first signal line G1 is a switching voltage for turning on the first transistor T1, and the third signal line G3 is a switching voltage for turning on the second transistor T2. When the first signal line G1 and the third signal line G3 are loaded with a valid signal (for example, a high-level voltage VGH), the first transistor T1 and the second transistor T2 are turned on, and the voltage of the second signal line G2 and the voltage of the fourth signal line G4 can be input into the display area AA; when the first signal line G1 and the third signal line G3 are loaded with an invalid signal (for example, a low-level voltage VGL), the first transistor T1 and the second transistor T2 are turned off, and the voltage of the second signal line G2 and the voltage of the fourth signal line G4 cannot be input into the display area AA; when the second signal line G2 is loaded with a valid signal (for example, a high-level voltage VGH), the pixel transistor in the display area AA is turned on, and the voltage of the fourth signal line G4 can be input into the pixel electrode; when the second signal line G2 is loaded with an invalid signal (for example, a low-level voltage VGL), the pixel transistor in the display area AA is turned off, and the voltage of the fourth signal line G4 cannot be input into the pixel electrode. The voltage of the fourth signal line G4 may be -5V (VDH) to 5V (VDL), and the voltage of the common electrode 5 (VCOM) may be 0V.

[0114] In one possible implementation, see Figure 6 , Figure 7As shown, the plurality of gate lines 2 include: a plurality of first sub-gate lines 21 (for example, providing GO signals), and a plurality of second sub-gate lines 22 (for example, providing GE signals); the plurality of data lines 3 include: a plurality of first sub-data lines 31 (data lines that can provide data signals for red sub-pixels), a plurality of second sub-data lines 32 (data lines that can provide data signals for green sub-pixels), and a plurality of third sub-data lines 33 (data lines that can provide data signals for blue sub-pixels); the plurality of first transistors T1 include: a plurality of first sub-transistors T11, and a plurality of second sub-transistors T12; the second signal line G2 includes: a first sub-signal line G21, and a second sub-signal line G22; the plurality of second transistors T2 include: a plurality of third sub-transistors T2R, a plurality of fourth sub-transistors T2G, and a plurality of fifth sub-transistors T2B; the fourth signal line includes: a third sub-signal line G4R, a fourth sub-signal line G4G, and a fifth sub-signal line G4B;

[0115] The first source T1B of each first sub-transistor T11 is electrically connected to the first sub-signal line G21, and the first drain T1C of each first sub-transistor T11 is electrically connected to the first sub-gate line 21; the first source T1B of each second sub-transistor T12 is electrically connected to the second sub-signal line G22, and the first drain of each second sub-transistor T12 is electrically connected to the second sub-gate line 22;

[0116] The second source T2B of each third sub-transistor T2R is electrically connected to the third sub-signal line G4R, and the second drain T2C of each third sub-transistor T2R is electrically connected to the first sub-data line 31; the second source T2B of each fourth sub-transistor T2G is electrically connected to the fourth sub-signal line G4G, and the second drain T2C of each fourth sub-transistor T2G is electrically connected to the second sub-data line 32; the second source T2B of each fifth sub-transistor T2B is electrically connected to the fifth sub-signal line G4B, and the second drain T2C of each fifth sub-transistor T2B is electrically connected to the third sub-data line 33.

[0117] The following is an example of the detection method of the embodiment of the present disclosure:

[0118] For example, combined with Figure 5A , Figure 8 As shown, it is detected whether the heating line J is short-circuited with the data line 3; wherein, a valid voltage (e.g., a high level voltage VGH) is applied to the first signal line G1 and the third signal line G3, a valid voltage (e.g., a high level voltage VGH) is applied to the second signal line G2, an invalid voltage (e.g., a low level voltage VGL, e.g., 0V) is applied to the fourth signal line G4, an invalid voltage (e.g., a low level voltage VGL, e.g., 0V) is applied to the common electrode 5, and 0V and 28V are applied to the two detection pads E1 respectively; as shown in FIG. Figure 5AAs shown, the heating trace J is directly above the data line 3. When the heating trace J and the data line 3 are not short-circuited, the voltage difference between the common electrode 5 and the pixel electrode 4 is 0V, the liquid crystal is not deflected, and the picture is black; when the second passivation layer 93 is damaged and causes the heating trace J and the data line 3 to be short-circuited, the voltage of the data line 3 is the same as that of the heating trace J. Since the voltage on the heating trace J is not 0V, the voltage difference between the common electrode 5 and the pixel electrode 4 is not 0V, so the vertical linearity of the lit picture is poor, and the product can be judged as a defective product.

[0119] For example, combined with Fig.9A , Fig. 9B and Fig.10 Show, among which, Fig.9A It can be a partial schematic diagram of the second peripheral area BB2, Fig. 9B for Fig.9A A schematic cross-sectional view along the dotted line A3-A3' is provided to detect whether the heating wiring J (the second heating wiring J2) is short-circuited with the first fan-out wiring FG (for example, the first fan-out wiring FG may be a fan-out wiring located in the second peripheral area BB2 and connected to the gate line 2). A valid voltage (for example, a high-level voltage VGH) is applied to the first signal line G1 and the third signal line G3, an invalid voltage (for example, a low-level voltage VGL, for example, 0V, corresponding to the signal applied to the gate line 2) is applied to the second signal line G2, a valid voltage (for example, a high-level voltage VGH, for example, 5V, corresponding to the signal applied to the data line 3) is applied to the fourth signal line G4, an invalid voltage (for example, a low-level voltage VGL, for example, 0V) is applied to the common electrode 5, and 0V and 28V are applied to the two detection pads E1, respectively; Fig.9A As shown, the heating routing J (the second heating routing J2) overlaps with the first fan-out routing FG (the first fan-out routing FG connected to the gate line 2, located in the layer where the gate line 2 is located). When the heating routing J (the second heating routing J2) and the first fan-out routing FG are not short-circuited, since the voltage of the second signal line G2 (corresponding to the gate line 2) is VGL, the pixel transistor of the display area AA is turned off, so the voltage of the fourth signal line G4 (corresponding to the data line 3) cannot be input to the pixel electrode, so the detection screen is displayed as a black screen; when there are cracks in the gate insulating layer 91 and the first passivation layer 92, the heating routing J (the second heating routing J2) and the first fan-out routing FG are short-circuited. Since the first fan-out routing FG is connected to the gate line 2, the voltage on the gate line 2 is the same as the voltage on the heating routing J (the second heating routing J2), which is VGH. At this time, the pixel transistor of the display area is turned on, and the voltage (5V) of the fourth signal line G4 can be input to the pixel electrode, and the detection screen is displayed as a white screen. According to the displayed screen, it can be determined whether the product is defective. In this detection screen, the voltage of the fourth signal line G4 can also be other voltage values ​​other than 0;

[0120] For example, combining Figure 11A-11C and Fig.12 As shown, Fig.11A It can be a partial schematic diagram of the fourth peripheral area BB4, Fig. 11B It can be a partial schematic diagram of the first peripheral area BB1, Fig. 11C Can be Fig.11A or Fig. 11B In the cross-sectional schematic diagram of the dotted line A4-A4', it is detected whether the heating line J is short-circuited with the common line 50 or the common electrode 5 (the common line 50 can be connected to the common electrode 5); wherein, a valid voltage (e.g., a high level voltage VGH) is applied to the first signal line G1 and the third signal line G3, a valid voltage (e.g., a high level voltage VGH) is applied to the second signal line G2, an invalid voltage (e.g., a low level voltage VGL, e.g., 0V) is applied to the fourth signal line G4, an invalid voltage (e.g., a low level voltage VGL, e.g., 0V) is applied to the common electrode 5, and 0V and 28V are applied to the two detection pads E1, respectively; Fig.11A and Fig. 11B As shown, the heating wiring J overlaps with the common wiring 50 or the common electrode 5. When the heating wiring J and the common wiring 50 or the common electrode 5 are not short-circuited, since the voltage of the second signal line G2 (corresponding to the gate line 2) is VGH, the pixel transistor of the display area AA is turned on, so the voltage (0V) of the fourth signal line G4 (corresponding to the data line 3) is input to the pixel electrode, so the detection screen is displayed as a black screen; when the third passivation layer 93 has a crack, the heating wiring J and the common wiring 50 (or the common electrode 5) are short-circuited, and the voltage on the common wiring 50 (or the common electrode 5) is the same as the voltage on the heating wiring J, which is not 0V. At this time, the voltage difference between the pixel electrode and the common wiring 50 (or the common electrode 5) is not 0V, and the detection screen is displayed as a grayscale screen. According to the displayed screen, it can be judged whether the product is a defective product.

[0121] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes a display substrate as provided in the embodiment of the present disclosure, and also includes an opposing substrate arranged opposite to the display substrate.

[0122] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0123] Based on the same inventive concept, the present disclosure also provides a method for manufacturing a display panel, see Fig.13 As shown, the production method comprises:

[0124] Step S100, aligning the front-drive display substrate with the counter substrate; wherein the front-drive display substrate comprises the display substrate according to any one of claims 1 to 11, and further comprises: a first detection line H1, and a second detection line H2; the first detection line H1 is connected to one of the detection pads E1, and the second detection line H2 is connected to another detection pad E1; one of the first binding terminals C1 in each first binding terminal pair C0 is connected to the first detection line H1, and the other first binding terminal C1 in each first binding terminal pair C0 is connected to the second detection line H2;

[0125] Step S200, testing the assembled display panel;

[0126] Step S300: When the display panel is confirmed to be a first type display panel, the display panel is cut, wherein at least a portion of the first detection line is cut off, and at least a portion of the second detection line is cut off. The first type display panel may be a display panel without defective display.

[0127] In a possible implementation manner, step S200, testing the assembled display panel, includes:

[0128] Among the first signal line, the second signal line, the third signal line, and the fourth signal line, providing an effective level signal to the first signal line, the second signal line, and the third signal line, providing a first detection signal to one of the detection pads, and providing a second detection signal to another detection pad;

[0129] When the display panel displays a black screen, it is confirmed that the display panel is a first type display panel; the second type display panel may be a display panel with a poor display;

[0130] When the display panel has poor linearity or displays a grayscale image, it is determined that the display panel is a second type display panel.

[0131] For example, combined with Figure 5A , Figure 8 As shown, it is detected whether the heating line J is short-circuited with the data line 3; wherein, a valid voltage (e.g., a high level voltage VGH) is applied to the first signal line G1 and the third signal line G3, a valid voltage (e.g., a high level voltage VGH) is applied to the second signal line G2, an invalid voltage (e.g., a low level voltage VGL, e.g., 0V) is applied to the fourth signal line G4, an invalid voltage (e.g., a low level voltage VGL, e.g., 0V) is applied to the common electrode 5, and 0V and 28V are applied to the two detection pads E1 respectively; as shown in FIG. Figure 5AAs shown, the heating trace J is directly above the data line 3. When the heating trace J and the data line 3 are not short-circuited, the voltage difference between the common electrode 5 and the pixel electrode 4 is 0V, the liquid crystal is not deflected, and the picture is black; when the second passivation layer 93 is damaged and causes the heating trace J and the data line 3 to be short-circuited, the voltage of the data line 3 is the same as that of the heating trace J. Since the voltage on the heating trace J is not 0V, the voltage difference between the common electrode 5 and the pixel electrode 4 is not 0V, so the vertical linearity of the lit picture is poor, and the product can be judged as a defective product.

[0132] For example, combining Figures 11A-11E and Fig.12 As shown, Fig.11A It can be a partial schematic diagram of the fourth peripheral area BB4, Fig. 11B for Fig.11A Schematic diagram of the stacking of the heating trace J and the common electrode 5, Fig. 11C It can be a partial schematic diagram of the first peripheral area BB1, Fig.11D for Fig. 11C Schematic diagram of the stacking of the heating trace J and the common electrode 5, Fig.11E Can be Fig.11A or Fig. 11C In the cross-sectional schematic diagram of the dotted line A4-A4', it is detected whether the heating line J is short-circuited with the common line 50 or the common electrode 5 (the common line 50 can be connected to the common electrode 5); wherein, a valid voltage (e.g., a high level voltage VGH) is applied to the first signal line G1 and the third signal line G3, a valid voltage (e.g., a high level voltage VGH) is applied to the second signal line G2, an invalid voltage (e.g., a low level voltage VGL, e.g., 0V) is applied to the fourth signal line G4, an invalid voltage (e.g., a low level voltage VGL, e.g., 0V) is applied to the common electrode 5, and 0V and 28V are applied to the two detection pads E1, respectively; Fig.11A and Fig. 11B As shown, the heating wiring J overlaps with the common wiring 50 or the common electrode 5. When the heating wiring J and the common wiring 50 or the common electrode 5 are not short-circuited, since the voltage of the second signal line G2 (corresponding to the gate line 2) is VGH, the pixel transistor of the display area AA is turned on, so the voltage (0V) of the fourth signal line G4 (corresponding to the data line 3) is input to the pixel electrode, so the detection screen is displayed as a black screen; when the third passivation layer 93 has a crack, the heating wiring J and the common wiring 50 (or the common electrode 5) are short-circuited, and the voltage on the common wiring 50 (or the common electrode 5) is the same as the voltage on the heating wiring J, which is not 0V. At this time, the voltage difference between the pixel electrode and the common wiring 50 (or the common electrode 5) is not 0V, and the detection screen is displayed as a grayscale screen. According to the displayed screen, it can be judged whether the product is a defective product.

[0133] In a possible implementation manner, step S200, testing the assembled display panel, includes:

[0134] Among the first signal line, the second signal line, the third signal line and the fourth signal line, providing an effective level signal to the first signal line, the second signal line and the fourth signal line, and providing a first detection signal to one of the detection pads, and providing a second detection signal to another detection pad;

[0135] When the display panel displays a black screen, confirm that the display panel is a first type display panel;

[0136] When the display panel displays a white screen, it is confirmed that the display panel is a second type display panel.

[0137] For example, combined with Fig.9A , Fig. 9B and Fig.10 Show, among which, Fig.9A It can be a partial schematic diagram of the second peripheral area BB2, Fig. 9B for Fig.9A A schematic cross-sectional view along the dotted line A3-A3' is provided to detect whether the heating wiring J (the second heating wiring J2) is short-circuited with the first fan-out wiring FG (for example, the first fan-out wiring FG may be a fan-out wiring located in the second peripheral area BB2 and connected to the gate line 2). A valid voltage (for example, a high-level voltage VGH) is applied to the first signal line G1 and the third signal line G3, an invalid voltage (for example, a low-level voltage VGL, for example, 0V, corresponding to the signal applied to the gate line 2) is applied to the second signal line G2, a valid voltage (for example, a high-level voltage VGH, for example, 5V, corresponding to the signal applied to the data line 3) is applied to the fourth signal line G4, an invalid voltage (for example, a low-level voltage VGL, for example, 0V) is applied to the common electrode 5, and 0V and 28V are applied to the two detection pads E1, respectively; Fig.9AAs shown, the heating routing J (the second heating routing J2) overlaps with the first fan-out routing FG (the first fan-out routing FG connected to the gate line 2, located in the layer where the gate line 2 is located). When the heating routing J (the second heating routing J2) and the first fan-out routing FG are not short-circuited, since the voltage of the second signal line G2 (corresponding to the gate line 2) is VGL, the pixel transistor of the display area AA is turned off, so the voltage of the fourth signal line G4 (corresponding to the data line 3) cannot be input to the pixel electrode, so the detection screen is displayed as a black screen; when there are cracks in the gate insulating layer 91 and the first passivation layer 92, the heating routing J (the second heating routing J2) and the first fan-out routing FG are short-circuited. Since the first fan-out routing FG is connected to the gate line 2, the voltage on the gate line 2 is the same as the voltage on the heating routing J (the second heating routing J2), which is VGH. At this time, the pixel transistor of the display area is turned on, and the voltage (5V) of the fourth signal line G4 can be input to the pixel electrode, and the detection screen is displayed as a white screen. Whether the product is defective can be determined based on the displayed screen. In this detection screen, the voltage of the fourth signal line G4 can also be other voltage values ​​other than 0.

[0138] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, including the above display panel provided by the embodiment of the present disclosure. The implementation of the display device can refer to the embodiment of the above display panel, and the repeated parts will not be repeated.

[0139] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0140] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0141] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display substrate, comprising a display area and a peripheral area located outside the display area; wherein: include: substrate; A plurality of heating wiring groups, at least part of which is located in the display area, and the plurality of heating wiring groups are arranged along a first direction and extend along a second direction; the heating wiring group comprises: at least two heating wirings extending along the second direction, and a first lead-out end and a second lead-out end connected to the heating wirings; A first binding terminal group is located in the peripheral area; the first binding terminal group includes: a plurality of first binding terminal pairs arranged along a first direction, the first binding terminal pair includes two first binding terminals; one end of one of the first binding terminals in the first binding terminal pair is electrically connected to the first lead-out terminal, and one end of another of the first binding terminals in the first binding terminal pair is electrically connected to the second lead-out terminal; A detection pad group, comprising: two detection pads arranged along the second direction; one of the detection pads is configured to receive a first detection signal to provide the first detection signal to one of the first binding terminals in each of the first binding terminal pairs, and the other of the detection pads is configured to receive a second detection signal to provide the second detection signal to the other of the first binding terminals in each of the first binding terminal pairs.

2. The display substrate according to claim 1, wherein: A plurality of first transfer electrodes are located in the peripheral area and on a side of the first binding terminal facing away from the substrate; The first switching electrode overlaps with the first binding terminal on the orthographic projection of the substrate at least in part of the orthographic projection of the substrate, and is electrically connected through a via hole at the overlapping position; The first transfer electrode includes: a first transfer portion and a second transfer portion; the first transfer portion and the second transfer portion both extend along the second direction, and the first transfer portion is located on a side of the first transfer portion away from the display area; The width of the second transition portion in the first direction is smaller than the width of the second transition portion in the first direction; in the first direction, the minimum spacing between adjacent second transition portions is larger than the minimum distance between adjacent first transition portions.

3. The display substrate according to claim 1 or 2, wherein: The detection pad comprises: a first detection electrode, and a second transfer electrode located on a side of the first detection electrode facing away from the substrate; At least part of the orthographic projection of the second switching electrode on the substrate overlaps with the orthographic projection of the first detection electrode on the substrate, and the electrodes are electrically connected at the overlapping position through a via hole.

4. The display substrate according to claim 3, wherein: The second transfer electrode comprises: a third transfer portion and a fourth transfer portion; the fourth transfer portion is located at a side of the third transfer portion away from the display area; The width of the fourth transition portion in the second direction is smaller than the width of the third transition portion in the second direction; in the second direction, the minimum distance between adjacent fourth transition portions is larger than the minimum distance between adjacent third transition portions.

5. The display substrate according to claim 4, wherein: The first detection electrode comprises: a first hollow portion, and a first surrounding portion located outside the first hollow portion; the orthographic projection of the third transition portion on the substrate covers the orthographic projection of the first surrounding portion on the substrate.

6. The display substrate according to claim 5, wherein: The detection pad further includes: a second detection electrode located on a side of the first detection electrode facing the substrate; The orthographic projection of the second detection electrode on the substrate overlaps with the orthographic projection of the first detection electrode on the substrate.

7. The display substrate according to claim 6, wherein: The second detection electrode includes: a second hollow portion, and a second surrounding portion located outside the second hollow portion; the orthographic projection of the second surrounding portion on the substrate overlaps with the orthographic projection of the first surrounding portion on the substrate.

8. The display substrate according to any one of claims 1 to 7, wherein: The display substrate further includes: an electrostatic structure and a first grounding line; the detection pad is connected to the first grounding line through the electrostatic structure.

9. The display substrate according to any one of claims 1 to 8, wherein: The display substrate comprises: a plurality of gate lines extending along a first direction, a plurality of data lines extending along the second direction, a common electrode, and a plurality of pixel electrodes; The display substrate further comprises: a first detection circuit and a second detection circuit located in the peripheral area; the first detection circuit comprises: a plurality of first transistors, a first signal line, and a second signal line; the second detection circuit comprises: a plurality of second transistors, a third signal line, and a fourth signal line; the first transistor comprises: a first control electrode, a first source electrode, and a first drain electrode; the second transistor comprises: a second control electrode, a second source electrode, and a second drain electrode; The first control electrode of each of the first transistors is electrically connected to the first signal line; the first source electrode of each of the first transistors is electrically connected to the second signal line, and the first drain electrode of each of the first transistors is electrically connected to the gate line; the second control electrode of each of the second transistors is electrically connected to the third signal line; the second source electrode of each of the second transistors is electrically connected to the fourth signal line, and the second drain electrode of each of the second transistors is electrically connected to the data line.

10. The display substrate according to claim 9, wherein: The plurality of gate lines include: a plurality of first sub-gate lines and a plurality of second sub-gate lines; the plurality of data lines include: a plurality of first sub-data lines, a plurality of second sub-data lines, and a plurality of third sub-data lines; the plurality of first transistors include: a plurality of first sub-transistors and a plurality of second sub-transistors; the second signal lines include: a first sub-signal line and a second sub-signal line; the plurality of second transistors include: a plurality of third sub-transistors, a plurality of fourth sub-transistors, and a plurality of fifth sub-transistors; the fourth signal lines include: a third sub-signal line, a fourth sub-signal line, and a fifth sub-signal line; The first source of each of the first sub-transistors is electrically connected to the first sub-signal line, and the first drain of each of the first sub-transistors is electrically connected to the first sub-gate line; the first source of each of the second sub-transistors is electrically connected to the second sub-signal line, and the first drain of each of the second sub-transistors is electrically connected to the second sub-gate line; The second source of each of the third sub-transistors is electrically connected to the third sub-signal line, and the second drain of each of the third sub-transistors is electrically connected to the first sub-data line; the second source of each of the fourth sub-transistors is electrically connected to the fourth sub-signal line, and the second drain of each of the fourth sub-transistors is electrically connected to the second sub-data line; the second source of each of the fifth sub-transistors is electrically connected to the fifth sub-signal line, and the second drain of each of the fifth sub-transistors is electrically connected to the third sub-data line.

11. The display substrate according to claim 9 or 10, wherein: The data line is located at a side of the layer where the gate line is located away from the substrate, and the common electrode is located at a side of the layer where the data line is located away from the layer where the gate line is located; the pixel electrode is located at a side of the common electrode away from the layer where the data line is located; the heating wiring is located between the layer where the data line is located and the layer where the common electrode is located; The heating trace and the first binding terminal are made of the same layer and the same material; the first transfer electrode and one of the pixel electrode or the common electrode are made of the same layer and the same material.

12. A display panel, wherein: It comprises the display substrate as described in any one of claims 1 to 11, and also comprises an opposing substrate arranged opposite to the display substrate.

13. A display device, wherein: Comprising the display panel as claimed in claim 12.

14. A method for manufacturing a display panel, wherein: include: The front-drive display substrate and the counter substrate are assembled; wherein the front-drive display substrate comprises the display substrate according to any one of claims 1 to 11, and further comprises: a first detection line and a second detection line; the first detection line is connected to one of the detection pads, and the second detection line is connected to the other detection pad; one of the first binding terminals in each of the first binding terminal pairs is connected to the first detection line, and the other of the first binding terminals in each of the first binding terminal pairs is connected to the second detection line; Testing the display panel after box assembly; When it is confirmed that the display panel is a first type of display panel, the display panel is cut, wherein at least a portion of the first detection line is cut off, and at least a portion of the second detection line is cut off.

15. The method of claim 14, wherein: The step of testing the display panel after packing includes: Among the first signal line, the second signal line, the third signal line and the fourth signal line, providing an effective level signal to the first signal line, the second signal line and the third signal line, providing a first detection signal to one of the detection pads, and providing a second detection signal to another detection pad; When the display panel displays a black screen, confirming that the display panel is the first type of display panel; When the display panel has poor linearity or displays a grayscale image, the display panel is confirmed to be a second type of display panel.

16. The method of claim 14, wherein: The step of testing the display panel after packing includes: Among the first signal line, the second signal line, the second signal line and the fourth signal line, providing an effective level signal to the first signal line, the second signal line and the fourth signal line, and providing a first detection signal to one of the detection pads, and providing a second detection signal to another detection pad; When the display panel displays a black screen, confirming that the display panel is the first type of display panel; When the display panel displays a white screen, it is confirmed that the display panel is a second type of display panel.

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