Wafer parameter prediction model training method and wafer parameter prediction method

Abstract

The invention discloses a training method of a wafer parameter prediction model and a prediction method of wafer parameters. The method comprises the following steps: acquiring a plurality of photoetching space images; performing gridding processing on the plurality of photoetching space images to obtain a plurality of grid space images; performing overall translation on all grids in each grid space image to obtain a translation space image corresponding to each grid space image; and training the wafer parameter prediction model based on the wafer parameter true values corresponding to the plurality of photoetching space images and the plurality of translation space images to obtain a trained wafer parameter prediction model, and constructing the wafer parameter prediction model based on a neural network model. As all grids in each grid space image are integrally translated, and the grid size in the translated space image is the same as the grid size of the corresponding grid space image, the trained wafer parameter prediction model can predict the parameters of the wafer under the condition of not depending on the grid size. And the wafer parameter prediction value corresponding to each photoetching space image can be accurately obtained.

Description

Technical Field

[0001] The present application belongs to the field of photolithography technology, and in particular relates to a training method for a wafer parameter prediction model and a method for predicting wafer parameters. Background Art

[0002] At present, photolithography technology has become a crucial step in the chip manufacturing process. In order to achieve higher integration and smaller feature sizes, it is necessary to improve the simulation accuracy and efficiency of photolithography simulation technology.

[0003] In the process of photolithography simulation, aerial images at different positions on the wafer are usually input into the simulation model to obtain simulation results. Due to the different positions of collecting aerial images, the grid sizes corresponding to the aerial images are inconsistent. The inconsistency of the grid size has a certain impact on the accuracy of the simulation results, that is, the accuracy of the simulation results has a certain dependence on the grid size.

[0004] Thus, grid dependency is an urgent problem to be solved in lithography simulation. Summary of the invention

[0005] The embodiments of the present application provide a method for training a wafer parameter prediction model and a method for predicting wafer parameters, which can more accurately determine the wafer parameters of a lithography space image without relying on the grid size of the lithography space image.

[0006] In a first aspect, an embodiment of the present application provides a method for training a wafer parameter prediction model, including: acquiring multiple lithography spatial images; gridding the multiple lithography spatial images to obtain multiple grid spatial images; translating all grids in each grid spatial image as a whole to obtain a translated spatial image corresponding to each grid spatial image; training a wafer parameter prediction model based on true values ​​of wafer parameters corresponding to the multiple lithography spatial images and the multiple translated spatial images to obtain a trained wafer parameter prediction model, wherein the wafer parameter prediction model is constructed based on a neural network model.

[0007] In an optional implementation of the first aspect, all grids in each grid space image are translated as a whole to obtain a translated space image corresponding to each grid space image, including: performing multiple overall translations on all grids in each grid space image, each overall translation obtaining a translated space image corresponding to each grid space image, wherein the process of multiple overall translations is as follows: the starting position of the next overall translation is the ending position of the current overall translation, and for each grid space image, the cumulative step length of the multiple overall translations of each grid does not exceed the side length of one grid.

[0008] In an optional implementation of the first aspect, a wafer parameter prediction model is trained based on the actual values ​​of wafer parameters corresponding to multiple lithography spatial images and multiple translational spatial images to obtain a trained wafer parameter prediction model, including: obtaining an optical threshold of wafer parameters; inputting the optical threshold of wafer parameters and multiple translational spatial images into the wafer parameter prediction model to obtain predicted values ​​of wafer parameters corresponding to the multiple translational spatial images; performing weighted calculation on the optical threshold of wafer parameters and the predicted values ​​of wafer parameters to obtain model predicted values; performing weighted calculation on the optical threshold of wafer parameters and the actual values ​​of wafer parameters to obtain model actual values; calculating a loss value of a loss function of the wafer parameter prediction model based on the model predicted values ​​and the actual values ​​of the model; and training the wafer parameter prediction model based on the loss value to obtain a trained wafer parameter prediction model.

[0009] In an optional implementation of the first aspect, the process of constructing a loss function includes: constructing a total loss function based on the sum of squares of differences between model prediction values ​​corresponding to multiple translational spatial images and model true values; and constructing a loss function based on a ratio of the total loss function to the total number of multiple translational spatial images.

[0010] In an optional implementation of the first aspect, obtaining the optical threshold of the wafer parameter includes: determining the optical threshold of the wafer parameter based on true values ​​of the wafer parameters corresponding to multiple reference grid space images, wherein the grid size of the reference grid space image is smaller than the grid size of the grid space image.

[0011] In an optional embodiment of the first aspect, the wafer parameter prediction model includes at least an input layer, at least one convolutional network module, at least one hole convolutional network module and an output layer, wherein the convolutional network module includes a convolution branch and a convolutional residual connection branch, the convolution branch includes a first convolutional layer, a first batch normalization layer and a first linear rectification function unit, the convolutional residual connection branch includes a second convolutional layer, a second batch normalization layer and a second linear rectification function unit, the convolution branch and the convolution residual connection branch have different sizes of convolution kernels, and the first batch normalization in the convolution branch The data output by the layer is merged with the data output by the convolution residual connection branch; the atrous convolution network module includes a atrous convolution branch and a atrous convolution residual connection branch, the atrous convolution branch includes a atrous convolution layer, a third batch normalization layer and a third linear rectification function unit, the atrous convolution residual connection branch includes a third convolution layer, a fourth batch normalization layer and a fourth linear rectification function unit, the size of the convolution kernel in the atrous convolution branch and the atrous convolution residual connection branch is different, and the data output by the third batch normalization layer in the atrous convolution branch is merged with the data output by the residual connection branch.

[0012] In an optional implementation of the first aspect, the wafer parameter optical threshold and the multiple translational aerial images are input into the wafer parameter prediction model to obtain wafer parameter prediction values ​​corresponding to the multiple translational aerial images, including: based on the input layer, performing pixel value normalization processing on the multiple translational aerial images to obtain the multiple translational aerial images after the pixel value normalization processing; based on at least one convolutional network module, performing feature extraction on the multiple translational aerial images after the pixel value normalization processing to obtain the multiple translational aerial images with the image resolution of the first resolution and the number of channels of the first predetermined value; based on at least one hole convolutional network module, performing feature extraction on the multiple translational aerial images after the pixel value normalization processing to obtain the multiple translational aerial images with the image resolution of the first resolution and the number of channels of the first predetermined value; The method comprises the following steps: performing feature extraction on a plurality of translational aerial images whose image resolution is the first resolution and whose channel number is the first predetermined value, and obtaining a plurality of translational aerial images whose image resolution is the first resolution and whose channel number is the second predetermined value, wherein the second predetermined value is greater than the first predetermined value; based on the output layer, processing the dimensions of the plurality of translational aerial images whose image resolution is the first resolution and whose channel number is the second predetermined value, and obtaining a plurality of translational aerial images whose image resolution is the second resolution, wherein the second resolution is less than the first resolution; and determining wafer parameter prediction values ​​corresponding to the plurality of translational aerial images based on the plurality of translational aerial images whose image resolution is the second resolution and the optical threshold of the wafer parameter.

[0013] In a second aspect, an embodiment of the present application provides a method for predicting wafer parameters, comprising: obtaining a measured lithography spatial image; and predicting the wafer parameters of the measured lithography spatial image using a wafer parameter prediction model trained using any one of the wafer parameter prediction model training methods in the first aspect.

[0014] In a third aspect, an embodiment of the present application provides a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the training method of the wafer parameter prediction model of the first aspect or the wafer parameter prediction method of the second aspect is implemented.

[0015] In a fourth aspect, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the training method of the wafer parameter prediction model of the first aspect or the wafer parameter prediction method of the second aspect.

[0016] In the training method of the wafer parameter prediction model of the embodiment of the present application, the multiple acquired lithography space images are gridded to obtain multiple grid space images after gridding. For each grid space image, all grids in the grid space image are translated as a whole, and the translation space image corresponding to each grid space image can be obtained, so that multiple translation space images corresponding to multiple grid space images can be obtained. Since all grids in each grid space image are translated as a whole, the grid size in the translation space image and the grid size in the corresponding grid space image are the same. Then, based on the actual values ​​of the wafer parameters corresponding to the multiple translation space images and the multiple lithography space images, the wafer parameter prediction model is trained, so that the trained wafer parameter prediction model can reduce the dependence on the grid size, reduce the number of occurrences of numerical oscillations and instability in the simulation results, and improve the accuracy and reliability of the simulation results. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 It is a flowchart of a method for training a wafer parameter prediction model provided by an embodiment of the present application;

[0019] Figure 2 It is a schematic diagram of performing gridding processing on multiple lithography spatial images to obtain multiple grid spatial images provided by an embodiment of the present application;

[0020] Figure 3 is a schematic diagram of overall translation of all grids of a grid space image provided by an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of overall translation of all grids of a grid space image provided by another embodiment of the present application;

[0022] Figure 5 It is a schematic diagram of interpolating a target grid in a grid space image to obtain a translation space image provided by an embodiment of the present application;

[0023] Figure 6 is a schematic diagram of a convolutional network module provided by an embodiment of the present application;

[0024] Figure 7 is a schematic diagram of a dilated convolutional network module provided by an embodiment of the present application;

[0025] Figure 8It is a schematic diagram of the network structure of a wafer parameter prediction model provided by an embodiment of the present application;

[0026] Fig. 9 It is a flowchart of a method for predicting wafer parameters provided by an embodiment of the present application;

[0027] Fig.10 is a flow chart of a method for predicting wafer parameters provided by another embodiment of the present application;

[0028] Fig.11 It is a structural schematic diagram of a training device for a wafer parameter prediction model provided by an embodiment of the present application;

[0029] Fig.12 It is a structural schematic diagram of a device for predicting wafer parameters provided by an embodiment of the present application;

[0030] Fig.13 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application.

[0031] The above drawings include the following reference numerals:

[0032] 500, target grid; 1100, training device for wafer parameter prediction model; 1110, first acquisition module; 1120, processing module; 1130, translation module; 1140, training module; 1200, wafer parameter prediction device; 1210, second acquisition module; 1220, prediction module; 1301, processor; 1302, memory; 1303, communication interface; 1310, bus. DETAILED DESCRIPTION

[0033] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0034] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0035] At present, photolithography technology has become a crucial step in the chip manufacturing process. In order to achieve higher integration and smaller feature sizes, it is necessary to improve the simulation accuracy and efficiency of photolithography simulation technology. In the photolithography simulation process, the aerial images at different positions on the wafer are usually input into the simulation model to obtain simulation results. Due to the different positions of collecting aerial images, the grid sizes corresponding to the aerial images are inconsistent. The inconsistency of the grid size may cause the simulation results to oscillate, be unstable, or fail to converge. This situation leads to low reliability of the simulation results and has a certain impact on the prediction and optimization of the photolithography process.

[0036] From the above analysis, it can be seen that the grid dependence in lithography simulation can be summarized as the sensitivity of the accuracy of the simulation results to the grid size of the aerial image. Specifically, when the grid size of the aerial image is large, the simulation model cannot accurately capture high-frequency features and complex physical phenomena, resulting in large deviations in wafer parameters. When the grid size of the aerial image is small, the simulation model can more accurately capture complex physical phenomena and tiny geometric features, and can obtain more accurate wafer parameters. However, too small a grid size will make the simulation model computationally intensive. For example, when the simulation model is a neural network model, the smaller the grid size of the aerial image, the more computing units are required. Each computing unit needs to perform complex numerical calculations, resulting in an increase in computing time. Therefore, when processing large-scale or complex lithography simulation tasks, as the grid size decreases, the required storage space and computing resources also increase.

[0037] Therefore, there is an urgent need for a method that can solve the problem of grid dependency while ensuring the accuracy of simulation results.

[0038] In order to solve the above-mentioned problems, the present application provides a method for training a wafer parameter prediction model and a method for predicting wafer parameters. In the method for training a wafer parameter prediction model, a plurality of acquired lithography space images are gridded, and a plurality of grid space images after gridding can be obtained. For each grid space image, all grids in the grid space image are translated as a whole, and a translation space image corresponding to each grid space image can be obtained, so that a plurality of translation space images corresponding to a plurality of grid space images can be obtained. Since all grids in each grid space image are translated as a whole, the grid size in the translation space image and the grid size in the corresponding grid space image are the same. Then, based on the actual values ​​of wafer parameters corresponding to the plurality of translation space images and the plurality of lithography space images, the wafer parameter prediction model is trained, so that the trained wafer parameter prediction model can reduce the dependence on the grid size, reduce the number of occurrences of numerical oscillation and instability in the simulation results, and improve the accuracy and reliability of the simulation results.

[0039] It should be noted that the application scenarios described in the above embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. It is known to those skilled in the art that with the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems. The training method of the wafer parameter prediction model provided in the embodiments of the present application can be applied to various application scenarios in which the wafer parameter prediction model needs to be trained, and the prediction method of the wafer parameters provided in the embodiments of the present application can be applied to various application scenarios in which the wafer parameters need to be predicted.

[0040] Next, the training method of the wafer parameter prediction model in this application is introduced.

[0041] The execution subject of the wafer parameter prediction model training method may be an electronic device or a wafer parameter prediction model training device.

[0042] Figure 1 FIG. 1 is a flow chart of a method for training a wafer parameter prediction model provided by an embodiment of the present application. Figure 1 As shown, the training method of the wafer parameter prediction model in the embodiment of the present application includes steps S101 to S104.

[0043] In step S101 , a plurality of lithography aerial images are acquired.

[0044] During the photolithography process, the light emitted by the light source is homogenized by the illumination system and then irradiated onto a mask with a specific pattern. The pattern on the mask modulates the light so that the light passing through the mask or the light reflected from the mask is focused and imaged on the wafer surface or other specific positions, thereby forming a photolithography spatial image.

[0045] In actual application, multiple lithography aerial images can be collected from one wafer or from multiple wafers.

[0046] There are many ways to obtain multiple lithography spatial images.

[0047] In one embodiment, multiple lithography aerial images can be obtained based on a method of photoresist exposure and development. For example, photoresist is coated on a wafer surface, and photolithography exposure and development processes are performed to convert the light intensity distribution of the lithography aerial image into a pattern structure of the photoresist, thereby obtaining multiple lithography aerial images.

[0048] In another embodiment, multiple lithography aerial images can be obtained by simulation. For example, the information of key points on the wafer is input into the simulation software, and the lighting conditions and simulation conditions are set in the simulation software, and the Hopkins imaging model is used to obtain multiple lithography aerial images. The lighting conditions can be conventional lighting but are not limited to conventional lighting, and the simulation conditions include polarization and numerical aperture (NA), wherein the polarization can be transverse electric (TE) polarization and the NA can be 1.35.

[0049] In step S102, a plurality of lithography aerial images are gridded to obtain a plurality of grid aerial images.

[0050] The gridding process is the process of dividing the two-dimensional plane image into grids in an equidistant or non-equidistant manner.

[0051] like Figure 2 As shown, multiple lithography spatial images are gridded to obtain multiple grid spatial images corresponding to the multiple lithography spatial images. In one embodiment, the grid sizes of the multiple grid spatial images can be dx=28 nanometers (nm) and dy=28nm, where dx is the division of the horizontal axis direction of the lithography spatial image and dy is the division of the vertical axis direction of the lithography spatial image.

[0052] In one embodiment, multiple grid aerial images can be obtained in the following manner. Specifically, the information of key points on the wafer is input into the simulation software, the lighting conditions are set to conventional lighting but not limited to conventional lighting, the polarization is TE polarization, the NA is 1.35, the grid size is dx=28nm and dy is 28nm, and the Hopkins imaging model is used to obtain multiple grid aerial images.

[0053] In step S103, all grids in each grid space image are translated as a whole to obtain a translated space image corresponding to each grid space image.

[0054] There are many ways to translate all grids in each grid space image as a whole to obtain a translated space image corresponding to each grid space image.

[0055] In one embodiment, Figure 3 As shown, a grid space image ( Figure 3 All grids in the spatial image (represented by the solid line in the middle) are translated along the horizontal axis by the target distance (0.5 grids) to obtain the translated spatial image ( Figure 3 The spatial image is represented by the dotted line in the figure).

[0056] In another embodiment, Figure 4 As shown, a grid space image ( Figure 4 All grids in the spatial image (represented by the solid line in the middle) are translated along the vertical axis by the target distance (0.5 grids) to obtain the translated spatial image ( Figure 4 The spatial image is represented by the dotted line in the figure).

[0057] All grids in each grid space image are translated as a whole to obtain the translation space image corresponding to each grid space image, such as Figure 3 and Figure 4 As shown, the grid size in the translational spatial image is the same as the grid size in the corresponding grid spatial image. The translational spatial image is subsequently input into the wafer parameter prediction model. The wafer parameter prediction model can extract more image features, so that the wafer parameter prediction model can predict the wafer parameters more accurately.

[0058] In the actual application process, a grid space image can be translated multiple times to obtain multiple translated space images. The multiple translated space images are input into the wafer parameter prediction model, so that the wafer parameter prediction model can extract more image features, thereby more accurately predicting the wafer parameters. Specifically, all grids in each grid space image are translated as a whole to obtain a translated space image corresponding to each grid space image, including: all grids in each grid space image are translated as a whole multiple times, and each overall translation obtains a translated space image corresponding to each grid space image, wherein the process of multiple overall translations is: the starting position of the next overall translation is the end position of the current overall translation, and for each grid space image, the cumulative step length of multiple overall translations of each grid does not exceed the side length of one grid.

[0059] The following takes the example of performing multiple overall translations on a grid space image along the horizontal axis to obtain multiple translated space images to introduce the multiple overall translation process.

[0060] like Figure 5 As shown, the target grid 500 in the grid space image can be interpolated to obtain the target distance of each overall translation (such as Figure 5 The distance between two adjacent dotted lines shown in FIG. 1 is shown in FIG. 1 ). All grids in the grid space image are translated as a target distance to obtain a translation space image. Then, the end position of the current overall translation is used as the starting position of the next overall translation, and the grid space image is translated as a target distance again to obtain another translation space image. The grid space image is translated according to the above steps until the target grid 500 is translated, and multiple translation space images are obtained. Figure 5 As shown in FIG. 1 , five translational spatial images can be obtained by performing five overall translations on all grids in the grid spatial image.

[0061] Of course, in the process of performing multiple overall translations on all grids in each grid space image, the starting position of each overall translation can be the same. For example, the starting position of each overall translation can be Figure 3 or Figure 4 The starting position shown in is obtained until the total number of overall translations is reached. In addition, the step size of each overall translation may be different.

[0062] In step S104, a wafer parameter prediction model is trained based on the actual values ​​of wafer parameters corresponding to multiple lithography aerial images and multiple translational aerial images to obtain a trained wafer parameter prediction model, wherein the wafer parameter prediction model is constructed based on a neural network model.

[0063] Optionally, the wafer parameters may be the height of the pattern formed on the wafer surface, the spacing between adjacent patterns, and the critical dimension (CD), etc. Specifically, the critical dimension may be the width of the linear pattern on the wafer surface and the diameter of various hole structures, etc. For example, the hole structure may be a contact hole, a via hole, etc.

[0064] There are many ways to train the wafer parameter prediction model to obtain the trained wafer parameter prediction model.

[0065] In one embodiment, based on the actual values ​​of wafer parameters corresponding to multiple lithography spatial images and multiple translational spatial images, the wafer parameter prediction model is trained multiple times, and when the number of training times reaches a preset number of training times, a trained wafer parameter prediction model is obtained.

[0066] In another embodiment, based on the true values ​​of wafer parameters corresponding to multiple lithography aerial images, multiple translation aerial images and a loss function, the wafer parameter prediction model is trained multiple times to obtain a trained wafer parameter prediction model.

[0067] Specifically, an optical threshold of wafer parameters is obtained; the optical threshold of wafer parameters and a plurality of translational spatial images are input into a wafer parameter prediction model to obtain wafer parameter prediction values ​​corresponding to the plurality of translational spatial images; a weighted calculation is performed on the optical threshold of wafer parameters and the predicted values ​​of wafer parameters to obtain a model predicted value; a weighted calculation is performed on the optical threshold of wafer parameters and the true values ​​of wafer parameters to obtain a model true value; based on the model predicted values ​​and the true values ​​of the model, a loss value of a loss function of the wafer parameter prediction model is calculated; based on the loss value, the wafer parameter prediction model is trained to obtain a trained wafer parameter prediction model.

[0068] In this embodiment, in the process of training the wafer parameter prediction model using the true values ​​of the wafer parameters corresponding to multiple lithography spatial images, multiple translational spatial images and the optical thresholds of the wafer parameters, the optical thresholds of the wafer parameters can guide the training of the wafer parameter prediction model, which can improve the reliability and accuracy of the prediction results.

[0069] In one embodiment, obtaining the optical threshold of the wafer parameter includes: determining the optical threshold of the wafer parameter based on the real values ​​of the wafer parameters corresponding to multiple reference grid space images, wherein the grid size of the reference grid space image is smaller than the grid size of the grid space image.

[0070] In this embodiment, the grid size of the reference grid space image is smaller than the grid size of the grid space image, that is, the grid of the reference grid space image is denser than the grid in the grid space image. In this way, the optical threshold of the wafer parameter is determined by using the true values ​​of the wafer parameters corresponding to multiple reference grid space images, so that the determined optical threshold of the wafer parameter is more accurate. Subsequently, the optical threshold of the wafer parameter is used to guide the training of the wafer parameter prediction model, so that the prediction accuracy of the wafer parameter prediction model is higher.

[0071] Optionally, when the wafer parameter is a critical dimension, the wafer parameter optical threshold may be a critical dimension optical threshold.

[0072] In one embodiment, multiple reference grid aerial images can be obtained in the following manner: Specifically, the information of key points on the wafer is input into the simulation software, and the lighting conditions are set to conventional lighting but not limited to conventional lighting, polarization is TE polarization, NA is 1.35, the grid size is dx=7nm, and dy is 7nm, thereby obtaining multiple reference grid aerial images.

[0073] In an optional embodiment, the process of performing weighted calculation on the wafer parameter optical threshold and the wafer parameter prediction value to obtain the model prediction value may include: determining the weight of the wafer parameter optical threshold, and determining the weight of the wafer parameter prediction value; calculating the product of the wafer parameter optical threshold and the weight of the wafer parameter optical threshold, and calculating the product of the wafer parameter prediction value and the weight of the wafer parameter prediction value; calculating the sum of the product of the wafer parameter optical threshold and the weight of the wafer parameter optical threshold and the product of the wafer parameter prediction value and the weight of the wafer parameter prediction value to obtain the model prediction value.

[0074] The process of calculating the true value of the model can refer to the process of calculating the predicted value of the model, which will not be repeated here.

[0075] In one embodiment, the process of constructing the loss function includes: constructing a total loss function based on the sum of squares of differences between model prediction values ​​and model true values ​​corresponding to multiple translational spatial images; and constructing a loss function based on the ratio of the total loss function to the total number of multiple translational spatial images.

[0076] In this embodiment, the optical threshold of the wafer parameter and the predicted value of the wafer parameter are weighted to obtain the model predicted value, and the optical threshold of the wafer parameter and the true value of the wafer parameter are weighted to obtain the true value of the model; based on the model predicted value and the true value of the model, a loss function is constructed, so that the prediction error of the wafer parameter prediction model can be more accurately reflected based on the loss function. Subsequently, the wafer parameter prediction model is trained based on the loss value of the loss function, which can reduce the oscillation and fluctuation of the wafer parameter prediction model during the training process and improve the convergence speed of the wafer parameter prediction model.

[0077] Alternatively, the loss function can be expressed as Among them, Prec is used to represent the model prediction value, Pdef is used to represent the model true value, and T is used to represent the total number of multiple translational spatial images.

[0078] The wafer parameter prediction model of the present application is constructed based on a neural network model. The wafer parameter prediction model at least includes an input layer, at least one convolutional network module, at least one hole convolutional network module and an output layer.

[0079] The convolutional network module includes a convolution branch and a convolutional residual connection branch. The convolution branch includes a first convolutional layer, a first batch normalization layer and a first linear rectification function unit. The convolutional residual connection branch includes a second convolutional layer, a second batch normalization layer and a second linear rectification function unit. The sizes of the convolution kernels in the convolution branch and the convolutional residual connection branch are different. The data output by the first batch normalization layer in the convolution branch is merged with the data output by the convolutional residual connection branch.

[0080] like Figure 6 As shown, the convolutional network module (i.e., CM network module) consists of a convolution branch and a convolutional residual connection branch. Among them, the data input to the convolutional network module is "K×K×D", "K×K" is used to represent the resolution of the input translational spatial image, and D is used to represent the number of channels of the input data. The convolution branch consists of the first convolution layer (Conv), the first batch normalization layer (BatchNorm), and the first linear rectifier function unit (ReLU). The convolution kernel of the first convolution layer in the convolution branch is 3×3, the step size is (2, 2), and the number of channels is N. The convolutional residual connection branch consists of the second convolution layer (Conv), the second batch normalization layer (BatchNorm), and the second linear rectifier function unit. The convolution kernel of the second convolution layer in the convolutional residual connection branch is 1×1, the step size is (2, 2), and the number of channels is N. Setting the size of the convolution kernel in the convolution branch and the convolutional residual connection branch to be different can enable the wafer parameter prediction model to learn more different types of features. For example, the 1×1 convolution kernel can focus on the information interaction and dimensional transformation between channels, and the 3×3 convolution kernel can focus on the extraction of local spatial features. The combined use of 1×1 and 3×3 convolution kernels allows the wafer parameter prediction model to extract richer and more diverse features. In addition, in addition to deepening the structure, the 1×1 convolution kernel in the convolution residual connection branch can also improve nonlinearity by introducing an additional second linear rectifier unit (ReLU). In this scheme, different numbers of channels are set so that the wafer parameter prediction model can extract features from multiple different dimensions. A larger number of channels can enable the wafer parameter prediction model to learn complex functional relationships and improve the expressive power of the wafer parameter prediction model. The convolution branch and the convolution residual connection branch in this scheme form two parallel layers, which can solve the problem of the deepening degradation of the wafer parameter prediction model. Figure 6 As shown, the data input to the CM network module is K×K×B, and the output data is K / 2×K / 2×N. Figure 6 The + in the figure is used to indicate that the data output by the convolution branch and the data output by the convolution residual connection branch are merged together.

[0081] The atrous convolution network module includes a atrous convolution branch and a atrous convolution residual connection branch. The atrous convolution branch includes a atrous convolution layer, a third batch normalization layer and a third linear rectification function unit. The atrous convolution residual connection branch includes a third convolution layer, a fourth batch normalization layer and a fourth linear rectification function unit. The sizes of the convolution kernels in the atrous convolution branch and the atrous convolution residual connection branch are different. The data output by the batch normalization layer in the atrous convolution branch is merged with the data output by the residual connection branch.

[0082] like Figure 7 As shown in the figure, the dilated convolutional network module (i.e., DM network module) consists of a dilated convolution branch and a dilated convolution residual connection branch. The data input to the dilated convolutional network module is "K×K×D", "K×K" is used to represent the resolution of the input translational spatial image, and D is used to represent the number of channels of the input data. The dilated convolution branch consists of a dilated convolution layer (Conv), a third batch normalization layer (BatchNorm), and a third linear rectifier unit (ReLU). The convolution kernel of the dilated convolution layer in the dilated convolution branch is 3×3, the number of channels is N, and the dilation rate (Dilation Rate) = α. The dilated convolution residual connection branch consists of a third convolution layer (Conv), a fourth batch normalization layer (BatchNorm), and a fourth linear rectifier unit (ReLU). The convolution kernel of the third convolution layer in the dilated convolution residual connection branch is 1×1 and the number of channels is N. "ɑ" is used to represent the distance between the convolution kernel parameters in the dilated convolution. The use of dilated convolution can maintain the receptive field of the neural network. like Figure 7 As shown, the data input to the DM network module is K×K×B, and the output data is K / 2×K / 2×N, and Figure 7 The + in the figure indicates that the data output by the dilated convolution branch and the data output by the dilated convolution residual connection branch are merged together.

[0083] Table 1

[0084]

[0085] In an optional embodiment, Figure 8 As shown in Table 1, the network layers in the wafer parameter prediction model may include the input layer ( Figure 8), convolutional layer, batch normalization layer, linear rectifier function unit, three convolutional network modules (CM network modules), two hole convolutional network modules (DM network modules), two convolutional layers, pooling layer, Flatten, two fully connected layers, two linear rectifier function units and output layer ( Figure 8 The sizes of the translational spatial images output by each network layer are shown in Table 1.

[0086] Among them, the two convolutional layers after the DM network module in Table 1 can filter the multiple translational spatial images output by the DM network module to remove the grid artifacts caused by the hole convolution. In addition, the resolution of the multiple translational spatial images output by the output layer can be adjusted according to actual needs, so as to obtain multiple translational spatial images of corresponding resolution or corresponding dimension.

[0087] In one embodiment, the optical threshold of the wafer parameter and the multiple translational aerial images are input into the wafer parameter prediction model to obtain the wafer parameter prediction values ​​corresponding to the multiple translational aerial images, including: based on the input layer, performing pixel value normalization processing on the multiple translational aerial images to obtain the multiple translational aerial images after the pixel value normalization processing; based on at least one convolutional network module, performing feature extraction on the multiple translational aerial images after the pixel value normalization processing to obtain the multiple translational aerial images with the image resolution of the first resolution and the number of channels of the first predetermined value; based on at least one hole convolutional network module, performing feature extraction on the multiple translational aerial images after the pixel value normalization processing to obtain the multiple translational aerial images with the image resolution of the first resolution and the number of channels of the first predetermined value; Performing feature extraction on a plurality of translational aerial images whose channel number is a first predetermined value, obtaining a plurality of translational aerial images whose image resolution is a first resolution and whose channel number is a second predetermined value, wherein the second predetermined value is greater than the first predetermined value; based on the output layer, processing the dimensions of the plurality of translational aerial images whose image resolution is the first resolution and whose channel number is the second predetermined value, obtaining a plurality of translational aerial images whose image resolution is a second resolution, wherein the second resolution is less than the first resolution; determining wafer parameter prediction values ​​corresponding to the plurality of translational aerial images based on the plurality of translational aerial images whose image resolution is the second resolution and the optical threshold value of the wafer parameter.

[0088] By processing multiple translational aerial images using an input layer, at least one convolutional network module, at least one atrous convolutional network module, and an output layer, multiple translational aerial images with an image resolution of the second resolution can be obtained. Based on at least one convolutional network module and at least one atrous convolutional network module, feature extraction is performed on multiple translational aerial images, and more and richer features of multiple translational aerial images can be extracted. Using multiple translational aerial images with an image resolution of the second resolution and a wafer parameter optical threshold, wafer parameter prediction values ​​corresponding to the multiple translational aerial images are determined, so that wafer parameter prediction values ​​of the multiple translational aerial images can be accurately and quickly obtained.

[0089] Optionally, the first resolution may be 32×32, the first predetermined value may be 128, the second predetermined value may be 512, and the second resolution may be 256×1.

[0090] In the actual application process, multiple lithography spatial images and the actual values ​​of wafer parameters corresponding to the multiple lithography spatial images, multiple translational spatial images and wafer parameter optical thresholds can be input into the wafer parameter prediction model. The wafer parameter prediction model processes the multiple translational spatial images to obtain the wafer parameter prediction values ​​and wafer parameter optical thresholds corresponding to the multiple translational spatial images. Afterwards, the wafer parameter prediction model can be reversely trained using the wafer parameter prediction values ​​and wafer parameter optical thresholds corresponding to the multiple translational spatial images. That is, the wafer parameter prediction model is trained through the two processes of forward training and reverse training, so that the trained wafer parameter prediction model can be quickly obtained.

[0091] In the training method of the wafer parameter prediction model of the present application, a plurality of acquired lithography space images are gridded, and a plurality of grid space images after the gridding process can be obtained. For each grid space image, all grids in the grid space image are translated as a whole, and a translation space image corresponding to each grid space image can be obtained, so that a plurality of translation space images corresponding to the plurality of grid space images can be obtained. Since all grids in each grid space image are translated as a whole, the grid size in the translation space image and the grid size in the corresponding grid space image are the same. Then, based on the actual values ​​of the wafer parameters corresponding to the plurality of translation space images and the plurality of lithography space images, the wafer parameter prediction model is trained, so that the trained wafer parameter prediction model can reduce the dependence on the grid size, reduce the number of occurrences of numerical oscillations and instability phenomena in the simulation results, and improve the accuracy and reliability of the simulation results.

[0092] Next, the method for predicting wafer parameters in this application is introduced.

[0093] The execution subject of the wafer parameter prediction method may be an electronic device or a wafer parameter prediction device.

[0094] Fig. 9 FIG. 1 is a flow chart of a method for predicting wafer parameters provided by an embodiment of the present application. Fig. 9 As shown, the method for predicting wafer parameters in the embodiment of the present application includes steps S901 and S902.

[0095] In step S901, a measured lithography aerial image is acquired.

[0096] In step S902 , the wafer parameters of the measured lithography aerial image are predicted using the trained wafer parameter prediction model.

[0097] In the wafer parameter prediction method of the present application, a wafer parameter prediction model is trained based on the actual values ​​of wafer parameters corresponding to multiple lithography space images and multiple translation space images, so that the trained wafer parameter prediction model can accurately predict the predicted values ​​of wafer parameters corresponding to each lithography space image. After obtaining the trained wafer parameter prediction model, the trained wafer parameter prediction model is used to predict the wafer parameters of the measured lithography space image, so that the wafer parameters of the measured lithography space image can be obtained more accurately.

[0098] like Fig.10 As shown, for ease of understanding, the processing of the wafer parameter prediction method of the present application is described below. The wafer parameter prediction method includes steps S1001 to S1005.

[0099] In step S1001, the optical threshold of the wafer parameter is determined based on the real values ​​of the wafer parameters corresponding to the multiple reference grid space images.

[0100] In step S1002, a plurality of lithography aerial images are gridded to obtain a plurality of grid aerial images.

[0101] In step S1003, the plurality of grid space images are translated to obtain translated space images corresponding to the plurality of network space images.

[0102] In step S1004, a wafer parameter prediction model is trained based on the true values ​​of wafer parameters corresponding to the multiple lithography aerial images, the multiple translation aerial images and the wafer parameter optical thresholds to obtain a trained wafer parameter prediction model.

[0103] In step S1005 , the wafer parameters of the measured lithography aerial image are predicted using the trained wafer parameter prediction model.

[0104] The present application utilizes the optical threshold of wafer parameters as a guide to train a wafer parameter prediction model, so that the wafer parameter prediction model can obtain higher accuracy, thereby reducing the number of computing units in the wafer parameter prediction model, and reducing computing time and resource consumption.

[0105] The wafer parameter prediction model trained in this application can reduce the dependence on the grid size. By utilizing the global learning ability of the wafer parameter prediction model, the occurrence of numerical oscillation and instability can be reduced, thereby improving the robustness and reliability of the simulation process.

[0106] It should be noted that the training device of the wafer parameter prediction model is a device corresponding to the training method of the above-mentioned wafer parameter prediction model. All implementation methods in the above-mentioned method embodiments are applicable to the embodiments of the device and can achieve the same technical effects, which will not be repeated here.

[0107] Based on the same inventive concept, the embodiment of the present application also provides a training device for a wafer parameter prediction model. Fig.11 The training device of the wafer parameter prediction model provided in the embodiment of the present application is described in detail.

[0108] The wafer parameter prediction model training device 1100 provided in the embodiment of the present application includes a first acquisition module 1110, a processing module 1120, a translation module 1130 and a training module 1140.

[0109] The first acquisition module 1110 is used to acquire multiple lithography aerial images.

[0110] The processing module 1120 is used to perform gridding processing on the multiple lithography aerial images to obtain multiple grid aerial images.

[0111] The translation module 1130 is used to translate all grids in each grid space image as a whole to obtain a translated space image corresponding to each grid space image.

[0112] The training module 1140 is used to train the wafer parameter prediction model based on the actual values ​​of the wafer parameters corresponding to multiple lithography spatial images and multiple translational spatial images to obtain a trained wafer parameter prediction model, wherein the wafer parameter prediction model is constructed based on a neural network model.

[0113] In one embodiment, the translation module is further used to perform multiple overall translations on all grids in each grid spatial image, and each overall translation obtains a translation spatial image corresponding to each grid spatial image, wherein the process of multiple overall translations is as follows: the starting position of the next overall translation is the end position of the current overall translation, and for each grid spatial image, the cumulative step length of the multiple overall translations of each grid does not exceed the side length of one grid.

[0114] In one embodiment, the training module is also used to obtain the optical threshold of the wafer parameter; input the optical threshold of the wafer parameter and multiple translational spatial images into the wafer parameter prediction model to obtain the wafer parameter prediction values ​​corresponding to the multiple translational spatial images; perform weighted calculation on the optical threshold of the wafer parameter and the wafer parameter prediction value to obtain the model prediction value; perform weighted calculation on the optical threshold of the wafer parameter and the true value of the wafer parameter to obtain the model true value; based on the model prediction value and the model true value, calculate the loss value of the loss function of the wafer parameter prediction model; based on the loss value, train the wafer parameter prediction model to obtain the trained wafer parameter prediction model.

[0115] In one embodiment, the training module is further used to construct a total loss function based on the sum of squares of differences between model prediction values ​​and model true values ​​corresponding to multiple translational spatial images; and to construct a loss function based on the ratio of the total loss function to the total number of multiple translational spatial images.

[0116] In one embodiment, the training module is further used to determine the optical threshold of the wafer parameter based on the real values ​​of the wafer parameters corresponding to the multiple reference grid spatial images, wherein the grid size of the reference grid spatial image is smaller than the grid size of the grid spatial image.

[0117] In one embodiment, the wafer parameter prediction model includes at least an input layer, at least one convolutional network module, at least one void convolutional network module and an output layer, wherein the convolutional network module includes a convolution branch and a convolutional residual connection branch, the convolution branch includes a first convolutional layer, a first batch normalization layer and a first linear rectification function unit, the convolutional residual connection branch includes a second convolutional layer, a second batch normalization layer and a second linear rectification function unit, the convolution branch has a different size of convolution kernel from the convolutional residual connection branch, and the data output by the first batch normalization layer in the convolution branch is merged with the data output by the convolutional residual connection branch; the void convolutional network module includes a void convolution branch and a void convolution residual connection branch, the void convolution branch includes a void convolution layer, a third batch normalization layer and a third linear rectification function unit, the void convolution residual connection branch includes a third convolution layer, a fourth batch normalization layer and a fourth linear rectification function unit, the void convolution branch has a different size of convolution kernel from the void convolution residual connection branch, and the data output by the third batch normalization layer in the void convolution branch is merged with the data output by the residual connection branch.

[0118] In one embodiment, the training module is further used to perform pixel value normalization processing on the multiple translational aerial images based on the input layer to obtain multiple translational aerial images after pixel value normalization processing; based on at least one convolutional network module, perform feature extraction on the multiple translational aerial images after pixel value normalization processing to obtain multiple translational aerial images with image resolution of the first resolution and channel number of the first predetermined value; based on at least one hole convolutional network module, perform feature extraction on the multiple translational aerial images with image resolution of the first resolution and channel number of the first predetermined value to obtain multiple translational aerial images with image resolution of the first resolution and channel number of the second predetermined value, wherein the second predetermined value is greater than the first predetermined value; based on the output layer, process the dimensions of the multiple translational aerial images with image resolution of the first resolution and channel number of the second predetermined value to obtain multiple translational aerial images with image resolution of the second resolution, wherein the second resolution is less than the first resolution; based on the multiple translational aerial images with image resolution of the second resolution and the wafer parameter optical threshold, determine the wafer parameter prediction values ​​corresponding to the multiple translational aerial images.

[0119] like Fig.12 As shown, the wafer parameter prediction device 1200 provided in the embodiment of the present application includes a second acquisition module 1210 and a prediction module 1220 .

[0120] The second acquisition module 1210 is used to acquire the measured lithography aerial image.

[0121] The prediction module 1220 is used to predict the wafer parameters of the measured lithography spatial image by using the trained wafer parameter prediction model.

[0122] Fig.13 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application is shown.

[0123] The electronic device may include a processor 1301 and a memory 1302 storing computer program instructions.

[0124] Specifically, the processor 1301 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0125] The memory 1302 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 1302 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 1302 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 1302 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 1302 is a non-volatile solid-state memory.

[0126] The memory may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium device, an optical storage medium device, a flash memory device, an electrical, optical or other physical / tangible memory storage device. Therefore, typically, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to the first aspect or the second aspect of the present application.

[0127] The processor 1301 reads and executes computer program instructions stored in the memory 1302 to implement any one of the wafer parameter prediction model training methods or wafer parameter prediction methods in the above embodiments.

[0128] In one example, the electronic device may further include a communication interface 1303 and a bus 1310. Fig.13 As shown, the processor 1301, the memory 1302, and the communication interface 1303 are connected via a bus 1310 and communicate with each other.

[0129] The communication interface 1303 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0130] Bus 1310 includes hardware, software or both parts coupled to each other.For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 1310 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the application considers any suitable bus or interconnection.

[0131] The electronic device can execute the training method of the wafer parameter prediction model or the wafer parameter prediction method in the embodiment of the present application, thereby realizing the combination Figures 1 to 10 A training method for a wafer parameter prediction model or a wafer parameter prediction method is described.

[0132] In addition, in combination with the training method of the wafer parameter prediction model or the wafer parameter prediction method in the above embodiments, the embodiments of the present application may provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any one of the wafer parameter prediction model training methods or wafer parameter prediction methods in the above embodiments is implemented.

[0133] An embodiment of the present application also provides a computer program product, including a computer program, which, when executed, implements any one of the wafer parameter prediction model training methods or wafer parameter prediction methods in the above-mentioned embodiments.

[0134] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0135] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0136] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0137] The above reference is according to the method of the embodiment of the present application, the flow chart of the device (system) and the computer program product and / or the block diagram described various aspects of the present application.It should be understood that each square box in the flow chart and / or the block diagram and the combination of each square box in the flow chart and / or the block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the realization of the function / action specified in one or more square boxes of the flow chart and / or the block diagram.Such a processor can be but is not limited to a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit.It can also be understood that each square box in the block diagram and / or the flow chart and the combination of the square boxes in the block diagram and / or the flow chart can also be realized by the dedicated hardware that performs the specified function or action, or can be realized by the combination of dedicated hardware and computer instructions.

[0138] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A training method for a wafer parameter prediction model, characterized in that: include: Acquire multiple lithography spatial images; Performing gridding processing on the plurality of lithography aerial images to obtain a plurality of grid aerial images; Performing overall translation of all grids in each grid space image to obtain a translation space image corresponding to each grid space image; Based on the actual values ​​of the wafer parameters corresponding to the multiple lithography spatial images and the multiple translational spatial images, a wafer parameter prediction model is trained to obtain the trained wafer parameter prediction model, wherein the wafer parameter prediction model is constructed based on a neural network model.

2. The method according to claim 1, characterized in that All grids in each grid space image are translated as a whole to obtain a translated space image corresponding to each grid space image, including: All grids in each of the grid space images are translated as a whole for multiple times, and each overall translation obtains a translated space image corresponding to each of the grid space images, wherein the process of multiple overall translations is as follows: the starting position of the next overall translation is the ending position of the current overall translation, and for each of the grid space images, the cumulative step length of the multiple overall translations of each grid does not exceed the side length of one grid.

3. The method according to claim 1, characterized in that Based on the wafer parameter true values ​​corresponding to the plurality of lithography aerial images and the plurality of translation aerial images, a wafer parameter prediction model is trained to obtain the trained wafer parameter prediction model, including: Obtaining optical thresholds of wafer parameters; Inputting the wafer parameter optical threshold and the plurality of translational spatial images into the wafer parameter prediction model to obtain wafer parameter prediction values ​​corresponding to the plurality of translational spatial images; Performing weighted calculation on the wafer parameter optical threshold and the wafer parameter prediction value to obtain a model prediction value; Performing weighted calculation on the wafer parameter optical threshold and the wafer parameter true value to obtain a model true value; Based on the model predicted value and the model true value, calculating the loss value of the loss function of the wafer parameter prediction model; Based on the loss value, the wafer parameter prediction model is trained to obtain the trained wafer parameter prediction model.

4. The method according to claim 3, characterized in that The process of constructing the loss function includes: constructing a total loss function based on the sum of squares of differences between the model prediction values ​​corresponding to the plurality of translational spatial images and the model true values; The loss function is constructed based on a ratio of the total loss function to the total number of the plurality of translational spatial images.

5. The method according to claim 3, characterized in that: Obtain optical thresholds of wafer parameters, including: The wafer parameter optical threshold is determined based on the real values ​​of the wafer parameters corresponding to a plurality of reference grid aerial images, wherein the grid size of the reference grid aerial image is smaller than the grid size of the grid aerial image.

6. The method according to claim 3, characterized in that: The wafer parameter prediction model at least includes an input layer, at least one convolutional network module, at least one hole convolutional network module and an output layer, wherein: The convolution network module includes a convolution branch and a convolution residual connection branch, the convolution branch includes a first convolution layer, a first batch normalization layer and a first linear rectification function unit, the convolution residual connection branch includes a second convolution layer, a second batch normalization layer and a second linear rectification function unit, the convolution branch and the convolution residual connection branch have different sizes of convolution kernels, and the data output by the first batch normalization layer in the convolution branch is merged with the data output by the convolution residual connection branch; The atrous convolution network module includes a atrous convolution branch and a atrous convolution residual connection branch, the atrous convolution branch includes a atrous convolution layer, a third batch normalization layer and a third linear rectification function unit, the atrous convolution residual connection branch includes a third convolution layer, a fourth batch normalization layer and a fourth linear rectification function unit, the size of the convolution kernel in the atrous convolution branch is different from that in the atrous convolution residual connection branch, and the data output by the third batch normalization layer in the atrous convolution branch is merged with the data output by the residual connection branch.

7. The method according to claim 6, characterized in that Inputting the wafer parameter optical threshold and the plurality of translational spatial images into the wafer parameter prediction model to obtain wafer parameter prediction values ​​corresponding to the plurality of translational spatial images, comprises: Based on the input layer, pixel value normalization processing is performed on the plurality of translational spatial images to obtain the plurality of translational spatial images after pixel value normalization processing; Based on the at least one convolutional network module, feature extraction is performed on the plurality of translational spatial images after pixel value normalization processing to obtain the plurality of translational spatial images having an image resolution of a first resolution and a channel number of a first predetermined value; Based on the at least one atrous convolutional network module, feature extraction is performed on a plurality of the translational aerial images having an image resolution of the first resolution and a number of channels of the first predetermined value, to obtain a plurality of the translational aerial images having an image resolution of the first resolution and a number of channels of a second predetermined value, wherein the second predetermined value is greater than the first predetermined value; Based on the output layer, processing the dimensions of the plurality of translational aerial images having the first resolution and the second predetermined number of channels to obtain the plurality of translational aerial images having the second resolution, wherein the second resolution is smaller than the first resolution; Based on the plurality of the translational aerial images having an image resolution of the second resolution and the wafer parameter optical threshold, wafer parameter prediction values ​​corresponding to the plurality of the translational aerial images are determined.

8. A method for predicting wafer parameters, characterized in that: include: Obtaining a measured lithography aerial image; The wafer parameter prediction model trained by the method described in any one of claims 1 to 7 is used to predict the wafer parameters of the measured lithography aerial image.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the training method for a wafer parameter prediction model as described in any one of claims 1 to 7 or the wafer parameter prediction method as described in claim 8.

10. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the training method of the wafer parameter prediction model as described in any one of claims 1 to 7 or the wafer parameter prediction method as described in claim 8.

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