Synchronous clock signal generation circuit and voltage conversion circuit

Abstract

The embodiment of the invention relates to a synchronous clock signal generation circuit and a voltage conversion circuit. A plurality of power supplies are electrically connected together to form a multiphase switch converter, wherein one is a host and the other is a slave. Each voltage conversion circuit comprises a synchronous clock signal generation circuit, and the synchronous clock signal generation circuit comprises an identification circuit, a monopulse trigger, a first logic circuit, a first time delay circuit, a second time delay circuit and a second logic circuit. The voltage conversion circuit in the host can automatically generate a synchronous clock signal and transmit the synchronous clock signal to the slave through the synchronous pin, and the voltage conversion circuit in each slave can delay the synchronous clock signal generated by the host to a corresponding phase according to requirements and generate a synchronous clock signal required by the slave. According to the scheme, synchronization and phase dislocation of the multi-phase switching converter can be achieved only through one pin, the structure is simple, power consumption is low, and efficiency is high.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and more particularly to synchronous clock signal generating circuits and voltage conversion circuits. Background Art

[0002] With the development of electronic technology, more and more high-performance modules (such as central processing units in servers, communication equipment, etc.) require higher current and lower voltage power supply. This puts higher requirements on the design of switching converters.

[0003] Multiphase switching converters are widely used in power solutions for high-performance central processing units due to their superior performance. Multiphase switching converters can adopt an architecture mode in which each switching converter is controlled individually, or an architecture mode in which a master-slave cascade control is adopted. For the architecture mode in which a master-slave cascade control is adopted, the total number of phases of the multiphase switch can be easily adjusted according to the needs of the specific application, and there is no need to adjust the control circuit logic and structure of each phase circuit. It has good scalability and is therefore widely used in multiphase switching converters. In a multiphase switching converter, a synchronous clock signal is required to synchronize each phase circuit and control the phase shift. In the prior art, two pins are usually used, such as SYNIN and SYNOUT, to respectively realize the reception of the synchronous clock signal and the output of the synchronous clock signal after the phase shift. These designs are relatively complex, require two pins, and are not advantageous in terms of chip area consumption. Summary of the invention

[0004] The purpose of the present invention is to solve the above problems in the prior art and to provide a synchronous clock signal generating circuit and a related voltage conversion circuit.

[0005] According to one aspect of the present invention, a synchronous clock signal generating circuit is provided. The synchronous clock signal generating circuit is used to provide a synchronous clock signal for a voltage conversion circuit. The voltage conversion circuit includes a synchronous pin. The synchronous pins of multiple voltage conversion circuits are coupled together to form a multi-phase switching converter, in which one voltage conversion circuit serves as a host and the other voltage conversion circuits serve as slaves. The synchronous clock signal generating circuit includes: an identification circuit for generating an identification signal, and the identification signal is used to identify each phase voltage conversion circuit; a single pulse trigger, which receives a synchronous clock signal and generates a single pulse signal at the edge of the synchronous clock signal; a first logic circuit, which has a first input terminal, a second input terminal, a third input terminal and an output terminal. The first input terminal of the first logic circuit receives an enable signal, the second input terminal of the first logic circuit is coupled to the single pulse signal, the third input terminal of the first logic circuit is coupled to the synchronous pin, and the fourth input terminal of the first logic circuit receives an identification signal. The first logic circuit performs a logical operation on the enable signal, the single pulse signal, the voltage signal on the synchronous pin and the identification signal to generate a first logic signal. The first logic circuit The signal is used to set the starting time of the synchronous clock signal; the first delay circuit receives the first logic signal and the identification signal, and starts the timing of the first time length according to the first logic signal and the identification signal to output the first delay signal, wherein, when the identification signal identifies the voltage conversion circuit as the host, the first time length is the period of the synchronous clock signal; when the identification signal identifies the voltage conversion circuit as the slave, the first time length is the phase difference between the synchronous clock signal generated by the slave and the synchronous clock signal generated by the host; the second delay circuit receives the synchronous clock signal, and starts the timing of the second time length according to the synchronous clock signal to output the second delay signal, and the second time length is the pulse width of the synchronous clock signal; the second logic circuit receives the enable signal, the first delay signal and the second delay signal, and performs logic operations on the enable signal, the first delay signal and the second delay signal, and then generates a synchronous clock signal at its output end; wherein, when the identification signal identifies the voltage conversion circuit as the host, the synchronous clock signal generating circuit will also output the synchronous clock signal through the synchronous pin.

[0006] According to another aspect of the present invention, a voltage conversion circuit is provided. The voltage conversion circuit includes: the synchronous clock signal generating circuit as described above, which is used to generate a synchronous clock signal; a power switch; and a control unit, which receives a feedback signal and a synchronous clock signal, and generates a control signal according to the feedback signal and the synchronous clock signal, wherein the feedback signal represents the output voltage of the voltage conversion circuit, and the control signal is used to adjust the on-time and off-time of the power switch, thereby converting the input voltage received by the voltage conversion circuit into an output voltage.

[0007] By using the embodiments of the present disclosure, the transmission of the synchronous clock signal of the multi-phase switching converter can be realized by only using one pin. The voltage conversion circuit in the host can generate the synchronous clock signal by itself and transmit the synchronous clock signal to the slave through the synchronous pin. The voltage conversion circuit in each slave can delay the synchronous clock signal generated by the host by the corresponding phase as required and generate the synchronous clock signal required by the slave. This solution can realize the synchronization and phase shift of the multi-phase switching converter, has a simple structure, low power consumption, and high efficiency, and achieves the desired technical effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 1 is a circuit diagram of a multi-phase switching converter cascade system 100 according to an embodiment of the present invention;

[0009] Figure 2 FIG. 1 is a schematic diagram of the internal circuit structure of a voltage conversion circuit 1N according to an embodiment of the present invention;

[0010] Figure 3 FIG. 2 is a circuit schematic diagram showing a synchronous clock signal generating circuit according to an embodiment of the present invention.

[0011] Figure 4 According to the present invention Figure 3 The embodiment illustrates a schematic diagram of waveforms of relevant parameters of a host in a two-phase switching converter cascade system;

[0012] Figure 5 According to the present invention Figure 3 The embodiment illustrates a schematic diagram of waveforms of relevant parameters of a slave in a two-phase switching converter cascade system;

[0013] Figure 6 According to one embodiment of the present invention, a circuit schematic diagram of the identification circuit 31 and the first delay circuit 34 in the synchronous clock signal generating circuit 21 is shown;

[0014] Figure 7 A circuit schematic diagram of the second delay circuit 35 is shown according to an embodiment of the present invention.

[0015] As shown in the accompanying drawings, the same reference numerals refer to the same parts in all the different views. The accompanying drawings provided herein are for the purpose of illustrating embodiments, principles, concepts, etc., and are not drawn to scale. DETAILED DESCRIPTION

[0016] Next, a non-restrictive description of the specific embodiments of the present invention will be made in conjunction with the accompanying drawings. References to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" that appear throughout this specification do not necessarily all refer to the same embodiment. The verbs "include" and "have" are used as open restrictions in this article, which neither exclude nor require the existence of undescribed features. Unless otherwise clearly stated, the features recorded in the dependent claims can be freely combined with each other. The elements defined by "one" or "one" (i.e., singular form) throughout the document do not exclude the possibility of multiple elements. Further, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connection" is used to specify the direct electrical connection between circuit elements, while the term "coupling" is used to specify the electrical connection between circuit elements that can be direct or can be via one or more other elements. On the contrary, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The term "and / or" as used herein includes any and all combinations of one or more related listed items. When referring to the voltage of a node or terminal, unless otherwise indicated, the voltage is considered to be the voltage between the node and a reference potential (usually ground). In addition, when referring to the potential of a node or terminal, unless otherwise indicated, the potential is considered to refer to the reference potential. The voltage and potential of a given node or a given terminal will be further designated with the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals of the same electronic circuit may be different. In particular, the high and low states of a logic signal may correspond to a voltage or current that may not be completely constant in a high or low state.

[0017] Figure 1 FIG. 1 is a schematic diagram of a multi-phase switching converter cascade system 100 according to an embodiment of the present invention. Figure 1 In the illustrated embodiment, the multi-phase switching converter cascade system 100 includes N voltage conversion circuits 11, 12, ..., 1N connected in parallel, for providing the same output voltage VOUT, each voltage conversion circuit serving as a phase circuit of the multi-phase switching converter cascade system 100, wherein N is an integer greater than or equal to 2. In one embodiment, a plurality of parallel voltage conversion circuits are illustrated as integrated circuit chips with the same structure and function, and those skilled in the art should understand that the multi-phase parallel switching multi-phase switching converter cascade system 100 can arbitrarily select the number of voltage conversion circuits according to the requirements of system power and load.

[0018] In one embodiment, the N voltage conversion circuits 11, 12, ..., 1N are configured in a master-slave cascade operation mode, wherein one phase circuit is configured as a master and the remaining phase circuits are configured as slaves. Figure 1 In the embodiment shown, the voltage conversion circuit 11 is set as a master, and the remaining voltage conversion circuits 12, ..., 1N are set as slaves. Figure 1 In the illustrated embodiment, each voltage conversion circuit includes a plurality of pins. For the sake of simplicity and clarity, only the pins used for illustration are shown. Figure 1 The pins of the working principle of the embodiment are shown, and other pins are not shown. Figure 1 In the illustrated embodiment, each voltage conversion circuit includes an input pin IN, a switch pin SW, a feedback pin FB, a current sharing pin IBAL, a mode pin MODE and a synchronization pin SYN.

[0019] See also Figure 1 The input pin IN is used to receive the input voltage VIN; the switch pin SW provides the switch voltage VSW; the voltage conversion circuit also includes a power unit. The power unit includes at least one power switch, and the input voltage VIN received by the input pin IN is converted into the switch voltage VSW at the switch pin SW by controlling the on and off switching of at least one power switch.

[0020] The feedback pin FB is used to receive a voltage feedback signal VFB representing the output voltage VOUT of the multi-phase switching converter cascade system 100. Figure 1 In the illustrated embodiment, the output voltage VOUT generates a voltage feedback signal VFB through a voltage dividing resistor.

[0021] Continue to see Figure 1 In the application scenario where multiple voltage conversion circuits are cascaded into a multi-phase multi-phase switching converter cascade system 100, the current sharing pins IBAL of each voltage conversion circuit are connected together to control the output current of each voltage conversion circuit so that the output current of each voltage conversion circuit is equal. In the application scenario where the voltage conversion circuit is used alone, the current sharing pins IBAL of the voltage conversion circuit are floating and kept in an open circuit state.

[0022] The mode pin MODE is used to determine the master and slave in multiple voltage conversion circuits, as well as the order of each phase circuit. Figure 1In the illustrated embodiment, a first resistor is electrically connected between the mode pin MODE and the reference ground, thereby generating a voltage signal on the mode pin, and an identification circuit inside the voltage conversion circuit identifies whether the voltage conversion circuit is a master or a slave, and the order of each phase circuit according to the voltage on the mode pin. The resistance values ​​of the first resistors coupled to the mode pins of each voltage conversion circuit are not equal. In another embodiment, the mode pin of the voltage conversion circuit can be connected to an externally provided digital signal, and the identification circuit inside the voltage conversion circuit identifies whether the voltage conversion circuit is a master or a slave, and the order of each phase circuit according to the external digital signal.

[0023] The synchronization pin SYN is used to synchronize each voltage conversion circuit in an application where multiple voltage conversion circuits are cascaded into a multi-phase switch converter cascade system 100. Here, "synchronization" means that the corresponding power switches in each voltage conversion circuit are turned on in sequence with the same phase delayed. The synchronization pins SYN of each voltage conversion circuit are coupled together, and the voltage conversion circuit as the host will generate a synchronization clock signal and transmit the synchronization clock signal to the voltage conversion circuit as the slave through the synchronization pin SYN.

[0024] In other embodiments, the voltage conversion circuit further includes other pins, such as a ground pin GND, etc. In order not to obscure the key points of the present invention, these pins are not described again.

[0025] exist Figure 1 In the illustrated embodiment, the switching converter cascade system 100 further includes N output inductors, an output capacitor Cout, and a feedback circuit. Specifically, the output inductor L1 is coupled between the pin SW of the voltage conversion circuit 11 and the output end of the switching converter cascade system 100; the output inductor L2 is coupled between the pin SW of the voltage conversion circuit 12 and the output end of the switching converter cascade system 100. Similarly, the output inductor LN is coupled between the pin SW of the voltage conversion circuit 1N and the output end of the switching converter cascade system 100. The output capacitor Cout is coupled between the output end of the switching converter cascade system 100 and the reference ground.

[0026] Those skilled in the art will understand that Figure 1 In the illustrated embodiments, the inductor is shown as being outside the voltage conversion circuit. In other embodiments, the inductor may be integrated inside the voltage conversion circuit as a part of the power unit. That is, the power unit includes the inductor in addition to the upper switch tube and the lower switch tube. Figure 1 In the illustrated embodiment, N phase circuits are illustrated as operating in a cascade control manner, but each phase circuit has an independent control circuit and power unit, so in some other embodiments, each phase circuit can operate independently as a single-phase circuit even when no other phase circuits exist.

[0027] Figure 2 FIG. 1 is a schematic diagram of the internal circuit structure of a voltage conversion circuit 1N according to an embodiment of the present invention. Figure 2 In the illustrated embodiment, the power unit in the voltage conversion circuit 1N includes an upper switch tube HS and a lower switch tube LS. The upper switch tube HS and the lower switch tube LS are connected in series between the input pin IN and the reference ground, and their common node is coupled to the switch pin SW. By controlling the on and off time of the upper switch tube HS and the lower switch tube LS, the input voltage VIN received by the voltage conversion circuit is converted into the final output voltage VOUT.

[0028] exist Figure 2 In the illustrated embodiment, the upper switch tube HS and the lower switch tube LS are both illustrated as metal semiconductor field effect transistors (MOSFET), but those skilled in the art can understand that the upper switch tube HS and the lower switch tube LS can also be other suitable controllable semiconductor power switch devices. At the same time, the power unit may not be a BUCK topology, but other suitable types of isolated or non-isolated topologies, such as BOOST topology, BUCK-BOOST topology, Z-type topology, CUK topology, FLYBACK topology, etc.

[0029] exist Figure 2 In the illustrated embodiment, each voltage conversion circuit 1N includes a synchronization signal generating circuit 21 and a control unit 22. The synchronization signal generating circuit 21 is coupled to the synchronization pin SYN and the mode pin MODE, and generates a synchronization clock signal CLK_N. The control unit 22 receives the feedback signal VFB and the synchronization clock signal CLK_N, and generates control signals CH and CL according to the feedback signal VFB and the synchronization clock signal CLK_N, which are used to control the on and off time of the upper switch tube HS and the lower switch tube LS, respectively. In one embodiment, the control signals CH and CL are complementary signals.

[0030] In one embodiment, the voltage conversion circuit 1N further includes a current sharing circuit 23. The current sharing circuit 23 generates a current sharing adjustment signal. At this time, the control unit 22 further receives the current sharing adjustment signal and generates a control signal according to the feedback signal VFB, the synchronous clock signal CLK_N and the current sharing adjustment signal.

[0031] Figure 3 According to one embodiment of the present invention, a circuit schematic diagram of a synchronous clock signal generating circuit is shown. Figure 3As shown, the synchronous clock signal generating circuit 21 is used to provide a synchronous clock signal CLK_N for the voltage conversion circuit. The synchronous clock signal generating circuit 21 includes an identification circuit 31, a single pulse trigger 32, a first logic circuit 33, a first delay circuit 34, a second delay circuit 35 and a second logic circuit 36.

[0032] The identification circuit 31 is used to generate an identification signal, and the identification signal is used to identify each phase voltage conversion circuit. In one embodiment, the identification signal is used to identify each phase voltage conversion circuit, including determining whether each voltage conversion circuit is a master or a slave, and the order between each phase circuit. In one embodiment, the identification signal includes a plurality of logic high and low level signals, one of which can be used as a master-slave indication signal, and the master-slave indication signal is used to indicate whether the voltage conversion circuit is a master or a slave. For example, in Figure 3 In the illustrated embodiment, the identification signal is indicated as MS-all, and the identification signal MS-all includes a plurality of logic high and low level signals, wherein one of the logic high and low level signals M / S can be used as a master-slave indication signal (hereinafter collectively referred to as "master-slave indication signal M / S") to indicate that the voltage conversion circuit is a master or a slave. In other embodiments, the identification circuit can also generate a master-slave indication signal M / S alone to indicate that the voltage conversion circuit is a master or a slave, rather than selecting one of the plurality of logic high and low level signals as the master-slave indication signal, which are all within the scope of the embodiments disclosed in the present invention.

[0033] The one-shot trigger 32 receives the synchronous clock signal CLK_N and generates a one-shot pulse signal Va at the edge of the synchronous clock signal CLK_N. In one embodiment, the one-shot trigger 32 generates a positive one-shot pulse signal Va at the rising edge of the synchronous clock signal CLK_N.

[0034] The first logic circuit 33 has a first input terminal, a second input terminal, a third input terminal and an output terminal. The first input terminal of the first logic circuit 33 receives an enable signal EN, the second input terminal of the first logic circuit 33 is coupled to the single pulse signal Va, the third input terminal of the first logic circuit 33 is coupled to the synchronization pin SYN, and the fourth input terminal receives the master-slave indication signal M / S. The first logic circuit 33 performs a logic operation on the enable signal EN, the single pulse signal, the level signal on the synchronization pin SYN, and the master-slave indication signal M / S to generate a first logic signal, and the first logic signal is used to set the starting time of the synchronization clock signal CLK_N. In one embodiment, the synchronization pin SYN receives a logic high and low level signal, which has two states: a logic high level and a logic low level. Figure 3 In the illustrated embodiment, the first logic circuit is shown as two inverters, an AND gate and a first RS trigger 331, and the connection relationship thereof is as follows: Figure 3 As shown, the working principle will be further described in combination with a specific circuit later.

[0035] The first delay circuit 34 receives the first logic signal and the identification signal MS-all, and starts timing the first duration according to the first logic signal and the identification signal MS-all to output the first delay signal Vd. When the identification signal MS-all identifies the voltage conversion circuit as a host, the first duration is the period of the synchronous clock signal CLK_N; when the identification signal MS-all identifies the voltage conversion circuit as a slave, the first duration is the phase difference between the synchronous clock signal generated by the slave and the synchronous clock signal generated by the host. In one embodiment, the phase difference is determined by the number of phases of the multi-phase switching converter. For different slaves, the first duration of the first delay circuit timing is different. For example, in a two-phase switching converter, that is, including two voltage conversion circuits, the voltage conversion circuit 11 is set as the master, and the voltage conversion circuit 12 is set as the slave, then the first time length set by the first delay circuit in the voltage conversion circuit 11 is the period of the synchronous clock signal CLK_1, and the first time length set by the first delay circuit in the voltage conversion circuit 12 is the phase difference between the synchronous clock signal CLK_2 generated by it and the synchronous clock signal CLK_1 generated by the voltage conversion circuit 11. At this time, the phase difference between CLK_2 and CLK_1 is 180°, and the first time length set by the first delay circuit in the voltage conversion circuit 12 is half of the period of the synchronous clock signal CLK_1. For another example, in a three-phase switching converter, the voltage conversion circuit 11 is set as the master, and the voltage conversion circuits 12 and 13 are set as slaves, then the first time length set by the first delay circuit in the voltage conversion circuit 11 is the period of the synchronous clock signal CLK_1, the phase difference between CLK_2 and CLK_1 is 120°, and the phase difference between CLK_3 and CLK_1 is 240°. At this time, the first time length set by the first delay circuit in the voltage conversion circuit 12 is 1 / 3 of the cycle of CLK_1, and the first time length set by the first delay circuit in the voltage conversion circuit 13 is 2 / 3 of the cycle of the synchronous clock signal CLK_1.

[0036] The second delay circuit 35 receives the synchronous clock signal CLK_N, and starts timing the second time length according to the synchronous clock signal CLK_N to output the second delay signal Ve, wherein the second time length is the pulse width of the synchronous clock signal CLK_N. In one embodiment, the second time length is the high level pulse width of the synchronous clock signal CLK_N.

[0037] The second logic circuit 36 ​​has a first input terminal, a second input terminal, a third input terminal and an output terminal. The first input terminal of the second logic circuit 36 ​​receives the enable signal EN, the second input terminal of the second logic circuit 36 ​​receives the first delay signal Vd, and the third input terminal of the second logic circuit 36 ​​receives the second delay signal and the first delay signal Vd. The second logic circuit 36 ​​performs a logic operation on the enable signal EN, the first delay signal Vd and the second delay signal Ve, and then generates a synchronous clock signal CLK_N at its output terminal. Figure 3 In the illustrated embodiment, the second logic circuit is illustrated as two inverters, an OR gate, and a second RS flip-flop 361, and the connection relationship thereof is as follows: Figure 3 As shown, the working principle will be further described in combination with a specific circuit later.

[0038] In one embodiment, when the identification signal M / S identifies that the voltage conversion circuit is a host, the synchronous clock signal CLK_N is output through the synchronization pin. That is to say, the synchronous clock signal CLK_N generated by the voltage conversion circuit as a host will also be output through the synchronization pin SYN, and the synchronous clock signal CLK_N generated by the voltage conversion circuit as a slave does not need to be output through the synchronization pin SYN. ​​In one embodiment, the synchronous clock signal generating circuit 21 also includes a master-slave switch 37, a first end of the master-slave switch 37 is coupled to the output end of the second logic circuit 36, a second end of the master-slave switch 37 is coupled to the synchronization pin SYN, and the control end of the master-slave switch receives the master-slave indication signal M / S. When the voltage conversion circuit acts as a host, the master-slave switch 37 is turned on, and when the voltage conversion circuit acts as a slave, the master-slave switch 37 is turned off. In other embodiments, it is also possible not to use a switch, but to use other devices or circuits to control whether the synchronous clock signal CLK_N is sent to the synchronization pin SYN.

[0039] Understandably, Figure 3 The schematic diagrams of a specific embodiment of the first logic circuit and the second logic circuit are respectively illustrated. This is only a schematic display for illustrating the function of the logic circuit. In other embodiments, the first logic circuit and the second logic circuit can also use other logic devices to achieve the same logic function, which is not limited here.

[0040] Figure 4 and Figure 5 According to the present invention Figure 3 The embodiment illustrates a schematic diagram of waveforms of relevant parameters in a two-phase switching converter cascade system, wherein: Figure 4 FIG. 1 shows waveforms of relevant parameters in the synchronous clock signal generating circuit in the voltage conversion circuit 11 as the host. Figure 5 Shown are the relevant parameter waveforms in the synchronous clock signal generating circuit in the voltage conversion circuit 12 as a slave.

[0041] Figure 4 From top to bottom, the waveforms of the enable signal EN in the voltage conversion circuit 11 as the host, the single pulse signal Va, the master-slave indication signal M / S, the output level Vb of the AND gate in the first logic circuit 33, the output level Vc of the first logic circuit 33, the first delay signal Vd, the second delay signal Ve and the synchronous clock signal CLK_1 are respectively illustrated.

[0042] Next, we will combine Figure 3 and Figure 4 The working principle of the synchronization signal generating circuit 21 in the voltage conversion circuit 11 (hereinafter referred to as the "host") as the host is described below. Figure 4 and Figure 5 In the principle description of the waveform, a logic high level is represented by "1" and a logic low level is represented by "0".

[0043] Because the voltage conversion circuit 11 is the master, the master-slave indication signal M / S is 1, and regardless of the level state of the input signal of the synchronization pin SYN of the host 11, the level Vb of the AND gate output terminal in the first logic circuit 33 is 1.

[0044] Before time t1, when the enable signal EN is 1, the RS flip-flop 331 is enabled and turned off, and the output of the RS flip-flop 331 is 0, so the output level Vc of the first logic circuit 33 is 1, the first delay circuit 34 is not started, and the first delay signal Vd outputted by it is 1. At the same time, because the enable signal EN is 1, the RS flip-flop 361 is enabled and turned off, and the output level of the RS flip-flop 361 is 0. Similarly, because the enable signal EN is 1, the synchronous clock signal CLK_1 is 0. The second delay circuit 35 is also not started, and the output second delay signal Ve is 1.

[0045] At time t1, the enable signal EN changes from 1 to 0. Since the output level of the RS trigger 361 is still 0, the synchronous clock signal CLK_1 changes to 1. At this time, the single pulse trigger 32 generates a single pulse signal Va with a certain pulse width (for example, 10ns) at the rising edge of the synchronous clock signal CLK_1. Vb is still 1, so Vc continues to be a high level 1 for the pulse width of the single pulse signal Va and then changes to 0. The first delay circuit 34 starts timing the first duration T1, and the first delay signal Vd outputted by it remains at 1 until the timing ends at time t3.

[0046] At the same time, at time t1, after the synchronous clock signal CLK_1 becomes 1, the second delay circuit 35 also starts timing, and the second delay signal Ve outputted by it is 1. When the timing of the second duration (for example, 150ns) ends at time t2, Ve becomes 0, and the output level of the RS trigger 361 becomes 1, and the synchronous clock signal CLK_1 becomes 0. Subsequently, when the first duration (for example, 2us, corresponding to a frequency of 500kHz) of the timing of the first delay circuit 34 ends at time t3, Vd becomes 0, the output level of the RS trigger 361 becomes 0, and the synchronous clock signal CLK_1 becomes 1 again. When the synchronous clock signal CLK_1 becomes 1 again, the single pulse signal Va becomes 1 again briefly, and Vc becomes 1 briefly and then returns to 0 again. The first delay circuit 34 is reset and the delay timing of the first duration is restarted. By repeating the above process, the synchronous clock signal generating circuit can generate a synchronous clock signal CLK_1 with a period of the first duration (2us) and a high level width of the second duration (150ns).

[0047] In addition, the master-slave switch 37 is turned on by the master-slave indication signal M / S, and the synchronous clock signal CLK_1 generated by the voltage conversion circuit 11 as the master is output through the synchronous pin SYN.

[0048] Figure 5 From top to bottom, the figure illustrates the waveform of the enable signal EN in the voltage conversion circuit 12 as a slave, the single pulse signal Va, the master-slave indication signal M / S, the output level Vb of the AND gate in the first logic circuit 33, the output level Vc of the first logic circuit 33, the first delay signal Vd, the second delay signal Ve and the synchronous clock signal CLK_2, and the synchronous clock signal CLK_1 generated by the host voltage conversion circuit 11.

[0049] Next, we will combine Figure 3 and Figure 5 The working principle of the synchronization signal generating circuit 21 in the voltage conversion circuit 12 as a slave is described as follows.

[0050] Because the voltage conversion circuit 12 is a slave, the master-slave indication signal M / S is 0, so the level state of the level Vb at the output terminal of the AND gate in the first logic circuit 33 is the same as the logic state of the synchronous clock signal CLK_1 received by the synchronous pin SYN.

[0051] Before time t1, when the enable signal EN is 1, the RS flip-flop 331 is enabled and turned off, and the output of the RS flip-flop 331 is 0, so the output level Vc of the first logic circuit 33 is 1, the first delay circuit 34 is not started, and the first delay signal Vd outputted by it is 1. At the same time, because the enable signal EN is 1, the RS flip-flop 361 is enabled and turned off, and the output level of the RS flip-flop 361 is 0. Similarly, because the enable signal EN is 1, the synchronous clock signal CLK_2 is 0. The second delay circuit 35 is also not started, and the output second delay signal Ve is 1.

[0052] At time t1, the enable signal EN changes from 1 to 0. Since the output level of the RS trigger 361 is still 0, the synchronous clock signal CLK_2 changes to 1. At this time, the single pulse trigger 32 generates a single pulse signal Va with a certain pulse width (for example, 10ns) at the rising edge of the synchronous clock signal CLK_2. The state of Vb is the same as that of the synchronous clock signal CLK_1, which is 1. Therefore, Vc continues to be a high level 1 with a pulse width of the single pulse signal Va and then changes to 0. The first delay circuit 34 starts timing, and the first delay signal Vd output by it remains at 1 until the timing ends at time t3.

[0053] At the same time, at time t1, after the synchronous clock signal CLK_2 becomes 1, the second delay circuit 35 also starts timing, and the second delay signal Ve outputted by it continues to be 1. When the second duration (e.g., 150ns) is finished at time t2, Ve becomes 0, and the output level of the RS trigger 361 becomes 1, and the synchronous clock signal CLK_2 becomes 0. Subsequently, at time t3 when the first duration of timing by the first delay circuit 34 ends, Vd becomes 0, the output level of the RS trigger 361 becomes 0, and the synchronous clock signal CLK_2 becomes 1 again. Because it is a two-phase switching converter, the phase difference is 180°, and the period of the synchronous clock signal CLK_1 is T1 (2us), and the first duration is 1 / 2T1 (1us).

[0054] At time t3 when the synchronous clock signal CLK_2 becomes 1 again, the single pulse signal Va briefly becomes 1 again and then returns to 0. Since the output state of the RS trigger 331 is also related to the synchronous clock signal CLK_1 input by the synchronous pin SYN, when Va becomes 0, since the synchronous clock signal CLK_1 is 0 at this time, Vb is 0 and Vc remains unchanged at 1. At time t4, when the rising edge of the synchronous clock signal CLK_1 generated by the host comes again, Vb becomes 1, Vc becomes 0, and the first delay circuit 34 restarts the delay timing of the first duration. By repeating the above process, the synchronous clock signal generating circuit in the slave voltage conversion circuit 12 can generate a synchronous clock signal CLK_2 with a period of 2us, a high level width of 150ns, and a phase shift time of 1us.

[0055] Furthermore, in the voltage conversion circuit 12 , the master-slave switch 37 is turned off by the master-slave indication signal M / S, and the synchronous clock signal CLK_2 is not outputted through the synchronous pin SYN.

[0056] Figure 6 According to an embodiment of the present invention, a circuit schematic diagram of an identification circuit 31 and a first delay circuit 34 in a synchronous clock signal generating circuit 21 is shown. The identification circuit 31 is used to generate at least two identification signals. Figure 1 In the figure, it is shown as the first identification signal MS-1 and the second identification signal MS-2. Any one of the first identification signal MS-1 and the second identification signal MS-2 can be used as the master-slave indication signal M / S. Figure 6 In the illustrated embodiment, the first identification signal MS-1 is used as the master-slave indication signal M / S. The first delay circuit includes at least two current sources and delay switches corresponding to the number of current sources. Also taking a two-phase switching converter as an example, that is, having two switching conversion circuits, in this application scenario, the first delay circuit 34 includes a first current source I1, a second current source I2, a first delay capacitor C1-dly, a first delay switch M1, a second delay switch M2, a first reset switch M1-dly and a first delay comparator 341.

[0057] The first delay capacitor C1-dly has a first end and a second end, and the first end of the first delay capacitor C1-dly is connected to the reference ground. The first delay switch M1 has a first end, a second end and a control end, the first end of the first delay switch M1 is coupled to the first current source I1, the second end of the first delay switch M1 is coupled to the second end of the first delay capacitor C1-dly, and the control end of the first delay switch M1 receives the first identification signal MS-1. The second delay switch M2 has a first end, a second end and a control end, the first end of the second delay switch M2 is coupled to the second current source, the second end of the second delay switch M2 is coupled to the second end of the first delay capacitor C1-dly, and the control end of the second delay switch M2 receives the second identification signal MS-2. The first reset switch M1-dly has a first end, a second end and a control end. The first end of the first reset switch M1-dly is coupled to the first end of the first delay capacitor C1-dly, the second end of the first reset switch M1-dly is coupled to the second end of the first delay capacitor C1-dly, and the control end of the first reset switch M1-dly receives the first logic signal Vc. The first delay comparator 341 has a first input end, a second input end and an output end. The first input end of the first delay comparator 341 is coupled to the second end of the first delay capacitor C1-dly, the second input end of the first delay comparator 341 receives the first delay reference value Vref1, and the first delay comparator 341 compares the voltage on the second end of the first delay capacitor C1-dly with the first delay reference value Vref1, and outputs the first delay signal Vd at the output end.

[0058] Continue to see Figure 6 , the identification circuit 31 is illustrated as including a mode setting current source I0 , an identification comparison circuit 311 and a third logic circuit 312 .

[0059] The mode setting current source I0 is coupled to the mode pin MODE. Usually, the mode pin MODE is also connected to a first resistor. The mode setting current source I0 flows through the first resistor to generate a mode voltage on the mode pin MODE. Each voltage conversion circuit can be set with a first resistor of different resistance to generate different mode voltages. In one embodiment, the voltage conversion circuit with the largest mode voltage can be set as the master, and the rest can be set as slaves. The order of the phase circuits is arranged in sequence according to the size of the mode voltage.

[0060] The identification comparison circuit 311 compares the mode voltage on the mode pin MODE with the reference value Vm1 and outputs a comparison signal. Figure 6 In the illustrated embodiment, since a two-phase converter is taken as an example, only one voltage comparator CA1 is included in the identification comparison circuit 311. When the mode voltage is less than the reference value Vm1, it indicates that the phase circuit is a slave; when the mode voltage is greater than the reference value Vm1, it indicates that the phase circuit is a master. In other embodiments, the identification comparison circuit 311 may include multiple voltage comparators. For example, in a three-phase converter, the identification comparison circuit 311 may include two voltage comparators, and the two comparators compare the mode voltage with the reference value Vm1 and the reference value Vm2 respectively to output two comparison signals. When the mode voltage is greater than the reference value Vm1 and greater than the reference value Vm2, it indicates that the phase circuit is a master; when the mode voltage is greater than the reference value Vm1 and less than the reference value Vm2, it indicates that the phase circuit is a first slave; when the mode voltage is less than the reference value Vm1 and less than the reference value Vm2, it indicates that the phase circuit is a second slave. Other embodiments can be deduced in the same manner.

[0061] The third logic circuit 312 receives the comparison signal, performs a logic operation on the comparison signal, and outputs a first identification signal MS-1 and a second identification signal MS-2. Figure 6 In the illustrated embodiment, since a two-phase converter is used as an example, the third logic circuit 312 includes only one inverter, the first identification signal MS-1 is the comparison signal, and the second identification signal MS-2 is the inverted signal of the comparison signal. In other embodiments, the third logic circuit 312 may include multiple logic modules to provide corresponding identification signals after performing logic operations on multiple comparison signals.

[0062] exist Figure 6In the illustrated embodiment, when the voltage conversion circuit is the host, the high-level first identification signal MS-1 is used to turn on the first delay switch M1, and the low-level second identification signal MS-2 is used to turn off the second delay switch M2. When the first reset switch M1-dly is turned off, the first current source I1 charges the first delay capacitor C1-dly, and timing begins. When the voltage on the first delay capacitor C1-dly rises to the first delay reference value Vref1, the logic state of the first delay signal Vd changes, and timing ends.

[0063] When the voltage conversion circuit is a slave, the low-level first identification signal MS-1 is used to disconnect the first delay switch M1, and the high-level second identification signal MS-2 is used to turn on the second delay switch M2. When the first reset switch M1-dly is disconnected, the second current source I2 charges the first delay capacitor C1-dly, and the timing starts. When the voltage on the first delay capacitor C1-dly rises to the first delay reference value Vref1, the logic state of the first delay signal Vd changes, and the timing ends.

[0064] By setting the first current source I1 and the second current source I2 of different values, the value of the first duration can be changed. It can be understood that the specific circuit schematic diagram shown above only takes a two-phase switching converter as an example. In a multi-phase switching converter, the number of corresponding components can be increased to achieve synchronous phase-shifting control between more phase circuits. For example, increasing the number of identification comparators to generate a corresponding number of identification signals, and then adding a corresponding number of reset switches and current sources in the first delay circuit 34, a corresponding number of delay times can be generated, and then a corresponding number of synchronous clock signals with phase differences can be generated.

[0065] Figure 7 According to one embodiment of the present invention, a circuit schematic diagram of the second delay circuit 35 is shown. Figure 7 As shown, the second delay circuit 35 includes a third current source I3 , a second delay capacitor C2 -dly, a second reset switch M2 -dly and a second delay comparator 351 .

[0066] The second delay capacitor C2-dly has a first end and a second end, and the first end of the second delay capacitor C2-dly is connected to the reference ground. The first reset switch M2-dly has a first end, a second end and a control end, the first end of the second reset switch M2-dly is coupled to the first end of the second delay capacitor C2-dly, the second end of the second reset switch M2-dly is coupled to the second end of the second delay capacitor C2-dly, and the control end of the second reset switch M2-dly receives the synchronous clock signal CLK_N through an inverter. The second delay comparator 351 has a first input end, a second input end and an output end, the first input end of the second delay comparator 351 is coupled to the second end of the second delay capacitor C2-dly, the second input end of the second delay comparator 351 receives the second delay reference value Vref2, the second delay comparator 351 compares the voltage on the second end of the second delay capacitor C2-dly with the second delay reference value Vref2, and outputs the second delay signal Ve at the output end.

[0067] Although the present invention has been described above with reference to several typical embodiments, it should be understood by those skilled in the art that the terms used in the disclosed embodiments of the present invention are illustrative and exemplary, rather than restrictive, and are only used to describe specific embodiments, and are not intended to limit the present invention. In addition, various modifications in form and details made by those skilled in the art to the embodiments disclosed in the present invention without departing from the principles and concepts of the present invention and without creative efforts, all of which fall within the scope of protection defined by the claims of the present application or their equivalents.

Claims

1. A synchronous clock signal generating circuit, characterized in that: The synchronous clock signal generating circuit is used to provide a synchronous clock signal for a voltage conversion circuit, the voltage conversion circuit includes a synchronous pin, and the synchronous pins of multiple voltage conversion circuits are coupled together to form a multi-phase switching converter, wherein one voltage conversion circuit serves as a master and the other voltage conversion circuits serve as slaves. The synchronous clock signal generating circuit includes: An identification circuit, used for generating an identification signal, wherein the identification signal is used for identifying each phase voltage conversion circuit; A single pulse trigger receives a synchronous clock signal and generates a single pulse signal at the edge of the synchronous clock signal; A first logic circuit has a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal of the first logic circuit receives an enable signal, the second input terminal of the first logic circuit is coupled to a single pulse signal, the third input terminal of the first logic circuit is coupled to a synchronization pin, and the fourth input terminal of the first logic circuit receives an identification signal. The first logic circuit performs a logic operation on the enable signal, the single pulse signal, the level signal on the synchronization pin and the identification signal to generate a first logic signal, wherein the first logic signal is used to set a starting time of a synchronization clock signal; a first delay circuit, receiving a first logic signal and an identification signal, and starting timing of a first duration according to the first logic signal and the identification signal to output a first delay signal, wherein when the identification signal identifies the voltage conversion circuit as a host, the first duration is a period of the synchronous clock signal; when the identification signal identifies the voltage conversion circuit as a slave, the first duration is a phase difference between the synchronous clock signal generated in the slave and the synchronous clock signal generated in the host; A second delay circuit receives a synchronous clock signal and starts timing a second time length according to the synchronous clock signal to output a second delay signal, wherein the second time length is a pulse width of the synchronous clock signal; A second logic circuit receives the enable signal, the first delay signal and the second delay signal, performs a logic operation on the enable signal, the first delay signal and the second delay signal, and generates a synchronous clock signal at its output terminal; When the identification signal identifies the voltage conversion circuit as the host, the synchronous clock signal generating circuit will also output the synchronous clock signal through the synchronous pin.

2. The synchronous clock signal generating circuit as claimed in claim 1, characterized in that: For different slaves, the first time length of the first delay circuit is different.

3. The synchronous clock signal generating circuit as claimed in claim 1, characterized in that: The identification signal includes at least a first identification signal and a second identification signal, and the first delay circuit includes: at least two current sources: a first current source and a second current source; At least two delay switches corresponding to the number of current sources: a first delay switch and a second delay switch; A first delay capacitor has a first end and a second end, and the first end of the first delay capacitor is connected to a reference ground; The first delay switch has a first end, a second end and a control end, the first end of the first delay switch is coupled to the first current source, the second end of the first delay switch is coupled to the second end of the first delay capacitor, and the control end of the first delay switch receives a first identification signal; The second delay switch has a first end, a second end and a control end, the first end of the second delay switch is coupled to the second current source, the second end of the second delay switch is coupled to the second end of the first delay capacitor, and the control end of the second delay switch receives the second identification signal; A first reset switch having a first end, a second end and a control end, the first end of the first reset switch being coupled to the first end of the first delay capacitor, the second end of the first reset switch being coupled to the second end of the first delay capacitor, and the control end of the first reset switch receiving a first logic signal; The first delay comparator has a first input terminal, a second input terminal and an output terminal. The first input terminal of the first delay comparator is coupled to the second terminal of the first delay capacitor. The second input terminal of the first delay comparator receives a first delay reference value. The first delay comparator compares the voltage on the second terminal of the first delay capacitor with the first delay reference value and outputs a first delay signal at the output terminal.

4. The synchronous clock signal generating circuit as claimed in claim 3, characterized in that: The voltage conversion circuit further includes a mode pin, and a first resistor is electrically connected between the mode pin and a reference ground, wherein the resistance values ​​of the first resistor coupled to the mode pin of each voltage conversion circuit are not equal.

5. The synchronous clock signal generating circuit as claimed in claim 4, characterized in that: The identification circuit comprises: A mode setting current source is coupled to the mode pin, and a current of the mode setting current source flows through the first resistor to generate a mode voltage on the mode pin; The identification comparison circuit compares the mode voltage with the corresponding reference value and outputs a comparison signal; The third logic circuit receives the comparison signal, performs a logic operation on the comparison signal, and outputs a first identification signal and a second identification signal.

6. The synchronous clock signal generating circuit as claimed in claim 1, characterized in that: The second delay circuit comprises: a third current source; A second delay capacitor has a first end and a second end, and the first end of the second delay capacitor is connected to a reference ground; A second reset switch has a first end, a second end and a control end, the first end of the second reset switch is coupled to the first end of the second delay capacitor, the second end of the second reset switch is coupled to the second end of the second delay capacitor, and the control end of the second reset switch receives a synchronous clock signal through an inverter; The second delay comparator has a first input terminal, a second input terminal and an output terminal. The first input terminal of the second delay comparator is coupled to the second terminal of the second delay capacitor. The second input terminal of the second delay comparator receives a second delay reference value. The second delay comparator compares the voltage on the second terminal of the second delay capacitor with the second delay reference value and outputs a second delay signal at the output terminal.

7. The synchronous clock signal generating circuit as claimed in claim 1, characterized in that: The voltage conversion circuit further includes a mode pin, and the identification circuit receives an external digital signal through the mode pin and generates an identification signal according to the external digital signal.

8. The synchronous clock signal generating circuit as claimed in claim 1, characterized in that: The identification signal includes multiple logic high and low level signals, one of which serves as a master-slave indication signal, and the master-slave indication signal is used to indicate whether the voltage conversion circuit is a master or a slave. The first logic circuit receives the master-slave indication signal and performs logical operations on the enable signal, the single pulse signal, the level signal on the synchronization pin, and the master-slave indication signal to generate a first logic signal.

9. The synchronous clock signal generating circuit as claimed in claim 8, characterized in that: Further including: The master-slave switch has a first end, a second end and a control end. The first end of the master-slave switch is coupled to the output end of the second logic circuit, the second end of the master-slave switch is coupled to the synchronization pin, and the control end of the master-slave switch receives a master-slave indication signal.

10. The synchronous clock signal generating circuit as claimed in claim 1, characterized in that: When the voltage conversion circuit starts up, the enable signal enables the synchronous clock signal generating circuit to start up to generate the synchronous clock signal.

11. A voltage conversion circuit, characterized in that: include: A synchronous clock signal generating circuit as claimed in any one of claims 1 to 10, used to generate a synchronous clock signal; Power switch; A control unit receives a feedback signal and a synchronous clock signal, and generates a control signal according to the feedback signal and the synchronous clock signal, wherein the feedback signal represents the output voltage of the voltage conversion circuit, and the control signal is used to adjust the on time and off time of the power switch, thereby converting the input voltage received by the voltage conversion circuit into an output voltage.

Images